WO2014092551A1 - Système et procédé de gestion optimale de mémoire entre cpu et unité fpga - Google Patents

Système et procédé de gestion optimale de mémoire entre cpu et unité fpga Download PDF

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Publication number
WO2014092551A1
WO2014092551A1 PCT/MY2013/000265 MY2013000265W WO2014092551A1 WO 2014092551 A1 WO2014092551 A1 WO 2014092551A1 MY 2013000265 W MY2013000265 W MY 2013000265W WO 2014092551 A1 WO2014092551 A1 WO 2014092551A1
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WIPO (PCT)
Prior art keywords
memory
fpga
data
host cpu
cpu
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Application number
PCT/MY2013/000265
Other languages
English (en)
Inventor
Shafiq Bin Alias MOHD
Ettikan Kandasamy A/L KARUPPIAH
Ong Hong HOE
Shahirina Binti Mohd TAHIR
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Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2014092551A1 publication Critical patent/WO2014092551A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17325—Synchronisation; Hardware support therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to memory management between devices. More particularly, the present invention relates to a system and method for managing memory between a host device and FPGA.
  • FIG. 1 illustrates a typical set up of a system that includes a host center processing unit (CPU) 102 and a Field Programmable Gate Array (FPGA) 104.
  • the host CPU 102 is adapted to receive video streams from multiple imaging devices 101.
  • the host CPU has a CPU 111, an internal host memory 112 that holds applications 114 therein and a root complex module 113.
  • the root complex module 113 connects the CPU 111 and the internal host memory 112 to a Peripheral Component Interconnect Express (PCIe) interface.
  • PCIe Peripheral Component Interconnect Express
  • the PCIe interface can be used to connect the host CPU 111 with the FPGA 104.
  • the FPGA 104 has a Direct Memory Allocation (DMA) module 121 to receive transmission from the root complex module 113 through the PCIe interface to allow the data to be stored on the FPGA external memory 150.
  • DMA Direct Memory Allocation
  • the host CPU 102 serves as an out memory to the FPGA 104 as in memory when writing data to the external memory 150, and vise versa when it is reading data from the external memory 150.
  • a system for synchronising memory data transfer comprising a host Central Processing Unit (CPU) having a memory optimizer; and a Field Programmable Gate Array (FPGA) having a memory load identifier.
  • CPU Central Processing Unit
  • FPGA Field Programmable Gate Array
  • the memory optimizer operationally checks memory utilization at an idle state in the FPGA and determines whether to drop/retain AV data based on the memory utilization on the FPGA; and when data is processed on the FPGA, the memory load identifier operationally checks memory utilization at an idle sate in the host CPU and determines whether to drop/retain AV data based on the memory utilization on the host CPU.
  • the CPU memory optimizer comprises a dynamic size memory and the FPGA memory load identifier comprises a fixed size memory.
  • the FPGA comprises a Direct Memory Access (DMA) controller, an external memory. Further, the memory utilization in the FPGA and the memory utilization in the host CPU are received from the host CPU and the FPGA respectively through a feedback signal therefrom.
  • DMA Direct Memory Access
  • a method for synchronizing memory during data transfer between a host CPU and a Field Programmable Gate Array comprises mapping the data from a memory of the host CPU to one or more memories associated with the FPGA; self- checking memory utilization at an idle state in the FPGA; sending a first feedback regarding the memory utilization information to the host CPU; determining whether data drop/retain is required on the host CPU based on the first feedback; mapping data from a memory associated with FPGA to one or more memories in host CPU; self- checking memory utilization at an idle state in the host CPU; sending a second feedback regarding the memory utilization information to the FPGA; host CPU; and determining whether data drop/retain is required on the FPGA based on the second feedback.
  • FPGA Field Programmable Gate Array
  • the memory mapping on the host CPU comprises checking a memory threshold on the host CPU upon receiving input data; tagging the data with label information on a virtual memory of the host CPU; controlling the flow of the input data based on the first feedback at the beginning, during or/and ending of the data transfer from host CPU to FPGA; retaining data by continuing the mapping transfer execution as the FPGA is demanding more data; dropping data at the beginning of packet transmission by slowing down the transmission rate at host CPU; monitoring and checking the FPGA memory status flags of being either almost full or almost empty or full or empty, monitoring memory rate/speed and error signal during the transfer or/and before sending back data to host CPU memory optimizer; FPGA is sending data to endpoint of FPGA memory.
  • the memory mapping on FPGA comprises checking continuously memory status flag of the host CPU through the first feedback; tagging the output packet in the DMA controller register, wherein data is tagged with ID parameters including Input/Output, memory flag, memory rate, error signal and camera ID; controlling the flow of data on the FPGA based on the host CPU memory threshold, memory rate/speed and error signal at the beginning, during or/and ending of the data transfer from FPGA; retaining data by continuing the mapping transfer as the host CPU is demanding more data; dropping frame at the beginning of packet transmission by slowing down the transmission rate at host CPU or/and on the DMA control register in FPGA.
  • the method may comprise updating synchronization status of host CPU and the FPGA. It is possible that the data comprises sequence of image frame.
  • FIG. 1 illustrates a typical set up of a system that includes a host center processing unit (CPU) and a Field Programmable Gate Array (FPGA);
  • CPU host center processing unit
  • FPGA Field Programmable Gate Array
  • FIG. 2 illustrates a schematic block diagram of a host CPU and a Field
  • FIG. 3 illustrates a block diagram of read and write operations of a system having a host CPU and a FPGA in accordance with one embodiment of the present invention
  • FIG. 4 A exemplifies a header of a data packet for sending from the host CPU to the FPGA of FIG. 3 in accordance with one embodiment of the present invention
  • FIG. 4B exemplifies a header of a data packet for sending from the
  • FIG. 5 illustrates a memory mapping of a system having a host and a
  • FIG. 6A and 6B illustrate flow charts of data processes in accordance with one embodiment of the present invention
  • FIG. 7 illustrates a state machines diagram of the memory management of the system in accordance with one embodiment of the present invention
  • FIG. 8 A illustrates a process carried out in the state A of the state machine of FIG. 7 in accordance with one embodiment of the present invention
  • FIG. 8B illustrates a process carried out in the state B of the state machine of FIG. 7 in accordance with one embodiment of the present invention
  • FIG. 8C illustrates a process carried out in the state C of the state machine of FIG. 7 in accordance with one embodiment of the present invention
  • FIG. 8D illustrates a process carried out in the state D of the state machine of FIG. 7 in accordance with one embodiment of the present invention.
  • FIG. 2 illustrates a schematic block diagram of a host CPU 202 and a
  • FPGA Field Programmable Gate Array
  • the present embodiment is implementable on a system adapted to receive data from an Audio Video (AV) device that operationally captures audio-video data streams. More specifically, the system is adapted to handle data streams transmitted from multiple AV devices, wherein the data streams are transmitted to the host CPU 202 at a dynamic arrival rate.
  • the system adapts a tagging mechanism to the parallel streaming whereby the packet header provides information based on priority and camera number sequence to ensure optimal data transfer.
  • the host CPU 202 is connected to the FPGA 204 via a PCIe link 206.
  • the host CPU 202 comprises a memory optimizer 221, software applications 222, an application programming interface (API) 223 and an API deriver 224.
  • the CPU memory optimizer 221 is adapted to measure memory threshold on the host CPU 222 and to provide a tagging mechanism in virtual memory to label information on the parallel AV streams as their parameters for optimal data transmissions to FPGA.
  • the information may include camera ID, number of images, priority, frame size, sequence number and etc.
  • the FPGA 204 comprises a PCIe intellectual property (IP) core 221 and a dynamic memory allocation (DMA) module 222.
  • IP PCIe intellectual property
  • DMA dynamic memory allocation
  • the PCIe IP core 221 receives/transmit data through a transaction, data link and physical layers.
  • the PCIe IP core 221 also facilitates a virtual memory for managing memory allocations.
  • the DMA module 222 comprises a DMA controller 223 and a memory load identifier 225.
  • the memory load identifier 225 in FPGA 204 operationally measures memory load and provide tagging mechanism in FPGA 204 to label information on the memory parameters, such as memory flags, memory rate, and etc., for optimal data transmission with the host CPU 202.
  • the memory optimizer 221 on the host CPU 202 and the memory load identifier 225 on the FPGA 204 feedback to each other based on tags associated to the data.
  • the memory optimizer 221 and the memory load identifier 225 are capable to drop or retain frames as required before the data is being channeled to the external memory, such as SDRAM, for processing.
  • Motion-JPEG (MJPEG) frames may be skipped at the beginning of packet transfer to ensure harmonization between the host CPU 202 and the FPGA 204.
  • MJPEG Motion-JPEG
  • FIG. 3 illustrates a block diagram of read and write operations of a system having a host CPU 302 and a FPGA 304 in accordance with one embodiment of the present invention.
  • the host CPU 302 is connected with the FPGA 304 via a PCIe link 306.
  • the host CPI 302 has application modules 312 and driver 314.
  • the application modules 312 are adapted for handling data, such as acquitting data, processing data, transmitting data to the FPGA 304 and the like.
  • the FPGA comprises a PCIe mega core 322 and a DMA module 324.
  • the PCIe mega core 322 maps the data transmitted from the host CPU 302 via the PCIe link 306. Once the data is received through eh PCIe link 306.
  • the memory load identifier 324 has a decipher engine 326, a DMA controller 328 and a high performance memory controller 330.
  • the decipher engine 326 provides cipher/decipher read/write operations to the data.
  • the ciphered/deciphered data passes through the DMA controller 328. Status flags are being tagged to the data.
  • the data that is tagged will be channeled to the high performance memory controller 330 before transmitting to the external memory 350, such as SDRAM.
  • FIG. 4A exemplifies a header of a data packet for sending from the host
  • FIG. 4B exemplifies a header of a data packet for sending from the
  • FIG. 5 illustrates a memory mapping of a system having a host and a
  • FPGA in accordance with one embodiment of the present invention.
  • Data acquired by the host will be processed through a virtual memory 502, a physical memory 504, a PCIe BAR 506 and FPGA external memory 508.
  • the virtual memory 502 and the physical memory 504 are resided at the host.
  • a memory optimizer determines the availability of the memory. Once the availability of the memory is determined, the frame drop or retain is carried out.
  • a drop frame collector calls a function to dispose the image frames to be dropped before mapping back from memory frame buffer of the memory optimizer to the physical memory for transferring.
  • For the frame data that is being retained it is being mapped to the physical memory and reside at a manage heap of the physical memory 504.
  • the frame data is further mapped to the PCIe BAR 506. Thereafter, the frame data is processing through DMA controller before channel to FPGA external memory 508.
  • FIGs. 6A and 6B illustrate flow charts of data processes in accordance with one embodiment of the present invention.
  • the data processes include an in- memory data process (as in FIG. 6A) and an out-memory data process (as in FIG. 6B) with respect to the host CPU.
  • Both in-memory data process and out-memory data process shows data processing between application software 602 and an FPGA hardware 604 connected through a PCIe link 606.
  • the application software 602 is resided at the host CPU.
  • the data process starts with capturing audio-video
  • the AV data includes sequences of image frams that forms the video data.
  • the image frames are wrapped at step 613.
  • the image frames are being tagged by the memory optimizer at step 614.
  • the data are then mapped from the user space to physical memory of the host CPU at step 616.
  • the data is being sent to the FPGA hardware 604 through the PCIe link 606 where the data are mapped from the physically memory to PCIe Base Address Register (BAR) at step 620, and subsequently channeled to the DMA controller at step 621.
  • BAR PCIe Base Address Register
  • the FPGA memory load identifier measures memory loads and tags memory parameters into the header of each data package.
  • Measuring of the memory loads may include measuring memory rate at step 631, measuring error signal at step 632 and checking memory status flags at step 633. Once the data are being tagged with the memory parameters, the data is mapped accordingly at step 626 for channeling to the external memory of the FPGA at step 627.
  • the memory load identifier transmits a feedback signal to the memory optimizer at step 628 through the PCIe link 606.
  • the memory optimizer 615 receives the feedback signal from the FPGA hardware 604.
  • the memory optimizer 615 processes the images to decide the image frames to be dropped or retained at step 617.
  • the AV data is taken from the external memory in step 651 and send to the DMA controller in step 652.
  • Memory allocation done by the DMA controller 652 is affected by the memory load identifier in step 655.
  • the memory load identifier determines the frames to be dropped/retained in step 657 based on the frame tagging done on the memory load identifier in step 656.
  • the AV data from the external memory of the FPGA is being mapped to the PCIe BAR for transmitting to the host CUP in step 254. Once transmitted, the data is further mapped from PCIe BAR to physically memory of the host CPU in step 261.
  • the data is further mapped from the physical memory into user space in step 662.
  • the data mapped in the user space is channeled to the memory optimizer at 665.
  • the memory optimizer measures the memory threshold of the host CPU in step 666, checks the data arrival rate in step 667 and checks the status flag in step 668.
  • the image frames is being unwrapped from the data in step 663 for streaming in step 664.
  • the memory optimizer sends feedback signals to the
  • step 669 the feedback signal is fed to the memory load identifier.
  • FIG. 7 illustrates a state machines diagram of the memory management of the system in accordance with one embodiment of the present invention.
  • the state machine is carried out in four states: state A, state B, state C and state D.
  • state A and state C are carried out on the host CPU side whilst state B and state D are carried out on the FPGA.
  • the conditions to trigger state A and state D at the include memory threshold (either full or empty), arrival rate/speed, sequence number.
  • the conditions to trigger state B and state C on the FPGA include memory flags (almost full/almost empty/full/empty), memory rate and speed, error signal and etc.
  • FIG. 8A illustrates a process carried out in the state A of the state machine of FIG. 7 in accordance with one embodiment of the present invention.
  • the host CPU receives AV streaming from the camera in step 801.
  • the user space memory block is the locked at virtual memory for memory mapping in step 802.
  • the image frames is then wrapped with ID parameters of the image frames in step 803.
  • the memory is further mapped from virtual memory to physical memory in step 804.
  • the virtual memory reads a feedback from FPGA at the state B in step 805.
  • the feedback contains the memory state of the FPGA.
  • step 807 the memory state of the FPGA is being checked if it is sufficient. If the memory is sufficient, all the frames are retained in step 808.
  • the frames are then tagged based on the feedback signal received from state B in step 809. If the memory is determined to be insufficient in the step 807, image frames are dropped at the beginning of the transmission in step 810. A feedback signal regarding the dropped frames is sent to the state D in step 811.
  • FIG. 8B illustrates a process carried out in the state B of the state machine of FIG. 7 in accordance with one embodiment of the present invention.
  • step 821 data received from the previous state, i.e. state A, is being mapped from the physical memory to PCIe BAR then to the DMA.
  • the memory load identifier of the FPGA updates the status flags, image size, and etc. on the DMA controller in step 822.
  • the memory load identifier further determines if the FPGA's external memory is sufficient in step 823. If the external memory is sufficient, memory mapping from PCIe BAR to the external memory is carried out in step 824, and the data is sent to the FPGA external memory in step 825.
  • a trigger is sent to activate state C in step 826.
  • a feedback signal is sent to the host CPU in step 827 during first interrupt to the base address of stolen region in virtual memory.
  • a trigger is sent in step 828 to the state A. Besides looping back to the state A, the process reverts to the step 821 for self-checking on the out-coming data rate from FPGA for balancing memory load between the host CPU and the FPGA.
  • FIG. 8C illustrates a process carried out in the state C of the state machine of FIG. 7 in accordance with one embodiment of the present invention.
  • the FPGA completes the video processing.
  • the memory load identifier checks ID parameters from DMA memory controller. The memory load identifier checks if the CPU memory is sufficient in step 843. Information regarding the CPU memory is contained in a feedback signal from the memory optimizer of the host CPU at step 850. The feedback signal is sent from the memory optimizer to the DMA controller. The DMA controller reads the feedback signal upon receiving a trigger from state D in step 851.
  • step 843 if the host CPU memory is sufficient, the FPGA retains frame in step 844. Accordingly, the status flags, image size and etc. are updated on the DMA controller in step 845. The data is then mapped from PCIe BAR to physical memory for transmitting to the host CPU in step 846. If the host CPU memory is determined to be insufficient. The images frames are dropped at the beginning of transmission in step 847. The memory load identifier sends trigger to state C.
  • the trigger is sent to state C as a propagation signal to inform the FPGA's load identifier to update the status of the FPGA on the host CPU so that FPGA's memory load identifier can either supply more frames or limit the total frames to be sent over to host CPU in step 848.
  • the memory needed is being checked in state C.
  • FIG. 8D illustrates a process carried out in the state D of the state machine of FIG. 7 in accordance with one embodiment of the present invention.
  • the FPGA sends back the data by writing it to the host CPU.
  • the memory optimizer receives a function call to measure memory threshold at the virtual memory. Such function call is initiated through a trigger received from the state C in step 863. Accordingly, the CUP memory is checked whether it is sufficient at step 864. If the CPU memory is sufficient, memory mapping is carried our between the CPU and the FPGA in step 865. The data is then received from the FPGA in step 866 and in turn send to the application of the host CPU for processing in step 867.
  • step 864 if the CPU memory is not sufficient, a feedback is sent to FPGA during first interrupt to the base address of stolen region in the virtual memory in step 868.
  • the camera's ID parameter is updated whiles receiving the image frames from FPGA in step 869.
  • step 870 FPGA drop frames at the base address level at the FPGA load identifier.
  • step 871 a trigger is sent to activate state A.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Stored Programmes (AREA)
  • Hardware Redundancy (AREA)

Abstract

La présente invention porte sur un système de synchronisation de transfert de données de mémoire. Le système comprend une unité centrale (CPU) hôte comportant un dispositif d'optimisation de mémoire ; et un circuit intégré prédiffusé programmable (FPGA) comportant un dispositif d'identification de charge de mémoire. Lorsque des données sont reçues sur la CPU hôte, le dispositif d'optimisation de mémoire contrôle fonctionnellement l'utilisation de mémoire au niveau d'un état de veille dans le FPGA et détermine d'abandonner/retenir des données sur la base de l'utilisation de mémoire sur le FPGA ; et lorsque des données sont traitées sur le FPGA, le dispositif d'identification de charge de mémoire contrôle fonctionnellement l'utilisation de mémoire au niveau d'un état de veille dans la CPU hôte et détermine d'abandonner/retenir des données sur la base de l'utilisation de mémoire sur la CPU hôte. Un procédé de synchronisation de données mémoire est également décrit conjointement.
PCT/MY2013/000265 2012-12-13 2013-12-13 Système et procédé de gestion optimale de mémoire entre cpu et unité fpga WO2014092551A1 (fr)

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MYPI2012005435A MY186464A (en) 2012-12-14 2012-12-14 System and method for optimal memory management between cpu and fpga unit

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WO2016175814A1 (fr) * 2015-04-30 2016-11-03 Hewlett Packard Enterprise Development Lp Mise en correspondance d'ouvertures de différentes tailles
WO2018093371A1 (fr) * 2016-11-17 2018-05-24 Intel Corporation Dispositif de brouillard multi-usages
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WO2016175814A1 (fr) * 2015-04-30 2016-11-03 Hewlett Packard Enterprise Development Lp Mise en correspondance d'ouvertures de différentes tailles
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CN112131828A (zh) * 2020-09-18 2020-12-25 山东云海国创云计算装备产业创新中心有限公司 一种数据处理方法、装置、设备及可读存储介质
CN112131828B (zh) * 2020-09-18 2022-06-17 山东云海国创云计算装备产业创新中心有限公司 一种数据处理方法、装置、设备及可读存储介质
CN113840272A (zh) * 2021-10-12 2021-12-24 北京奕斯伟计算技术有限公司 数据传输方法、数据传输装置以及电子装置
CN113840272B (zh) * 2021-10-12 2024-05-14 北京奕斯伟计算技术股份有限公司 数据传输方法、数据传输装置以及电子装置

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