WO2014080668A1 - High frequency amplifier circuit - Google Patents

High frequency amplifier circuit Download PDF

Info

Publication number
WO2014080668A1
WO2014080668A1 PCT/JP2013/070842 JP2013070842W WO2014080668A1 WO 2014080668 A1 WO2014080668 A1 WO 2014080668A1 JP 2013070842 W JP2013070842 W JP 2013070842W WO 2014080668 A1 WO2014080668 A1 WO 2014080668A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
field effect
voltage
fet
effect transistor
Prior art date
Application number
PCT/JP2013/070842
Other languages
French (fr)
Japanese (ja)
Inventor
廣岡博之
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2014080668A1 publication Critical patent/WO2014080668A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/15—Indexing scheme relating to amplifiers the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

Definitions

  • the present invention relates to a high-frequency amplifier circuit that amplifies and outputs an input high-frequency signal, and more particularly, to a high-frequency amplifier circuit that uses an enhancement type field effect transistor as an amplifying element.
  • a transmission circuit of a communication device is provided with a high-frequency amplifier circuit that amplifies a high-frequency signal used for communication.
  • a high-frequency amplifier circuit for example, a field effect transistor (hereinafter referred to as “FET”) for amplifying a high-frequency signal is used as shown in FIG.
  • FET field effect transistor
  • the gate bias voltage of the high frequency amplification FET is applied through a resistor.
  • Patent Document 1 it is known that the drain current varies due to manufacturing variations of the high frequency amplification FET, and the high frequency amplification circuit described in Patent Document 1 has the following configuration.
  • the gate of the high frequency amplification FET is provided with a gate bias circuit including a compensation FET having the same structure as the high frequency amplification FET.
  • the gate bias circuit has a configuration in which a compensation FET and two resistors are cascaded between a gate bias (-VGG) application terminal and a ground. Specifically, a resistor, a compensation FET, and a resistor are connected from the gate bias ( ⁇ VGG) application terminal side. Each resistor is connected to the drain and source of the compensation FET.
  • a gate bias ( ⁇ VGG) is directly applied to the gate of the compensation FET.
  • the pinch off voltage of the compensation FET when the pinch-off voltage of the high frequency amplification FET deviates from the design value, the pinch off voltage of the compensation FET similarly deviates from the design value. Due to the deviation of the pinch-off voltage of the compensation FET, the output voltage of the gate bias circuit (the gate bias voltage of the high-frequency amplification FET) changes so as to compensate for the deviation of the pinch-off voltage.
  • the high-frequency amplification FET and the compensation FET described in Patent Document 1 having such a configuration are composed of a depletion-side FET.
  • FIG. 13 is a circuit diagram of a conventional high-frequency amplifier circuit.
  • the high frequency amplifier circuit 10P includes a field effect transistor 101 (FET 101) for high frequency amplification.
  • the FET 101 is an enhancement type.
  • the high frequency signal input terminal Pin is connected to the gate of the FET 101 through the input matching circuit 901.
  • Gate bias voltage setting circuit 110P is series-connected resistors 211P between the gate bias voltage application terminal P VG and the ground, and a 212P.
  • the connection point of the resistors 211P and 212P is connected to the gate of the FET 101 via the resistor 213P.
  • the gate bias voltage of the FET 101 is changed by changing the resistance ratio of the resistors 211P and 212P, and the drain current of the FET 101, that is, the output power of the high-frequency amplifier circuit 10P is adjusted.
  • Patent Document 1 uses a depletion type FET for each FET. Therefore, Patent Document 1 does not describe a method for suppressing variation in drain current due to manufacturing variations of a high-frequency amplification FET in a high-frequency amplification circuit with respect to a case where an enhancement type FET is used.
  • FIG. 14 is a characteristic diagram showing the relationship between the gate bias voltage and the drain current of a conventional high-frequency amplifier circuit.
  • FIG. 15 is a characteristic diagram showing the relationship between the fluctuation of the pinch-off voltage and the drain current when the gate bias voltage is fixed in the conventional high-frequency amplifier circuit.
  • the relationship between the gate bias voltage V GG and the drain current I DD is non-linear, and when the gate bias voltage V GG exceeds a predetermined value, the drain current I DD increases.
  • the gate bias voltage VGG in a region where the drain current IDD is nonlinear and changes rapidly must be used.
  • the amount of change in the drain current IDD according to the change in the gate bias voltage VGG is large, and it is difficult to stably obtain the target output power.
  • the variation of the drain current I DD in accordance with the fluctuation amount of the pinch-off voltage of the FET for high frequency amplification is also non-linear.
  • the drain current IDD increases rapidly even when the base bias voltage is the same as compared to when the pinch-off voltage is high.
  • An object of the present invention is to provide a high-frequency amplifier circuit that can obtain stable output power even if the gate bias voltage VGG and the pinch-off voltage of the high-frequency amplifier FET vary.
  • the present invention relates to a high-frequency amplifier circuit including a field-effect transistor for high-frequency amplification and a gate bias voltage setting circuit that determines the gate bias of the field-effect transistor, and has the following characteristics.
  • the field effect transistor for high frequency amplification is an enhancement type.
  • the gate bias voltage setting circuit includes a constant voltage circuit that outputs a predetermined voltage in a state where an input gate bias voltage VGG input from the outside is applied, and a voltage compensation circuit having a plurality of enhancement type field effect transistors for compensation.
  • the plurality of compensation field effect transistors include a first compensation field effect transistor to which a voltage input from a constant voltage circuit is applied, and a drain current between the drain and source due to an increase in drain current of the first compensation field effect transistor.
  • the second compensation field effect transistor has a second on-resistance that decreases on-resistance and increases on-resistance between the drain and source due to a decrease in drain current of the first compensation field-effect transistor.
  • the gate bias voltage of the field effect transistor for high frequency amplification is adjusted to The drain current of the field effect transistor is kept constant.
  • the gate bias voltage of the field effect transistor for high frequency amplification is adjusted and the drain of the field effect transistor for high frequency amplification is adjusted. The current is kept constant.
  • the high frequency amplifier circuit of the present invention may have the following configuration.
  • the second compensation field effect transistor is grounded at the source.
  • Two resistors are connected in series between the source of the first compensating field effect transistor and the drain of the second compensating field effect transistor.
  • the gate of the second compensation field effect transistor is connected to the connection point of the two resistors.
  • the drain of the second compensation field effect transistor is connected to the gate of the field effect transistor for high frequency amplification.
  • This configuration shows a specific circuit configuration example of the voltage compensation circuit.
  • the drain of the first compensation field effect transistor is connected to the same drive voltage application terminal as the drain of the field effect transistor for high frequency amplification.
  • the current that can be applied to the gate of the field effect transistor for high frequency amplification can be increased.
  • the resistor connected in series to the gate of the field effect transistor for high frequency amplification has a low resistance, a large current can be supplied to the gate. Therefore, the output characteristics of the high frequency amplifier circuit can be improved.
  • a high-impedance circuit having high impedance for a high-frequency signal is connected between the drain of the first compensation field-effect transistor and the drain of the field-effect transistor for high-frequency amplification. It is preferable that
  • the high impedance circuit of the high frequency amplifier circuit of the present invention may be a resistor.
  • the high impedance circuit of the high frequency amplifier circuit of the present invention may be a coil.
  • the high impedance circuit of the high frequency amplifier circuit of the present invention may be a parallel resonance circuit of a coil and a capacitor whose resonance frequency is the frequency of the high frequency signal.
  • the constant voltage circuit of the high frequency amplifier circuit of the present invention includes a plurality of enhancement type field effect transistors for constant voltage, and each of the plurality of constant voltage field effect transistors is diode-connected and cascade-connected. Preferably it is.
  • This configuration shows a specific configuration example of the constant voltage circuit.
  • the constant voltage circuit has the same fluctuation characteristics as the pinch-off voltage of the field effect transistor for high frequency amplification.
  • the voltage also changes. Therefore, it is possible to generate an appropriate and stable voltage corresponding to the pinch-off voltage of the field effect transistor for high frequency amplification.
  • the constant voltage circuit of the high-frequency amplifier circuit of the present invention may include a plurality of n-type bipolar transistors, and each of the plurality of n-type bipolar transistors may be diode-connected and cascade-connected.
  • This configuration shows a case where the constant voltage circuit is configured by a bipolar transistor. Even with such a bipolar transistor, a constant voltage circuit can be configured and a stable voltage can be output.
  • the drain current of the high frequency amplification FET can be stabilized. As a result, a high-frequency amplifier circuit with stable output power can be realized.
  • FIG. 1 is a circuit diagram of a high frequency amplifier circuit according to a first embodiment of the present invention. It is a characteristic diagram showing a first relationship between the input gate bias voltage V GG and the drain current I DD in the high frequency amplifying circuit of the embodiment of the present invention. It is a characteristic diagram showing the relationship between the variation amount [Delta] V p and the drain current I DD of the pinch-off voltage V p in the high frequency amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6 is a characteristic diagram showing the relationship between the variation of the bias voltage V GG , the fluctuation amount ⁇ V p of the pinch-off voltage V p , and the drain current I DD in the high frequency amplifier circuit of the first embodiment of the present invention.
  • FIG. 6 is a characteristic diagram showing a relationship between an input gate bias voltage V GG and a drain current I DD when a bias resistance is changed in the high frequency amplifier circuit of the present embodiment. It is a circuit diagram of the high frequency amplifier circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram of the high frequency amplifier circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram of the high frequency amplifier circuit which concerns on the 4th Embodiment of this invention.
  • FIG. 1 is a circuit diagram of a high-frequency amplifier circuit according to the first embodiment of the present invention.
  • the high-frequency amplifier circuit 10 includes a field-effect transistor 101 (hereinafter simply referred to as “FET 101”) for high-frequency amplification.
  • FET 101 is an enhancement type FET.
  • the FET 101 is grounded at the source, and obtains power from the drain.
  • the gate of the FET 101 is connected to the high frequency signal input terminal Pin through the input matching circuit 901.
  • the gate of the FET 101 is connected to the gate bias voltage application terminal PVG via the gate bias voltage setting circuit 110.
  • the drain of the FET 101 is connected to the drive voltage application terminal PVD via the choke coil 301 (inductance L1).
  • a connection point between the choke coil 301 and the drive voltage application terminal PVD is connected to the ground via a bypass capacitor 401 (capacitance C1).
  • connection point between the drain of the FET 101 and the choke coil 301 is connected to the high-frequency signal output terminal Pout via the output matching circuit 902.
  • the input gate bias voltage V GG applied from the gate bias voltage application terminal P VG is stabilized by the gate bias voltage setting circuit 110 according to the characteristics of the FET 101, Compensated by the amplifying gate bias voltage V GG1 and applied to the gate of the FET 101.
  • FET 101 is controlled to flow a drain current I DD to desired.
  • the high frequency signal S RF is applied to the gate of the FET 101.
  • RF signal S RF is amplified by the amplification factor corresponding to the drain current I DD by FET 101.
  • the amplified high frequency signal S RF is output from the high frequency signal output terminal Pout via the output matching circuit 902.
  • the gate bias voltage setting circuit 110 includes a constant voltage circuit 111 and a voltage compensation circuit 112.
  • a resistor 201 and a constant voltage circuit 111 are connected in series between the gate bias voltage application terminal PVG and the ground.
  • a connection point between the resistor 201 and the constant voltage circuit 111 is connected to the gate of the FET 101 via the voltage compensation circuit 112.
  • the constant voltage circuit 111 includes three field effect transistors (FETs) 104, 105, and 106.
  • the FETs 104, 105, and 106 are enhancement type FETs like the FET 101.
  • the FETs 104, 105, and 106 and the FET 101 are manufactured on the same semiconductor substrate, and are further formed at close positions on the semiconductor substrate.
  • FETs 104, 105, and 106 are connected in cascade between the resistor 201 and the ground. More specifically, the drain of the FET 104 is connected to the resistor 201, and the source of the FET 104 is connected to the drain of the FET 105. The source of the FET 105 is connected to the drain of the FET 106, and the source of the FET 106 is connected to the ground.
  • the drain and gate of the FET 104 are connected.
  • the drain and gate of the FET 105 are connected.
  • the drain and gate of the FET 106 are connected.
  • each FET 104, 105, 106 functions as a diode. Therefore, the three-stage cascade connection circuit of FETs 104, 105, and 106 is equivalent to a circuit in which three diodes are connected in series.
  • the constant voltage circuit 110 including the three-stage cascade circuit of the FETs 104, 105, and 106 becomes a circuit that can obtain a constant voltage obtained by adding the pinch-off voltages of the FETs 104, 105, and 106.
  • the voltage at the connection point between the resistor 201 and the constant voltage circuit 111 in other words, the input voltage of the voltage compensation circuit 112 (the voltage corresponding to V GG2 in FIG. 1) is the voltage by the constant voltage circuit. Become. As a result, even if the input gate bias voltage V GG varies, this variation can be suppressed to some extent, and a more stable voltage V GG2 can be obtained.
  • the FETs 104, 105, and 106 are formed on the same semiconductor substrate to have the same characteristics as the FET 101, so that the pinch-off voltage of the FET 101 and the pinch-off voltages of the FETs 104, 105, and 106 are Therefore, the voltage V GG2 corresponding to the fluctuation rate of the pinch-off voltage of the FET 101 can be obtained.
  • the voltage V GG2 is not always stable with high accuracy, and may vary due to variations in the input gate bias voltage V GG .
  • the voltage compensation circuit 112 shown below suppresses the influence of such variations on the amplification gate bias voltage V GG1 of the FET 101.
  • the voltage compensation circuit 112 includes FETs 102 and 103 and resistors 202, 203 and 204.
  • the FETs 102 and 103 are composed of enhancement type FETs like the FETs 101, 104, 105, and 106.
  • the FETs 102 and 103 and the FETs 101, 104, 105, and 106 are manufactured on the same semiconductor substrate, and are formed at positions adjacent to each other on the semiconductor substrate.
  • the FETs 101 to 106 have the same gate voltage-drain current characteristics.
  • the FET 102 corresponds to the first compensation field effect transistor of the present invention
  • the FET 103 corresponds to the second compensation field effect transistor of the present invention.
  • the gate of the FET 102 is connected to a connection point between the resistor 201 and the constant voltage circuit 111. Therefore, the gate bias voltage of the FET 102 is the voltage V GG2 described above.
  • the drain of the FET 102 is connected to the drive voltage application terminal PVD via the choke coil 301.
  • the source of the FET 102 is connected to the drain of the FET 103 through a series circuit of resistors 202 and 203.
  • the FET 103 is grounded at the source.
  • the gate of the FET 103 is connected to a connection point between the resistor 202 and the resistor 203.
  • the drain of the FET 103 is connected to the gate of the FET 101 via the resistor 204.
  • the voltage compensation circuit 112 having such a circuit configuration operates as follows.
  • the drain current IDS2 in accordance with the voltage V GG2 flows.
  • the drain current I DS2 flows through the resistors 202 and 203, and a voltage corresponding to the drain current I DS2 is generated in each of the resistors 202 and 203.
  • the drain current I DS2 of the FET 102 increases.
  • the current flowing through the resistors 202 and 203 increases, and the voltage across the resistors 202 and 203 increases.
  • V GG2 decreases, the reverse operation is performed and the amplification gate bias voltage V GG1 does not change.
  • the high frequency amplifier circuit of this embodiment is a characteristic diagram showing the relationship between the input gate bias voltage V GG and the drain current I DD when the there is no variation of the pinch-off voltage Vp.
  • a predetermined value 1.8 [V] in this example
  • the radio frequency amplifier circuit of the present embodiment is a characteristic diagram showing the relationship between the pinch-off voltage V p of the variation amount [Delta] V p and the drain current I DD when fixing the input gate bias voltage V GG. As shown in FIG. 3, even if the pinch-off voltage V p of the FET101 for high frequency amplification is changed, the drain current I DD is hardly changed.
  • the drain current I DD having a desired current value is not affected by variations in the input gate bias voltage V GG and the pinch-off voltage V p of the FET 101 for high frequency amplification. Can be output stably.
  • Figure 4 is a characteristic diagram showing the relationship between the bias voltage V GG variations and pinch-off voltage V p of the variation amount [Delta] V p and the drain current I DD of the radio frequency amplifier circuit of the present embodiment.
  • Each characteristic curve in FIG. 4 has a different pinch-off voltage.
  • drain by suppressing both the influence of the variation amount [Delta] V p of variation and the pinch-off voltage V p of the bias voltage V GG consists current value to the desired
  • the current I DD can be output stably.
  • the current for providing the amplification gate bias voltage V GG1 is the drain current I DS2 of the FET 102.
  • the power supply for supplying the drain current IDS2 is the drive power supply voltage V DD applied from the drive voltage application terminal PVD .
  • the drive power supply voltage V DD is a power supply for supplying a drain current, and can supply a larger amount of current than the input gate bias voltage VGG .
  • the high frequency amplifier circuit 10 when used as a power amplifier, it may be operated up to the saturation region of the FET, and the gate current of the FET 101 for high frequency amplification increases particularly rapidly in the saturation region.
  • a high-resistance series resistance is connected between the gate of the high-frequency amplification FET 101 and a terminal to which the gate bias voltage VGG is applied to the high-frequency amplification FET 101, a voltage is generated by the series resistance. A drop occurs, and the gate voltage of the FET 101 for high frequency amplification quickly becomes equal to or lower than the pinch-off voltage, and an increase in output power is suppressed.
  • the resistance connected in series with the gate in order to increase the output power, the resistance connected in series with the gate must be lowered.
  • the resistance when the resistance is lowered, the current flowing through the terminal to which the gate bias voltage VGG is applied increases. .
  • the terminal to which the gate bias voltage VGG is applied is a control power source for the FET, there are many cases where the supply current is limited, and a large current cannot be handled. Therefore, in the conventional configuration, the resistance connected in series with the gate cannot be reduced.
  • FIG. 5 is a diagram showing the characteristics of the gate voltage and output power of the FET 101 for high frequency amplification in the high frequency amplifier circuit of the present invention and the conventional high frequency amplifier circuit when the high frequency input power is changed.
  • the gate voltage of the FET 101 for high frequency amplification is less likely to be lower than that of the conventional configuration even if the power of the input high frequency signal is increased. That is, the effect that the value of the resistor connected in series with the gate is reduced is exhibited.
  • higher output power than the conventional configuration can be obtained.
  • FIG. 6 is a characteristic diagram showing the relationship between the input gate bias voltage V GG and the drain current I DD when the bias resistance is changed in the high frequency amplifier circuit of this embodiment.
  • V GG input gate bias voltage
  • I DD drain current I DD
  • FIG. 7 is a circuit diagram of a high-frequency amplifier circuit according to the second embodiment of the present invention.
  • the high-frequency amplifier circuit 10A of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111A, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
  • the constant voltage circuit 111A is a circuit in which FETs 104A, 105A, and 106A are cascaded in three stages. Each FET 104A, 105A, 106A has a drain and a source connected. With this configuration, each of the FETs 104A, 105A and 106A can be made to function as a so-called Schottky diode because the drain and the source are short-circuited.
  • the resistor 201 is connected to the input terminal (gate) of the FET 104A.
  • the output terminal (drain, source) of the FET 104A is connected to the input terminal (gate) of the FET 105A.
  • the output terminal (drain, source) of the FET 105A is connected to the input terminal (gate) of the FET 106A.
  • the output terminal (drain, source) of the FET A is connected to the ground.
  • FETs are cascade-connected, but the Schottky diode elements may be cascade-connected using a two-terminal Schottky diode element.
  • FIG. 8 is a circuit diagram of a high-frequency amplifier circuit according to the third embodiment of the present invention.
  • the high-frequency amplifier circuit 10B of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111B, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
  • the constant voltage circuit 111B is a circuit in which n-type bipolar transistors 104B, 105B, and 106B are cascade-connected in three stages. Specifically, the resistor 201 is connected to the collector of the bipolar transistor 104B. The collector of the bipolar transistor 105B is connected to the emitter of the bipolar transistor 104B. The collector of the bipolar transistor 106B is connected to the emitter of the bipolar transistor 105B. The emitter of the bipolar transistor 106B is connected to the ground. The collector and base of the bipolar transistor 104B are directly connected to each other. The collector and base of the bipolar transistor 105B are directly connected to each other. The collector and base of the bipolar transistor 106B are directly connected to each other.
  • FIG. 9 is a circuit diagram of a high-frequency amplifier circuit according to the fourth embodiment of the present invention.
  • the high-frequency amplifier circuit 10C of this embodiment is such that a resistor 501 is connected between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112, and the other configuration is the first embodiment. This is the same as the high-frequency amplifier circuit 10 according to FIG.
  • This resistor 501 corresponds to the high impedance circuit of the present invention.
  • FIG. 10 is a circuit diagram of a high-frequency amplifier circuit according to the fifth embodiment of the present invention.
  • the high-frequency amplifier circuit 10D of this embodiment has a coil 601 connected between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112, and the other configuration is the same as that of the first embodiment. This is the same as the high-frequency amplifier circuit 10.
  • the resistor 501 shown in the fourth embodiment is replaced with the coil 601.
  • This coil 601 corresponds to the high impedance circuit of the present invention.
  • FIG. 11 is a circuit diagram of a high-frequency amplifier circuit according to the sixth embodiment of the present invention.
  • the high-frequency amplifier circuit 10E of this embodiment is configured by connecting a parallel resonant circuit of a coil 601 and a capacitor 602 between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112. Is the same as the high-frequency amplifier circuit 10 according to the first embodiment.
  • the resistor 501 shown in the fourth embodiment or the coil 601 shown in the fifth embodiment is replaced with a parallel resonance circuit of the coil 601 and the capacitor 602.
  • the parallel resonant circuit of the coil 601 and the capacitor 602 corresponds to the high impedance circuit of the present invention.
  • the element values of the coil 601 and the capacitor 602 are determined so that the resonance frequency of the parallel resonance circuit of the coil 601 and the capacitor 602 matches the frequency of the high-frequency signal amplified by the high-frequency amplifier circuit 10E.
  • FIG. 12 is a circuit diagram of a high-frequency amplifier circuit according to the seventh embodiment of the present invention.
  • the high-frequency amplifier circuit 10F of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111F, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
  • the constant voltage circuit 111F includes four field effect transistors (FETs) 104, 105, 106, and 107.
  • the FETs 104, 105, 106, and 107 are enhancement type FETs.
  • FETs 104, 105, 106, and 107 are connected in cascade between the resistor 201 and the ground. More specifically, the drain of the FET 104 is connected to the resistor 201, and the source of the FET 104 is connected to the drain of the FET 105. The source of the FET 105 is connected to the drain of the FET 106, the source of the FET 106 is connected to the drain of the FET 107, and the source of the FET 107 is connected to the ground.
  • the drain and gate of the FET 104 are connected.
  • the drain and gate of the FET 105 are connected.
  • the drain and gate of the FET 106 are connected.
  • the drain and gate of the FET 107 are connected.
  • a constant voltage circuit composed of cascaded four-stage FETs can be realized.
  • the number of cascade-connected FETs for configuring the constant voltage circuit is not limited to three as shown in the first embodiment, and the number of stages may be set as appropriate according to use. . This is the same even when a bipolar transistor is used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

This high frequency amplifier circuit (10) is provided with an FET (101) for high frequency amplification, a constant voltage circuit (111), and a voltage compensation circuit (112). A resistor (201) and the constant voltage circuit (111) are series-connected between a gate bias voltage application terminal (PVG) and the ground. The voltage compensation circuit (112) is connected between the FET (101) and the connection point of the resistor (201) and the constant voltage circuit (111) The voltage compensation circuit (110) is provided with an FET (102) the gate of which is connected to the connection point of the resistor (201) and the constant voltage circuit (111), resistors (202, 203) series-connected between the ground and the source of the FET (102), and an FET (103). The gate of the FET (103) is connected to the connection point of the resistors (202, 203), and the drain of the FET (103) is connected to the gate of the FET (101) through a resistor (204).

Description

高周波増幅回路High frequency amplifier circuit
　本発明は、入力された高周波信号を増幅して出力する高周波増幅回路、特に、エンハンスメント型の電界効果トランジスタを増幅素子として用いる高周波増幅回路に関する。 The present invention relates to a high-frequency amplifier circuit that amplifies and outputs an input high-frequency signal, and more particularly, to a high-frequency amplifier circuit that uses an enhancement type field effect transistor as an amplifying element.
　従来、通信機器の送信回路には、通信に利用する高周波信号を増幅する高周波増幅回路が備えられている。基本的な高周波増幅回路の構成としては、例えば、特許文献１の従来技術の図６にも示されているように、高周波信号増幅用の電界効果トランジスタ（以下、「ＦＥＴ」と称する。）が備えられており、抵抗器を介して高周波増幅用ＦＥＴのゲートバイアス電圧が印加されている。 Conventionally, a transmission circuit of a communication device is provided with a high-frequency amplifier circuit that amplifies a high-frequency signal used for communication. As a basic configuration of the high-frequency amplifier circuit, for example, a field effect transistor (hereinafter referred to as “FET”) for amplifying a high-frequency signal is used as shown in FIG. The gate bias voltage of the high frequency amplification FET is applied through a resistor.
　この構成では、高周波増幅用ＦＥＴの製造バラツキによりドレイン電流がばらつくことが分かっており、特許文献１に記載の高周波増幅回路では、次の構成を備えている。 In this configuration, it is known that the drain current varies due to manufacturing variations of the high frequency amplification FET, and the high frequency amplification circuit described in Patent Document 1 has the following configuration.
　高周波増幅用ＦＥＴのゲートには、高周波増幅用ＦＥＴと同じ構造からなる補償用ＦＥＴを含むゲートバイアス回路が備えられている。ゲートバイアス回路は、ゲートバイアス（－ＶＧＧ）の印加端子とグランドとの間に、補償用ＦＥＴと二個の抵抗器とが縦続接続された構成からなる。具体的には、ゲートバイアス（－ＶＧＧ）の印加端子側から、抵抗器、補償用ＦＥＴ、抵抗器が接続される。各抵抗器は、補償用ＦＥＴのドレインとソースに接続される。補償用ＦＥＴのゲートには、ゲートバイアス（－ＶＧＧ）が直接印加される。 The gate of the high frequency amplification FET is provided with a gate bias circuit including a compensation FET having the same structure as the high frequency amplification FET. The gate bias circuit has a configuration in which a compensation FET and two resistors are cascaded between a gate bias (-VGG) application terminal and a ground. Specifically, a resistor, a compensation FET, and a resistor are connected from the gate bias (−VGG) application terminal side. Each resistor is connected to the drain and source of the compensation FET. A gate bias (−VGG) is directly applied to the gate of the compensation FET.
　このような構成の場合、高周波増幅用ＦＥＴのピンチオフ電圧が設計値からずれた場合、補償用ＦＥＴのピンチオフ電圧も同じように設計値からずれる。この補償用ＦＥＴのピンチオフ電圧のズレによって、ゲートバイアス回路の出力電圧（高周波増幅用ＦＥＴのゲートバイアス電圧）が、ピンチオフ電圧のズレを補償するように変化する。 In such a configuration, when the pinch-off voltage of the high frequency amplification FET deviates from the design value, the pinch off voltage of the compensation FET similarly deviates from the design value. Due to the deviation of the pinch-off voltage of the compensation FET, the output voltage of the gate bias circuit (the gate bias voltage of the high-frequency amplification FET) changes so as to compensate for the deviation of the pinch-off voltage.
　このような構成からなる特許文献１に記載の高周波増幅用ＦＥＴと補償用ＦＥＴは、デプレッション側のＦＥＴからなる。 The high-frequency amplification FET and the compensation FET described in Patent Document 1 having such a configuration are composed of a depletion-side FET.
　また、従来の高周波増幅回路として、図１３に示す高周波増幅回路がある。図１３は、従来の高周波増幅回路の回路図である。高周波増幅回路１０Ｐは、高周波増幅用の電界効果トランジスタ１０１（ＦＥＴ１０１）を備える。ＦＥＴ１０１は、エンハンスメント型からなる。ＦＥＴ１０１のゲートは、入力整合回路９０１を介して、高周波信号入力端子Ｐｉｎが接続されている。 Further, as a conventional high-frequency amplifier circuit, there is a high-frequency amplifier circuit shown in FIG. FIG. 13 is a circuit diagram of a conventional high-frequency amplifier circuit. The high frequency amplifier circuit 10P includes a field effect transistor 101 (FET 101) for high frequency amplification. The FET 101 is an enhancement type. The high frequency signal input terminal Pin is connected to the gate of the FET 101 through the input matching circuit 901.
　また、ＦＥＴ１０１のゲートは、ゲートバイアス電圧設定回路１１０Ｐを介して、ゲートバイアス電圧印加端子ＰＶＧに接続されている。ゲートバイアス電圧設定回路１１０Ｐは、ゲートバイアス電圧印加端子ＰＶＧとグランドとの間に直列接続された抵抗器２１１Ｐ，２１２Ｐを備える。抵抗器２１１Ｐ，２１２Ｐの接続点は、抵抗器２１３Ｐを介して、ＦＥＴ１０１のゲートに接続されている。 The gate of the FET101 with a gate bias voltage setting circuit 110P, which is connected to the gate bias voltage applying terminal P VG. Gate bias voltage setting circuit 110P is series-connected resistors 211P between the gate bias voltage application terminal P VG and the ground, and a 212P. The connection point of the resistors 211P and 212P is connected to the gate of the FET 101 via the resistor 213P.
　このような構成では、抵抗器２１１Ｐ，２１２Ｐの抵抗比を変化させることで、ＦＥＴ１０１のゲートバイアス電圧を変化させ、ＦＥＴ１０１のドレイン電流すなわち高周波増幅回路１０Ｐの出力電力を調整している。 In such a configuration, the gate bias voltage of the FET 101 is changed by changing the resistance ratio of the resistors 211P and 212P, and the drain current of the FET 101, that is, the output power of the high-frequency amplifier circuit 10P is adjusted.
特開２０００－１２４７４９号公報JP 2000-1224749 A
　しかしながら、特許文献１に記載の高周波増幅回路は、各ＦＥＴにデプレッション型ＦＥＴを用いている。したがって、特許文献１には、高周波増幅回路における高周波増幅用ＦＥＴの製造バラツキによるドレイン電流のばらつきを抑制する方法について、エンハンスメント型ＦＥＴを用いた場合に関しての記載が無い。 However, the high-frequency amplifier circuit described in Patent Document 1 uses a depletion type FET for each FET. Therefore, Patent Document 1 does not describe a method for suppressing variation in drain current due to manufacturing variations of a high-frequency amplification FET in a high-frequency amplification circuit with respect to a case where an enhancement type FET is used.
　また、特許文献１に記載の高周波増幅回路では、図１３に示した従来の高周波増幅回路１０Ｐと同様に、入力するゲートバイアス電圧を変化させなければ、ドレイン電流を制御することができない。 In the high-frequency amplifier circuit described in Patent Document 1, the drain current cannot be controlled unless the input gate bias voltage is changed, as in the conventional high-frequency amplifier circuit 10P shown in FIG.
　また、図１３に示した従来の高周波増幅回路１０Ｐでは、次に示す問題が生じる。図１４は従来の高周波増幅回路のゲートバイアス電圧とドレイン電流との関係を示す特性図である。図１５は従来の高周波増幅回路においてゲートバイアス電圧を固定した時のピンチオフ電圧の変動分とドレイン電流との関係を示す特性図である。 Further, the conventional high frequency amplifier circuit 10P shown in FIG. 13 has the following problems. FIG. 14 is a characteristic diagram showing the relationship between the gate bias voltage and the drain current of a conventional high-frequency amplifier circuit. FIG. 15 is a characteristic diagram showing the relationship between the fluctuation of the pinch-off voltage and the drain current when the gate bias voltage is fixed in the conventional high-frequency amplifier circuit.
　図１４に示すように、従来の高周波増幅回路１０Ｐでは、ゲートバイアス電圧ＶＧＧとドレイン電流ＩＤＤとの関係は非線形であり、ゲートバイアス電圧ＶＧＧが所定値以上になると、急激にドレイン電流ＩＤＤが増加する。 As shown in FIG. 14, in the conventional high-frequency amplifier circuit 10P, the relationship between the gate bias voltage V GG and the drain current I DD is non-linear, and when the gate bias voltage V GG exceeds a predetermined value, the drain current I DD increases.
　高周波増幅回路として高い出力電力を得ようとする場合、このドレイン電流ＩＤＤが非線形で急激に変化する領域のゲートバイアス電圧ＶＧＧを用いなければならない。しかしながら、この領域を用いた場合、ゲートバイアス電圧ＶＧＧの変化に応じたドレイン電流ＩＤＤの変化量が大きく、目標とした出力電力を安定して得ることが難しい。 When a high output power is to be obtained as a high-frequency amplifier circuit, the gate bias voltage VGG in a region where the drain current IDD is nonlinear and changes rapidly must be used. However, when this region is used, the amount of change in the drain current IDD according to the change in the gate bias voltage VGG is large, and it is difficult to stably obtain the target output power.
　また、図１５に示すように、高周波増幅用のＦＥＴのピンチオフ電圧の変動量に応じたドレイン電流ＩＤＤの変化量も非線形である。特に、所定のピンチオフ電圧が低くなった場合には、同じベースバイアス電圧であっても、ピンチオフ電圧が高い時と比較して、急激にドレイン電流ＩＤＤが増加する。 Further, as shown in FIG. 15, the variation of the drain current I DD in accordance with the fluctuation amount of the pinch-off voltage of the FET for high frequency amplification is also non-linear. In particular, when the predetermined pinch-off voltage is low, the drain current IDD increases rapidly even when the base bias voltage is the same as compared to when the pinch-off voltage is high.
　このように、ゲートバイアス電圧ＶＧＧが安定であっても、高周波増幅用のＦＥＴ１０１のピンチオフ電圧にバラツキが生じると、同様にドレイン電流が大幅に変化してしまう。 In this way, even if the gate bias voltage VGG is stable, if the pinch-off voltage of the FET 101 for high frequency amplification varies, the drain current will also change significantly.
　本発明の目的は、ゲートバイアス電圧ＶＧＧや高周波増幅用ＦＥＴのピンチオフオフ電圧にバラツキがあっても、安定した出力電力を得られる高周波増幅回路を提供することにある。 An object of the present invention is to provide a high-frequency amplifier circuit that can obtain stable output power even if the gate bias voltage VGG and the pinch-off voltage of the high-frequency amplifier FET vary.
　この発明は、高周波増幅用の電界効果トランジスタと、該電界効果トランジスタのゲートバイアスを決定するゲートバイアス電圧設定回路と、を備えた高周波増幅回路に関するものであり、次の特徴を有する。高周波増幅用の電界効果トランジスタはエンハンスメント型である。ゲートバイアス電圧設定回路は、外部入力される入力ゲートバイアス電圧ＶＧＧが印加された状態で所定電圧を出力する定電圧回路と、エンハンスメント型の複数の補償用電界効果トランジスタを有する電圧補償回路とを備える。複数の補償用電界効果トランジスタは、定電圧回路から入力される電圧が印加される第１の補償用電界効果トランジスタと、該第１の補償用電界効果トランジスタのドレイン電流の増加によりドレインソース間のオン抵抗が低下し、第１の補償用の電界効果トランジスタのドレイン電流の低下によりドレインソース間のオン抵抗が上昇する第２の補償用電界効果トランジスタを、有する。 The present invention relates to a high-frequency amplifier circuit including a field-effect transistor for high-frequency amplification and a gate bias voltage setting circuit that determines the gate bias of the field-effect transistor, and has the following characteristics. The field effect transistor for high frequency amplification is an enhancement type. The gate bias voltage setting circuit includes a constant voltage circuit that outputs a predetermined voltage in a state where an input gate bias voltage VGG input from the outside is applied, and a voltage compensation circuit having a plurality of enhancement type field effect transistors for compensation. Prepare. The plurality of compensation field effect transistors include a first compensation field effect transistor to which a voltage input from a constant voltage circuit is applied, and a drain current between the drain and source due to an increase in drain current of the first compensation field effect transistor. The second compensation field effect transistor has a second on-resistance that decreases on-resistance and increases on-resistance between the drain and source due to a decrease in drain current of the first compensation field-effect transistor.
　この構成では、ゲートバイアス電圧設定回路に入力される電圧が変動した場合に、ゲートバイアス電圧設定回路から出力される電圧、すなわち高周波増幅用の電界効果トランジスタのゲートバイアス電圧が調整され、高周波増幅用の電界効果トランジスタのドレイン電流は一定に保たれる。同様に、高周波増幅用の電界効果トランジスタのピンチオフ電圧が設計値からずれている場合であっても、高周波増幅用の電界効果トランジスタのゲートバイアス電圧が調整され、高周波増幅用の電界効果トランジスタのドレイン電流は一定に保たれる。 In this configuration, when the voltage input to the gate bias voltage setting circuit fluctuates, the voltage output from the gate bias voltage setting circuit, that is, the gate bias voltage of the field effect transistor for high frequency amplification is adjusted to The drain current of the field effect transistor is kept constant. Similarly, even when the pinch-off voltage of the field effect transistor for high frequency amplification is deviated from the design value, the gate bias voltage of the field effect transistor for high frequency amplification is adjusted and the drain of the field effect transistor for high frequency amplification is adjusted. The current is kept constant.
　また、この発明の高周波増幅回路は、次の構成であってもよい。第２の補償用電界効果トランジスタはソース接地されている。第１の補償用電界効果トランジスタのソースと第２の補償用電界効果トランジスタのドレインとの間には、二個の抵抗器が直列接続されている。第２の補償用電界効果トランジスタのゲートは、二個の抵抗器の接続点に接続されている。第２の補償用電界効果トランジスタのドレインは、高周波増幅用の電界効果トランジスタのゲートに接続されている。 The high frequency amplifier circuit of the present invention may have the following configuration. The second compensation field effect transistor is grounded at the source. Two resistors are connected in series between the source of the first compensating field effect transistor and the drain of the second compensating field effect transistor. The gate of the second compensation field effect transistor is connected to the connection point of the two resistors. The drain of the second compensation field effect transistor is connected to the gate of the field effect transistor for high frequency amplification.
　この構成では、電圧補償回路の具体的な回路構成例を示している。 This configuration shows a specific circuit configuration example of the voltage compensation circuit.
　また、この発明の高周波増幅回路では、第１の補償用電界効果トランジスタのドレインは、高周波増幅用の電界効果トランジスタのドレインと同じ駆動電圧印加端子に接続されていることが好ましい。 In the high frequency amplifier circuit of the present invention, it is preferable that the drain of the first compensation field effect transistor is connected to the same drive voltage application terminal as the drain of the field effect transistor for high frequency amplification.
　この構成では、高周波増幅用の電界効果トランジスタのゲートに印加可能な電流を大きくすることができる。これにより、高周波増幅用の電界効果トランジスタのゲートに直列接続する抵抗器を低抵抗にしても、ゲートに大きな電流を供給できる。したがって、高周波増幅回路の出力特性を向上させることができる。 In this configuration, the current that can be applied to the gate of the field effect transistor for high frequency amplification can be increased. Thereby, even if the resistor connected in series to the gate of the field effect transistor for high frequency amplification has a low resistance, a large current can be supplied to the gate. Therefore, the output characteristics of the high frequency amplifier circuit can be improved.
　また、この発明の高周波増幅回路では、第１の補償用電界効果トランジスタのドレインと、高周波増幅用の電界効果トランジスタのドレインとの間に、高周波信号に対して高インピーダンスとなる高インピーダンス回路が接続されていることが好ましい。 In the high-frequency amplifier circuit of the present invention, a high-impedance circuit having high impedance for a high-frequency signal is connected between the drain of the first compensation field-effect transistor and the drain of the field-effect transistor for high-frequency amplification. It is preferable that
　この構成では、高周波増幅用の電界効果トランジスタから出力される増幅後の高周波信号が、高周波増幅用の電界効果トランジスタのゲート電圧を供給する回路側に帰還することを抑制できる。これにより、高周波増幅回路の出力特性をさらに向上させることができる。 In this configuration, it is possible to prevent the amplified high-frequency signal output from the high-frequency amplification field effect transistor from returning to the circuit side that supplies the gate voltage of the high-frequency amplification field-effect transistor. As a result, the output characteristics of the high-frequency amplifier circuit can be further improved.
　また、この発明の高周波増幅回路の高インピーダンス回路は抵抗器であってもよい。 The high impedance circuit of the high frequency amplifier circuit of the present invention may be a resistor.
　また、この発明の高周波増幅回路の高インピーダンス回路はコイルであってもよい。 The high impedance circuit of the high frequency amplifier circuit of the present invention may be a coil.
　また、この発明の高周波増幅回路の高インピーダンス回路は、高周波信号の周波数を共振周波数とするコイルとコンデンサの並列共振回路であってもよい。 Further, the high impedance circuit of the high frequency amplifier circuit of the present invention may be a parallel resonance circuit of a coil and a capacitor whose resonance frequency is the frequency of the high frequency signal.
　これらの構成では、高インピーダンス回路の具体的な回路構成例を示している。 These configurations show specific circuit configuration examples of the high impedance circuit.
　また、この発明の高周波増幅回路の定電圧回路は、エンハンスメント型の複数の定電圧用電界効果トランジスタを備え、複数の定電圧用電界効果トランジスタは、それぞれがダイオード接続され、且つ、縦続接続されていることが好ましい。 The constant voltage circuit of the high frequency amplifier circuit of the present invention includes a plurality of enhancement type field effect transistors for constant voltage, and each of the plurality of constant voltage field effect transistors is diode-connected and cascade-connected. Preferably it is.
　この構成では、定電圧回路の具体的な構成例を示している。このように、高周波増幅用の電界効果トランジスタと同じ特性の電界効果トランジスタのみで定電圧回路を構成することで、高周波増幅用の電界効果トランジスタのピンチオフ電圧と同じような変動特性で定電圧回路の電圧も変化する。したがって、高周波増幅用の電界効果トランジスタのピンチオフ電圧に応じた適切で安定な電圧を発生することができる。 This configuration shows a specific configuration example of the constant voltage circuit. In this way, by configuring a constant voltage circuit only with a field effect transistor having the same characteristics as the field effect transistor for high frequency amplification, the constant voltage circuit has the same fluctuation characteristics as the pinch-off voltage of the field effect transistor for high frequency amplification. The voltage also changes. Therefore, it is possible to generate an appropriate and stable voltage corresponding to the pinch-off voltage of the field effect transistor for high frequency amplification.
　また、この発明の高周波増幅回路の定電圧回路は、複数のｎ型のバイポーラトランジスタを備え、複数のｎ型のバイポーラトランジスタは、それぞれがダイオード接続され、且つ、縦続接続されていてもよい。 The constant voltage circuit of the high-frequency amplifier circuit of the present invention may include a plurality of n-type bipolar transistors, and each of the plurality of n-type bipolar transistors may be diode-connected and cascade-connected.
　この構成では、定電圧回路をバイポーラトランジスタで構成する場合を示している。このようなバイポーラトランジスタであっても、定電圧回路を構成することができ、安定した電圧を出力することができる。 This configuration shows a case where the constant voltage circuit is configured by a bipolar transistor. Even with such a bipolar transistor, a constant voltage circuit can be configured and a stable voltage can be output.
　この発明によれば、ゲートバイアス電圧ＶＧＧや高周波増幅用のＦＥＴのピンチオフオフ電圧にバラツキがあっても、高周波増幅用のＦＥＴのドレイン電流を安定させることができる。これにより、安定した出力電力の高周波増幅回路を実現することができる。 According to the present invention, even if the gate bias voltage VGG and the pinch-off voltage of the high frequency amplification FET vary, the drain current of the high frequency amplification FET can be stabilized. As a result, a high-frequency amplifier circuit with stable output power can be realized.
本発明の第１の実施形態に係る高周波増幅回路の回路図である。1 is a circuit diagram of a high frequency amplifier circuit according to a first embodiment of the present invention. 本発明の第１の実施形態の高周波増幅回路における入力ゲートバイアス電圧ＶＧＧとドレイン電流ＩＤＤとの関係を示す特性図である。It is a characteristic diagram showing a first relationship between the input gate bias voltage V GG and the drain current I DD in the high frequency amplifying circuit of the embodiment of the present invention. 本発明の第１の実施形態の高周波増幅回路におけるピンチオフ電圧Ｖｐの変動量ΔＶｐとドレイン電流ＩＤＤとの関係を示す特性図である。It is a characteristic diagram showing the relationship between the variation amount [Delta] V p and the drain current I DD of the pinch-off voltage V p in the high frequency amplifier circuit according to the first embodiment of the present invention. 本発明の第１の実施形態の高周波増幅回路におけるバイアス電圧ＶＧＧのバラツキとピンチオフ電圧Ｖｐの変動量ΔＶｐとドレイン電流ＩＤＤとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing the relationship between the variation of the bias voltage V GG , the fluctuation amount ΔV p of the pinch-off voltage V p , and the drain current I DD in the high frequency amplifier circuit of the first embodiment of the present invention. 入力電力を変化させた場合における本発明の高周波増幅回路と従来の高周波増幅回路における高周波増幅用のＦＥＴ１０１のゲート電圧と出力電力との特性を示す図である。It is a figure which shows the characteristic of the gate voltage and output power of FET101 for high frequency amplification in the high frequency amplifier circuit of this invention and the conventional high frequency amplifier circuit when input power is changed. 本実施形態の高周波増幅回路におけるバイアス抵抗を変化させた場合の入力ゲートバイアス電圧ＶＧＧとドレイン電流ＩＤＤとの関係を示す特性図である。FIG. 6 is a characteristic diagram showing a relationship between an input gate bias voltage V GG and a drain current I DD when a bias resistance is changed in the high frequency amplifier circuit of the present embodiment. 本発明の第２の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 5th Embodiment of this invention. 本発明の第６の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 6th Embodiment of this invention. 本発明の第７の実施形態に係る高周波増幅回路の回路図である。It is a circuit diagram of the high frequency amplifier circuit which concerns on the 7th Embodiment of this invention. 従来の高周波増幅回路の回路図である。It is a circuit diagram of the conventional high frequency amplifier circuit. 従来の高周波増幅回路のゲートバイアス電圧とドレイン電流との関係を示す特性図である。It is a characteristic view which shows the relationship between the gate bias voltage and drain current of the conventional high frequency amplifier circuit. 従来の高周波増幅回路のピンチオフ電圧の変動分とドレイン電流との関係を示す特性図である。It is a characteristic view which shows the relationship between the fluctuation part of the pinch-off voltage of the conventional high frequency amplifier circuit, and drain current.
　本発明の第１の実施形態に係る高周波増幅回路について、図を参照して説明する。図１は、本発明の第１の実施形態に係る高周波増幅回路の回路図である。 A high-frequency amplifier circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a high-frequency amplifier circuit according to the first embodiment of the present invention.
　高周波増幅回路１０は、高周波増幅用の電界効果トランジスタ１０１（以下、単に「ＦＥＴ１０１」と称する。）を備える。ＦＥＴ１０１は、エンハンスメント型のＦＥＴである。ＦＥＴ１０１はソース接地されており、ドレインから電力を得る。 The high-frequency amplifier circuit 10 includes a field-effect transistor 101 (hereinafter simply referred to as “FET 101”) for high-frequency amplification. The FET 101 is an enhancement type FET. The FET 101 is grounded at the source, and obtains power from the drain.
　ＦＥＴ１０１のゲートは、入力整合回路９０１を介して、高周波信号入力端子Ｐｉｎに接続されている。ＦＥＴ１０１のゲートは、ゲートバイアス電圧設定回路１１０を介して、ゲートバイアス電圧印加端子ＰＶＧに接続されている。 The gate of the FET 101 is connected to the high frequency signal input terminal Pin through the input matching circuit 901. The gate of the FET 101 is connected to the gate bias voltage application terminal PVG via the gate bias voltage setting circuit 110.
　ＦＥＴ１０１のドレインは、チョークコイル３０１（インダクタンスＬ１）を介して、駆動電圧印加端子ＰＶＤに接続されている。チョークコイル３０１と駆動電圧印加端子ＰＶＤとの接続点は、バイパスコンデンサ４０１（キャパシタンスＣ１）を介して、グランドに接続されている。 The drain of the FET 101 is connected to the drive voltage application terminal PVD via the choke coil 301 (inductance L1). A connection point between the choke coil 301 and the drive voltage application terminal PVD is connected to the ground via a bypass capacitor 401 (capacitance C1).
　ＦＥＴ１０１のドレインとチョークコイル３０１の接続点は、出力整合回路９０２を介して、高周波信号出力端子Ｐｏｕｔに接続されている。 The connection point between the drain of the FET 101 and the choke coil 301 is connected to the high-frequency signal output terminal Pout via the output matching circuit 902.
　このような回路構成からなる高周波信号増幅回路１０は、ゲートバイアス電圧印加端子ＰＶＧから印加された入力ゲートバイアス電圧ＶＧＧがゲートバイアス電圧設定回路１１０で、ＦＥＴ１０１の特性に応じて安定化され、増幅用ゲートバイアス電圧ＶＧＧ１に補償されてＦＥＴ１０１のゲートに印加される。これにより、ＦＥＴ１０１は、所望とするドレイン電流ＩＤＤが流れるように制御される。 In the high-frequency signal amplifier circuit 10 having such a circuit configuration, the input gate bias voltage V GG applied from the gate bias voltage application terminal P VG is stabilized by the gate bias voltage setting circuit 110 according to the characteristics of the FET 101, Compensated by the amplifying gate bias voltage V GG1 and applied to the gate of the FET 101. Thus, FET 101 is controlled to flow a drain current I DD to desired.
　このようなＦＥＴ１０１に対して、高周波信号入力端子Ｐｉｎから高周波信号ＳＲＦを印加すると、高周波信号ＳＲＦは、入力整合回路９０１を介して、ＦＥＴ１０１のゲートに印加される。 For such FET 101, by applying a high-frequency signal S RF from the RF signal input terminal Pin, the high frequency signal S RF, via the input matching circuit 901, it is applied to the gate of the FET 101.
　高周波信号ＳＲＦは、ＦＥＴ１０１によってドレイン電流ＩＤＤに応じた増幅率で増幅される。増幅された高周波信号ＳＲＦは、出力整合回路９０２を介して高周波信号出力端子Ｐｏｕｔから出力される。 RF signal S RF is amplified by the amplification factor corresponding to the drain current I DD by FET 101. The amplified high frequency signal S RF is output from the high frequency signal output terminal Pout via the output matching circuit 902.
　次に、ゲートバイアス電圧設定回路１１０の具体的な構成について説明する。ゲートバイアス電圧設定回路１１０は、定電圧回路１１１、電圧補償回路１１２を備える。ゲートバイアス電圧印加端子ＰＶＧとグランドとの間には、抵抗器２０１と定電圧回路１１１とが直列接続されている。抵抗器２０１と定電圧回路１１１との接続点は、電圧補償回路１１２を介して、ＦＥＴ１０１のゲートに接続されている。 Next, a specific configuration of the gate bias voltage setting circuit 110 will be described. The gate bias voltage setting circuit 110 includes a constant voltage circuit 111 and a voltage compensation circuit 112. A resistor 201 and a constant voltage circuit 111 are connected in series between the gate bias voltage application terminal PVG and the ground. A connection point between the resistor 201 and the constant voltage circuit 111 is connected to the gate of the FET 101 via the voltage compensation circuit 112.
　定電圧回路１１１は、三個の電界効果トランジスタ（ＦＥＴ）１０４，１０５，１０６からなる。ＦＥＴ１０４，１０５，１０６は、ＦＥＴ１０１と同じくエンハンスメント型のＦＥＴで構成されている。例えば、ＦＥＴ１０４，１０５，１０６とＦＥＴ１０１は、同じ半導体基板上に製造されたものであり、さらには、当該半導体基板上の近接する位置に形成されている。 The constant voltage circuit 111 includes three field effect transistors (FETs) 104, 105, and 106. The FETs 104, 105, and 106 are enhancement type FETs like the FET 101. For example, the FETs 104, 105, and 106 and the FET 101 are manufactured on the same semiconductor substrate, and are further formed at close positions on the semiconductor substrate.
　ＦＥＴ１０４，１０５，１０６は、抵抗器２０１とグランドとの間に、縦続接続されている。より具体的には、ＦＥＴ１０４のドレインは抵抗器２０１に接続されており、ＦＥＴ１０４のソースはＦＥＴ１０５のドレインに接続されている。ＦＥＴ１０５のソースはＦＥＴ１０６のドレインに接続されており、ＦＥＴ１０６のソースはグランドに接続されている。 FETs 104, 105, and 106 are connected in cascade between the resistor 201 and the ground. More specifically, the drain of the FET 104 is connected to the resistor 201, and the source of the FET 104 is connected to the drain of the FET 105. The source of the FET 105 is connected to the drain of the FET 106, and the source of the FET 106 is connected to the ground.
　ＦＥＴ１０４のドレインとゲートは接続されている。ＦＥＴ１０５のドレインとゲートは接続されている。ＦＥＴ１０６のドレインとゲートは接続されている。この構成により、それぞれのＦＥＴ１０４，１０５，１０６はダイオードとして機能する。したがって、ＦＥＴ１０４，１０５，１０６の三段縦続接続回路は、ダイオードが三個直列接続された回路と等価になる。 The drain and gate of the FET 104 are connected. The drain and gate of the FET 105 are connected. The drain and gate of the FET 106 are connected. With this configuration, each FET 104, 105, 106 functions as a diode. Therefore, the three-stage cascade connection circuit of FETs 104, 105, and 106 is equivalent to a circuit in which three diodes are connected in series.
　これにより、ＦＥＴ１０４，１０５，１０６の三段縦続接続回路からなる定電圧回路１１０は、ＦＥＴ１０４，１０５，１０６のピンチオフ電圧を加算した定電圧が得られる回路となる。 Thereby, the constant voltage circuit 110 including the three-stage cascade circuit of the FETs 104, 105, and 106 becomes a circuit that can obtain a constant voltage obtained by adding the pinch-off voltages of the FETs 104, 105, and 106.
　このような回路構成から、抵抗器２０１と定電圧回路１１１との接続点の電圧、言い換えれば電圧補償回路１１２の入力電圧（図１のＶＧＧ２に相当する電圧）は、定電圧回路による電圧となる。これにより、入力ゲートバイアス電圧ＶＧＧにバラツキがあっても、このバラツキをある程度抑制して、より安定した電圧ＶＧＧ２を得ることができる。特に、本実施形態に示すように、ＦＥＴ１０４，１０５，１０６を同じ半導体基板上に形成するなどＦＥＴ１０１と同じ特性のものとすることで、ＦＥＴ１０１のピンチオフ電圧と、ＦＥＴ１０４，１０５，１０６のピンチオフ電圧とが同じ変動率となるので、ＦＥＴ１０１のピンチオフ電圧の変動率に応じた電圧ＶＧＧ２を得ることができる。 From such a circuit configuration, the voltage at the connection point between the resistor 201 and the constant voltage circuit 111, in other words, the input voltage of the voltage compensation circuit 112 (the voltage corresponding to V GG2 in FIG. 1) is the voltage by the constant voltage circuit. Become. As a result, even if the input gate bias voltage V GG varies, this variation can be suppressed to some extent, and a more stable voltage V GG2 can be obtained. In particular, as shown in the present embodiment, the FETs 104, 105, and 106 are formed on the same semiconductor substrate to have the same characteristics as the FET 101, so that the pinch-off voltage of the FET 101 and the pinch-off voltages of the FETs 104, 105, and 106 are Therefore, the voltage V GG2 corresponding to the fluctuation rate of the pinch-off voltage of the FET 101 can be obtained.
　ただし、この電圧ＶＧＧ２も高精度に安定であるとは限らず、入力ゲートバイアス電圧ＶＧＧのバラツキにより、バラツキを有することがある。このようなバラツキが、ＦＥＴ１０１の増幅用ゲートバイアス電圧ＶＧＧ１に与える影響を、次に示す電圧補償回路１１２によって抑制している。 However, the voltage V GG2 is not always stable with high accuracy, and may vary due to variations in the input gate bias voltage V GG . The voltage compensation circuit 112 shown below suppresses the influence of such variations on the amplification gate bias voltage V GG1 of the FET 101.
　電圧補償回路１１２は、ＦＥＴ１０２，１０３、抵抗器２０２，２０３，２０４を備える。 The voltage compensation circuit 112 includes FETs 102 and 103 and resistors 202, 203 and 204.
　ＦＥＴ１０２，１０３は、ＦＥＴ１０１，１０４，１０５，１０６と同じくエンハンスメント型のＦＥＴで構成されている。例えば、ＦＥＴ１０２，１０３とＦＥＴ１０１，１０４，１０５，１０６は、同じ半導体基板上に製造されたものであり、さらには、当該半導体基板上の近接する位置に形成されている。このように、全てのＦＥＴ１０１～１０６を同じエンハンスメント型にすることのより、ＦＥＴ１０１～１０６は、ゲート電圧－ドレイン電流特性が同じになる。ＦＥＴ１０２は本発明の第１の補償用電界効果トランジスタに相当し、ＦＥＴ１０３は本発明の第２の補償用電界効果トランジスタに相当する。 The FETs 102 and 103 are composed of enhancement type FETs like the FETs 101, 104, 105, and 106. For example, the FETs 102 and 103 and the FETs 101, 104, 105, and 106 are manufactured on the same semiconductor substrate, and are formed at positions adjacent to each other on the semiconductor substrate. Thus, by making all the FETs 101 to 106 the same enhancement type, the FETs 101 to 106 have the same gate voltage-drain current characteristics. The FET 102 corresponds to the first compensation field effect transistor of the present invention, and the FET 103 corresponds to the second compensation field effect transistor of the present invention.
　ＦＥＴ１０２のゲートは、抵抗器２０１と定電圧回路１１１との接続点に接続されている。したがって、ＦＥＴ１０２のゲートバイアス電圧は、上述の電圧ＶＧＧ２となる。ＦＥＴ１０２のドレインは、チョークコイル３０１を介して駆動電圧印加端子ＰＶＤに接続されている。 The gate of the FET 102 is connected to a connection point between the resistor 201 and the constant voltage circuit 111. Therefore, the gate bias voltage of the FET 102 is the voltage V GG2 described above. The drain of the FET 102 is connected to the drive voltage application terminal PVD via the choke coil 301.
　ＦＥＴ１０２のソースは、抵抗器２０２，２０３の直列回路を介して、ＦＥＴ１０３のドレインに接続されている。ＦＥＴ１０３はソース接地されている。ＦＥＴ１０３のゲートは、抵抗器２０２と抵抗器２０３との接続点に接続されている。ＦＥＴ１０３のドレインは、抵抗器２０４を介してＦＥＴ１０１のゲートに接続されている。 The source of the FET 102 is connected to the drain of the FET 103 through a series circuit of resistors 202 and 203. The FET 103 is grounded at the source. The gate of the FET 103 is connected to a connection point between the resistor 202 and the resistor 203. The drain of the FET 103 is connected to the gate of the FET 101 via the resistor 204.
　このような回路構成からなる電圧補償回路１１２は、次に示すように動作する。ＦＥＴ１０２に電圧ＶＧＧ２が印加されると、当該電圧ＶＧＧ２に応じたドレイン電流ＩＤＳ２が流れる。ドレイン電流ＩＤＳ２は抵抗器２０２，２０３に流れ、抵抗器２０２と抵抗器２０３とでそれぞれにドレイン電流ＩＤＳ２に応じた電圧が発生する。 The voltage compensation circuit 112 having such a circuit configuration operates as follows. When the voltage V GG2 is applied to FET 102, the drain current IDS2 in accordance with the voltage V GG2 flows. The drain current I DS2 flows through the resistors 202 and 203, and a voltage corresponding to the drain current I DS2 is generated in each of the resistors 202 and 203.
　抵抗器２０２と抵抗器２０３との接続点は、ＦＥＴ１０３のゲートに接続されているので、ドレイン電流ＩＤＳＤ２が流れると、抵抗器２０２と抵抗器２０３とによる分圧比に応じた電圧ＶＧＧ３がＦＥＴ１０３のゲートに印加される。ＦＥＴ１０３に電圧ＶＧＧ３が印加されると、ＦＥＴ１０３のオン抵抗に応じたドレインソース間電圧が生じる。これが電圧補償回路の出力電圧に相当する電圧ＶＧＧ４となる。この電圧ＶＧＧ４は、抵抗器２０４を介してＦＥＴ１０１のゲートに印加され、ＦＥＴ１０１のゲートには増幅用ゲートバイアス電圧ＶＧＧ１が印加される。 Since the connection point between the resistor 202 and the resistor 203 is connected to the gate of the FET 103 , when the drain current I DSD2 flows, the voltage V GG3 corresponding to the voltage division ratio between the resistor 202 and the resistor 203 is changed to the FET 103. Applied to the gate. When the voltage V GG3 is applied to the FET 103, a drain-source voltage corresponding to the on-resistance of the FET 103 is generated. This is a voltage V GG4 corresponding to the output voltage of the voltage compensation circuit. This voltage V GG4 is applied to the gate of the FET 101 via the resistor 204, and the amplifying gate bias voltage V GG1 is applied to the gate of the FET 101.
　このような構成では、ＦＥＴ１０２のゲート電圧ＶＧＧ２が変動した場合に、各電圧は次に示すように変化する。 In such a configuration, when the gate voltage V GG2 of FET102 is changed, changes as the voltage is below.
　例えば、ＶＧＧ２が上昇した場合、ＦＥＴ１０２のドレイン電流ＩＤＳ２は増加する。ドレイン電流ＩＤＳ２が増加すると、抵抗器２０２，２０３に流れる電流が増加し、抵抗器２０２，２０３の両端電圧が増加する。 For example, when V GG2 increases, the drain current I DS2 of the FET 102 increases. When the drain current IDS2 increases, the current flowing through the resistors 202 and 203 increases, and the voltage across the resistors 202 and 203 increases.
　抵抗器２０３の両端電圧が増加すると、ＦＥＴ１０３のゲート電圧ＶＧＧ３が上昇し、ＦＥＴ１０３のオン抵抗が低下する。ＦＥＴ１０３のドレインソース間電圧が上昇することが抑制される。この際、ＦＥＴ１０２，１０３が同じ特性を有するので、電圧ＶＧＧ２による電圧変動は結果的に打ち消され、電圧ＶＧＧ４は上昇しない。したがって、増幅用ゲートバイアス電圧ＶＧＧ１も変化しない。 When the voltage across the resistor 203 increases, the gate voltage V GG3 of the FET 103 increases and the on-resistance of the FET 103 decreases. An increase in the drain-source voltage of the FET 103 is suppressed. At this time, since FET102,103 have the same characteristics, the voltage variation due to voltage V GG2 is consequently canceled, the voltage V GG4 does not increase. Therefore, the amplification gate bias voltage V GG1 does not change.
　なお、ＶＧＧ２が低下した場合は、この逆の動作となり、増幅用ゲートバイアス電圧ＶＧＧ１は変化しない。 Note that when V GG2 decreases, the reverse operation is performed and the amplification gate bias voltage V GG1 does not change.
　このように本実施形態の構成を用いることで、入力ゲートバイアス電圧ＶＧＧのバラツキがあっても、高周波増幅用のＦＥＴ１０１のドレイン電流ＩＤＤを、所望の値で安定して出力することができる。 Thus, by using the configuration of this embodiment, even if there are variations in input gate bias voltage V GG, the drain current I DD of FET101 for high frequency amplification, it is possible to stably output a desired value .
　また、ピンチオフ電圧が異なるロットの高周波増幅回路の場合であっても、ＦＥＴ１０１～１０６が同じ特性を有するので、入力ゲートバイアス電圧ＶＧＧが変動する場合と同様に、高周波増幅用のＦＥＴ１０１のドレイン電流ＩＤＤの変動を抑制する作用効果を得ることができる。 Even in the case of a high frequency amplifier circuit of a lot with different pinch-off voltages, since the FETs 101 to 106 have the same characteristics, the drain current of the FET 101 for high frequency amplification is the same as when the input gate bias voltage V GG fluctuates. it is possible to obtain the effect of inhibiting the effect of variations in I DD.
　次に、本実施形態の構成を用いたことによる効果を、図２から図６を用いて説明する。 Next, effects obtained by using the configuration of the present embodiment will be described with reference to FIGS.
　図２は、本実施形態の高周波増幅回路において、ピンチオフ電圧Ｖｐの変動がないとした時の入力ゲートバイアス電圧ＶＧＧとドレイン電流ＩＤＤとの関係を示す特性図である。図２に示すように、入力ゲートバイアス電圧ＶＧＧが所定値（本例では１．８［Ｖ］）以上であれば、入力ゲートバイアス電圧ＶＧＧが変化しても、ドレイン電流ＩＤＤは殆ど変化しない。 2, the high frequency amplifier circuit of this embodiment is a characteristic diagram showing the relationship between the input gate bias voltage V GG and the drain current I DD when the there is no variation of the pinch-off voltage Vp. As shown in FIG. 2, if the input gate bias voltage V GG is equal to or higher than a predetermined value (1.8 [V] in this example), even if the input gate bias voltage V GG is changed, the drain current I DD is hardly changed. It does not change.
　図３は、本実施形態の高周波増幅回路において、入力ゲートバイアス電圧ＶＧＧを固定した時のピンチオフ電圧Ｖｐの変動量ΔＶｐとドレイン電流ＩＤＤとの関係を示す特性図である。図３に示すように、高周波増幅用のＦＥＴ１０１のピンチオフ電圧Ｖｐが変化しても、ドレイン電流ＩＤＤは殆ど変化しない。 3, the radio frequency amplifier circuit of the present embodiment, is a characteristic diagram showing the relationship between the pinch-off voltage V p of the variation amount [Delta] V p and the drain current I DD when fixing the input gate bias voltage V GG. As shown in FIG. 3, even if the pinch-off voltage V p of the FET101 for high frequency amplification is changed, the drain current I DD is hardly changed.
　このように本実施形態の構成を用いることで、入力ゲートバイアス電圧ＶＧＧや高周波増幅用のＦＥＴ１０１のピンチオフ電圧Ｖｐのバラツキに影響されることなく、所望とする電流値からなるドレイン電流ＩＤＤを安定して出力することができる。 As described above, by using the configuration of the present embodiment, the drain current I DD having a desired current value is not affected by variations in the input gate bias voltage V GG and the pinch-off voltage V p of the FET 101 for high frequency amplification. Can be output stably.
　図４は、本実施形態の高周波増幅回路におけるバイアス電圧ＶＧＧのバラツキとピンチオフ電圧Ｖｐの変動量ΔＶｐとドレイン電流ＩＤＤとの関係を示す特性図である。図４における各特性曲線は、それぞれピンチオフ電圧が異なる。図４に示すように、本実施形態の構成を用いることで、バイアス電圧ＶＧＧのバラツキとピンチオフ電圧Ｖｐの変動量ΔＶｐの双方の影響を抑圧して、所望とする電流値からなるドレイン電流ＩＤＤを安定して出力することができる。 Figure 4 is a characteristic diagram showing the relationship between the bias voltage V GG variations and pinch-off voltage V p of the variation amount [Delta] V p and the drain current I DD of the radio frequency amplifier circuit of the present embodiment. Each characteristic curve in FIG. 4 has a different pinch-off voltage. As shown in FIG. 4, by using the configuration of this embodiment, drain by suppressing both the influence of the variation amount [Delta] V p of variation and the pinch-off voltage V p of the bias voltage V GG, consists current value to the desired The current I DD can be output stably.
　さらに、本実施形態の構成では、次に示すような効果が得られる。 Furthermore, the configuration of the present embodiment provides the following effects.
　本実施形態の構成では、図１に示すように、増幅用ゲートバイアス電圧ＶＧＧ１を与えるための電流が、ＦＥＴ１０２のドレイン電流ＩＤＳ２である。そして、当該ドレイン電流ＩＤＳ２を供給するための電源は、駆動電圧印加端子ＰＶＤから印加される駆動電源電圧ＶＤＤである。一般に、駆動電源電圧ＶＤＤは、ドレイン電流を供給するための電源であり、入力ゲートバイアス電圧ＶＧＧよりも電流供給量を多くすることができる。 In the configuration of the present embodiment, as shown in FIG. 1, the current for providing the amplification gate bias voltage V GG1 is the drain current I DS2 of the FET 102. The power supply for supplying the drain current IDS2 is the drive power supply voltage V DD applied from the drive voltage application terminal PVD . In general, the drive power supply voltage V DD is a power supply for supplying a drain current, and can supply a larger amount of current than the input gate bias voltage VGG .
　ここで、高周波増幅回路１０をパワーアンプとして利用する場合、ＦＥＴの飽和領域まで動作させることがあり、飽和領域では特に高周波増幅用のＦＥＴ１０１のゲート電流が急激に増加する。この際、高周波増幅用のＦＥＴ１０１のゲートと、当該高周波増幅用のＦＥＴ１０１にゲートバイアス電圧ＶＧＧを印加する端子との間に、高抵抗の直列抵抗が接続されていると、当該直列抵抗により電圧降下が生じて、高周波増幅用のＦＥＴ１０１のゲート電圧がより早くピンチオフ電圧以下になってしまい、出力電力の増加が抑制される。ここで、出力電力を増加させるためには、ゲートに直列接続される抵抗を低くしなければならないが、抵抗を低くした場合、ゲートバイアス電圧ＶＧＧを印加する端子に流れる電流が増加してしまう。しかし、ゲートバイアス電圧ＶＧＧを印加する端子は、ＦＥＴの制御電源であるので、供給電流に制限がある場合が多く、大電流に対応できない。したがって、従来の構成では、ゲートに直列接続される抵抗を低くすることができなかった。 Here, when the high frequency amplifier circuit 10 is used as a power amplifier, it may be operated up to the saturation region of the FET, and the gate current of the FET 101 for high frequency amplification increases particularly rapidly in the saturation region. At this time, if a high-resistance series resistance is connected between the gate of the high-frequency amplification FET 101 and a terminal to which the gate bias voltage VGG is applied to the high-frequency amplification FET 101, a voltage is generated by the series resistance. A drop occurs, and the gate voltage of the FET 101 for high frequency amplification quickly becomes equal to or lower than the pinch-off voltage, and an increase in output power is suppressed. Here, in order to increase the output power, the resistance connected in series with the gate must be lowered. However, when the resistance is lowered, the current flowing through the terminal to which the gate bias voltage VGG is applied increases. . However, since the terminal to which the gate bias voltage VGG is applied is a control power source for the FET, there are many cases where the supply current is limited, and a large current cannot be handled. Therefore, in the conventional configuration, the resistance connected in series with the gate cannot be reduced.
　しかしながら、本実施形態の構成では、ＦＥＴ１０２を介して、高周波増幅用のＦＥＴ１０１のゲートに対して電流を多く供給できることで、ゲートに直列接続される抵抗（抵抗器２０２，２０３，２０４に相当）を低抵抗化することができる。これにより、高周波増幅回路の出力電力を向上させることができる。 However, in the configuration of this embodiment, since a large amount of current can be supplied to the gate of the FET 101 for high frequency amplification via the FET 102, a resistance (corresponding to the resistors 202, 203, and 204) connected in series to the gate is reduced. The resistance can be reduced. Thereby, the output power of the high frequency amplifier circuit can be improved.
　図５は、高周波入力電力を変化させた場合における本発明の高周波増幅回路と従来の高周波増幅回路における高周波増幅用のＦＥＴ１０１のゲート電圧と出力電力との特性を示す図である。図５に示すように、本実施形態の構成を用いることで、入力される高周波信号の電力を増加させても、高周波増幅用のＦＥＴ１０１のゲート電圧は、従来構成よりも低下しにくい。すなわち、ゲートに直列に接続される抵抗の値が小さくなっている効果が発揮されていることになる。さらに、本実施形態の構成を用いることで、従来構成よりも高い出力電力を得ることができる。 FIG. 5 is a diagram showing the characteristics of the gate voltage and output power of the FET 101 for high frequency amplification in the high frequency amplifier circuit of the present invention and the conventional high frequency amplifier circuit when the high frequency input power is changed. As shown in FIG. 5, by using the configuration of this embodiment, the gate voltage of the FET 101 for high frequency amplification is less likely to be lower than that of the conventional configuration even if the power of the input high frequency signal is increased. That is, the effect that the value of the resistor connected in series with the gate is reduced is exhibited. Furthermore, by using the configuration of the present embodiment, higher output power than the conventional configuration can be obtained.
　また、次に示す効果を得ることもできる。図６は、本実施形態の高周波増幅回路におけるバイアス抵抗を変化させた場合の入力ゲートバイアス電圧ＶＧＧとドレイン電流ＩＤＤとの関係を示す特性図である。図６に示すように、バイアス抵抗（抵抗器２０２，２０３）を変化させることにより、ドレイン電流ＩＤＤの電流値を変化させることができる。この際、いずれのバイアス抵抗値を採用しても、ＶＧＧの変動による影響を抑制することができるので、高周波増幅回路におけるドレイン電流ＩＤＤの調整が容易になる。 The following effects can also be obtained. FIG. 6 is a characteristic diagram showing the relationship between the input gate bias voltage V GG and the drain current I DD when the bias resistance is changed in the high frequency amplifier circuit of this embodiment. As shown in FIG. 6, by changing the bias resistor (resistors 202 and 203), it is possible to change the current value of the drain current I DD. At this time, regardless of which bias resistance value is employed, the influence of fluctuations in VGG can be suppressed, so that the drain current IDD in the high-frequency amplifier circuit can be easily adjusted.
　次に、本発明の第２の実施形態に係る高周波増幅回路について、図を参照して説明する。図７は、本発明の第２の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ａは、定電圧回路１１１Ａの構成が第１の実施形態に係る高周波増幅回路１０と異なるものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。したがって、異なる箇所のみを以下に説明する。 Next, a high frequency amplifier circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram of a high-frequency amplifier circuit according to the second embodiment of the present invention. The high-frequency amplifier circuit 10A of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111A, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
　定電圧回路１１１Ａは、ＦＥＴ１０４Ａ，１０５Ａ，１０６Ａが三段縦続接続された回路である。各ＦＥＴ１０４Ａ，１０５Ａ，１０６Ａはドレインとソースが接続されている。この構成により、各ＦＥＴ１０４Ａ，１０５Ａ，１０６Ａはドレインとソースが短絡されるので、所謂ショットキーダイオードとして機能させることができる。抵抗器２０１には、ＦＥＴ１０４Ａの入力端（ゲート）が接続されている。ＦＥＴ１０４Ａの出力端（ドレイン、ソース）はＦＥＴ１０５Ａの入力端（ゲート）に接続されている。ＦＥＴ１０５Ａの出力端（ドレイン、ソース）はＦＥＴ１０６Ａの入力端（ゲート）に接続されている。ＦＥＴＡの出力端（ドレイン、ソース）はグランドに接続されている。なお、本実施形態では、ＦＥＴを縦続接続する例を示したが、二端子のショットキーダイオード素子を用いて、当該ショットキーダイオード素子を縦続接続してもよい。 The constant voltage circuit 111A is a circuit in which FETs 104A, 105A, and 106A are cascaded in three stages. Each FET 104A, 105A, 106A has a drain and a source connected. With this configuration, each of the FETs 104A, 105A and 106A can be made to function as a so-called Schottky diode because the drain and the source are short-circuited. The resistor 201 is connected to the input terminal (gate) of the FET 104A. The output terminal (drain, source) of the FET 104A is connected to the input terminal (gate) of the FET 105A. The output terminal (drain, source) of the FET 105A is connected to the input terminal (gate) of the FET 106A. The output terminal (drain, source) of the FET A is connected to the ground. In the present embodiment, an example is shown in which FETs are cascade-connected, but the Schottky diode elements may be cascade-connected using a two-terminal Schottky diode element.
　このような構成であっても、第１の実施形態と同様に定電圧回路として機能し、第１の実施形態に係る高周波増幅回路１０と同じ作用効果を得ることができる。 Even with such a configuration, it functions as a constant voltage circuit as in the first embodiment, and can obtain the same effects as the high-frequency amplifier circuit 10 according to the first embodiment.
　次に、本発明の第３の実施形態に係る高周波増幅回路について、図を参照して説明する。図８は、本発明の第３の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ｂは、定電圧回路１１１Ｂの構成が第１の実施形態に係る高周波増幅回路１０と異なるものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。したがって、異なる箇所のみを以下に説明する。 Next, a high frequency amplifier circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram of a high-frequency amplifier circuit according to the third embodiment of the present invention. The high-frequency amplifier circuit 10B of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111B, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
　定電圧回路１１１Ｂは、ｎ型のバイポーラトランジスタ１０４Ｂ，１０５Ｂ，１０６Ｂが三段縦続接続された回路である。具体的には、抵抗器２０１には、バイポーラトランジスタ１０４Ｂのコレクタが接続されている。バイポーラトランジスタ１０４Ｂのエミッタはバイポーラトランジスタ１０５Ｂのコレクタが接続されている。バイポーラトランジスタ１０５Ｂのエミッタはバイポーラトランジスタ１０６Ｂのコレクタが接続されている。バイポーラトランジスタ１０６Ｂのエミッタはグランドに接続されている。バイポーラトランジスタ１０４Ｂのコレクタとベースは互いに直接接続されている。バイポーラトランジスタ１０５Ｂのコレクタとベースは互いに直接接続されている。バイポーラトランジスタ１０６Ｂのコレクタとベースは互いに直接接続されている。 The constant voltage circuit 111B is a circuit in which n-type bipolar transistors 104B, 105B, and 106B are cascade-connected in three stages. Specifically, the resistor 201 is connected to the collector of the bipolar transistor 104B. The collector of the bipolar transistor 105B is connected to the emitter of the bipolar transistor 104B. The collector of the bipolar transistor 106B is connected to the emitter of the bipolar transistor 105B. The emitter of the bipolar transistor 106B is connected to the ground. The collector and base of the bipolar transistor 104B are directly connected to each other. The collector and base of the bipolar transistor 105B are directly connected to each other. The collector and base of the bipolar transistor 106B are directly connected to each other.
　このような構成であっても、第１の実施形態と同様に定電圧回路として機能し、第１の実施形態に係る高周波増幅回路１０と同じ作用効果を得ることができる。 Even with such a configuration, it functions as a constant voltage circuit as in the first embodiment, and can obtain the same effects as the high-frequency amplifier circuit 10 according to the first embodiment.
　次に、本発明の第４の実施形態に係る高周波増幅回路について、図を参照して説明する。図９は、本発明の第４の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ｃは、高周波増幅用のＦＥＴ１０１のドレインと電圧補償回路１１２のＦＥＴ１０２のドレインとの間に抵抗器５０１が接続されたものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。この抵抗器５０１が本発明の高インピーダンス回路に相当する。 Next, a high frequency amplifier circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a circuit diagram of a high-frequency amplifier circuit according to the fourth embodiment of the present invention. The high-frequency amplifier circuit 10C of this embodiment is such that a resistor 501 is connected between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112, and the other configuration is the first embodiment. This is the same as the high-frequency amplifier circuit 10 according to FIG. This resistor 501 corresponds to the high impedance circuit of the present invention.
　このような構成とすることで、高周波増幅用のＦＥＴ１０１から出力される高周波信号が、抵抗器５０１で減衰されて、電圧補償回路１１２のＦＥＴ１０２のドレインに帰還することを抑制できる。これにより、増幅用ゲートバイアス電圧ＶＧＧ１を、より安定化することができる。 With such a configuration, it is possible to suppress a high frequency signal output from the FET 101 for high frequency amplification from being attenuated by the resistor 501 and fed back to the drain of the FET 102 of the voltage compensation circuit 112. As a result, the amplification gate bias voltage V GG1 can be further stabilized.
　次に、本発明の第５の実施形態に係る高周波増幅回路について、図を参照して説明する。図１０は、本発明の第５の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ｄは、高周波増幅用のＦＥＴ１０１のドレインと電圧補償回路１１２のＦＥＴ１０２のドレインとの間にコイル６０１が接続されたものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。言い換えれば、第４の実施形態に示した抵抗器５０１がコイル６０１に置き換わったものである。このコイル６０１が本発明の高インピーダンス回路に相当する。 Next, a high frequency amplifier circuit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a circuit diagram of a high-frequency amplifier circuit according to the fifth embodiment of the present invention. The high-frequency amplifier circuit 10D of this embodiment has a coil 601 connected between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112, and the other configuration is the same as that of the first embodiment. This is the same as the high-frequency amplifier circuit 10. In other words, the resistor 501 shown in the fourth embodiment is replaced with the coil 601. This coil 601 corresponds to the high impedance circuit of the present invention.
　このような構成とすることで、高周波増幅用のＦＥＴ１０１から出力される高周波信号が、コイル６０１で減衰されて、電圧補償回路１１２のＦＥＴ１０２のドレインに帰還することを抑制できる。これにより、増幅用ゲートバイアス電圧ＶＧＧ１を、より安定化することができる。 With such a configuration, it is possible to suppress the high-frequency signal output from the FET 101 for high-frequency amplification from being attenuated by the coil 601 and fed back to the drain of the FET 102 of the voltage compensation circuit 112. As a result, the amplification gate bias voltage V GG1 can be further stabilized.
　次に、本発明の第６の実施形態に係る高周波増幅回路について、図を参照して説明する。図１１は、本発明の第６の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ｅは、高周波増幅用のＦＥＴ１０１のドレインと電圧補償回路１１２のＦＥＴ１０２のドレインとの間にコイル６０１とコンデンサ６０２の並列共振回路が接続されたものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。言い換えれば、第４の実施形態に示した抵抗器５０１または第５の実施形態に示したコイル６０１がコイル６０１とコンデンサ６０２の並列共振回路に置き換わったものである。このコイル６０１とコンデンサ６０２との並列共振回路が本発明の高インピーダンス回路に相当する。 Next, a high frequency amplifier circuit according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a circuit diagram of a high-frequency amplifier circuit according to the sixth embodiment of the present invention. The high-frequency amplifier circuit 10E of this embodiment is configured by connecting a parallel resonant circuit of a coil 601 and a capacitor 602 between the drain of the FET 101 for high-frequency amplification and the drain of the FET 102 of the voltage compensation circuit 112. Is the same as the high-frequency amplifier circuit 10 according to the first embodiment. In other words, the resistor 501 shown in the fourth embodiment or the coil 601 shown in the fifth embodiment is replaced with a parallel resonance circuit of the coil 601 and the capacitor 602. The parallel resonant circuit of the coil 601 and the capacitor 602 corresponds to the high impedance circuit of the present invention.
　この際、コイル６０１とコンデンサ６０２との並列共振回路の共振周波数が、当該高周波増幅回路１０Ｅで増幅する高周波信号の周波数に一致するように、コイル６０１とコンデンサ６０２の素子値を決定する。 At this time, the element values of the coil 601 and the capacitor 602 are determined so that the resonance frequency of the parallel resonance circuit of the coil 601 and the capacitor 602 matches the frequency of the high-frequency signal amplified by the high-frequency amplifier circuit 10E.
　このような構成とすることで、高周波増幅用のＦＥＴ１０１から出力される高周波信号が、コイル６０１とコンデンサ６０２の並列共振回路で減衰されて、電圧補償回路１１２のＦＥＴ１０２のドレインに帰還することを抑制できる。これにより、増幅用ゲートバイアス電圧ＶＧＧ１を、より安定化することができる。 By adopting such a configuration, it is possible to suppress a high frequency signal output from the FET 101 for high frequency amplification from being attenuated by the parallel resonance circuit of the coil 601 and the capacitor 602 and fed back to the drain of the FET 102 of the voltage compensation circuit 112. it can. As a result, the amplification gate bias voltage V GG1 can be further stabilized.
　次に、本発明の第７の実施形態に係る高周波増幅回路について、図を参照して説明する。図１２は、本発明の第７の実施形態に係る高周波増幅回路の回路図である。本実施形態の高周波増幅回路１０Ｆは、定電圧回路１１１Ｆの構成が第１の実施形態に係る高周波増幅回路１０と異なるものであり、他の構成は第１の実施形態に係る高周波増幅回路１０と同じである。したがって、異なる箇所のみを以下に説明する。 Next, a high frequency amplifier circuit according to a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a circuit diagram of a high-frequency amplifier circuit according to the seventh embodiment of the present invention. The high-frequency amplifier circuit 10F of the present embodiment is different from the high-frequency amplifier circuit 10 according to the first embodiment in the configuration of the constant voltage circuit 111F, and other configurations are the same as those of the high-frequency amplifier circuit 10 according to the first embodiment. The same. Therefore, only different parts will be described below.
　定電圧回路１１１Ｆは、四個の電界効果トランジスタ（ＦＥＴ）１０４，１０５，１０６，１０７からなる。ＦＥＴ１０４，１０５，１０６，１０７は、エンハンスメント型のＦＥＴである。 The constant voltage circuit 111F includes four field effect transistors (FETs) 104, 105, 106, and 107. The FETs 104, 105, 106, and 107 are enhancement type FETs.
　ＦＥＴ１０４，１０５，１０６，１０７は、抵抗器２０１とグランドとの間に、縦続接続されている。より具体的には、ＦＥＴ１０４のドレインは抵抗器２０１に接続されており、ＦＥＴ１０４のソースはＦＥＴ１０５のドレインに接続されている。ＦＥＴ１０５のソースはＦＥＴ１０６のドレインに接続されており、ＦＥＴ１０６のソースはＦＥＴ１０７のドレインに接続されており、ＦＥＴ１０７のソースはグランドに接続されている。 FETs 104, 105, 106, and 107 are connected in cascade between the resistor 201 and the ground. More specifically, the drain of the FET 104 is connected to the resistor 201, and the source of the FET 104 is connected to the drain of the FET 105. The source of the FET 105 is connected to the drain of the FET 106, the source of the FET 106 is connected to the drain of the FET 107, and the source of the FET 107 is connected to the ground.
　ＦＥＴ１０４のドレインとゲートは接続されている。ＦＥＴ１０５のドレインとゲートは接続されている。ＦＥＴ１０６のドレインとゲートは接続されている。ＦＥＴ１０７のドレインとゲートは接続されている。 The drain and gate of the FET 104 are connected. The drain and gate of the FET 105 are connected. The drain and gate of the FET 106 are connected. The drain and gate of the FET 107 are connected.
　このような構成により、四段のＦＥＴの縦続接続からなる定電圧回路を実現できる。このように、定電圧回路を構成するために縦続接続するＦＥＴ数は、第１の実施形態に示すように三段であることに限るものではなく、使用に応じて段数は適宜設定すればよい。これは、バイポーラトランジスタを用いる場合でも同じである。 With such a configuration, a constant voltage circuit composed of cascaded four-stage FETs can be realized. As described above, the number of cascade-connected FETs for configuring the constant voltage circuit is not limited to three as shown in the first embodiment, and the number of stages may be set as appropriate according to use. . This is the same even when a bipolar transistor is used.
　なお、上述の各実施形態を組み合わせた回路構成であっても、第１の実施形態に係る高周波増幅回路１０と同じ作用効果を得ることができる。 In addition, even if it is a circuit structure which combined each above-mentioned embodiment, the same effect as the high frequency amplifier circuit 10 which concerns on 1st Embodiment can be acquired.
１０，１０Ａ，１０Ｂ，１０Ｃ，１０Ｄ，１０Ｅ，１０Ｆ，１０Ｐ：高周波増幅回路、
１０１：高周波増幅用のＦＥＴ、
１０２，１０３，１０４，１０５，１０６，１０４Ａ，１０５Ａ，１０６Ａ：ＦＥＴ、
１０４Ｂ，１０５Ｂ，１０６Ｂ：バイポーラトランジスタ、
２０１，２０２，２０３，２０４，２１１Ｐ，２１２Ｐ，２１３Ｐ，５０１：抵抗器、
３０１：チョークコイル、
４０１：バイパスコンデンサ、
６０１：コイル、
６０２：コンデンサ、
１１０，１１０Ｐ：ゲートバイアス電圧設定回路、
１１１，１１１Ａ，１１１Ｂ：定電圧回路、
１１２：電圧補償回路、
９０１：入力整合回路、
９０２：出力整合回路、
Ｐｉｎ：高周波信号入力端子、
Ｐｏｕｔ：高周波信号出力端子、
ＰＶＧ：ゲートバイアス電圧印加端子、
ＰＶＤ：駆動電圧印加端子 10, 10A, 10B, 10C, 10D, 10E, 10F, 10P: high frequency amplifier circuit,
101: FET for high frequency amplification,
102, 103, 104, 105, 106, 104A, 105A, 106A: FET,
104B, 105B, 106B: bipolar transistors,
201, 202, 203, 204, 211P, 212P, 213P, 501: resistors,
301: Choke coil,
401: Bypass capacitor,
601: coil,
602: Capacitor,
110, 110P: gate bias voltage setting circuit,
111, 111A, 111B: constant voltage circuit,
112: Voltage compensation circuit,
901: input matching circuit,
902: output matching circuit,
Pin: high frequency signal input terminal,
Pout: high frequency signal output terminal,
P VG : gate bias voltage application terminal,
P VD : Driving voltage application terminal

Claims (9)

  1. 　高周波増幅用の電界効果トランジスタと、該電界効果トランジスタのゲートバイアスを決定するゲートバイアス電圧設定回路と、を備えた高周波増幅回路であって、
    　前記高周波増幅用の電界効果トランジスタはエンハンスメント型であり、
    　前記ゲートバイアス電圧設定回路は、
    　外部入力される入力ゲートバイアス電圧ＶＧＧが印加された状態で、所定電圧を出力する定電圧回路と、
    　エンハンスメント型の複数の補償用電界効果トランジスタを有する電圧補償回路とを備え、
    　該複数の補償用電界効果トランジスタは、
    　前記定電圧回路から入力される電圧が印加される第１の補償用電界効果トランジスタと、
    　該第１の補償用電界効果トランジスタのドレイン電流の増加によりドレインソース間のオン抵抗が低下し、前記第１の補償用の電界効果トランジスタのドレイン電流の低下によりドレインソース間のオン抵抗が上昇する第２の補償用電界効果トランジスタを、有する、高周波増幅回路。     A high-frequency amplifier circuit comprising: a field-effect transistor for high-frequency amplification; and a gate bias voltage setting circuit that determines a gate bias of the field-effect transistor,
    The field effect transistor for high frequency amplification is an enhancement type,
    The gate bias voltage setting circuit includes:
    A constant voltage circuit that outputs a predetermined voltage in a state in which an input gate bias voltage VGG input from the outside is applied;
    A voltage compensation circuit having a plurality of enhancement-type field effect transistors for compensation,
    The plurality of compensating field effect transistors are:
    A first compensation field effect transistor to which a voltage input from the constant voltage circuit is applied;
    The on-resistance between the drain and the source decreases due to the increase in the drain current of the first compensation field effect transistor, and the on-resistance between the drain and source increases due to the decrease in the drain current of the first compensation field effect transistor. A high-frequency amplifier circuit having a second compensation field effect transistor.
  2. 　前記第２の補償用電界効果トランジスタはソース接地されており、
    　前記第１の補償用電界効果トランジスタのソースと前記第２の補償用電界効果トランジスタのドレインとの間には、二個の抵抗器が直列接続されており、
    　前記第２の補償用電界効果トランジスタのゲートは、前記二個の抵抗器の接続点に接続されており、
    　前記第２の補償用電界効果トランジスタのドレインが、前記高周波増幅用の電界効果トランジスタのゲートに接続されている、
    　請求項１に記載の高周波増幅回路。     The second compensation field effect transistor is grounded at the source,
    Two resistors are connected in series between the source of the first compensation field effect transistor and the drain of the second compensation field effect transistor,
    A gate of the second compensation field effect transistor is connected to a connection point of the two resistors;
    The drain of the second compensation field effect transistor is connected to the gate of the field effect transistor for high frequency amplification,
    The high frequency amplifier circuit according to claim 1.
  3. 　前記第１の補償用電界効果トランジスタのドレインは、前記高周波増幅用の電界効果トランジスタのドレインと同じ駆動電圧印加端子に接続されている、
    　請求項２に記載の高周波増幅回路。     The drain of the first compensation field effect transistor is connected to the same drive voltage application terminal as the drain of the field effect transistor for high frequency amplification,
    The high frequency amplifier circuit according to claim 2.
  4. 　前記前記第１の補償用電界効果トランジスタのドレインと、前記高周波増幅用の電界効果トランジスタのドレインとの間に、前記高周波信号に対して高インピーダンスとなる高インピーダンス回路が接続されている、
    　請求項３に記載の高周波増幅回路。     A high impedance circuit having a high impedance with respect to the high frequency signal is connected between a drain of the first compensation field effect transistor and a drain of the field effect transistor for high frequency amplification.
    The high frequency amplifier circuit according to claim 3.
  5. 　前記高インピーダンス回路は抵抗器である、請求項４に記載の高周波増幅回路。 The high-frequency amplifier circuit according to claim 4, wherein the high-impedance circuit is a resistor.
  6. 　前記高インピーダンス回路はコイルである、請求項４に記載の高周波増幅回路。 The high-frequency amplifier circuit according to claim 4, wherein the high-impedance circuit is a coil.
  7. 　前記高インピーダンス回路は、前記高周波信号の周波数を共振周波数とするコイルとコンデンサの並列共振回路である、請求項４に記載の高周波増幅回路。 The high-frequency amplifier circuit according to claim 4, wherein the high-impedance circuit is a parallel resonance circuit of a coil and a capacitor having a resonance frequency as a frequency of the high-frequency signal.
  8. 　前記定電圧回路は、エンハンスメント型の複数の定電圧用電界効果トランジスタを備え、
    　前記複数の定電圧用電界効果トランジスタは、それぞれがダイオード接続され、且つ、縦続接続されている、請求項１乃至請求項７のいずれかに記載の高周波増幅回路。     The constant voltage circuit includes a plurality of enhancement-type field effect transistors for constant voltage,
    The high-frequency amplifier circuit according to claim 1, wherein each of the plurality of constant voltage field effect transistors is diode-connected and cascade-connected.
  9. 　前記定電圧回路は、複数のｎ型のバイポーラトランジスタを備え、
    　前記複数のｎ型のバイポーラトランジスタは、それぞれがダイオード接続され、且つ、縦続接続されている、請求項１乃至請求項７のいずれかに記載の高周波増幅回路。     The constant voltage circuit includes a plurality of n-type bipolar transistors,
    The high-frequency amplifier circuit according to claim 1, wherein each of the plurality of n-type bipolar transistors is diode-connected and cascade-connected.
PCT/JP2013/070842 2012-11-21 2013-08-01 High frequency amplifier circuit WO2014080668A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012254840 2012-11-21
JP2012-254840 2012-11-21

Publications (1)

Publication Number Publication Date
WO2014080668A1 true WO2014080668A1 (en) 2014-05-30

Family

ID=50775860

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/070842 WO2014080668A1 (en) 2012-11-21 2013-08-01 High frequency amplifier circuit

Country Status (1)

Country Link
WO (1) WO2014080668A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3059492A1 (en) * 2016-11-29 2018-06-01 Stmicroelectronics (Grenoble 2) Sas METHOD AND APPARATUS FOR AUTOPOLARIZED AND SELF - RIGGED COMMON MODE AMPLIFICATION
JPWO2021186694A1 (en) * 2020-03-19 2021-09-23

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552611A (en) * 1978-10-11 1980-04-17 Nec Corp Constant-current circuit
JPH0284761A (en) * 1988-09-21 1990-03-26 Nec Corp Reference voltage generating circuit
JP2006339837A (en) * 2005-05-31 2006-12-14 Alps Electric Co Ltd Circuit integration high frequency amplifier
JP2007037149A (en) * 2005-07-27 2007-02-08 Infineon Technologies Ag Amplifier circuit and method for amplifying signal to be amplified
JP4616463B2 (en) * 2000-12-04 2011-01-19 アロカ株式会社 Radiation detector

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552611A (en) * 1978-10-11 1980-04-17 Nec Corp Constant-current circuit
JPH0284761A (en) * 1988-09-21 1990-03-26 Nec Corp Reference voltage generating circuit
JP4616463B2 (en) * 2000-12-04 2011-01-19 アロカ株式会社 Radiation detector
JP2006339837A (en) * 2005-05-31 2006-12-14 Alps Electric Co Ltd Circuit integration high frequency amplifier
JP2007037149A (en) * 2005-07-27 2007-02-08 Infineon Technologies Ag Amplifier circuit and method for amplifying signal to be amplified

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3059492A1 (en) * 2016-11-29 2018-06-01 Stmicroelectronics (Grenoble 2) Sas METHOD AND APPARATUS FOR AUTOPOLARIZED AND SELF - RIGGED COMMON MODE AMPLIFICATION
US10063189B2 (en) 2016-11-29 2018-08-28 Stmicroelectronics (Grenoble 2) Sas Method and device for self-biased and self-regulated common-mode amplification
JPWO2021186694A1 (en) * 2020-03-19 2021-09-23
WO2021186694A1 (en) * 2020-03-19 2021-09-23 三菱電機株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
US7420423B2 (en) Active balun device
US9203368B2 (en) Power amplifier
EP3335313B1 (en) Multi-stage amplifier with cascode stage and dc bias regulator
WO2022174645A1 (en) Amplitude modulation-phase modulation compensation circuit, radio frequency power amplifier and device
US9287830B2 (en) Stacked bias I-V regulation
US10673400B2 (en) Gain stabilization for supply modulated RF and microwave integrated circuits
KR102178526B1 (en) Power amplifier
US9722546B2 (en) Bias circuit for low quiescent current amplifier
US20190050008A1 (en) Voltage regulator
TWI633410B (en) Current mirror device and related amplifier circuit
CN110690861A (en) Multi-stage power amplifier with linear compensation function
KR20160113350A (en) Power amplifier
WO2014080668A1 (en) High frequency amplifier circuit
US10171039B2 (en) Devices and methods that facilitate power amplifier off state performance
US20050237114A1 (en) MMIC distributed amplifier gate control using active bias
US7688145B2 (en) Variable gain amplifying device
EP3334039B1 (en) Source follower
JP5684697B2 (en) Clipping circuit, differential amplifier circuit and amplifier circuit
US20160036396A1 (en) Power Amplifier, and Method of the Same
US20210367559A1 (en) Power amplifier circuit
JP5308407B2 (en) Amplifier circuit
KR102530677B1 (en) Stacked power amplifier with parallel varactor
KR100985795B1 (en) Bias circuit for compensating variation of threshold voltage and temperature and supply voltage and amplifier using that
US20240283408A1 (en) Amplification circuit, power amplification circuit, and bias generation circuit
US20230318537A1 (en) Power amplifier system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13857057

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13857057

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP