WO2014073050A1

WO2014073050A1 - Information processing device and information processing method

Info

Publication number: WO2014073050A1
Application number: PCT/JP2012/078830
Authority: WO
Inventors: 山田　隆; 憲一郎竹田
Original assignee: 富士通株式会社
Priority date: 2012-11-07
Filing date: 2012-11-07
Publication date: 2014-05-15

Abstract

An information processing device according to the present embodiment has: a network interface circuit which segments data into a plurality of packets and transmits the same, or combines a received plurality of packets into data; and a processing device which executes a driver for the network interface circuit. In addition, the network interface circuit has: a first processing unit which replicates headers of packets; and a second processing unit which outputs the headers replicated by the first processing unit to the driver. The driver which is executed by the processing device has a third processing unit which generates packets corresponding to the first-mentioned packets, using the headers received from the second processing unit and data acquired by combining the plurality of the packets with the network interface circuit or data prior to being segmented into the plurality of the packets by the network interface circuit.

Description

Information processing apparatus and information processing method

Related to communication data analysis technology.

If a communication trouble occurs, capture the data transferred on the communication line and analyze the header included in the captured data to identify the cause of the trouble.

The following technologies are known as capture technologies. Specifically, there is a technique for receiving a packet from a communication network and collecting header information included in the packet. In this technique, a communication board writes a packet to a storage area in a buffer by DMA (Dynamic Memory Access) transfer for the purpose of reducing CPU (Central Processing Unit) load.

Also, there is a technology in which a router having a function of collecting statistical information identifies packet flows and collects statistical information (for example, communication data amount) for each flow.

Also, there is a technology in which a terminal captures communication data on a network and detects an error (for example, cable disconnection or packet loss) that occurs during capturing.

By the way, if a problem occurs in a network using a high-speed communication line (hereinafter referred to as a high-speed communication line) with a communication speed of 10 Gbps or higher, for example, a dedicated LAN (Local Area Network) analyzer has been installed. To analyze. However, since it is not easy to install such an analyzer on a network, it may take time to capture data and start analysis, and it may not be possible to quickly deal with troubles.

JP 2003-87255 A JP 2006-5402 A JP 2009-27297 A

Accordingly, in one aspect, an object of the present invention is to provide a technique for enabling data transferred on a high-speed communication line to be captured.

An information processing apparatus according to the present invention includes: a network interface circuit that divides data into a plurality of packets and transmits the data; or a network interface circuit that integrates the received plurality of packets into data; and a processing device that executes a driver of the network interface circuit. Have. The network interface circuit includes a first processing unit that duplicates the header of the packet, and a second processing unit that outputs the header duplicated by the first processing unit to the driver, and is executed by the processing device. Using the header received from the second processing unit and the data obtained by the network interface circuit integrating a plurality of packets or the data before the network interface circuit divides the packet into a plurality of packets. A third processing unit for generating a packet corresponding to.

It will be possible to capture data transferred over high-speed communication lines.

FIG. 1 is a diagram for explaining capture when the offload function is implemented. FIG. 2 is a functional block diagram of the information processing apparatus. FIG. 3 is a diagram showing an outline of processing executed when a frame is transmitted. FIG. 4 is a diagram illustrating a processing flow of processing executed when a frame is transmitted. FIG. 5 is a diagram illustrating an example of LSO data. FIG. 6 is a diagram illustrating an example of data stored in the first control data storage unit. FIG. 7 is a diagram illustrating a processing flow of the cooperation processing 1. FIG. 8 is a diagram illustrating an example of data stored in the second control data storage unit. FIG. 9 is a diagram illustrating an example of a frame obtained by dividing LSO data. FIG. 10 is a diagram illustrating an example of a frame structure when the communication protocol is TCP. FIG. 11 is a diagram illustrating an example of a frame structure when the communication protocol is UDP. FIG. 12 is a diagram illustrating a process flow of the list generation process 1. FIG. 13 is a diagram illustrating an example of the header list. FIG. 14 is a diagram illustrating a processing flow of the frame generation processing 1. FIG. 15 is a diagram showing an outline of processing executed when a frame is received. FIG. 16 is a processing flow of processing executed when a frame is received. FIG. 17 is a diagram illustrating a process flow of the list generation process 2. FIG. 18 is a diagram illustrating an example of LRO data. FIG. 19 is a diagram illustrating a processing flow of the cooperation processing 2. FIG. 20 is a diagram illustrating a processing flow of the frame generation processing 2. FIG. 21 is a functional block diagram of a computer.

For example, in Ethernet (registered trademark), data is transferred in a format called a frame. The maximum frame length is about 1500 bytes, and this size does not change even if the communication speed increases. Therefore, as the communication speed increases, the number of frames processed per unit time increases, and the amount of processing executed by the OS (Operating System) kernel increases. As a result, the load on the CPU increases, the CPU becomes a bottleneck, and the throughput decreases. Here, the process executed by the kernel is, for example, a process of dividing a TCP (Transmission Control Protocol) packet (or UDP (User Datagram Protocol) packet) into frames, and a TCP packet (or UDP packet by integrating received frames) ) And a process of calculating the value of the checksum field in the IP (Internet Protocol) header and TCP header (or UDP header).

Therefore, in order to reduce the load on the CPU, a function (hereinafter referred to as an offload function) that causes the hardware on the network interface card to perform part of the processing executed by the OS kernel may be implemented. Here, examples of the offload function include the following.

(1) LSO (Large Send Offload)
(2) LRO (Large Receive Offload)
(3) Checksum off-road

In LSO, a LAN driver in the OS adds an IP header and a MAC (Media Access Control) header to a TCP packet (or UDP packet), and outputs the packet to a network interface card by DMA transfer without dividing the packet into frames. The network interface card divides data into frames according to a TCP header (or UDP header), an IP header, and a MAC header. As a result, the number of DMA transfers per unit time in the transmission process is reduced, so that the load on the CPU can be reduced.

In LRO, the network interface card integrates a plurality of received frames into one TCP packet (or UDP packet) and outputs it to the LAN driver by DMA transfer. The LAN driver outputs the packet as it is to a processing unit that executes TCP (or UDP) processing. As a result, the number of DMA transfers per unit time during reception is reduced, so that the load on the CPU can be reduced.

In the checksum offload, the hardware on the network interface executes processing for calculating the values of the checksum field of the TCP header (or UDP header) and the IP header. Thereby, the load on the CPU can be reduced.

However, if the offload function is implemented, it will not be possible to capture the frame transferred on the communication line. The capture when the offload function is implemented will be described with reference to FIG. In FIG. 1, as an implementation of LSO and LRO, an offload processing unit is provided in the network interface card. Therefore, the LAN driver does not receive the received data in the form of a frame, but is obtained by integrating the data before the division by the offload processing unit (hereinafter referred to as LSO data) and the offload processing unit. Data (hereinafter referred to as LRO data). Therefore, the capture processing unit that collects frames also receives LSO data and LRO data from the LAN driver. The headers of the original frames (that is, headers 1-1, 1-2, and 1-3) (for example, checksum field values) are not included in the headers of the LSO data and the LRO data. Therefore, even if the capture processing unit collects LSO data and LRO data, the frame cannot be analyzed.

Therefore, in the following, a technique for enabling the capture processing unit to capture a frame even when an offload function is implemented due to a high communication speed will be described.

FIG. 2 shows a functional block diagram of the information processing apparatus 1 in the present embodiment. The information processing apparatus 1 includes a network interface card 11 that is a LAN card, for example. Then, the OS kernel 12, the communication processing unit 13, and the capture processing unit 14 are executed by a CPU (not shown). The information processing apparatus 1 is connected to a transmission line 2 that is a high-speed (for example, 10 Gbps or higher) communication line. For this reason, the information processing apparatus 1 has the offload function described above.

The network interface card 11 includes a PHY circuit 1100, a MAC circuit 1101, a selection unit 1103 including a header processing unit 1104 and a second control data storage unit 1111, a DMA management unit 1105 including a DMA area 1106, and a cooperation unit 1108. The offload processing unit 1107 includes a transmission DMA area 1109 and a reception DMA area 1110. Although not shown in the figure because it is not directly related to the main part in the present embodiment, transmission DMA area 1109 and reception DMA area 1110 are each divided into a plurality of areas. By dividing into a plurality of areas, the kernel 12 recognizes that there are a plurality of network interface cards, and can assign a CPU to each of the plurality of network interface cards. This prevents the load from being concentrated on one CPU.

The PHY circuit 1100 executes conversion between an electric signal and a logic signal.

The MAC circuit 1101 executes processing for extracting a frame from the data received from the PHY circuit 1100.

The selection unit 1103 executes processing for determining which area of the reception DMA area 1110 to store in accordance with the MAC address included in the frame. The header processing unit 1104 generates a header list and stores it in the DMA area 1106. The header list includes a plurality of header lengths, payload lengths, and header sets. The header includes a TCP header or UDP header, an IP header, and a MAC header.

The DMA areas such as the DMA area 1106, the transmission DMA area 1109, and the reception DMA area 1110 are areas secured in a memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) or other storage devices. This is an area for storing data transferred by DMA.

The DMA management unit 1105 outputs the data stored in the DMA area 1106 to the LAN driver 1207 by DMA transfer.

The offload processing unit 1107 divides the LSO data stored in the transmission DMA area 1109 into frames and outputs the frames to the selection unit 1103. Further, the offload processing unit 1107 generates LRO data by integrating a plurality of frames, and stores the LRO data in the reception DMA area 1110. The cooperation unit 1108 outputs the length of the payload of LSO data (hereinafter referred to as LSO payload length) to the selection unit 1103. Further, when the offload processing unit 1107 integrates the frames, the cooperation unit 1108 outputs a transfer request for requesting output of the header list to the LAN driver 1207 to the DMA management unit 1105.

The kernel 12 includes an upper protocol processing unit 1200 and a LAN driver 1207 of the network interface card 11. The LAN driver 1207 includes a frame generation unit 1203. The LAN driver 1207 is assigned storage areas for a transmission buffer 1201, a reception buffer 1202, a first control data storage unit 1204, a list storage unit 1205, and a frame storage unit 1206.

The upper protocol processing unit 1200 executes TCP processing, UDP processing, and the like.

The transmission buffer 1201 stores LSO data. The reception buffer 1202 stores LRO data.

The frame generation unit 1203 generates a frame using the data stored in the first control data storage unit 1204, the header list stored in the list storage unit 1205, and the LSO data stored in the transmission buffer 1201, Stored in the frame storage unit 1206. In addition, the frame generation unit 1203 generates a frame using the data stored in the first control data storage unit 1204, the header list stored in the list storage unit 1205, and the LRO data stored in the reception buffer 1202. And stored in the frame storage unit 1206.

The communication processing unit 13 executes processing of higher-layer protocols (for example, FTP (File Transfer Protocol) and TELNET (TELecommunication NETwork)) than TCP and UDP.

The capture processing unit 14 reads the frame from the frame storage unit 1206 and executes frame analysis.

Next, the operation of the information processing apparatus 1 will be described with reference to FIGS. First, processing executed when transmitting a frame will be described with reference to FIGS. 3 to 14.

Fig. 3 shows an overview of the processing executed when transmitting a frame. In order to make the figure easy to understand, reference numerals and the like are omitted. The LAN driver 1207 receives LSO data from the upper protocol processing unit 1200. The LSO data is duplicated and output to the offload processing unit 1107 in the network interface card 11. Here, the LAN driver 1207 holds the copy source LSO data.

The offload processing unit 1107 divides the LSO data into frames. The header processing unit 1104 in the selection unit 1103 generates a header list by duplicating the frame header, and stores the header list in the DMA area 1106 managed by the DMA management unit 1105. In addition, the header processing unit 1104 outputs a transfer request for requesting transfer of the header list to the DMA management unit 1105. The DMA management unit 1105 outputs the header list to the LAN driver 1207 by DMA transfer. On the other hand, the selection unit 1103 outputs the frame to the MAC circuit 1101. The frame is transmitted to the destination device via the transmission path 2.

The frame generation unit 1203 in the LAN driver 1207 divides the LSO payload in the LSO data held by the LAN driver 1207. The frame generation unit 1203 generates a frame by adding a header included in the header list received from the DMA management unit 1105 to the data obtained by the division. The generated frames are collected by the capture processing unit 14.

In this way, the LAN driver 1207 can generate a frame using the header list generated in the network interface card 11 and the LSO data held by the LAN driver 1207.

The processing executed when transmitting a frame will be described in detail with reference to FIGS. In FIG. 4, the network interface card 11 is abbreviated as NIC. First, the LAN driver 1207 receives the LSO data from the upper protocol processing unit 1200 and stores it in the transmission buffer 1201 (FIG. 4: step S1). FIG. 5 shows an example of LSO data. In the example of FIG. 5, the LSO data includes an LSO header and an LSO payload.

When the LSO data is stored in the transmission buffer 1201, the frame generation unit 1203 stores the start address and the end address of the LSO payload in the first control data storage unit 1204 (step S3). These addresses are addresses indicating positions in the transmission buffer 1201.

FIG. 6 shows an example of data stored in the first control data storage unit 1204. In the example of FIG. 6, the capture flag, the start address of the LSO payload, the end address of the LSO payload, the start address of the LRO payload, the end address of the LRO payload, the start address of the header list, and the end address of the header list And a copy destination address are stored. The capture flag is set to “ON” when capture is instructed by the user, and is set to “OFF” when capture is not instructed by the user. When the capture flag is set to “ON”, the information processing apparatus 1 executes the processing described in the present embodiment. The start address and end address of the LRO payload are addresses indicating positions in the reception buffer 1202. The head address and the end address of the header list are addresses indicating positions in the list storage unit 1205. The copy destination address is an address indicating a position in the frame storage unit 1206.

The LAN driver 1207 duplicates the LSO data, and outputs the duplicated LSO data to the network interface card 11 (step S5). The LAN driver 1207 keeps the copy source LSO data in the transmission buffer 1201.

The offload processing unit 1107 in the network interface card 11 receives the LSO data output from the LAN driver 1207 (step S7). More specifically, the process in step S7 is a process in which the LSO data output by the LAN driver 1207 by DMA transfer is stored in the transmission DMA area 1109, and the offload processing unit 1107 reads the LSO data from the transmission DMA area 1109. .

When the offload processing unit 1107 receives the LSO data, the offload processing unit 1107 calls the cooperation unit 1108. And the cooperation part 1108 performs the cooperation process 1 (step S9). The cooperation process 1 will be described with reference to FIG.

First, the cooperation unit 1108 specifies the LSO payload length of the LSO data received in step S7 (FIG. 7: step S41).

The cooperation unit 1108 outputs the LSO payload length specified in step S41 to the selection unit 1103 (step S43). Then, the process returns to the original process.

In this way, the sorting unit 1103 can control the timing of the transfer request using the LSO payload length.

Returning to the description of FIG. 4, the selection unit 1103 receives the LSO payload length from the cooperation unit 1108 (step S11) and stores it in the second control data storage unit 1111 (step S13).

FIG. 8 shows an example of data stored in the second control data storage unit 1111. In the example of FIG. 8, a capture flag, an LSO payload length, a copied data length, a copy destination head address, and a copy destination address are stored. The capture flag is set to “ON” when capture is instructed by the user, and is set to “OFF” when capture is not instructed by the user. When the capture flag is set to “ON”, the information processing apparatus 1 executes the processing described in the present embodiment. The copied data length is the length of the LSO payload that has been copied. The copy destination head address and the copy destination address are addresses indicating positions in the DMA area 1106.

Meanwhile, the offload processing unit 1107 divides the LSO data received in step S7 into frames (step S15).

When dividing the LSO data, multiple frames are obtained. FIG. 9 shows an example of a frame obtained by dividing the LSO data. In the example of FIG. 9, a frame 1 including a header 1-1 and a payload 1-1 and a frame 2 including a header 1-2 and a payload 1-2 are obtained. In some cases, three or more frames are obtained.

When the communication protocol is TCP, the frame structure is as shown in the example of FIG. In the example of FIG. 10, the header of the frame includes a MAC header, an IP header, and a TCP header. The MAC header includes a destination MAC address, a source MAC address, and a type. The IP header includes an IP header length, an IP packet length, an upper protocol number, an IP header checksum, and the like. The TCP header includes a source port number, a destination port number, a data offset, a TCP checksum, and the like.

When the communication protocol is UDP, the frame structure is as shown in the example of FIG. In the example of FIG. 11, the header of the frame includes a MAC header, an IP header, and a UDP header. The MAC header includes a destination MAC address, a source MAC address, and a type. The IP header includes an IP header length, an IP packet length, an upper protocol number, an IP header checksum, and the like. The UDP header includes a source port number, a destination port number, a packet length, and a UDP checksum.

When the division is completed, the offload processing unit 1107 outputs the frame obtained by the division to the selection unit 1103 (step S17).

In response, the selection unit 1103 receives the frame from the offload processing unit 1107 (step S19) and calls the header processing unit 1104. Then, the header processing unit 1104 executes list generation processing 1 (step S21). List generation processing 1 will be described with reference to FIGS. 12 and 13. The list generation process 1 shown in FIG. 12 is a process for one frame. If there are a plurality of frames received in step S19, the list generation process 1 is executed for each of the plurality of frames.

First, the header processing unit 1104 specifies the header length and payload length of the frame (FIG. 12: step S51). The header length is specified using header length information included in the IP header and the TCP header, for example. The payload length differs between TCP and UDP. In the case of TCP, it is obtained by ((IP packet length included in IP header−IP header length included in IP header × 4) − (data offset included in TCP header × 4)). In the case of UDP, it is obtained by (packet length-8 included in UDP header).

The header processing unit 1104 sets the copy destination address stored in the second control data storage unit 1111 to the same address as the copy destination start address stored in the second control data storage unit 111 (step S53).

The header processing unit 1104 stores the header length and payload length of the frame in the area indicated by the copy destination address in the DMA area 1106 (step S55).

The header processing unit 1104 updates the copy destination address stored in the second control data storage unit 1111 by the amount of data stored in step S55 (step S57).

The header processing unit 1104 duplicates the header of the frame, and stores the header of the frame in the area indicated by the copy destination address in the DMA area 1106 (step S59). In step S59, the header length specified in step S51 is used.

FIG. 13 shows the contents of the header list stored in the DMA area 1106. The header list includes a plurality of header lengths, payload lengths, and header sets. The number of sets is the same as the number of frames obtained by dividing the LSO data.

The header processing unit 1104 updates the copy destination address stored in the second control data storage unit 1111 by the length of the header stored in step S59 (step S61).

The header processing unit 1104 adds the payload length specified in step S51 to the copied data length stored in the second control data storage unit 1111 (step S63).

The header processing unit 1104 determines whether the copied data length stored in the second control data storage unit 1111 is equal to the LSO payload length (step S65). If they are not equal (step S65: No route), there is a frame to be processed next, and the process proceeds to step S71. On the other hand, if they are equal (step S65: Yes route), the header processing unit 1104 outputs a transfer request to the DMA management unit 1105 (step S67).

The header processing unit 1104 sets the copied data length stored in the second control data storage unit 1111 to 0 (step S69).

The header processing unit 1104 sets the copy destination start address stored in the second control data storage unit 1111 as the start address of the free area in the DMA area 1106 (step S71). Then, the process returns to the original process.

If the above processing is executed, the DMA transfer can be performed for each LSO data instead of the DMA transfer for each frame, so that the load on the CPU can be reduced. Also, the number of DMA areas 1106 can be small.

Returning to the description of FIG. 4, the selection unit 1103 outputs the frame obtained by the division in step S15 to the MAC circuit 1101 (step S23).

On the other hand, the DMA management unit 1105 that has received the transfer request output in step S67 outputs the header list stored in the DMA area 1106 to the LAN driver 1207 by DMA transfer (step S25).

In response, the LAN driver 1207 receives the header list from the DMA management unit 1105 (step S27) and stores it in the list storage unit 1205. The LAN driver 1207 processes step S27 as an interrupt.

The LAN driver 1207 calls the frame generation unit 1203. Then, the frame generation unit 1203 executes frame generation processing 1 (step S29). The frame generation process 1 will be described with reference to FIG.

First, the frame generation unit 1203 stores the start address and end address of the header list in the first control data storage unit 1204 (FIG. 14: step S81). These addresses are addresses indicating positions in the list storage unit 1205.

The frame generation unit 1203 identifies one unprocessed set from the header list stored in the list storage unit 1205 (step S82).

The frame generation unit 1203 stores the header of the frame included in the set identified in step S82 in the area indicated by the copy destination address stored in the first control data storage unit 1204 (step S83).

The frame generation unit 1203 updates the copy destination address stored in the first control data storage unit 1204 by the amount of the header length of the frame stored in step S83 (step S85).

The frame generation unit 1203 extracts data corresponding to the payload length of the frame included in the specified set from the position indicated by the head address of the LSO payload stored in the first control data storage unit 1204 (step S87). . The data extracted in step S87 corresponds to the payload corresponding to the header of the frame included in the set specified in step S82.

The frame generation unit 1203 stores the data extracted in step S87 in the area indicated by the copy destination address stored in the first control data storage unit 1204 (step 89).

The frame generation unit 1203 updates the start address of the LSO payload stored in the first control data storage unit 1204 by the payload length included in the set specified in step S82 (step S91).

The frame generation unit 1203 changes the copy destination address stored in the first control data storage unit 1204 to the address of the next free area in the frame storage unit 1206 (step S93).

The frame generation unit 1203 determines whether the start address and the end address of the LSO payload stored in the first control data storage unit 1204 are the same (step S95). If they are not the same (step S95: No route), the process returns to step S82 to process the next set. On the other hand, if they are the same (step S95: Yes route), the process returns to the original process.

Returning to the description of FIG. 4, the LAN driver 1207 outputs the frame stored in the frame storage unit 1206 to the capture processing unit 14 (step S31).

By executing the processing as described above, even if the information processing apparatus 1 has an offload function, the data transmitted from the information processing apparatus 1 to the transmission path 2 can be acquired in the form of a frame. .

Secondly, processing executed when a frame is received will be described with reference to FIGS. 15 to 20.

FIG. 15 shows an outline of processing executed when a frame is received. In order to make the figure easy to understand, reference numerals and the like are omitted. When receiving a frame from the MAC circuit 1101, the header processing unit 1104 in the selection unit 1103 generates a header list by duplicating the header of the frame, and stores the header list in the DMA area 1106 managed by the DMA management unit 1105. The sorting unit 1103 outputs the frame to the offload processing unit 1107. The offload processing unit 1107 generates LRO data by integrating the frames. The LRO data is output to the LAN driver 1207. In addition, when the integration is completed, the cooperation unit 1108 in the offload processing unit 1107 outputs a transfer request for requesting output of the header list to the DMA management unit 1105. The DMA management unit 1105 outputs the header list to the LAN driver 1207 by DMA transfer.

The LAN driver 1207 duplicates the LRO data received from the network interface card 11. The frame generation unit 1203 in the LAN driver 1207 divides the LRO payload in the copied LRO data. The frame generation unit 1203 generates a frame by adding a header included in the header list received from the DMA management unit 1105 to the data obtained by the division. The generated frames are collected by the capture processing unit 14. On the other hand, the replication source LRO data is output to the higher-level protocol processing unit 1200.

As described above, the LAN driver 1207 can generate a frame using the header list generated in the network interface card 11 and the LRO data obtained by integrating the frames.

A process executed when a frame is received will be described in detail with reference to FIGS. First, the selection unit 1103 receives a frame from the MAC circuit 1101 (FIG. 16: step S101).

The sorting unit 1103 calls the header processing unit 1104. Then, the header processing unit 1104 executes list generation processing 2 (step S103). The list generation process 2 will be described with reference to FIG. The list generation process 2 shown in FIG. 17 is executed every time the selection unit 1103 receives a frame from the MAC circuit 1101.

First, the header processing unit 1104 identifies the header length and payload length of the frame (FIG. 17: step S131). Since the method for specifying the header length and the payload length in step S131 is the same as the method in step S51, description thereof will be omitted.

The header processing unit 1104 sets the copy destination address stored in the second control data storage unit 1111 to the same address as the copy destination start address stored in the second control data storage unit 111 (step S133).

The header processing unit 1104 stores the header length and payload length of the frame in the area indicated by the copy destination address in the DMA area 1106 (step S135).

The header processing unit 1104 updates the copy destination address stored in the second control data storage unit 1111 by the amount of data stored in step S135 (step S137).

The header processing unit 1104 duplicates the header of the frame, and stores the header of the frame in the area indicated by the copy destination address in the DMA area 1106 (step S139). In step S139, the header length specified in step S131 is used. The header processing unit 1104 updates the copy destination address stored in the second control data storage unit 1111 by the length of the header stored in step S139 (step S141). Then, the process returns to the original process. The contents of the header list stored in the DMA area 1106 are as shown in FIG.

If the above processing is executed, a header list used by the LAN driver 1207 can be prepared.

Returning to the description of FIG. 16, the selection unit 1103 outputs the frame received in step S101 to the offload processing unit 1107 (step S105).

In response, the offload processing unit 1107 receives a frame from the selection unit 1103 (step S107).

The offload processing unit 1107 generates LRO data by integrating a plurality of frames (step S109). In step S109, the offload processing unit 1107 generates LRO data by integrating the frame received in step S107 and the frame received before receiving the frame.

FIG. 18 shows an example of LRO data. In the example of FIG. 18, the LRO data includes an LRO header and an LRO payload. The LRO payload includes a plurality of frame payloads.

The offload processing unit 1107 calls the cooperation unit 1108. And the cooperation part 1108 performs the cooperation process 2 (step S111). The cooperation process 2 will be described with reference to FIG.

First, the cooperation unit 1108 identifies the copy destination head address and the copy destination address from the second control data storage unit 1111 (FIG. 19: Step S151). The copy destination start address represents the start address of the area where the header list is stored, and the copy destination address represents the end address of the area where the header list is stored.

The cooperation unit 1108 outputs a transfer request including the copy destination start address and the copy destination address specified in step S151 to the DMA management unit 1105 (step S153). Upon receiving the transfer request, the DMA management unit 1105 outputs the header list stored in the area specified by the copy destination start address and the copy destination address included in the transfer request to the LAN driver 1207 by DMA transfer.

The cooperation unit 1108 sets the copy destination head address stored in the second control data storage unit 1111 as the head address of the empty area in the DMA area 1106 (step S155). Then, the process returns to the original process.

If the above processing is executed, the DMA transfer can be performed for each LRO data instead of the DMA transfer for each frame, so that the load on the CPU can be reduced. Also, the number of DMA areas 1106 can be small.

16, the LAN driver 1207 receives the header list from the DMA management unit 1105 (step S113) and stores it in the list storage unit 1205. The LAN driver 1207 processes step S113 as an interrupt.

On the other hand, the offload processing unit 1107 stores the LRO data generated in step S109 in the reception DMA area 1110, and outputs the LRO data stored in the reception DMA area 1110 to the LAN driver 1207 by DMA transfer (step S115). ).

In response, the LAN driver 1207 receives the LRO data from the offload processing unit 1107, duplicates the LRO data, and stores it in the reception buffer 1202 (step S117). The replication source LRO data is output to the upper protocol processing unit 1200 in step 123.

The LAN driver 1207 calls the frame generation unit 1203. Then, the frame generation unit 1203 executes frame generation processing 2 (step S119). The frame generation process 2 will be described with reference to FIG.

First, the frame generation unit 1203 identifies the start address and the end address of the header list stored in the list storage unit 1205 (step S161). Then, the frame generation unit 1203 stores the start address and the end address of the header list specified in step S161 in the first control data storage unit 1204 (step S163).

The frame generation unit 1203 identifies one unprocessed set from the header list stored in the list storage unit 1205 (step S164).

The frame generation unit 1203 stores the header of the frame included in the set identified in step S164 in the area indicated by the copy destination address stored in the first control data storage unit 1204 (step S165).

The frame generation unit 1203 updates the copy destination address stored in the first control data storage unit 1204 by the amount of the header length of the frame stored in step S165 (step S167).

The frame generation unit 1203 extracts data corresponding to the payload length of the frame included in the specified set from the position indicated by the head address of the LRO payload stored in the first control data storage unit 1204 (step S169). . The data extracted in step S169 corresponds to the payload corresponding to the header of the frame included in the set specified in step S164.

The frame generation unit 1203 stores the data extracted in step S169 in the area indicated by the copy destination address stored in the first control data storage unit 1204 (step 171).

The frame generation unit 1203 updates the head address of the LRO payload stored in the first control data storage unit 1204 by the payload length included in the set identified in step S164 (step S173).

The frame generation unit 1203 changes the copy destination address stored in the first control data storage unit 1204 to the address of the next free area in the frame storage unit 1206 (step S175).

The frame generation unit 1203 determines whether the start address and the end address of the LRO payload stored in the first control data storage unit 1204 are the same (step S177). If they are not the same (step S177: No route), the process returns to step S164 to process the next set. On the other hand, if they are the same (step S177: Yes route), the process returns to the original process.

16, the LAN driver 1207 outputs the frame stored in the frame storage unit 1206 to the capture processing unit 14 (step S121).

Also, the LAN driver 1207 outputs the replication source LRO data to the higher-level protocol processing unit 1200 (step S123).

If the processing as described above is executed, even if the information processing apparatus 1 has an offload function, the data received by the information processing apparatus 1 from the transmission path 2 can be acquired in the form of a frame.

Although one embodiment of the present invention has been described above, the present invention is not limited to this. For example, the functional block configuration of the information processing apparatus 1 described above may not correspond to the actual program module configuration.

Further, the configuration of each table described above is an example, and the configuration as described above is not necessarily required. Further, in the processing flow, the processing order can be changed if the processing result does not change. Further, it may be executed in parallel.

In the above description, Ethernet (registered trademark) is used as an example, but it is not limited to Ethernet (registered trademark). The present embodiment may be applied to an apparatus in another network using a high-speed communication line.

In the above description, the network interface card has been described as an example of the communication interface. However, the communication interface is not limited to the network interface card. For example, it may be realized by a CPU such as a microcontroller mounted on a substrate or an LSI (Large Scale Integration) such as an FPGA (Field Programmable Gate Gate Array).

The selection unit 1103, header processing unit 1104, DMA management unit 1105, offload processing unit 1107, and linkage unit 1108 included in the network interface card 11 described above are executed by a CPU such as a microprocessor included in the expansion card. Alternatively, it may be executed by a hardware circuit.

The information processing apparatus 1 described above is a computer apparatus, and as shown in FIG. 21, a display connected to a memory 2501, a CPU 2503, a hard disk drive (HDD: Hard Disk Drive) 2505, and a display apparatus 2509. A control unit 2507, a drive device 2513 for a removable disk 2511, an input device 2515, and a communication control unit 2517 for connecting to a network are connected by a bus 2519. The operating system, application programs for executing the processing in this embodiment, the LAN driver 1207, and the like are stored in the HDD 2505, and are read from the HDD 2505 to the memory 2501 when executed by the CPU 2503. The CPU 2503 controls the display control unit 2507, the communication control unit 2517, and the drive device 2513 according to the processing content of the application program or the like to perform a predetermined operation. Further, data in the middle of processing is mainly stored in the memory 2501, but may be stored in the HDD 2505. In the embodiment of the present invention, an application program or the like for executing the processing described above is stored in a computer-readable removable disk 2511 and distributed, and installed in the HDD 2505 from the drive device 2513. In some cases, the HDD 2505 may be installed via a network such as the Internet and the communication control unit 2517. Such a computer device realizes various functions as described above by organically cooperating hardware such as the CPU 2503 and memory 2501 described above and programs such as OS and application programs. To do.

The above-described embodiment can be summarized as follows.

The information processing apparatus according to the first aspect of the present embodiment includes (A) an expansion card and (B) a driver for the expansion card. The expansion card described above has (a1) a first processing unit that duplicates the header of the packet, and (a2) a second processing unit that outputs the header duplicated by the first processing unit to the driver. . Then, the driver described above uses (b1) the header received from the second processing unit and the data obtained by the expansion card integrating the packets or the data before the expansion card is divided into packets. And a third processing unit for generating the same packet as the packet.

In this way, the driver can acquire data in the form of a packet even when the information processing apparatus has an offload function. This makes it possible to capture packets transferred on the high-speed communication line.

Further, the second processing unit described above may output the header (a21) to the driver by direct memory access. In this way, the load on the CPU can be reduced.

Further, when the expansion card described above receives (a3) data before being divided into packets from the driver, a fourth processing unit that outputs the payload length of the data before being divided into packets to the first processing unit May further be included. The first processing unit described above is (a11) the second processing unit when the total payload length of the packets processed by the first processing unit matches the payload length of the data before being divided into packets. On the other hand, it may be requested to output the header to the driver. In this way, it is possible to capture a packet transmitted by the information processing apparatus. Further, since data is output for each data before division, the number of times of output is reduced as compared with the case of outputting for each packet, and the load on the CPU can be reduced.

Further, the fourth processing unit described above may request (a31) that the second processing unit outputs the header to the driver when the integration of the received packets is completed. In this way, the packet received by the information processing apparatus can be captured. Further, since the data is output every time integration is completed, the number of times of output is reduced compared to the case of outputting for each packet, and the load on the CPU can be reduced.

Also, the third processing unit described above (b11) divides the data obtained by the expansion card integrating the packets or the payload of the data before the expansion card divides the packet, and obtained by the division. By adding a header to the data, the same packet as the packet may be generated. In this way, the driver can convert the data into a frame format.

Further, the header described above may include a TCP header or a UDP header, an IP header, and a MAC header.

Further, the packet described above may be a data link layer frame. As a result, for example, a frame transferred in Ethernet (registered trademark) can be captured.

The information processing method according to the second aspect of the present embodiment is executed by a computer having an expansion card and a driver for the expansion card. Then, the expansion card described above executes a process of (C) duplicating the header of the packet, (D) outputting the copied header to the driver, and the driver described above is (E) the expansion card. A process of generating the same packet as the packet may be executed using the header received from the data and data obtained by integrating the packets by the expansion card or data before the expansion card divides the packet.

A program for causing a computer to perform the processing according to the above method can be created. The program can be a computer-readable storage medium such as a flexible disk, a CD-ROM, a magneto-optical disk, a semiconductor memory, or a hard disk. It is stored in a storage device. The intermediate processing result is temporarily stored in a storage device such as a main memory.

Claims

A network interface circuit that divides data into a plurality of packets and transmits or integrates a plurality of received packets into data and a processing device that executes a driver of the network interface circuit,
The network interface circuit comprising:
A first processing unit for copying the header of the packet;
A second processing unit that outputs the header replicated by the first processing unit to the driver;
Have
The driver executed by the processing device is
Using the header received from the second processing unit and data obtained by integrating the plurality of packets by the network interface circuit or data before the network interface circuit divides the plurality of packets. An information processing apparatus comprising: a third processing unit that generates a packet corresponding to the packet.
The second processing unit is
The information processing apparatus according to claim 1, wherein the header is output to the driver by direct memory access.
The network interface circuit comprising:
A fourth processing unit that outputs the payload length of the data before being divided into the plurality of packets to the first processing unit when the data before being divided into the plurality of packets is received from the driver;
The first processing unit is
When the total payload length of the packets processed by the first processing unit matches the payload length of the data before being divided into the plurality of packets, the header is output to the driver to the second processing unit The information processing apparatus according to claim 1, wherein the information processing apparatus is requested to perform.
The fourth processing unit is
The information processing apparatus according to claim 3, wherein when the integration of the plurality of received packets is completed, the second processing unit is requested to output the header to the driver.
The third processing unit is
The network interface circuit divides the data obtained by integrating the plurality of packets or the payload of the data before the previous network interface circuit divides the plurality of packets, and the header is added to the data obtained by the division. The information processing apparatus according to claim 1, wherein a packet corresponding to the packet is generated by adding the packet.
The information processing apparatus according to claim 1, wherein the header includes a TCP header or a UDP header, an IP header, and a MAC header.
The information processing apparatus according to claim 1, wherein the packet is a data link layer frame.
An information processing method executed by a computer having a network interface circuit that divides data into a plurality of packets and transmits or receives a plurality of received packets into data and a processing device that executes a driver of the network interface circuit There,
The network interface circuit comprising:
Duplicate the header of the packet;
Execute the process to output the duplicated header to the driver,
The driver executed by the processing device is
Using the header received from the network interface circuit and the data obtained by integrating the plurality of packets by the network interface circuit or the data before the network interface circuit divides the plurality of packets, An information processing method for executing processing for generating a packet corresponding to the packet.
A program for causing a computer having a network interface circuit to divide data into a plurality of packets and transmit or receive the received plurality of packets into the data,
In the computer,
A packet header copied by the network interface circuit, and data obtained by the network interface circuit integrating the plurality of packets or data before the network interface circuit divides the plurality of packets. A program for executing processing for generating a packet corresponding to the packet.