WO2014063329A1 - 共享闪存的方法、控制器及系统 - Google Patents

共享闪存的方法、控制器及系统 Download PDF

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Publication number
WO2014063329A1
WO2014063329A1 PCT/CN2012/083496 CN2012083496W WO2014063329A1 WO 2014063329 A1 WO2014063329 A1 WO 2014063329A1 CN 2012083496 W CN2012083496 W CN 2012083496W WO 2014063329 A1 WO2014063329 A1 WO 2014063329A1
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Prior art keywords
flash
processor
controller
cache
initialization instruction
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PCT/CN2012/083496
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English (en)
French (fr)
Inventor
俞柏峰
王富
张迪煊
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华为技术有限公司
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Priority to PCT/CN2012/083496 priority Critical patent/WO2014063329A1/zh
Priority to CN201280002250.8A priority patent/CN103907108B/zh
Publication of WO2014063329A1 publication Critical patent/WO2014063329A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a method, a controller and a system for sharing a flash memory (FLASH).
  • a flash memory FLASH
  • BACKGROUND OF THE INVENTION With the development of information technology, the demand for data centers has gradually increased, and an important component of data centers is servers. Because ARM servers have low power consumption and low cost, servers in the data center can use ARM servers. In order to improve the overall computing power of the ARM server, multiple ARM processors are usually integrated on the ARM server board, and multiple ARM processors work in parallel. Each ARM processor is a separate entity with its own independent operating system, input and output devices, file processing system, etc. When starting the ARM processor, it needs to be guided by the Basic Input Output System (BIOS). And configure a FLASH chip for each BIOS to complete the boot function.
  • BIOS Basic Input Output System
  • each ARM server has multiple ARM processors integrated on the board, each ARM processor is configured with one FLASH chip, resulting in each ARM server board.
  • the number of FLASH chips is large, which occupies the printed circuit board (PCB) space of the board and increases the overall power consumption of the ARM processor on the board.
  • the embodiments of the present invention provide a method, a controller, and a system for sharing a flash memory, so as to solve the problem of allocating one FLASH for each processor in the prior art, thereby occupying system space and causing an increase in overall power consumption of the system.
  • a method for sharing a flash FLASH is provided, the method being applied to a system including at least two processors, the system further comprising a controller and at least one flash FLASH, the number of the FLASH being less than the processing
  • the controller includes a buffer allocated for each of the processors, the method comprising: the controller reading an initialization instruction for each processor from the FLASH;
  • the read initialization instructions are written into a cache allocated by each processor to cause each of the processors to read the initialization instructions from a cache allocated thereto.
  • the method further includes: the controller pre-preserving a correspondence between each of the at least two FLASHs and the processor, and a correspondence between each FLASH and a cache allocated for each of the processors;
  • the controller reads an initialization command for each processor from the FLASH, specifically: the controller according to the saved correspondence between each FLASH and the processor, from the FLASH corresponding to each processor
  • the processor reads the initialization instruction
  • the writing the read initialization instruction into the cache allocated by each processor is specifically: matching the read initialization instruction according to each FLASH and the cache allocated for each processor , written in the cache allocated for each processor.
  • the controller reads an initialization instruction for each processor from the FLASH, including:
  • the controller When the system is powered on, the controller reads, from the FLASH, a first initialization instruction having a capacity smaller than a space capacity of the cache according to a starting address indicated by each processor;
  • the controller After the processor reads the first initialization instruction from the buffer allocated thereto, the controller reads the remaining initialization instructions of the first initialization instruction in the address order from the FLASH.
  • the reading the read initialization instruction is written as each processor
  • the allocated cache includes:
  • Reading the read initialization instructions sequentially from the head of the cache allocated for each processor to the tail of the cache;
  • the read initialization instruction is rewritten from the head of the cache until the controller reads all initialization instructions from the FLASH.
  • the The amount of space in the cache is less than the space capacity of the FLASH.
  • a controller is provided, where the controller is applied in a system including at least two processors, the system further includes at least one flash memory, and the number of the FLASH is less than the number of the processors.
  • the controller includes a cache allocated for each of the processors, and the controller includes:
  • a reading unit configured to read an initialization instruction for each processor from the FLASH
  • the controller further includes:
  • a saving unit configured to pre-save the at least two when at least two FLASHs are included in the system
  • the reading unit is specifically configured to read an initialization instruction for the processor from a FLASH corresponding to each processor according to a correspondence between each FLASH and the processor saved by the saving unit;
  • the writing unit is specifically configured to write the read initialization instruction to each processor according to a correspondence between each FLASH saved by the saving unit and a cache allocated for each processor. In the cache.
  • the reading unit includes:
  • a first reading subunit configured to: when the system is powered on, read a first initialization instruction that has a capacity smaller than a volume of the buffer from the FLASH according to a starting address indicated by each processor;
  • a second read subunit configured to: after the each processor reads the first initialization instruction from the allocated cache, the controller reads the first order from the FLASH according to an address sequence The remaining initialization instructions of the initialization instruction.
  • the writing unit is specifically configured to read the reading unit
  • the initialization instructions are sequentially written to the tail of the cache starting from the cached header allocated for each processor, and re-sent from the cached header after the initialization instruction is filled in the cache
  • the write of the read initialization instruction is started until the controller reads all initialization instructions from the FLASH.
  • a system for sharing a flash memory FLASH comprising: a controller, at least two processors, and at least one flash memory, the number of the FLASH is less than the number of the processors, the controller Include a cache allocated for each of the processors, wherein
  • the controller is configured to read an initialization instruction for each processor from the FLASH, and write the read initialization instruction into a buffer allocated by each processor, so that each processing is performed.
  • the initialization instruction is read from the cache allocated for it.
  • the controller is further configured to pre-store a correspondence between each FLASH and the processor in the at least two FLASHs when the system includes at least two FLASHs, and each FLASH and each processing The corresponding relationship of the cache allocated by the device;
  • the controller is specifically configured to: according to the saved correspondence between each FLASH and the processor, read an initialization instruction from the FLASH corresponding to each processor, and read the read initialization instruction according to the controller.
  • the correspondence between each FLASH and the cache allocated for each processor is written into the cache allocated for each processor.
  • the controller is specifically configured to: when the system is powered on, according to the indication of each processor a first initialization instruction that reads a capacity from the FLASH that is smaller than a space capacity of the cache, and after the processor reads the first initialization instruction from the allocated cache, the controller The remaining initialization instructions of the first initialization instruction are read in the FLASH according to the address sequence.
  • the controller is specifically configured to read the initialization instruction Writing to the tail of the cache sequentially from the head of the buffer allocated for each processor, and writing the read from the head of the cache after the initialization instruction is filled in the cache Initializing instructions until the controller is from the
  • the controller is configured for each The space capacity of the buffer allocated by the processor is less than the space capacity of the FLASH.
  • the embodiment of the present invention is applied to a system including at least two processors, the system further comprising a controller and at least one FLASH, wherein the number of FLASHs is less than the number of processors, and the controller includes a cache allocated for each processor.
  • the controller reads the initialization instruction for each processor from the FLASH, and writes the read initialization instruction into the buffer allocated by each processor, so that each processor reads the initialization instruction from the allocated cache.
  • the embodiment of the present invention saves the system space by setting less than the number of processors of the FLASH in the system; and the embodiment of the present invention replaces the prior art and the processor by using the cache resources on the controller existing in the system.
  • a consistent number of FLASHs completes initialization of all processors, reducing overall system power consumption.
  • FIG. 1A is a schematic structural diagram of a server system to which an embodiment of the present invention is applied;
  • Figure IB is a schematic diagram of a processor architecture on a server board in the prior art;
  • FIG. 1C is a schematic structural diagram of a server board in FIG. 1A;
  • FIG. 2 is a flow chart of an embodiment of a method for sharing FLASH according to the present invention.
  • FIG. 3 is a schematic diagram of a controller performing a read/write operation on a cache according to an embodiment of the present invention
  • FIG. 4 is a block diagram of an embodiment of a controller of the present invention.
  • FIG. 5 is a block diagram of an embodiment of a system for sharing flash FLASH in accordance with the present invention.
  • FIG. 1A is a schematic structural diagram of a server system to which an embodiment of the present invention is applied:
  • the system consists of several server boards. For the sake of convenience, only six server boards are shown in Figure 1A. Each server board is interconnected through a network, and is connected to a switch (SWITCH), which can be an extended Peripheral Component Interconnect Express (PCI-E) switch, or Ethernet (Ether). Net, ETH) switch.
  • SWITCH Peripheral Component Interconnect Express
  • PCI-E Peripheral Component Interconnect Express
  • Net Net
  • a number of processors are integrated on each server board, each processor corresponding to a separate computer system with separate operating systems, input and output devices, and file systems.
  • the above processor may be specifically an ARM processor, a PPC (Power PC) processor, a Microprocessor Without Interlocked Piped Stages (MIPS) processor, an X86 processor, etc., for example, where an ARM processor integrates Linux. operating system.
  • FIG. 1B it is a schematic diagram of a processor architecture on a server board in the prior art:
  • FIG. 1B shows a server board having three processors, each of which includes a CPU and a FLASH configured for the CPU, and each CPU of the processor is connected to FIG. 1A. On the switch shown in . As shown in Figure 1B, each server board needs to be configured with the same number of processors as the FLASH.
  • Figure 1C shows the architecture of a server board in Figure 1A:
  • FIG. 1C still shows that there is three processors on one server board, and each processor includes one CPU. Unlike FIG. 1B, only one server board is configured in FIG. 1C.
  • FLASH the FLASH can be connected to a Complex Programmable Logic Device (CPU) on a server board or a Field Programmable Gate Array (FPGA) chip.
  • Figure 1C shows the FPGA chip as Example, the random access memory on the FPGA chip
  • the (Random Access Memory, RAM) resource acts as a proxy Buffer for the FLASH chip. It divides the free resources of the above RAM resources and can be utilized, and allocates a separate Buffer for each CPU of the processor.
  • RAM Random Access Memory
  • FIG. 1A and FIG. 1C only show a possible application scenario of the embodiment of the present invention, so that the embodiments of the present invention can be described in detail later.
  • the system involved in the embodiment of the present invention may be a server board shown in FIG. 1A and FIG. 1C, or may be a server system of the same model in the server system shown in FIG. 1A.
  • the system is composed, and the embodiment of the present invention is not limited; no matter which system is used, the system includes a controller, and the number of FLASH is less than the number of processors, and is included in the system as each processing in the system.
  • the cache of the allocation of the device is different from the configuration of one FLASH for each processor in the existing system.
  • each system in the embodiment of the present invention includes one. FLASH.
  • the method, controller and server for sharing FLASH in the embodiment of the present invention are respectively described below. Referring to FIG. 2, it is a flowchart of an embodiment of a method for sharing FLASH according to the present invention:
  • Step 201 The controller reads an initialization instruction for each processor from the FLASH.
  • a controller is usually disposed on each server board, and the specific implementation form of the controller may be a logic chip, such as a CPLD chip or an FPGA chip, and the logic chip may be used in a server list. Auxiliary control functions are implemented on the board. Since the RAM is usually configured with a RAM resource, the embodiment of the present invention may use a part of the RAM resource in the RAM resource as a proxy buffer of the FLASH (the cache allocated for the processor described in the embodiment of the present invention), that is, the foregoing part The RAM resources are divided, and a proxy Buffer is allocated to each processor, and the initialization operation of the BIOS (Basic Input Output System) after the power-on of a single processor is completed by the proxy Buffer.
  • BIOS Basic Input Output System
  • the BIOS is a set of programs that are hardened to the processor. It stores the program's most important basic input and output programs, system setup information, post-boot self-test programs, and system self-start programs. Its main function is to provide the lowest level, most direct hardware setup and control for the processor. Usually, after the processor is powered on, it needs to be booted by the BIOS. When booting, the initialization command stored in the FLASH is required.
  • the size of the proxy Buffer divided for each processor may be the same as the size of the FLASH, or may be smaller than the size of the FLASH, for example, a 512-byte proxy Buffer is allocated for each processor, and the present invention is implemented.
  • BUFF_SIZE is used to indicate the size of each proxy Buffer.
  • the controller may read, from the FLASH, a first initialization instruction whose capacity is less than the allocated space capacity of the cache according to the starting address indicated by each processor, when each deal with After the first initialization instruction is read from the allocated buffer, the controller reads the remaining initialization instructions except the first initialization instruction from the FLASH in the address order.
  • Step 202 Write the read initialization instruction into the buffer allocated by each processor, so that each processor reads the written initialization instruction from the allocated cache.
  • the controller sequentially writes the read initialization instructions from the cached header allocated for each processor to the tail of the cache, and after the initialization instruction is filled in the cache, the controller re- The buffered header begins to write the read initialization instruction until the controller reads all initialization instructions from the FLASH.
  • the controller when the controller does not receive the jump instruction of the processor, the controller sequentially reads the initialization instruction from the FLASH and writes the buffer allocated to the processor, and correspondingly, the processor In the allocated cache, the initialization instruction is read in the order in which the initialization instruction is written into the cache; when the controller receives the jump instruction of the processor, and the initialization instruction corresponding to the address on the FLASH indicated by the jump instruction has been written as the When the processor allocates a cache, the processor is notified to read the written initialization instruction from the location indicated by the cache jump instruction.
  • the processor initializes the address corresponding to the address 0 in the cache.
  • the instruction starts, and the initialization instruction is sequentially read. It is assumed that when the processor reads the initialization instruction corresponding to the address 50, the controller receives the jump instruction, indicating that the initialization instruction corresponding to the address 100 needs to be read, and the controller determines the address corresponding to the address 100.
  • the initialization instruction has been written into the cache, and the controller can notify the processor to jump from the initialization instruction corresponding to the address 50 to the initialization instruction corresponding to the address 100 for reading.
  • the initialization instruction corresponding to the address on the FLASH indicated by the jump instruction sent by the processor is not written into the cache allocated by the processor, according to the hop
  • the address on the FLASH indicated by the transfer instruction reads the initialization instruction from the FLASH, and the read initialization instruction is sequentially written to the cache from the head of the cache allocated for the processor, so that the processor starts from the head of the cache. Read the initialization instruction.
  • a server board when a server board includes a controller and at least two FLASHs, the controller pre-stores a correspondence between each FLASH of the at least two FLASHs and the processor, and each FLASH is Corresponding relationship of the cache allocated by each processor; correspondingly, the controller reads the initialization instruction for the processor from the FLASH corresponding to each processor according to the saved correspondence between each FLASH and the processor, and reads The fetched initialization instructions are written into the cache allocated to each processor according to the correspondence between each FLASH and the cache allocated for each processor.
  • each processor when there are multiple controllers on one server board, each processor is connected to one of the controllers, and for each controller, the controller divides the cache for the connected processors. Correspondingly, each processor reads the initial cache from its connected controller. Initialization instructions.
  • a processor in the system when a processor does not read an initialization instruction from a cache allocated for it within a preset time, it can be determined that an exception occurs in the processor. Since the controller divides the cache for each processor, each processor reads the initialization instructions from its respective cache. When an exception occurs in one processor, it does not affect other processors to read from the corresponding cache. Take the initialization instruction.
  • FIG. 3 is a schematic diagram of a controller performing a read/write operation on a cache according to an embodiment of the present invention: wherein, for a buffer space corresponding to each processor, the controller may allocate a FLASH read pointer and a buffer space for the cache space.
  • the CPU reads the pointer, the FLASH read pointer is used to instruct the controller to read the initialization instruction from the FLASH, and the CPU read pointer is used by the controller to control the processor to read the initialization instruction from the buffer space.
  • each processor divides a part of the address space to access the data on the FLASH for BIOS initialization after the system is powered on.
  • the address space divided by this part is in one-to-one correspondence with the FLASH address space, and the range is limited by the start address and the end address, wherein the start address of the divided address space corresponds to the start address of the FLASH, and the address space of the partition is divided.
  • the size of the space between the start address and the end address is the same as the size of the FLASH space, so that in the process of reading the initialization instruction, the address according to the divided address space corresponds to the address of the FLASH address space, thereby on the FLASH address.
  • the stored initialization instructions are read.
  • the processor does not directly obtain the initialization instruction from the FLASH, but the controller receives the address of the storage space indicated by the processor, and corresponds to the address of the FLASH according to the address of the storage space, and the address of the FLASH.
  • the stored initialization instruction is read into the cache allocated to the processor, and the processor reads the initialization instruction from the cache.
  • the controller may not need to read the initialization instruction consistent with the size of the buffer space from the FLASH. For example, the initialization instruction that reads the buffer size by half from the FLASH may be read first.
  • the processor can start reading the initialization instruction from the cache, the subsequent controller continues to read the remaining initialization instructions from the FLASH and write to the cache, and the processor synchronizes the initialization instructions from the cache until the processor reads Take all initialization instructions.
  • the controller When the controller reads the initialization instruction from the FLASH and writes to the cache, when the controller receives the jump instruction sent by the processor, if the initialization instruction stored on the FLASH address indicated by the jump instruction has been read yet In the cache, the processor directly reads the initialization fingers from the initialization instructions read into the cache. If the initialization instruction stored on the FLASH address indicated by the jump instruction has not been read into the cache yet, the controller sequentially reads the initialization instruction from the address of the FLASH indicated by the jump instruction, and from the cached header The part starts to write the read initialization instruction (that is, the initialization instruction that has been read in the overlay buffer), and the processor reads the initialization instruction corresponding to the jump instruction from the cache.
  • phase 1 when the system is initially powered on, both the FLASH read pointer and the CPU read pointer indicate the head of the cache space.
  • phase 2 after the system is initially powered on, the controller reads the initialization instruction of half the buffer space from the FLASH. At this time, the FLASH read pointer indicates the middle of the cache space, and the CPU read pointer still indicates the head of the cache space, that is, the processor has not started to read the initialization instruction from the cache space;
  • phase 3 when the controller continues to read the initialization instruction from FLASH, the FLASH read pointer moves downward from the middle of the cache space.
  • the processor starts to read the initialization instruction from the cache space, and correspondingly, the CPU reads the pointer from the cache space.
  • the head begins to move downwards;
  • phase 4 when the FLASH read pointer moves to the end of the buffer space, it indicates that the controller has read the initialization instruction from the FLASH that matches the size of the cache space, and the FLASH pointer re-jumps to the head of the cache space.
  • the device continues to read the initialization instruction from the cache space, and the CPU read pointer continues to move downward in the cache space;
  • phase 5 since the initialization instruction in the storage space above the location indicated by the CPU read pointer in the cache space has been read by the processor, the controller writes the initialization instruction read from the FLASH to the buffer space header, FLASH read The pointer continues to move downward from the head of the buffer space.
  • the processor reads the initialization instruction of the buffer space, it jumps to the head of the buffer space and continues to read the initialization instruction.
  • the CPU reads the pointer correspondingly. To the head of the cache space;
  • phase 6 when the controller receives the jump instruction sent by the processor, and the initialization instruction stored on the FLASH address indicated by the jump instruction is not read into the buffer space, the FLASH read pointer and the CPU read pointer jump to the same time.
  • the controller sequentially reads the initialization instruction from the address of the FLASH indicated by the jump instruction, and the initialization instruction that is not read by the CPU read pointer in the original cache space is followed by the FLASH read pointer according to the jump instruction.
  • the read initialization instruction overwrites and repeats the process starting from phase 1 above until the processor reads all initialization instructions on the FLASH from the cache space.
  • the present invention also provides an embodiment of a controller and a system for sharing flash FLASH.
  • 4 is a block diagram of an embodiment of a controller according to the present invention, the controller is applied in a system including at least two processors, the system further includes at least one flash FLASH, and the number of the FLASH is less than that of the processor.
  • the controller includes a cache allocated for each of the processors.
  • the controller includes: a reading unit 410 and a writing unit 420.
  • the reading unit 410 is configured to read an initialization instruction for each processor from the FLASH
  • the writing unit 420 is configured to write the initialization instruction read by the reading unit 410 into each
  • the processor allocates a cache to cause each of the processors to read the initialization instruction written by the write unit 420 from the allocated cache.
  • controller may further include:
  • a saving unit 430 configured to pre-store a correspondence between each of the at least two FLASHs and the processor, and allocate each FLASH to each of the processors when at least two FLASHs are included in the system. Corresponding relationship of the cache;
  • the reading unit 410 is specifically configured to read an initialization instruction for the processor from the FLASH corresponding to each processor according to the correspondence between each FLASH and the processor saved by the saving unit 430. ;
  • the writing unit 420 is specifically configured to write the read initialization instruction into each processor according to the correspondence between each FLASH saved by the saving unit 430 and the cache allocated for each processor. Allocated in the cache.
  • the reading unit 410 may include:
  • a first reading subunit 411 configured to: when the system is powered on, read, from the FLASH, a first initialization instruction that is smaller than a volume of the buffer according to a starting address indicated by each processor ;
  • a second reading subunit 412 configured to: after the each processor reads the first initialization instruction from the allocated cache, the controller reads the address from the FLASH according to the address order The remaining initialization instructions of an initialization instruction.
  • the writing unit 420 is specifically configured to sequentially write the initialization instruction read by the reading unit 410 from a cached header allocated for each processor to a tail of the cache. And when the initialization instruction is filled in the cache, the read initialization instruction is restarted from the head of the cache until the controller reads all initialization instructions from the FLASH.
  • FIG. 5 it is a block diagram of an embodiment of a system for sharing flash FLASH according to the present invention:
  • the system includes: a controller 510, a plurality of processors 520, and at least one flash FLASH 530, the number of which is less than the number of processors, and the controller 510 includes a buffer allocated for each processor. For convenience of illustration, only three processors 520 and one FLASH 530 are shown in FIG.
  • the controller 510 is configured to read an initialization instruction for each processor 520 from the FLASH 530, and write the read initialization instruction into a buffer allocated by each processor 520, so that Each of the processors 520 reads the initialization instructions from the allocated cache.
  • the controller 510 is further configured to pre-store a correspondence between each of the at least two FLASHs and the processor, and each of the FLASHs is Corresponding relationship of the cache allocated by each processor; correspondingly, the controller 510 is specifically configured to: according to the saved correspondence between each FLASH and the processor, from the FLASH corresponding to each processor The processor reads the initialization instruction and writes the read initialization instruction into the cache allocated for each processor according to the correspondence between each FLASH and the cache allocated for each processor.
  • the controller 510 may be specifically configured to: when the system is powered on, read a capacity from the FLASH 510 that is smaller than a volume of the cache according to a starting address indicated by each processor 520. a first initialization instruction, after the each processor 520 reads the first initialization instruction from the allocated cache, the controller reads the first initialization instruction from the FLASH 530 according to an address order Remaining initialization instructions.
  • the controller 510 may be specifically configured to sequentially write the read initialization instruction from a cached header allocated for each processor to a tail of the cache, when the cache After the initialization instruction is written, the read initialization instruction is rewritten from the buffered header until the controller reads all initialization instructions from the FLASH 530.
  • the space capacity of the buffer allocated to each processor 520 on the controller 510 may be smaller than the space capacity of the FLASH 530.
  • the embodiment of the present invention is applied to a system including at least two processors, the system further comprising a controller and at least one FLASH, wherein the number of FLASHs is less than the number of processors, and the controller is included for each The cache allocated by the processor, the controller reads the initialization instruction for each processor from the FLASH, and writes the read initialization instruction into the buffer allocated by each processor, so that each processor is allocated from the cache. Read the initialization instruction.
  • the embodiment of the present invention saves the system space by setting less than the number of processors of the FLASH in the system; and the embodiment of the present invention replaces the prior art and the processor by using the cache resources on the controller existing in the system.
  • a consistent number of FLASHs completes initialization of all processors, thereby reducing Power consumption of the entire system.
  • the techniques in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product, which may be stored in a storage medium such as a ROM/RAM. , a diskette, an optical disk, etc., includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention or in some portions of the embodiments.
  • a computer device which may be a personal computer, server, or network device, etc.

Abstract

共享闪存的方法、控制器及系统，该方法应用在包含至少两个处理器的系统中，所述系统还包含控制器以及至少一个FLASH，所述FLASH的数量少于所述处理器的数量，所述控制器包含为每个所述处理器分配的缓存，该方法包括：控制器从FLASH中为每个处理器读取初始化指令；将读取到的所述初始化指令写入为每个处理器分配的缓存中，以使所述每个处理器从为其分配的缓存中读取所述初始化指令。本发明实施例通过在系统中设置少于处理器数量的FLASH，从而节省了系统空间；并且由于本发明实施例通过系统中已有的控制器上的缓存资源，代替现有技术中与处理器数量一致的FLASH完成对所有处理器的初始化操作，从而降低了整个系统的功耗。

Description

共享闪存的方法、 控制器及系统
技术领域
本发明涉及计算机技术领域， 特别涉及共享闪存 （FLASH) 的方法、 控制器及系 统。 背景技术 随着信息化技术的发展， 对数据中心的需求量逐步增大， 数据中心的重要组 成部分是服务器。 由于 ARM服务器具有能耗低， 成本低的特点， 因此数据中心中 的服务器可以采用 ARM服务器。为了提高 ARM服务器的整体计算能力，通常在 ARM 服务器单板上集成多个 ARM处理器， 由多个 ARM处理器并行工作。 每个 ARM处理 器作为独立的个体， 具有各自独立的操作系统、输入输出设备、文件处理系统等， 在启动 ARM处理器时， 需要通过基本输入输出系统（Basic Input Output System, BIOS ) 进行系统引导， 并为每个 BIOS配置一个 FLASH芯片以完成引导功能。
发明人在对现有技术的研究过程中发现， 由于每个 ARM服务器单板上集成了 多个 ARM处理器， 而每个 ARM处理器都配置一个 FLASH芯片， 从而导致每个 ARM 服务器单板上设置的 FLASH 芯片数量较多， 占据了单板的印刷电路板 （Printed Circui t Board, PCB ) 空间， 且增加了单板上 ARM处理器的整体功耗。 发明内容
本发明实施例提供一种共享闪存的方法、控制器及系统， 以解决现有技术中为每 个处理器分配一个 FLASH, 从而占据系统空间， 导致系统整体功耗增加的问题。
为了解决上述技术问题， 本发明实施例公开了如下技术方案：
一方面，提供一种共享闪存 FLASH的方法，所述方法应用在包含至少两个处理器 的系统中， 所述系统还包含控制器以及至少一个闪存 FLASH, 所述 FLASH的数量少于 所述处理器的数量， 所述控制器包含为每个所述处理器分配的缓存， 所述方法包括： 所述控制器从所述 FLASH中为每个处理器读取初始化指令；
将读取到的所述初始化指令写入为每个处理器分配的缓存中，以使所述每个处理 器从为其分配的缓存中读取所述初始化指令。
结合一方面， 在第一种可能的实现方式中， 当所述系统中包含至少两个 FLASH 时，所述方法还包括： 所述控制器预先保存所述至少两个 FLASH中每个 FLASH与处理 器的对应关系， 以及每个 FLASH与为所述每个处理器分配的缓存的对应关系；
所述控制器从所述 FLASH中为每个处理器读取初始化指令具体为：所述控制器按 照保存的每个 FLASH与处理器的对应关系，从与每个处理器对应的 FLASH中为所述处 理器读取初始化指令；
所述将读取到的所述初始化指令写入为每个处理器分配的缓存中具体为：将读取 到的初始化指令按照每个 FLASH与为每个处理器分配的缓存之间的对应关系，写入为 每个处理器分配的缓存中。
结合一方面， 或第一种可能的实现方式， 在第二种可能的实现方式中， 所述控制 器从所述 FLASH中为每个处理器读取初始化指令， 包括：
当所述系统上电时， 控制器根据所述每个处理器指示的起始地址从所述 FLASH 中读取容量小于所述缓存的空间容量的第一初始化指令；
当所述每个处理器从为其分配的缓存中读取所述第一初始化指令后，所述控制器 从所述 FLASH中按照地址顺序读取除所述第一初始化指令的剩余初始化指令。
结合一方面， 或第一种可能的实现方式， 或第二种可能的实现方式， 在第三种可 能的实现方式中， 所述将读取到的所述初始化指令写入为每个处理器分配的缓存中， 包括：
将读取到的所述初始化指令从为每个处理器分配的缓存的头部开始顺序写到所 述缓存的尾部；
当所述缓存内写满所述初始化指令后，重新从所述缓存的头部开始写入读取到的 初始化指令， 直至所述控制器从所述 FLASH中读取完所有初始化指令。
结合一方面， 或第一种可能的实现方式， 或第二种可能的实现方式， 或第三种可 能的实现方式，在第四种可能的实现方式中，所述为每个处理器分配的缓存的空间容 量小于所述 FLASH的空间容量。
另一方面， 提供一种控制器， 所述控制器应用在包含至少两个处理器的系统中， 所述系统还包含至少一个闪存 FLASH, 所述 FLASH的数量少于所述处理器的数量， 所 述控制器包含为每个所述处理器分配的缓存， 所述控制器包括：
读取单元， 用于从所述 FLASH中为每个处理器读取初始化指令；
写入单元，用于将所述读取单元读取到的所述初始化指令写入为每个处理器分配 的缓存中，以使所述每个处理器从为其分配的缓存中读取所述写入单元写入的所述初 始化指令。 结合另一方面， 在第一种可能的实现方式中， 所述控制器还包括：
保存单元， 用于当所述系统中包含至少两个 FLASH 时， 预先保存所述至少两个
FLASH中每个 FLASH与处理器的对应关系， 以及每个 FLASH与为所述每个处理器分配 的缓存的对应关系；
所述读取单元，具体用于按照所述保存单元保存的每个 FLASH与处理器的对应关 系， 从与每个处理器对应的 FLASH中为所述处理器读取初始化指令；
所述写入单元， 具体用于将读取到的初始化指令按照所述保存单元保存的每个 FLASH 与为每个处理器分配的缓存之间的对应关系， 写入为每个处理器分配的缓存 中。
结合另一方面， 或第一种可能的实现方式， 在第二种可能的实现方式中， 所述读 取单元包括：
第一读取子单元，用于当所述系统上电时，根据所述每个处理器指示的起始地址 从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令；
第二读取子单元，用于当所述每个处理器从分配的缓存中读取所述第一初始化指 令后，所述控制器从所述 FLASH中按照地址顺序读取除所述第一初始化指令的剩余初 始化指令。
结合另一方面， 或第一种可能的实现方式， 或第二种可能的实现方式， 在第三种 可能的实现方式中，所述写入单元， 具体用于将所述读取单元读取到的所述初始化指 令从为每个处理器分配的缓存的头部开始顺序写到所述缓存的尾部，以及当所述缓存 内写满所述初始化指令后， 重新从所述缓存的头部开始写入读取到的初始化指令，直 至所述控制器从所述 FLASH中读取完所有初始化指令。
又一方面， 提供一种共享闪存 FLASH的系统， 所述系统包括： 控制器、 至少两个 处理器及至少一个闪存 FLASH, 所述 FLASH的数量少于所述处理器的数量， 所述控制 器包含为每个所述处理器分配的缓存， 其中，
所述控制器，用于从所述 FLASH中为每个处理器读取初始化指令，将读取到的所 述初始化指令写入为每个处理器分配的缓存中，以使所述每个处理器从为其分配的缓 存中读取所述初始化指令。
结合又一方面， 在第一种可能的实现方式中，
所述控制器，还用于当所述系统中包含至少两个 FLASH时， 预先保存所述至少两 个 FLASH中每个 FLASH与处理器的对应关系，以及每个 FLASH与为所述每个处理器分 配的缓存的对应关系； 所述控制器， 具体用于按照保存的每个 FLASH与处理器的对应关系， 从与每个处 理器对应的 FLASH中为所述处理器读取初始化指令，以及将读取到的初始化指令按照 每个 FLASH与为每个处理器分配的缓存之间的对应关系，写入为每个处理器分配的缓 存中。
结合又一方面， 或第一种可能的实现方式， 在第二种可能的实现方式中， 所述控制器， 具体用于当所述系统上电时，根据所述每个处理器指示的起始地址 从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令，当所述每个处 理器从分配的缓存中读取所述第一初始化指令后，所述控制器从所述 FLASH中按照地 址顺序读取除所述第一初始化指令的剩余初始化指令。
结合又一方面， 或第一种可能的实现方式， 或第二种可能的实现方式， 在第三种 可能的实现方式中，所述控制器， 具体用于将读取到的所述初始化指令从为每个处理 器分配的缓存的头部开始顺序写到所述缓存的尾部，当所述缓存内写满所述初始化指 令后， 重新从所述缓存的头部开始写入读取到的初始化指令，直至所述控制器从所述
FLASH中读取完所有初始化指令。
结合又一方面， 或第一种可能的实现方式， 或第二种可能的实现方式， 或第三种 可能的实现方式，在第四种可能的实现方式中，所述控制器上为每个处理器分配的缓 存的空间容量小于所述 FLASH的空间容量。
本发明实施例应用在包含至少两个处理器的系统中，该系统还包含控制器以及至 少一个 FLASH, 其中 FLASH的数量少于处理器的数量， 控制器包含为每个处理器分配 的缓存，控制器从 FLASH中为每个处理器读取初始化指令，将读取到的初始化指令写 入为每个处理器分配的缓存中， 以使每个处理器从分配的缓存中读取初始化指令。本 发明实施例通过在系统中设置少于处理器数量的 FLASH, 从而节省了系统空间； 并且 由于本发明实施例通过系统中已有的控制器上的缓存资源，代替现有技术中与处理器 数量一致的 FLASH完成对所有处理器的初始化操作， 从而降低了整个系统的功耗。 附图说明 为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现 有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅 是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前 提下， 还可以根据这些附图获得其他的附图。
图 1A为应用本发明实施例的一个服务器系统的架构示意图； 图 IB为现有技术中一个服务器单板上的处理器架构示意图；
图 1C为图 1A中一个服务器单板的架构示意图；
图 2为本发明共享 FLASH的方法的实施例流程图；
图 3为本发明实施例中控制器对缓存进行读写操作的示意图；
图 4为本发明控制器的实施例框图；
图 5为本发明共享闪存 FLASH的系统的实施例框图。 具体实施方式 为了使本技术领域的人员更好地理解本发明实施例中的技术方案，并使本发明实 施例的上述目的、特征和优点能够更加明显易懂， 下面结合附图对本发明实施例中技 术方案作进一步详细的说明。
参见图 1A， 为应用本发明实施例的一个服务器系统的架构示意图：
该系统由若干服务器单板组成， 为了示例方便， 图 1A中仅示出了六个服务器单 板。 各个服务器单板之间通过网络进行互联， 均连接到交换机（SWITCH)上， 该交换 机可以为扩展的夕卜设组件互连标准 (Peripheral Component Interconnect Express, PCI-E) 交换机， 或者以太网 （Ether Net, ETH) 交换机。 在每个服务器单板上集成 了若干处理器， 每个处理器都对应于一个独立的计算机系统， 具备独立的操作系统、 输入输出设备和文件系统等。 上述处理器可以具体为 ARM处理器， PPC (Power PC) 处理器， 无内部互锁流水级 (Microprocessor Without Interlocked Piped Stages, MIPS) 处理器， X86处理器等， 例如， 其中 ARM处理器上集成 Linux操作系统。
参见图 1B， 为现有技术中一个服务器单板上的处理器架构示意图：
其中， 为了示例方便， 图 1B中示出了一个服务器单板上具有三个处理器， 每个 处理器均包含一个 CPU和为该 CPU配置的 FLASH, 每个处理器的 CPU均连接到图 1A 中示出的交换机上。 由图 1B可知， 每个服务器单板上需要配置与处理器数量一致的 FLASH。
参见图 1C， 为图 1A中一个服务器单板的架构示意图：
其中， 为了示例方便， 图 1C中仍然示出一个服务器单板上具有三个处理器， 每 个处理器均包含一个 CPU, 与图 1B 中不同， 图 1C中的服务器单板上仅配置了一个 FLASH , 该 FLASH 可以连接服务器单板上的复杂可编程逻辑器件 （Complex Programmable Logic Device, CPU))或者现场可编程门阵列（Field Programmable Gate Array, FPGA) 芯片， 图 1C中以示出 FPGA芯片为例， 将 FPGA芯片上的随机存储器 (Random Access Memory, RAM) 资源作为 FLASH芯片的代理 Buffer, 即将上述 RAM 资源中空闲的， 可以被利用的资源进行划分， 为每个处理器的 CPU 分配一段独立的 Buffer。
需要说明的是， 上述图 1A和图 1C仅示出了一种本发明实施例可能的应用场景， 以便后续可以对本发明实施例进行详细的描述。在实际的应用中，本发明实施例中涉 及的系统可以是图 1A和图 1C中示出的一个服务器单板， 也可以是图 1A中示出的服 务器系统中， 由具有相同型号的处理器组成的系统， 对此本发明实施例不进行限制； 无论对于上述何种系统，该系统中还包括控制器，以及数量少于处理器数量的 FLASH, 在控制器上包含为系统中每个处理器分配的缓存，与现有系统中为每个处理器配置一 个 FLASH不同，应用本发明实施例可以根据需要灵活减少系统中 FLASH的数量，优选 的， 本发明实施例的每个系统中包含一个 FLASH。 下面分别描述本发明实施例中共享 FLASH的方法、 控制器及服务器。 参见图 2， 为本发明共享 FLASH的方法的实施例流程图：
步骤 201 : 控制器从 FLASH中为每个处理器读取初始化指令。
在现有的服务器系统中， 每个服务器单板上通常会设置一个控制器， 该控制器的 具体实现形式可以为一块逻辑芯片，例如 CPLD芯片或者 FPGA芯片， 该逻辑芯片可以 用于在服务器单板上实现辅助控制功能。 由于逻辑芯片上通常配置有 RAM资源， 因此 本发明实施例可以将上述 RAM资源中的部分 RAM资源，作为 FLASH的代理 Buffer (本 发明实施例中描述的为处理器分配的缓存）， 即将上述部分 RAM资源进行划分， 为每 个处理器分配一段代理 Buffer, 通过该代理 Buffer完成对单个处理器上电后的基本 输入输出系统 （BIOS, Basic Input Output System) 初始化操作。
BIOS 是一组固化到处理器上的程序， 它保存着处理器最重要的基本输入输出的 程序、 系统设置信息、 开机后自检程序和系统自启动程序。其主要功能是为处理器提 供最底层的、 最直接的硬件设置和控制。 通常处理器上电后， 需要通过 BIOS进行系 统引导， 在引导时需要采用 FLASH上存储的初始化指令。
本发明实施例中， 为每个处理器划分的代理 Buffer的大小可以与 FLASH大小相 同，或者，也可以小于 FLASH的大小，例如，为每个处理器划分 512字节的代理 Buffer, 本发明实施例中用 BUFF_SIZE表示每个代理 Buffer的大小。
本步骤中， 可选的， 当系统初始上电时， 控制器可以根据每个处理器指示的起始 地址从 FLASH中读取容量小于分配的缓存的空间容量的第一初始化指令，当每个处理 器从分配的缓存中读取第一初始化指令后，控制器从 FLASH中按照地址顺序读取除第 一初始化指令的剩余初始化指令。
步骤 202 : 将读取到的初始化指令写入为每个处理器分配的缓存中， 以使每个处 理器从分配的缓存中读取写入的初始化指令。
可选的，控制器将读取到的初始化指令从为每个处理器分配的缓存的头部开始顺 序写到缓存的尾部， 当该缓存内写满所述初始化指令后，控制器重新从该缓存的头部 开始写入读取到的初始化指令， 直至控制器从 FLASH中读取完所有初始化指令。
本步骤中， 可选的， 当控制器未接收到处理器的跳转指令时， 控制器从 FLASH 上顺序读取初始化指令并写入为处理器分配的缓存中，相应的， 处理器从该分配的缓 存中， 按照初始化指令写入缓存的顺序读取初始化指令； 当控制器接收到处理器的跳 转指令，且跳转指令指示的 FLASH上的地址所对应的初始化指令已写入为该处理器分 配的缓存时，则通知处理器从所述缓存上跳转指令指示的位置开始读取已写入的初始 化指令。 例如， 假设控制器未接收到跳转指令， 并且控制器已经将 FLASH上地址 0 至地址 127对应的初始化指令读入到为处理器分配的缓存中，则处理器从缓存中地址 0对应的初始化指令开始， 顺序读取初始化指令； 假设当处理器读取到地址 50对应 的初始化指令时，控制器接收到跳转指令，指示需要读取地址 100对应的初始化指令， 控制器判断地址 100对应的初始化指令已经写入缓存，则控制器可以通知处理器从地 址 50对应的初始化指令处， 跳转到地址 100对应的初始化指令处进行读取。
可选的， 上述实施例中， 在 BIOS初始化操作过程中， 当处理器发出的跳转指令 指示的 FLASH上的地址所对应的初始化指令未写入为该处理器分配的缓存时，按照该 跳转指令指示的 FLASH上的地址从 FLASH读取初始化指令，将读取到的初始化指令从 为处理器分配的缓存的头部开始顺序写入该缓存，以使处理器从该缓存的头部开始读 取初始化指令。
本发明实施例中， 当一个服务器单板上包含一个控制器及至少两个 FLASH时，控 制器预先保存至少两个 FLASH中每个 FLASH与处理器的对应关系， 以及每个 FLASH 与为所述每个处理器分配的缓存的对应关系； 相应的， 控制器按照保存的每个 FLASH 与处理器的对应关系， 从与每个处理器对应的 FLASH中为处理器读取初始化指令， 并 将读取到的初始化指令按照每个 FLASH与为每个处理器分配的缓存之间的对应关系， 写入为每个处理器分配的缓存中。本发明实施例中， 当一个服务器单板上有多个控制 器时， 则每个处理器与其中一个控制器连接， 对于每一个控制器， 由该控制器为所连 接的处理器划分缓存，相应的， 每个处理器从所连接控制器为其划分的缓存上读取初 始化指令。
另外，对于系统中的处理器， 当某个处理器在预设的时间内未从为其分配的缓存 中读取初始化指令时， 则可以确定该处理器发生异常。 由于控制器为每个处理器都划 分了缓存， 因此每个处理器都从其各自的缓存中读取初始化指令， 当某个处理器发生 异常时， 不影响其他处理器从对应的缓存中读取初始化指令。
由上述实施例可见， 本发明实施例通过在系统中设置少于处理器数量的 FLASH, 从而节省了系统空间； 并且由于本发明实施例通过系统中已有的控制器上的缓存资 源，代替现有技术中与处理器数量一致的 FLASH完成对所有处理器的初始化操作， 从 而降低了整个系统的功耗。 参见图 3， 为本发明实施例中一种控制器对缓存进行读写操作的示意图： 其中， 对于每个处理器对应的一个缓存空间，控制器可以为该缓存空间分配一个 FLASH读指 针和一个 CPU读指针， FLASH读指针用于指示控制器从 FLASH中读入初始化指令， CPU 读指针用于控制器控制处理器从缓存空间读出初始化指令。
通常每个处理器都会划分出一部分地址空间用来访问 FLASH上的数据，用于系统 上电后的 BIOS初始化操作。 这部分划分出的地址空间与 FLASH地址空间一一对应， 范围由起始地址和结束地址进行限定， 其中划分出的地址空间的起始地址与 FLASH 的起始地址对应， 划分出的地址空间的起始地址与结束地址之间的空间大小与 FLASH 的空间大小一致， 以便于在读取初始化指令的过程中，根据划分出的地址空间的地址 对应到 FLASH地址空间的地址， 从而对 FLASH地址上存储的初始化指令进行读取。
本发明实施例中， 处理器不再直接从 FLASH获取初始化指令， 而是由控制器接收 处理器指示的存储空间的地址， 并按照该存储空间的地址对应到 FLASH的地址，将该 FLASH的地址上存储的初始化指令读取到为处理器分配的缓存中， 并由处理器从缓存 中读入初始化指令。 其中， 当系统上电时， 为了减小初始化操作的时间， 控制器初始 可以无需从 FLASH中读取与缓存空间大小一致的初始化指令，例如，可以首先从 FLASH 读取缓存空间大小一半的初始化指令并写入缓存，然后处理器就可以开始从缓存读取 初始化指令，后续控制器持续从 FLASH读取剩余的初始化指令并写入缓存， 而处理器 同步从缓存读取初始化指令， 直至处理器读取完所有的初始化指令。
在控制器从 FLASH读取初始化指令并写入缓存的过程中，当控制器接收到处理器 发送的跳转指令时，如果跳转指令指示的 FLASH的地址上存储的初始化指令当前已经 读取到缓存中， 则处理器直接从读取到缓存中的初始化指令开始顺序读取初始化指 令； 如果跳转指令指示的 FLASH的地址上存储的初始化指令当前还未读取到缓存中， 则控制器从该跳转指令指示的 FLASH的地址开始顺序读取初始化指令，并从缓存的头 部开始写入读取的初始化指令 （即覆盖缓存中已经读入的初始化指令）， 而处理器相 应从缓存读取跳转指令对应的初始化指令。
下面结合图 3中示出的六个阶段，对应用本发明共享闪存 FLASH的实施例中， 单 个处理器上电后的 BIOS初始化过程进行描述。
在阶段①，系统初始上电时， FLASH读指针和 CPU读指针均指示缓存空间的头部； 在阶段②， 系统初始上电后，控制器从 FLASH中读入缓存空间大小一半的初始化 指令，此时 FLASH读指针指示缓存空间的中部， CPU读指针仍然指示缓存空间的头部， 即处理器还未开始从缓存空间读取初始化指令；
在阶段③， 当控制器继续从 FLASH读入初始化指令时， FLASH读指针相应从缓存 空间中部向下移动， 此时处理器开始从缓存空间读取初始化指令， 相应的， CPU读指 针从缓存空间头部开始向下移动；
在阶段④， 当 FLASH读指针移动到缓存空间尾部时， 说明控制器已经从 FLASH 中读入了与缓存空间大小一致的初始化指令，则 FLASH指针重新跳转到缓存空间的头 部， 此时处理器继续从缓存空间读取初始化指令， CPU读指针在缓存空间内继续向下 移动；
在阶段⑤，由于缓存空间内 CPU读指针所指示位置以上的存储空间内的初始化指 令已经由处理器读取过， 因此控制器将从 FLASH读取的初始化指令写入缓存空间头 部， FLASH读指针从缓存空间的头部开始继续向下移动， 相应的， 处理器读取完缓存 空间的初始化指令后，跳转到缓存空间的头部继续读取初始化指令，此时 CPU读指针 相应跳转到缓存空间头部；
在阶段⑥， 当控制器接收到处理器发送的跳转指令， 且该跳转指令指示的 FLASH 地址上存储的初始化指令未读取到缓存空间，则 FLASH读指针和 CPU读指针同时跳转 到缓存空间的头部，后续由控制器从跳转指令指示的 FLASH的地址开始顺序读取初始 化指令，原来缓存空间中未被 CPU读指针读取完的初始化指令将被 FLASH读指针按照 跳转指令读取的初始化指令覆盖， 并重复执行从前述阶段①开始的流程，直至处理器 从缓存空间读取完 FLASH上所有的初始化指令。 与本发明共享闪存 FLASH的方法的实施例相对应，本发明还提供了控制器和共享 闪存 FLASH的系统的实施例。 参见图 4， 为本发明控制器的实施例框图， 该控制器应用在包含至少两个处理器 的系统中， 该系统还包含至少一个闪存 FLASH, 所述 FLASH的数量少于所述处理器的 数量，所述控制器包含为每个所述处理器分配的缓存，对于系统的详细描述与前述方 法实施例部分一致， 在此不再赘述。
该控制器包括： 读取单元 410和写入单元 420。
其中， 读取单元 410， 用于从所述 FLASH中为每个处理器读取初始化指令； 写入单元 420， 用于将所述读取单元 410读取到的所述初始化指令写入为每个处 理器分配的缓存中，以使所述每个处理器从分配的缓存中读取所述写入单元 420写入 的所述初始化指令。
可选的， 所述控制器还可以包括：
保存单元 430， 用于当所述系统中包含至少两个 FLASH时， 预先保存所述至少两 个 FLASH中每个 FLASH与处理器的对应关系，以及每个 FLASH与为所述每个处理器分 配的缓存的对应关系；
相应的， 所述读取单元 410， 具体用于按照所述保存单元 430保存的每个 FLASH 与处理器的对应关系， 从与每个处理器对应的 FLASH 中为所述处理器读取初始化指 令；
所述写入单元 420， 具体用于将读取到的初始化指令按照所述保存单元 430保存 的每个 FLASH与为每个处理器分配的缓存之间的对应关系，写入为每个处理器分配的 缓存中。
可选的， 读取单元 410可以包括：
第一读取子单元 411， 用于当所述系统上电时， 根据所述每个处理器指示的起始 地址从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令；
第二读取子单元 412， 用于当所述每个处理器从分配的缓存中读取所述第一初始 化指令后，所述控制器从所述 FLASH中按照地址顺序读取除所述第一初始化指令的剩 余初始化指令。
可选的， 写入单元 420， 可以具体用于将所述读取单元 410读取到的所述初始化 指令从为每个处理器分配的缓存的头部开始顺序写到所述缓存的尾部，以及当所述缓 存内写满所述初始化指令后， 重新从所述缓存的头部开始写入读取到的初始化指令， 直至所述控制器从所述 FLASH中读取完所有初始化指令。 参见图 5， 为本发明共享闪存 FLASH的系统的实施例框图： 该系统包括： 控制器 510、 若干处理器 520及至少一个闪存 FLASH530 , 该 FLASH 的数量少于处理器的数量，控制器 510包含为每个处理器分配的缓存。为了示例方便， 图 5中仅示出了三个处理器 520和一个 FLASH530。
其中， 所述控制器 510， 用于从所述 FLASH530中为每个处理器 520读取初始化 指令，将读取到的所述初始化指令写入为每个处理器 520分配的缓存中， 以使所述每 个处理器 520从分配的缓存中读取所述初始化指令。
可选的， 当所述系统中包含至少两个 FLASH时， 所述控制器 510， 还用于预先保 存所述至少两个 FLASH中每个 FLASH与处理器的对应关系，以及每个 FLASH与为所述 每个处理器分配的缓存的对应关系； 相应的， 所述控制器 510， 具体用于按照保存的 每个 FLASH与处理器的对应关系，从与每个处理器对应的 FLASH中为所述处理器读取 初始化指令，以及将读取到的初始化指令按照每个 FLASH与为每个处理器分配的缓存 之间的对应关系， 写入为每个处理器分配的缓存中。
可选的， 所述控制器 510， 可以具体用于当所述系统上电时， 根据所述每个处理 器 520指示的起始地址从所述 FLASH510中读取容量小于所述缓存的空间容量的第一 初始化指令， 当所述每个处理器 520从分配的缓存中读取所述第一初始化指令后，所 述控制器从所述 FLASH530中按照地址顺序读取除所述第一初始化指令的剩余初始化 指令。
可选的， 所述控制器 510， 可以具体用于将读取到的所述初始化指令从为每个处 理器分配的缓存的头部开始顺序写到所述缓存的尾部，当所述缓存内写满所述初始化 指令后， 重新从所述缓存的头部开始写入读取到的初始化指令，直至所述控制器从所 述 FLASH530中读取完所有初始化指令。
上述实施例中，优选的，控制器 510上为每个处理器 520分配的缓存的空间容量 可以小于所述 FLASH530的空间容量。 由上述实施例可见，本发明实施例应用在包含至少两个处理器的系统中， 该系统 还包含控制器以及至少一个 FLASH, 其中 FLASH的数量少于处理器的数量， 控制器包 含为每个处理器分配的缓存，控制器从 FLASH中为每个处理器读取初始化指令，将读 取到的初始化指令写入为每个处理器分配的缓存中，以使每个处理器从分配的缓存中 读取初始化指令。 本发明实施例通过在系统中设置少于处理器数量的 FLASH, 从而节 省了系统空间； 并且由于本发明实施例通过系统中已有的控制器上的缓存资源，代替 现有技术中与处理器数量一致的 FLASH完成对所有处理器的初始化操作，从而降低了 整个系统的功耗。
本领域的技术人员可以清楚地了解到本发明实施例中的技术可借助软件加必需 的通用硬件平台的方式来实现。基于这样的理解，本发明实施例中的技术方案本质上 或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产 品可以存储在存储介质中， 如 R0M/RAM、 磁碟、 光盘等， 包括若干指令用以使得一台 计算机设备（可以是个人计算机， 服务器， 或者网络设备等）执行本发明各个实施例 或者实施例的某些部分所述的方法。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部 分互相参见即可， 每个实施例重点说明的都是与其他实施例的不同之处。尤其， 对于 系统实施例而言， 由于其基本相似于方法实施例， 所以描述的比较简单， 相关之处参 见方法实施例的部分说明即可。
以上所述的本发明实施方式， 并不构成对本发明保护范围的限定。任何在本发明 的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明的保护范围之 内。

Claims

权 利 要 求
1、 一种共享闪存 FLASH的方法， 其特征在于， 所述方法应用在包含至少两 个处理器的系统中，所述系统还包含控制器以及至少一个闪存 FLASH,所述 FLASH 的数量少于所述处理器的数量， 所述控制器包含为每个所述处理器分配的缓存， 所述方法包括：
所述控制器从所述 FLASH中为每个处理器读取初始化指令；
将读取到的所述初始化指令写入为每个处理器分配的缓存中，以使所述每个 处理器从为其分配的缓存中读取所述初始化指令。
2、 根据权利要求 1所述的方法， 其特征在于， 当所述系统中包含至少两个
FLASH 时， 所述方法还包括： 所述控制器预先保存所述至少两个 FLASH 中每个 FLASH与处理器的对应关系， 以及每个 FLASH与为所述每个处理器分配的缓存的 对应关系；
所述控制器从所述 FLASH中为每个处理器读取初始化指令具体为：所述控制 器按照保存的每个 FLASH与处理器的对应关系，从与每个处理器对应的 FLASH中 为所述处理器读取初始化指令；
所述将读取到的所述初始化指令写入为每个处理器分配的缓存中具体为：将 读取到的初始化指令按照每个 FLASH 与为每个处理器分配的缓存之间的对应关 系， 写入为每个处理器分配的缓存中。
3、根据权利要求 1或 2所述的方法，其特征在于，所述控制器从所述 FLASH 中为每个处理器读取初始化指令， 包括：
当所述系统上电时， 控制器根据所述每个处理器指示的起始地址从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令；
当所述每个处理器从为其分配的缓存中读取所述第一初始化指令后，所述控 制器从所述 FLASH 中按照地址顺序读取除所述第一初始化指令的剩余初始化指 令。
4、 根据权利要求 1至 3任意一项所述的方法， 其特征在于， 所述将读取到 的所述初始化指令写入为每个处理器分配的缓存中， 包括：
将读取到的所述初始化指令从为每个处理器分配的缓存的头部开始顺序写 到所述缓存的尾部；
当所述缓存内写满所述初始化指令后，重新从所述缓存的头部开始写入读取 到的初始化指令， 直至所述控制器从所述 FLASH中读取完所有初始化指令。
5、 根据权利要求 1至 4任意一项所述的方法， 其特征在于， 所述为每个处 理器分配的缓存的空间容量小于所述 FLASH的空间容量。
6、 一种控制器， 其特征在于， 所述控制器应用在包含至少两个处理器的系 统中， 所述系统还包含至少一个闪存 FLASH, 所述 FLASH的数量少于所述处理器 的数量， 所述控制器包含为每个所述处理器分配的缓存， 所述控制器包括： 读取单元， 用于从所述 FLASH中为每个处理器读取初始化指令； 写入单元，用于将所述读取单元读取到的所述初始化指令写入为每个处理器 分配的缓存中，以使所述每个处理器从为其分配的缓存中读取所述写入单元写入 的所述初始化指令。
7、 根据权利要求 6所述的控制器， 其特征在于， 所述控制器还包括： 保存单元， 用于当所述系统中包含至少两个 FLASH时， 预先保存所述至少两 个 FLASH中每个 FLASH与处理器的对应关系，以及每个 FLASH与为所述每个处理 器分配的缓存的对应关系；
所述读取单元，具体用于按照所述保存单元保存的每个 FLASH与处理器的对 应关系， 从与每个处理器对应的 FLASH中为所述处理器读取初始化指令；
所述写入单元，具体用于将读取到的初始化指令按照所述保存单元保存的每 个 FLASH与为每个处理器分配的缓存之间的对应关系，写入为每个处理器分配的 缓存中。
8、 根据权利要求 6或 7所述的控制器， 其特征在于， 所述读取单元包括： 第一读取子单元， 用于当所述系统上电时， 根据所述每个处理器指示的起始 地址从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令； 第二读取子单元，用于当所述每个处理器从分配的缓存中读取所述第一初始 化指令后，所述控制器从所述 FLASH中按照地址顺序读取除所述第一初始化指令 的剩余初始化指令。
9、 根据权利要求 6至 8任意一项所述的控制器， 其特征在于，
所述写入单元，具体用于将所述读取单元读取到的所述初始化指令从为每个 处理器分配的缓存的头部开始顺序写到所述缓存的尾部，以及当所述缓存内写满 所述初始化指令后， 重新从所述缓存的头部开始写入读取到的初始化指令， 直至 所述控制器从所述 FLASH中读取完所有初始化指令。
10、 一种共享闪存 FLASH的系统， 其特征在于， 所述系统包括： 控制器、 至 少两个处理器及至少一个闪存 FLASH,所述 FLASH的数量少于所述处理器的数量， 所述控制器包含为每个所述处理器分配的缓存， 其中，
所述控制器， 用于从所述 FLASH中为每个处理器读取初始化指令， 将读取到 的所述初始化指令写入为每个处理器分配的缓存中，以使所述每个处理器从为其 分配的缓存中读取所述初始化指令。
11、 根据权利要求 10所述的系统， 其特征在于，
所述控制器， 还用于当所述系统中包含至少两个 FLASH时， 预先保存所述至 少两个 FLASH中每个 FLASH与处理器的对应关系，以及每个 FLASH与为所述每个 处理器分配的缓存的对应关系；
所述控制器， 具体用于按照保存的每个 FLASH与处理器的对应关系， 从与每 个处理器对应的 FLASH中为所述处理器读取初始化指令，以及将读取到的初始化 指令按照每个 FLASH与为每个处理器分配的缓存之间的对应关系，写入为每个处 理器分配的缓存中。
12、 根据权利要求 10或 11所述的系统， 其特征在于，
所述控制器， 具体用于当所述系统上电时， 根据所述每个处理器指示的起始 地址从所述 FLASH中读取容量小于所述缓存的空间容量的第一初始化指令，当所 述每个处理器从分配的缓存中读取所述第一初始化指令后， 所述控制器从所述 FLASH中按照地址顺序读取除所述第一初始化指令的剩余初始化指令。
13、 根据权利要求 10至 12任意一项所述的系统， 其特征在于，
所述控制器，具体用于将读取到的所述初始化指令从为每个处理器分配的缓 存的头部开始顺序写到所述缓存的尾部， 当所述缓存内写满所述初始化指令后， 重新从所述缓存的头部开始写入读取到的初始化指令， 直至所述控制器从所述 FLASH中读取完所有初始化指令。
14、根据权利要求 10至 13任意一项所述的系统， 其特征在于， 所述控制器 上为每个处理器分配的缓存的空间容量小于所述 FLASH的空间容量。
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