WO2014060631A1 - High-precision temperature-to-digital converter with low power consumption - Google Patents

High-precision temperature-to-digital converter with low power consumption Download PDF

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Publication number
WO2014060631A1
WO2014060631A1 PCT/ES2013/070720 ES2013070720W WO2014060631A1 WO 2014060631 A1 WO2014060631 A1 WO 2014060631A1 ES 2013070720 W ES2013070720 W ES 2013070720W WO 2014060631 A1 WO2014060631 A1 WO 2014060631A1
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WIPO (PCT)
Prior art keywords
temperature
digital
voltage
resistor
thermistor
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PCT/ES2013/070720
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Spanish (es)
French (fr)
Inventor
Manuel DELGADO RESTITUTO
Jesús RUIZ AMAYA
Alberto RODRÍGUEZ PÉREZ
José Antonio RODRÍGUEZ RODRÍGUEZ
Jens Masuch
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Consejo Superior De Investigaciones Científicas (Csic)
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Publication of WO2014060631A1 publication Critical patent/WO2014060631A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K2219/00—Thermometers with dedicated analog to digital converters

Definitions

  • the present invention discloses a high-precision temperature-to-digital converter with low power consumption such that the converter measures a temperature by quantifying physical parameters and converts the measurement made into a digital value that reflects the temperature value. measure.
  • the invention is part of the field of physical technologies and more, specifically, in the field of information and communications technologies in low consumption and high precision applications.
  • a particular application of the present invention is in clinical settings.
  • the present invention solves the technical problem associated with temperature measuring devices that, due to the very nature of the measuring devices, require low power consumption in their operation.
  • An example of these types of low-consumption devices are those associated with "RFID” radio frequency identifiers ("Radio Frequency IDentification").
  • RFID devices use radio frequency receiving waves as a power source instead of batteries.
  • body temperature is an essential indication of the health status of an individual, so that the use of devices for measurement is not only widespread in hospital areas, but also in domestic settings. With a view to reducing the degree of discomfort arising from the use of these devices, the latest proposals for monitoring body temperature tend to use wireless technologies.
  • a conveniently insulated sensor against environmental conditions and in direct contact with the individual under monitoring measures the temperature and transfers the measurement result to a reading instrument located within the coverage of radio frequency communications. In this way, the reading of the measurement is carried out at a distance without reducing the levels of mobility or comfort of the individual.
  • the device does not require any type of calibration during the manufacturing process or any adjustment of components prior to each measurement. This obliges the use of design strategies that mitigate and / or cancel the errors of the data acquisition and processing circuitry, so that the measurement of the temperature only counts the sensor response and is not contaminated by the imperfections of the reading circuit In this case, the accuracy and resolution of the measurement will be given directly by the tolerance of the sensor device.
  • the device for measuring body temperature has a low form factor that can be easily attached to the body, without the need to remove the device after each measurement. This not only results in greater ease of use and comfort for the patient, but also allows quick and precise measurements without the need to derive predictive values (greater uncertainty in measurement and greater power consumption due to extra circuitry). This is so, because the sensor device is at all times in contact with the body and, therefore, in a stationary regime, so it is not necessary to apply extrapolation routines.
  • the digitalization of the temperature measurement is much simpler and more efficient than in the systems based on the monitoring of potential differences.
  • the oscillator circuitry itself is sensitive and non-linear against variations with temperature, so it is generally necessary to provide external adjustment mechanisms to achieve minimum accuracy requirements.
  • a third option for the quantification of temperature increases tries to add the advantages of the previous configurations, on the one hand the simplicity of the circuitry of reading of the mechanisms based on tension and, on the other, the ease of digitization in the case of solutions based on time.
  • the present invention discloses a converter device or simply "converter" which comprises two aspects.
  • the first aspect is associated with the converter's own components, and the second aspect is associated with a particular method for measuring and digitizing the temperature in the previous converter.
  • the present invention discloses a converter whose main advantages over the state of the art are that: it is capable of measuring the temperature and transforming the measured value into a digital value in a short time interval (few seconds);
  • the present invention synergistically combines both aspects of the present invention (converter device and method).
  • the first aspect of the invention is associated with the high-precision digital-to-digital converter with low power consumption comprising:
  • a reading and conversion circuit that measures the resistance of the thermistor and converts said temperature representative value into a digital code for further processing; such that the resistor and thermistor RTH, on the one hand, and resistor RP, on the other, form two circuit branches that are connected at one end to a common node and where the resulting three terminals are connected to as many nodes of the circuit of reading and conversion.
  • the previously defined temperature reading and conversion circuit in turn comprises:
  • VCM mixed signal processing core common
  • VREFN negative reference voltage
  • VREFP positive reference voltage
  • the clock phase generator which receives a "CLKTS” clock signal and sends to the mixed signal processing core a signal formed by pulse trains of the same frequency as the "CLKTS” clock signal received; in addition, the clock phase generator is connected to the digital control to which it sends a clock signal "CLKTSYS” identical to the clock signal "CLKTS” but with a delay of two delay units;
  • the digital control has a RESET input, a TRDY binary output and an NTEMP output that represents the temperature measured digitally.
  • the reference voltage generator included in the temperature reading and conversion circuit described above comprises:
  • VBG stable voltage
  • VSSA negative power rail
  • VDDA positive power rail
  • a resistive divider that in turn comprises three temperature-insensitive resistors
  • each of the analog keys is several orders of magnitude lower than the resistors of the RTH thermistor, the RP resistor and the RS resistor.
  • the operational amplifier together with the resistive branches (RTH thermistor, RP resistor, RS resistor) and the CINT integration capacitor (externally connected between the VN and VO nodes) form a Miller dual-input integrator (the terminals of the non-resistive branches connected to each other) capable of generating triangular analog signals by properly controlling the logic signals generated in the digital control circuit.
  • the analog key assemblies connect the terminals of the Miller integrator in a complementary way to one or another reference voltage of those provided by the generator circuit. All active elements of the converter can be implemented so that they are virtually immune to variations in the supply voltage (high PSRR of the "Power Supply Rejection Ratio") so that the set is appropriate in applications where energy resources can Be potentially unstable.
  • the other aspect of the invention is the method for measuring and digitizing the resistance of the RTH thermistor comprised in the high-precision digital-to-digital converter with low power consumption defined above, where the method comprises the following four stages that follow one after the other. :
  • AU O-CALIBRATION • a second stage, called AU O-CALIBRATION, where the external thermistor is short-circuited and two ramps are generated at the output of the operational amplifier, one positive and the other negative;
  • the first ramp has a fixed duration of NI clock cycles with FTS frequency and is obtained by connecting the resistor branch RP to a VREFP voltage and the resistor branch RS to a VREFN voltage;
  • the second ramp is generated by connecting the branch of the resistor RP to a virtual ground node and the branch of the resistor RS to a VREFP voltage and concludes when the comparator detects that the output of the operational amplifier is less than the common mode voltage;
  • the duration of this second ramp is monitored by a counter that determines the number of clock cycles, N2AU, contained in said interval, once the self-calibration stage is concluded, the N2AU value is stored in an address of the digital register;
  • the MEASURE stage • a fourth stage, called the MEASURE stage, where the AUTO-CALIBRATION stage is repeated, only that, in this case, the RTH thermistor is not short-circuited and the duration of the second ramp during the measurement stage is monitored by a counter that determines the number of clock cycles, N2TH, contained in said interval; Once the measurement stage is completed, the N2TH value is stored in another address of the digital register;
  • the impact of the imperfections of the analog circuitry included in the active circuit linked to the digital-to-digital converter is null in the first approximation since both the self-calibration and measurement stage follow
  • the same operating protocol and non-ideal components of the terms N2AU and N2TH are canceled when the incremental value is calculated.
  • the NI value and the frequency of operation of the converter are high enough (to reduce the quantization error inherent in the digital count)
  • the accuracy in measuring the temperature at a given reading time is basically given for thermistor tolerance. Therefore, there is no need for calibration during the calibration phase of the device.
  • Figure 1 represents a block diagram of the temperature-to-digital converter according to an embodiment of the present invention.
  • the digital-to-digital converter comprises a "REFERENCE VOLTAGE GENERATOR” block, a “CLOCK PHASE GENERATOR” block, a “MIXED SIGNAL CORE” block and a "DIGITAL CONTROL” block.
  • Figure 2 depicts a block diagram of the reference voltage generator according to an embodiment of the present invention comprising a temperature stable voltage generator, a resistive divider, three voltage followers and a set of capacitors.
  • Figure 3 shows a time diagram of the input / output signals involved in the clock phase generation block according to an embodiment of the present invention.
  • Figure 4 shows an embodiment of the circuit that implements the "CLOCK PHASE GENERATOR” block.
  • Figure 5 represents the block diagram of the mixed signal processing core “SIGNAL-MIXED NUCLEUS” according to an embodiment of the invention, comprising an analog key structure, an "OTA” transconductance amplifier, a comparator " COMP “and control logic.
  • Figure 6 shows a time diagram of the main signals involved in the mixed signal processing core "MIXED SIGNAL NUCLEUS" during the measurement process of the temperature-to-digital converter (method for measuring and digitizing the resistance of the RTH thermistor ) according to an embodiment of the present invention.
  • Figure 7 represents the block diagram of the digital control circuit "DIGITAL CONTROL" according to an embodiment of the present invention.
  • FIG. 1 represents the block diagram of the temperature-to-digital converter 1000 according to an embodiment of the present invention.
  • Said converter 1000 comprises, as active elements, a reference voltage generator 1100, a clock phase generator 1200, a mixed signal processing core 1300 and a digital control block 1400.
  • Analog blocks 1100 and 1300 employ currents of polarization that are preferably synthesized from a temperature-insensitive current cell with compensated curvature and distributed as many times as necessary using current mirrors.
  • the active blocks 1100-1400 are integrated in a single manufactured microchip on a substrate that is chosen from: silicon, silicon on insulator, silicon-germanium, indium phosphide and gallium arsenide.
  • a substrate that is chosen from: silicon, silicon on insulator, silicon-germanium, indium phosphide and gallium arsenide.
  • silicon substrate is used.
  • the temperature-to-digital converter 1000 comprises several passive elements. Specifically, it has a thermistor 1510, whose resistance RTH depends on the temperature and a set of reference devices with virtually invariable values with the temperature formed by a resistor 1520 with RS resistance, a resistor 1530 with RP resistance and an integration capacitor 1540 with CINT capacity.
  • the thermistor 1510 and the resistors RS 1520 and RP 1530 satisfy the RS + RTH ⁇ RP condition, in the entire range of temperature variation for which the 1000-to-digital converter 1000 is designed.
  • the inputs to the temperature-to-digital converter 1000 are RESET and CLKTS.
  • the RESET signal is a step signal used to start the measurement process of the 1000 digital-to-digital converter and to bring the digital control means 1400 to their default values.
  • the start of the measurement process occurs with the rising edge of the RESET signal, while the reset of control logic 1400 occurs with the falling edge of the RESET signal.
  • the minimum time in which the RESET signal must remain with a logical ⁇ 0 'value to reset the state of digital logic 1400 is one cycle of the CLKTS reference clock.
  • Said CLKTS signal is a periodic pulse train with known frequency FTS, which is used for the generation of the logic control signals and for sequencing the operation of the digital block 1400.
  • the output of the temperature-to-digital converter 1000 is given by two signals that are TRDY and NTEMP ⁇ LNT-1: 0>.
  • TRDY is a control signal that is activated when data related to body temperature measurement is available and deactivated when a new measurement cycle begins. Accordingly, the TRDY signal remains at logic ⁇ 0 'after the system reset and takes the logical value ⁇ 1' when the measurement process ends.
  • NTEMP ⁇ LNT-1: 0> is a serial digital representation of an LNT number of bits representative of temperature measurement, in accordance with the present invention. Additionally, the temperature-to-digital converter 1000 provides the TRTH, TRS, VN, TRP and VO terminals for the connection of discrete devices 1510, 1520, 1530 and 1540 as shown in Figure 1.
  • the reference voltage generator 1100 of the temperature-to-digital converter 1000 is responsible for providing stable and regulated voltages to the analog core 1300, from stable power rails, VDDA and VSSA.
  • Block 1100 provides three output voltages, VCM, VREFN and VREFP.
  • the first (VCM) is the common mode of the circuit, and the remaining ones (VREFN and VREFP) are negative and positive reference voltages displaced below and above the common mode value, respectively.
  • Figure 2 shows the internal block diagram of a particular embodiment of the reference voltage generator 1100 and preferably comprises a block 1110 that provides a stable voltage-insensitive VBG voltage, a resistive divider 1120, disposed between the VBG and VSSA terminals, formed by three insensitive resistors with temperature 1121, 1122 and 1123 at whose intermediate nodes the voltage values scaled VTP, VTM and VTN are generated; three tension followers 1130, 1140 and 1150, which obtain the voltages VREFP, VCM and VREFN from the tensions in the intermediate nodes of the resistance ladder, VTP, VTM and VTN, respectively; and a capacitive network 1160 formed by capacitors 1161, 1162 and 1163 connected, respectively, between the outputs of the voltage followers 1130, 1140 and 1150 and the negative feed rail VSSA.
  • a block 1110 that provides a stable voltage-insensitive VBG voltage
  • a resistive divider 1120 disposed between the VBG and VSSA terminals, formed by three insensitive resistors with temperature
  • Followers 1130, 1140 and 1150 are used to stabilize the output voltages of the reference generator against variations in load conditions.
  • Capacitors 1161, 1162 and 1163 are used to increase the variation time constants of the corresponding nodes and decrease the contributions of thermal noise in the output voltages VREFP, VCM and VREFN.
  • FIG 3 shows the time diagram 1201 of the signals involved in the clock phase generator 1200.
  • the clock phase generator 1200 receives the CLKTS signal as input and produces two outputs, CLKTSYS and STROBE.
  • the first, CLKTSYS is a copy of the CLKTS input signal delayed by two delay units, each of DEL duration.
  • the second, STROBE is a train of periodic pulses with the same frequency as the CLKTS input signal.
  • the rising edges of the STROBE and CLKTS signals are aligned but, in the case of the STROBE signal, the duration of the state ⁇ 1 'is only one delay unit, DEL.
  • the duration DEL of the delay unit is typically of the order of nanoseconds and, therefore, much less than the duration of a half-period of the CLKTS signal.
  • FIG 4 shows the block diagram of a possible embodiment of the clock phase generator 1200.
  • the digital tracker chains 1210 and 1220 each introduce a delay DEL in the propagation of their respective input signals. Consequently, the CLKTSYS signal accumulates a delay with respect to the CLKTS signal.
  • the inverter 1240 together with the NAND gate 1230 whose inputs are, on the one hand, the CLKTS signal and, on the other, the output of the chain of buffers 1210, generate the STROBE signal with the temporal characteristics indicated above in the Figure 3.
  • the delay caused by the concatenation of the NAND gate 1230 and the inverter 1240 is much less than the delay DEL generated by the digital tracker chains 1210 or 1220. All logic gates included in the clock phase generator use digital power rails, VDDD and VSSD.
  • the mixed-signal processing core 1300 of the temperature-to-digital converter 1000 generates a single logic output COMP that is transferred to the digital control block 1400 and has as input the reference voltages VREFP, VREFN and VCM obtained in the generator reference voltages 1100; a set of two SRTH and SRB logic signals from the digital control block 1400; and a STROBE logic signal provided by the clock phase generator 1200. Additionally, the core 1300 has the terminals TRTH, TRS, VN, TRP and VO for the connection of discrete devices 1510, 1520, 1530 and 1540, such as Figure 1 shows. Unless explicitly stated otherwise, all circuit elements included in the 1300 mixed-signal processing core employ analog, VDDA and VSSA power rails.
  • the objective of the mixed signal processing core 1300 is to perform a resistance-to-time transformation so that the difference between the resistors of the thermistor 1510 and the linear resistor 1530 is quantified by time intervals whose duration It depends on the value of these resistors. Since the resistance RTH of the thermistor 1510 depends on the temperature while the resistance RP of the resistor 1530 is virtually invariable with the temperature, the measurement made in this block indirectly reflects the temperature to which the thermistor 1510 is exposed.
  • Figure 5 shows the block diagram of a possible embodiment of the mixed-signal processing core 1300 of the temperature-to-digital converter 1000 comprising an operational transconductance amplifier 1370, a comparator 1380 connected to the VO output of the amplifier 1370 and a set of two logical inverters 1390 to obtain the denied signals SRTHN and SRBN of the control signals SRTH and SRB, respectively.
  • 1390 inverters use digital power rails, VDDD and VSSD.
  • the 1380 comparator detects the sign of the difference in VO-VCM voltages in the moments defined by the STROBE signal provided by the clock phase generator 1200.
  • the non-inverting terminal of the amplifier 1370 is connected to the common mode voltage VCM generated by the generator of reference voltages 1100.
  • a first resistive branch comprises the analog keys 1310, 1320 , 1330 and 1340, controlled by the logic signals SRB, SRTH, SRBN and SRTHN, respectively; thermistor 1510 (connected between nodes TRTH and TRS); and the 1520 series resistor (connected between the TRS and VN nodes).
  • a second branch comprises analog keys 1350 and 1360, controlled by the logic signals SRB and SRBN, respectively; and parallel resistor 1530 (connected between nodes TRP and VN).
  • the ON resistance of the analog keys included in the mixed-signal processing core 1300 is in all cases several orders of magnitude less than the resistances of the discrete components 1510, 1520 and 1530.
  • the operational amplifier 1370 together with the resistive branches and the capacitor 1540 (externally connected between the VN and VO nodes) form a double-input Miller integrator (the terminals of the non-connected resistive branches) capable of generating triangular analog signals by the adequate control of the logic signals generated in the digital control circuit 1400.
  • the operation of the mixed-signal processing core 1300 is divided into four phases, called AUTO-ZERO 1, AUTO-CALIBRATE, AUTO-ZERO 2 AND MEASURE, which are exemplified in time diagram 1301 of Figure 6.
  • a first phase called the AUTO-ZERO 1 phase
  • the SRTH logic signal is high ⁇ 1 '
  • analog key 1320 is closed while 1340 is open
  • thermistor 1510 is isolated from the rest of the circuitry.
  • the control signal SRB can take one or another logical value.
  • the VO-VCM sign is positive
  • the comparator output 1380 takes the value ⁇ 1 '
  • the digital control block 1400 causes the SRB control signal to take the value ⁇ 1' so that the keys 1310 and 1350 are closed while keys 1330 and 1360 are open.
  • the parallel resistor 1530 is shorted and the series resistor 1520 is connected to the positive reference voltage VREFP.
  • the time diagram in Figure 6 illustrates the state of the signals in this first case.
  • the VO-VCM sign is negative
  • the output of comparator 1380 takes the value ⁇ 0 '
  • the digital control block 1400 causes the SRB control signal to take the value ⁇ 0' so that the keys 1310 and 1350 are open while keys 1330 and 1360 are closed.
  • the parallel resistor 1530 is connected to the positive reference voltage VREFP while the series resistor 1520 is connected to the negative reference voltage VREFN.
  • the output voltage VO of the amplifier 1370 evolves towards the value of the common mode voltage VCM, such that the absolute value of the VO-VCM difference is reduced until it is canceled.
  • the AUTO-ZERO 1 phase concludes when the output of comparator 1380 changes state.
  • the SRTH logic signal is high ⁇ 1 '
  • the analog key 1320 is closed while the 1340 is open
  • the thermistor 1510 is isolated from the rest of the circuitry.
  • the AUTO-CALIBRATION phase is divided into two stages. In a first stage, the control signal SRB takes the value ⁇ 0 'so that the VO output of the amplifier 1370 grows linearly with time.
  • the digital control block 1400 keeps the SRB signal in the ⁇ 0 'state for a period of time corresponding to NI cycles of the CLKTSYS clock, provided by the clock phase generator 1200.
  • the integration capacitor 1540 with CINT capability must be choose in such a way that after the NI cycles, the VO voltage does not exceed the output range of amplifier 1370.
  • the means and procedures for performing this action will be detailed below.
  • the SRB control signal takes the value ⁇ 1 'so that the VO output of amplifier 1370 decreases linearly with time. This configuration is maintained until comparator 1380 detects that the VO-VCM sign is negative, at which point the phase of O-CALIBRATED AU concludes.
  • the time elapsed during this second stage is measured in the digital control block 1400 as the number of complete clock cycles CLKTSYS, N2AU ⁇ LNT-1: 0>, counted since the control signal SRB takes the value ⁇ 1 'until that the output of comparator 380 takes the value ⁇ 0 '.
  • a third phase called the AUTO-ZERO 2 phase
  • This phase has the task of setting the output voltage VO of the amplifier 1370 to the value of the mode voltage VCM common before beginning the MEASURE phase (fourth phase in the operation of the 1300 mixed-signal processing core). It must be taken into account that the 1380 comparator operates in discrete instants of time according to the pulses contained in the STROBE periodic train.
  • a fourth and final phase called the MEASURE phase
  • the SRTH logic signal is at a high level ⁇ 0 '
  • the analog key 1320 is open while the 1340 is closed
  • the thermistor 1510 is connected in series with the resistor 1520.
  • the procedures used in the MEASURE phase are identical to those used in the SELF-CALIBRATION phase.
  • the number of complete CLKTSYS clock cycles counted in digital control block 1400 during the second stage of the MEASURE phase is N2TH ⁇ LNT-1: 0>.
  • the length of the digital word N2TH is identical to that used by the word N2AU, that is, LN.
  • the digital control block 1400 of the temperature-to-digital converter 1000 receives CLKTSYS, RESET and COMP signals as input signals; and generates the output signals, SRTH, SRB, TRDY and NTEMP ⁇ LNT-1: 0>.
  • the CLKTSYS signal timing the sequence of operations of the digital control block 1400 and synchronizes the state of the digital gates with their falling edges.
  • the RESET signal restarts the status of the digital control block 1400 before starting the measurement process.
  • the COMP signal is the output of comparator 1380 and is used as a control signal for the activation or deactivation of the SRTH and SRB signals according to the procedure described in relation to Figure 6.
  • the TRDY signal indicates when the measurement process has concluded in which case it takes the logical value ⁇ 1 '; by default it is in ⁇ 0 'logical.
  • NTEMP is the representative value of the temperature measured by the 1000 digital-to-digital converter. All circuit elements included in the digital control block use digital power rails, VDDD and VSSD.
  • Figure 7 shows a possible implementation of the digital control logic 400 comprising a control block 1410, a binary counter 1420 and a combinational adder 1430.
  • the control block 1410 is activated with the falling edges of the CLKTSYS clock and carries out four basic operations: first, it monitors the status of the COMP signal and according to its value, activates or deactivates the SRTH and SRB signals as detailed in relation to figure 6; second, it manages the control of the counter 1420 to be able to determine the number of cycles elapsed during the generation of the up and down ramps of the Miller integrator of Figure 5; third, it stores the numbers of cycles elapsed during the AUTO-CALIBRATION phase, N2AU ⁇ LNT-1: 0>, and the MEASURE phase N2TH ⁇ LNT-1: 0>; and fourth, set the TRDY signal to value logical ⁇ 1 'when the measurement process concludes.
  • control block 1410 uses the falling edge of the RESET input signal to reset the logic gates to its default value, and the rising edge of said signal to establish the start of the measurement process.
  • counter 1420 is a synchronous LNT bit counter active by rising edges of the CLKTSYS clock.
  • Counter 1420 has the CLKTSYS, RESET, ENABLE and CLR signals as inputs and generates the digital word C ⁇ LNT-1: 0> as output, which accounts for the number of clock cycles elapsed while the counter is active.
  • the word C ⁇ LNT-1: 0> is transferred to any of the digital registers available in the control block 1410 for further processing.
  • the RESET signal at a low level, or the CLR signal at a high level reset the counter 1420.
  • the ENABLE signal at a high level activates the operation of the counter 1420 and at a low level, deactivates it.
  • Block 1430 is a combinational adder that obtains the difference between the values N2AU ⁇ LNT-1: 0> and N2TH ⁇ LNT-1: 0> and provides the output of digital block 1400, NTEMP ⁇ LNT-1: 0>, this is,
  • NTEMP N2 AU - N2TH ( ⁇
  • the digital word NTEMP is, in fact, the representative value of the temperature measured by the digital-to-digital converter 1000. It can be checked analytically that the resistance value of the thermistor 1510 can be approximated by an RTH A value that is related , in first approximation, with the value of NTEMP by the equation: NTEMP
  • NTEMP uniquely determines the approximate value RTH A of the resistance of thermistor 1510.
  • N1 RTH of the CLKTSYS watch used in temperature measurement N1 RTH of the CLKTSYS watch used in temperature measurement.
  • said number of cycles must be chosen so that the discretization error is negligible compared to the usual tolerances in thermistors.
  • the precision in the measurement of the temperature in a given reading time is basically given by the tolerance of the thermistor which, by means of appropriate calibration techniques, can reach accuracies of the order of + 0.01 ° C in the range from 0 to 70 ° C.
  • the temperature-to-digital converter is used for clinical purposes to measure the body temperature of patients.
  • the converter uses an interchangeable thermistor in direct contact with the individual's skin and reaches an accuracy of approximately + 0.1 ° C (limited by the thermistor tolerance) in a temperature range of 30-45 ° C.
  • the active reading and conversion circuit can operate with intonation supply voltages to IV and, for an FTS operating frequency of around 3-4kHz, it obtains a consumption of around 4 microwatts.
  • the time taken by the device for measuring and converting body temperature is of the same order of magnitude as clinical thermometers based on infrared detection (of the order of seconds), however, aspects such as the cost of implementation, consumption of current or form factor are much lower in this embodiment of the present invention.

Abstract

The invention relates to a high-precision temperature-to-digital converter with low power consumption. The power is obtained from wireless waves. The invention also relates to a method for measuring the temperature associated with the converter. The converter comprises a thermistor RTH (1510), the resistance of which depends on the temperature; a resistor RP (1530), a resistor RS (1520), and an integration capacitor CINT (1540) which are temperature invariable; and a reading and conversion circuit (1300) that measures the resistance of the thermistor and converts said value representative of the temperature into a digital code for subsequent processing. The method comprises fours steps such that the resistance of the RTH thermistor is proportional to an expression dependent on the temperature NTEMP.

Description

DESCRIPCIÓN  DESCRIPTION
CONVERTIDOR TEMPERATURA-A-DIGITAL DE ALTA PRECISIÓN CON BAJO CONSUMO DE POTENCIA HIGH PRECISION TEMPERATURE-TO-DIGITAL CONVERTER WITH LOW POWER CONSUMPTION
Objeto de la invención Object of the invention
La presente invención divulga un convertidor temperatura-a-digital de alta precisión con bajo consumo de potencia de tal forma que el convertidor mide una temperatura mediante la cuantificación de parámetros físicos y convierte la medida realizada en un valor digital que refleja el valor de la temperatura medida. The present invention discloses a high-precision temperature-to-digital converter with low power consumption such that the converter measures a temperature by quantifying physical parameters and converts the measurement made into a digital value that reflects the temperature value. measure.
La invención se enmarca dentro del sector de las tecnologías físicas y más, en concreto, en el ámbito de las tecnologías de la información y las comunicaciones en aplicaciones de bajo consumo y alta precisión. Una particular aplicación de la presente invención se encuentra en entornos clínicos . The invention is part of the field of physical technologies and more, specifically, in the field of information and communications technologies in low consumption and high precision applications. A particular application of the present invention is in clinical settings.
La presente invención resuelve el problema técnico asociado con dispositivos de medición de temperatura que, debido a la propia naturaleza de los dispositivos de medición, precisan consumos bajos de potencia en su funcionamiento. Un ejemplo de estos tipos de dispositivos de bajo consumo, son los asociados con identificadores por radiofrecuencia "RFID" (de sus siglas en inglés "Radio Frequency IDentification" ) . Los dispositivos de tipo RFID utilizan las ondas receptoras de radiofrecuencia como fuente de alimentación en lugar de baterías . The present invention solves the technical problem associated with temperature measuring devices that, due to the very nature of the measuring devices, require low power consumption in their operation. An example of these types of low-consumption devices are those associated with "RFID" radio frequency identifiers ("Radio Frequency IDentification"). RFID devices use radio frequency receiving waves as a power source instead of batteries.
Antecedentes de la invención Background of the invention
Uno de los sectores de la técnica de especial relevancia de la presente invención, aunque no el único, es la aplicación en entornos clínicos. Dentro de los entornos clínicos, la temperatura corporal es un indicativo esencial del estado de salud de un individuo, por lo que la utilización de aparatos para su medición está no sólo extendida en recintos hospitalarios, sino también en entornos domésticos. Con vistas a reducir el grado de incomodidad derivados del uso de estos aparatos, las últimas propuestas para la monitorización de la temperatura corporal tienden al uso de tecnologías inalámbricas. En estos sistemas, un sensor convenientemente aislado frente a condiciones ambientales y en contacto directo con el individuo bajo monitorización mide la temperatura y transfiere el resultado de la medición a un instrumento lector localizado dentro de la cobertura de las comunicaciones a radio frecuencia. De este modo, la lectura de la medición se realiza a distancia sin reducir los niveles de movilidad o confort del individuo . One of the sectors of the art of special relevance of the present invention, although not the only one, is the application in clinical settings. Within clinical settings, body temperature is an essential indication of the health status of an individual, so that the use of devices for measurement is not only widespread in hospital areas, but also in domestic settings. With a view to reducing the degree of discomfort arising from the use of these devices, the latest proposals for monitoring body temperature tend to use wireless technologies. In these systems, a conveniently insulated sensor against environmental conditions and in direct contact with the individual under monitoring measures the temperature and transfers the measurement result to a reading instrument located within the coverage of radio frequency communications. In this way, the reading of the measurement is carried out at a distance without reducing the levels of mobility or comfort of the individual.
Con vistas a alargar el tiempo de vida útil del dispositivo sensor y favorecer su reutilización, es necesario el uso de técnicas de bajo consumo de potencia que además proporcionen una rápida lectura de la temperatura, sin perjuicio de la precisión necesaria en aplicaciones clínicas (aproximadamente +0.1°C en un rango de 30-45°C) . Estos requisitos son incluso más importantes en sistemas inalámbricos en los que los recursos energéticos no proceden de baterías sino que se generan a partir del procesamiento de variables del entorno, como ocurre en tecnologías RFID ("Radio Frequency IDentification" ) pasivas. En este caso, resulta además prioritario que las mediciones del sensor sean esencialmente inmunes a la influencia de los cambios en la tensión de alimentación. With a view to lengthening the lifetime of the sensor device and favoring its reuse, it is necessary to use low power consumption techniques that also provide a rapid temperature reading, without prejudice to the precision required in clinical applications (approximately + 0.1 ° C in a range of 30-45 ° C). These requirements are even more important in wireless systems where energy resources do not come from batteries but are generated from the processing of environmental variables, as in passive RFID (Radio Frequency IDentification) technologies. In this case, it is also a priority that the sensor measurements are essentially immune to the influence of changes in the supply voltage.
Además, con el objetivo de reducir los costes de producción, resulta conveniente que el dispositivo no requiera ningún tipo de calibrado durante el proceso de fabricación ni ningún ajuste de componentes previo a cada medida. Ello obliga al empleo de estrategias de diseño que atenúen y/o cancelen los errores propios de la circuitería de adquisición y procesado de datos, de modo que la medición de temperatura de cuenta exclusivamente de la respuesta del sensor y no esté contaminada por las imperfecciones del circuito de lectura. En tal caso, la precisión y resolución de la medición vendrá dada directamente por la tolerancia del dispositivo sensor. In addition, in order to reduce production costs, it is convenient that the device does not require any type of calibration during the manufacturing process or any adjustment of components prior to each measurement. This obliges the use of design strategies that mitigate and / or cancel the errors of the data acquisition and processing circuitry, so that the measurement of the temperature only counts the sensor response and is not contaminated by the imperfections of the reading circuit In this case, the accuracy and resolution of the measurement will be given directly by the tolerance of the sensor device.
Por último, es importante que el aparato para la medición de temperatura corporal tenga bajo factor de forma que se pueda adosar fácilmente al cuerpo, sin que haya necesidad de retirar el dispositivo tras cada medida. Esto no sólo redunda en una mayor facilidad de uso y comodidad para el paciente, sino que, permite medidas rápidas y precisas sin necesidad de derivar valores predictivos (mayor incertidumbre en la medida y mayor consumo de potencia por la circuiteria extra) . Esto es asi, porque el dispositivo sensor está en todo momento en contacto con el cuerpo y, por tanto, en régimen estacionario, por lo que no hace falta aplicar rutinas de extrapolación. Finally, it is important that the device for measuring body temperature has a low form factor that can be easily attached to the body, without the need to remove the device after each measurement. This not only results in greater ease of use and comfort for the patient, but also allows quick and precise measurements without the need to derive predictive values (greater uncertainty in measurement and greater power consumption due to extra circuitry). This is so, because the sensor device is at all times in contact with the body and, therefore, in a stationary regime, so it is not necessary to apply extrapolation routines.
A lo largo de los años, se han propuesto numerosos métodos y aparatos para medir la temperatura corporal, desde el tradicional termómetro de mercurio hasta los más recientes dispositivos basados en tecnología de infrarrojos. Son, sin embargo, los convertidores temperatura-a-digital basados en termistores intercambiables, los que mejor se ajustan al paradigma de bajo coste e inocuidad en el uso. Estos convertidores se basan en última instancia en la cuantificación y digitalización de la diferencia entre las resistencias de un termistor y un resistor insensible a las variaciones con la temperatura. En unos casos dicha diferencia se transforma en un incremento de potencial que posteriormente se convierte a formato binario mediante un convertidor analógico-digital . Este tipo de convertidores se encuentran divulgados en el estado de la técnica en la Patente US-B2-7497615 "Digital temperature sensor, and system and method for measuring temperature", en la Patente US-A-4130019 "Self- compensating thermocouple reading circuí t" o en la Patente US-A- 4114442. "Temperature monitoring system". El procedimiento es similar al que se emplea en sensores semiconductores inteligentes en los que se compara una tensión PTAT (del inglés "Proportional to Absolute Temperature") con la salida, aproximadamente independiente de la temperatura, de un generador de tensiones de referencia. El procedimiento está descrito en la solicitud de Patente US-A1- 2012/0106589 "Body temperature measuring system, data reading device, and drívíng control method thereof" o en la Patente US-A-4448549 "Temperature sensing device". El problema de estas configuraciones es que las variaciones de tensión inducidas por los cambios de temperatura son pequeñas lo que exige convertidores de datos de altas prestaciones, usualmente con mecanismos de corrección de no- idealidades y calibrado, que aumentan el consumo del convertidor temperatura-a-digital. Alternativamente, los incrementos entre las resistencias del termistor y la referencia se miden en tiempo en lugar de en tensión, de forma que la variable representativa de la temperatura se expresa en función de frecuencias de oscilación o duraciones de pulsos eléctricos. Esta solución requiere el uso de osciladores controlados, como por ejemplo por anillos de inversores (ver estado de la técnica: Patente US-B2-6695475 "Temperature sensing circuit and method" o Patente US-A-4602871 "Thermistor thermometer") , osciladores de relajación (ver estado de la técnica: Patente US-A- 5317520 "Computeri zed remote resistance measurement system with fault detection" o Patente US-A-4480312 "Temperature sensor/controller system") u osciladores RC (ver estado de la técnica: Patente US-B2- 8025438 "Electronic clinical thermometer, method of controlling the same, and control program" o la Patente US-B2-7778791 "Electronic clinical thermometer, method of controlling the same, and control program") . La digitalización de la medida de temperatura, basada en recuentos digitales a partir de un reloj estable con la temperatura, es mucho más simple y eficiente que en los sistemas basados en la monitorización de diferencias de potencial. Sin embargo, la circuiteria del propio oscilador es sensible y no-lineal frente a variaciones con la temperatura, por lo que es generalmente necesario proporcionar mecanismos de ajuste externos para lograr unos requisitos mínimos de precisión. Una tercera opción para la cuantificación de incrementos de temperatura trata de sumar las ventajas de las anteriores configuraciones, por un lado la simplicidad de la circuiteria de lectura de los mecanismos basados en tensión y, por otro, la facilidad de digitalización en el caso de soluciones basadas en tiempo. La idea consiste en generar señales dinámicas que evolucionen de forma proporcional al valor de la resistencia del termistor o de la referencia, de forma que la conversión de datos también se realice mediante recuentos digitales (ver estado de la técnica: solicitud de Patente US-A1-2011/0098966 "Electronic clinical thermometer and operatíon control method" o la Patente n° US-A-4270119 "Dual slope system A-D converter") . Desafortunadamente, las soluciones propuestas son muy sensibles a las variaciones de la tensión de alimentación del circuito de lectura y no cancelan completamente las no-idealidades del mismo por lo que la precisión alcanzada es limitada. Over the years, numerous methods and devices have been proposed to measure body temperature, from the traditional mercury thermometer to the latest devices based on infrared technology. They are, however, temperature-to-digital converters based on interchangeable thermistors, which best fit the paradigm of low cost and safety in use. These converters are ultimately based on the quantification and digitization of the difference between the resistors of a thermistor and a resistor insensitive to variations with temperature. In some cases this difference is transformed into an increase in potential that is subsequently converted to a binary format using an analog-digital converter. These types of converters are disclosed in the state of the art in US-B2-7497615 "Digital temperature sensor, and system and method for measuring temperature", in US-A-4130019 "Self-compensating thermocouple reading circuí t "or in US-A-4114442." Temperature monitoring system ". The procedure is similar to that used in intelligent semiconductor sensors in which a PTAT voltage (from "Proportional to Absolute Temperature") is compared with the output, approximately independent of temperature, of a reference voltage generator. The procedure is described in patent application US-A1- 2012/0106589 "Body temperature measuring system, data reading device, and drívíng control method thereof" or in US-A-4448549 "Temperature sensing device". The problem with these configurations is that the voltage variations induced by the temperature changes are small, which requires high-performance data converters, usually with non-ideality correction and calibration mechanisms, which increase the consumption of the temperature-to converter. -digital. Alternatively, the increments between the thermistor resistors and the reference are measured in time instead of voltage, so that the representative variable of the temperature is expressed as a function of oscillation frequencies or duration of electrical pulses. This solution requires the use of controlled oscillators, such as inverter rings (see prior art: US-B2-6695475 "Temperature sensing circuit and method" or US-A-4602871 "Thermistor thermometer"), oscillators of relaxation (see state of the art: US-A-5317520 "Computeri zed remote resistance measurement system with fault detection" or US-A-4480312 "Temperature sensor / controller system") or RC oscillators (see state of the art : US-B2- 8025438 "Electronic clinical thermometer, method of controlling the same, and control program" or US-B2-7778791 "Electronic clinical thermometer, method of controlling the same, and control program"). The digitalization of the temperature measurement, based on digital counts from a stable clock with the temperature, is much simpler and more efficient than in the systems based on the monitoring of potential differences. However, the oscillator circuitry itself is sensitive and non-linear against variations with temperature, so it is generally necessary to provide external adjustment mechanisms to achieve minimum accuracy requirements. A third option for the quantification of temperature increases tries to add the advantages of the previous configurations, on the one hand the simplicity of the circuitry of reading of the mechanisms based on tension and, on the other, the ease of digitization in the case of solutions based on time. The idea is to generate dynamic signals that evolve proportionally to the value of the resistance of the thermistor or of the reference, so that the data conversion is also carried out by means of digital counts (see state of the art: patent application US-A1-2011 / 0098966 "Electronic clinical thermometer and operation control method" or the Patent No. US-A-4270119 "Dual slope system AD converter"). Unfortunately, the proposed solutions are very sensitive to variations in the supply voltage of the reading circuit and do not completely cancel the non-idealities of the same, so the accuracy achieved is limited.
Por tanto, no hay en el estado de la técnica dispositivos convertidores temperatura-a-digital que, siendo de bajo consumo (micro-amperios), disponga de una suficiente precisión en la medida y de una suficiente inmunidad frente a imperfecciones de los componentes comprendidos en el dispositivo. Therefore, there are no devices in the state of the art temperature-to-digital converter devices that, being of low consumption (micro-amps), have sufficient measurement accuracy and sufficient immunity against imperfections of the components included on the device
Descripción de la invención Description of the invention
Analizados los antecedentes de la invención, se plantea como problema técnico a resolver encontrar un dispositivo convertidor de temperatura-a-digital de alta precisión con bajo consumo de potencia e inmune a las imperfecciones de los componentes comprendidos en el dispositivo . Analyzed the background of the invention, it is proposed as a technical problem to solve finding a high-precision digital-to-digital converter device with low power consumption and immune to the imperfections of the components included in the device.
En el contexto de la presente invención, se considera bajo consumo de potencia al orden de magnitud del micro-amperio. In the context of the present invention, it is considered low power consumption at the order of magnitude of the micro-ampere.
Para solventar el problema técnico planteado, la presente invención divulga un dispositivo convertidor o simplemente "convertidor" que comprende dos aspectos . El primer aspecto está asociado con los propios componentes del convertidor, y el segundo aspecto está asociado con un método particular para medir y digitalizar la temperatura en el convertidor anterior. To solve the technical problem raised, the present invention discloses a converter device or simply "converter" which comprises two aspects. The first aspect is associated with the converter's own components, and the second aspect is associated with a particular method for measuring and digitizing the temperature in the previous converter.
La presente invención divulga un convertidor cuyas principales ventajas frente al estado de la técnica son que: es capaz de medir la temperatura y transformar el valor medido en un valor digital en un intervalo corto de tiempo (pocos segundos ) ; The present invention discloses a converter whose main advantages over the state of the art are that: it is capable of measuring the temperature and transforming the measured value into a digital value in a short time interval (few seconds);
tiene un consumo de micro-amperios;  it has a consumption of micro-amps;
tiene una alta precisión: error en la medida menor al 0.28%.  It has high precision: measurement error less than 0.28%.
Para alcanzar las ventajas anteriormente descritas frente al estado de la técnica, la presente invención combina sinérgicamente ambos aspectos de la presente invención (dispositivo convertidor y método). To achieve the above-described advantages over the prior art, the present invention synergistically combines both aspects of the present invention (converter device and method).
Como se ha indicado anteriormente, el primer aspecto de la invención está asociado con el convertidor de temperatura-a-digital de alta precisión con bajo consumo de potencia que comprende: As indicated above, the first aspect of the invention is associated with the high-precision digital-to-digital converter with low power consumption comprising:
• un termistor RTH cuya resistencia depende de la temperatura; • an RTH thermistor whose resistance depends on the temperature;
• un conjunto de elementos discretos invariables con la temperatura que comprende : • a set of discrete elements invariable with the temperature comprising:
o un resistor RP;  or an RP resistor;
o un resistor RS;  or an RS resistor;
o un condensador de integración CINT;  or a CINT integration capacitor;
• un circuito de lectura y conversión que mide la resistencia del termistor y convierte dicho valor representativo de la temperatura, en un código digital para su posterior procesado; tal que el resistor y el termistor RTH, por un lado, y el resistor RP, por otro, forman dos ramas de circuito que se conectan por un extremo a un nudo común y donde los tres terminales resultantes están conectados a otros tantos nudos del circuito de lectura y conversión.  • a reading and conversion circuit that measures the resistance of the thermistor and converts said temperature representative value into a digital code for further processing; such that the resistor and thermistor RTH, on the one hand, and resistor RP, on the other, form two circuit branches that are connected at one end to a common node and where the resulting three terminals are connected to as many nodes of the circuit of reading and conversion.
El circuito de lectura y conversión de la temperatura anteriormente definido a su vez comprende: The previously defined temperature reading and conversion circuit in turn comprises:
• un generador de tensiones de referencia;  • a reference voltage generator;
• un generador de fases de reloj ;  • a clock phase generator;
• un control digital;  • a digital control;
• un núcleo de procesado de señal mixta conectado con:  • a mixed signal processing core connected with:
o el generador de tensiones de referencia que envía al núcleo de procesado de señal mixta una tensión en modo común "VCM", una tensión de referencia negativa "VREFN" y una tensión de referencia positiva "VREFP"; or the reference voltage generator that sends a mode mode voltage to the mixed signal processing core common "VCM", a negative reference voltage "VREFN" and a positive reference voltage "VREFP";
o el generador de fases de reloj , el cual recibe una señal de reloj "CLKTS" y envía al núcleo de procesado de señal mixta una señal formada por trenes de pulsos de la misma frecuencia que la señal de reloj "CLKTS" recibida; además, el generador de fases de reloj está conectado con el control digital al cual envía una señal de reloj "CLKTSYS" idéntica a la señal de reloj "CLKTS" pero con un retraso de dos unidades de retraso;  or the clock phase generator, which receives a "CLKTS" clock signal and sends to the mixed signal processing core a signal formed by pulse trains of the same frequency as the "CLKTS" clock signal received; in addition, the clock phase generator is connected to the digital control to which it sends a clock signal "CLKTSYS" identical to the clock signal "CLKTS" but with a delay of two delay units;
o el control digital al cual envía una señal lógica "COMP" y del cual recibe una señal "SRTH" y una señal "SRB"; además, el control digital tiene una entrada RESET, una salida binaria TRDY y una salida NTEMP que representa la temperatura medida de forma digital .  or the digital control to which it sends a logic signal "COMP" and from which it receives a signal "SRTH" and a signal "SRB"; In addition, the digital control has a RESET input, a TRDY binary output and an NTEMP output that represents the temperature measured digitally.
El generador de tensiones de referencia comprendido en el circuito de lectura y conversión de la temperatura anteriormente descrito comprende : The reference voltage generator included in the temperature reading and conversion circuit described above comprises:
• un generador de tensión que proporciona un voltaje estable "VBG", insensible con la temperatura y conectado con un raíl de alimentación negativa "VSSA" y un raíl de alimentación positiva "VDDA"; • a voltage generator that provides a stable voltage "VBG", insensitive to temperature and connected with a negative power rail "VSSA" and a positive power rail "VDDA";
• un divisor resistivo que a su vez comprende tres resistencias insensibles frente a temperatura;  • a resistive divider that in turn comprises three temperature-insensitive resistors;
• tres seguidores de tensión que obtienen la tensión de referencia positiva "VREFP", la tensión en modo común "VCM" y la tensión de referencia negativa "VREFN" a partir de las tensiones en los nudos intermedios de la escalera de resistencias "VTP", "VTM" y "VTN", respectivamente; y una red capacitiva formada por los condensadores conectados, respectivamente, entre las salidas de los tres seguidores de tensión y el raíl de alimentación negativa "VSSA". núcleo de procesado de señal mixta comprendido en el circuito de lectura y conversión de la temperatura anteriormente descrito comprende : • three voltage followers that obtain the positive reference voltage "VREFP", the common mode voltage "VCM" and the negative reference voltage "VREFN" from the tensions in the intermediate nodes of the resistance ladder "VTP" , "VTM" and "VTN", respectively; and a capacitive network formed by the capacitors connected, respectively, between the outputs of the three voltage followers and the "VSSA" negative power rail. core of mixed signal processing included in the circuit reading and conversion of the temperature described above comprises:
• un amplificador operacional;  • an operational amplifier;
• un comparador conectado a la salida del amplificador operacional;  • a comparator connected to the output of the operational amplifier;
• un conjunto de dos inversores lógicos que proporcionan dos señales negativas "SRTHN" y "SRBN" de las señales de control "SRTH" y "SRB", respectivamente;  • a set of two logical inverters that provide two negative signals "SRTHN" and "SRBN" of the control signals "SRTH" and "SRB", respectively;
• un primer conjunto de llaves analógicas;  • a first set of analog keys;
• un segundo conjunto de llaves analógicas;  • a second set of analog keys;
donde la resistencia de cada una de las llaves analógicas es varios órdenes de magnitud inferior a las resistencias del termistor RTH, del resistor RP y del resistor RS . where the resistance of each of the analog keys is several orders of magnitude lower than the resistors of the RTH thermistor, the RP resistor and the RS resistor.
El amplificador operacional, junto con las ramas resistivas (termistor RTH, resistor RP, resistor RS) y el condensador de integración CINT (conectado externamente entre los nudos VN y VO) forman un integrador Miller de doble entrada (los terminales de las ramas resistivas no conectados entre si) capaz de generar señales analógicas triangulares mediante el adecuado control de las señales lógicas generadas en el circuito de control digital. A tal fin, los conjuntos de llaves analógicas conectan de forma complementaria los terminales del integrador Miller a una u otra tensión de referencia de las proporcionadas por el circuito generador. Todos los elementos activos del convertidor se pueden implementar de forma que sean virtualmente inmunes a las variaciones de la tensión de alimentación (alto PSRR del inglés "Power Supply Rejection Ratio") de forma que el conjunto resulta apropiado en aplicaciones en donde los recursos energéticos pueden ser potencialmente inestables . The operational amplifier, together with the resistive branches (RTH thermistor, RP resistor, RS resistor) and the CINT integration capacitor (externally connected between the VN and VO nodes) form a Miller dual-input integrator (the terminals of the non-resistive branches connected to each other) capable of generating triangular analog signals by properly controlling the logic signals generated in the digital control circuit. To this end, the analog key assemblies connect the terminals of the Miller integrator in a complementary way to one or another reference voltage of those provided by the generator circuit. All active elements of the converter can be implemented so that they are virtually immune to variations in the supply voltage (high PSRR of the "Power Supply Rejection Ratio") so that the set is appropriate in applications where energy resources can Be potentially unstable.
El otro aspecto de la invención es el método para medir y digitalizar la resistencia del termistor RTH comprendido en el convertidor temperatura-a-digital de alta precisión con bajo consumo de potencia definido anteriormente, donde el método comprende las siguientes cuatro etapas que se suceden consecutivamente: The other aspect of the invention is the method for measuring and digitizing the resistance of the RTH thermistor comprised in the high-precision digital-to-digital converter with low power consumption defined above, where the method comprises the following four stages that follow one after the other. :
• una primera etapa, denominada de AUTO-CERO 1, en donde se descarga el condensador de integración de forma que la tensión de salida del amplificador operacional toma el valor de modo común, VCM; • a first stage, called AUTO-ZERO 1, where discharge the integration capacitor so that the output voltage of the operational amplifier takes the common mode value, VCM;
• una segunda etapa, denominada de AU O-CALIBRADO, en donde se cortocircuita el termistor externo y se generan dos rampas a la salida del amplificador operacional, una positiva y otra negativa; la primera rampa tiene una duración fija de NI ciclos de reloj con frecuencia FTS y se obtiene conectando la rama del resistor RP a una tensión VREFP y la rama del resistor RS a una tensión VREFN; la segunda rampa se genera conectando la rama del resistor RP a un nudo de tierra virtual y la rama del resistor RS a una tensión VREFP y concluye cuando el comparador detecta que la salida del amplificador operacional es inferior a la tensión de modo común; la duración de esta segunda rampa se monitoriza mediante un contador que determina el número de ciclos de reloj, N2AU, contenido en dicho intervalo, una vez concluida la etapa de auto-calibrado, el valor N2AU se guarda en una dirección del registro digital;  • a second stage, called AU O-CALIBRATION, where the external thermistor is short-circuited and two ramps are generated at the output of the operational amplifier, one positive and the other negative; the first ramp has a fixed duration of NI clock cycles with FTS frequency and is obtained by connecting the resistor branch RP to a VREFP voltage and the resistor branch RS to a VREFN voltage; the second ramp is generated by connecting the branch of the resistor RP to a virtual ground node and the branch of the resistor RS to a VREFP voltage and concludes when the comparator detects that the output of the operational amplifier is less than the common mode voltage; the duration of this second ramp is monitored by a counter that determines the number of clock cycles, N2AU, contained in said interval, once the self-calibration stage is concluded, the N2AU value is stored in an address of the digital register;
• una tercera etapa, denominada de AUTO-CERO 2, en donde se descarga el condensador de integración de forma que la tensión de salida del amplificador operacional toma el valor de modo común, VCM; y,  • a third stage, called AUTO-ZERO 2, where the integration capacitor is discharged so that the output voltage of the operational amplifier takes the common mode value, VCM; Y,
• una cuarta etapa, denominada etapa de MEDIDA, en donde se repite la etapa de AUTO-CALIBRADO, sólo que, en este caso, el termistor RTH no está cortocircuitado y la duración de la segunda rampa durante la etapa de medida se monitoriza mediante un contador que determina el número de ciclos de reloj, N2TH, contenido en dicho intervalo; una vez concluida la etapa de medida, el valor N2TH se guarda en otra dirección del registro digital;  • a fourth stage, called the MEASURE stage, where the AUTO-CALIBRATION stage is repeated, only that, in this case, the RTH thermistor is not short-circuited and the duration of the second ramp during the measurement stage is monitored by a counter that determines the number of clock cycles, N2TH, contained in said interval; Once the measurement stage is completed, the N2TH value is stored in another address of the digital register;
de acuerdo con este procedimiento, la resistencia del termistor RTH es proporcional al término dependiente de la temperatura NTEMP = (N2AU - N2TH) donde dicho término se calcula mediante un sumador binario a partir de los valores almacenados en las dos direcciones del registro digital. According to this procedure, the resistance of the thermistor RTH is proportional to the temperature dependent term NTEMP = (N2AU - N2TH) where said term is calculated by a binary adder from the values stored in the two directions of the digital register.
De acuerdo con el método para derivar un valor representativo de la resistencia de un termistor conforme a la presente invención, el impacto de las imperfecciones de la circuiteria analógica incluida en el circuito activo vinculado al convertidor temperatura-a-digital es nulo en primera aproximación dado que tanto la etapa de auto- calibración como de medición siguen el mismo protocolo de funcionamiento y las componentes no-ideales de los términos N2AU y N2TH se cancelan cuando se calcula el valor incremental. De este modo, si el valor de NI y la frecuencia de operación del convertidor son lo suficientemente altas (para reducir el error de cuantización inherente al recuento digital), la precisión en la medida de la temperatura en un tiempo de lectura determinado viene básicamente dada por la tolerancia del termistor. Por tanto, no hay necesidad de calibración durante la fase de calibración del dispositivo. According to the method to derive a representative value from the resistance of a thermistor according to the present invention, the impact of the imperfections of the analog circuitry included in the active circuit linked to the digital-to-digital converter is null in the first approximation since both the self-calibration and measurement stage follow The same operating protocol and non-ideal components of the terms N2AU and N2TH are canceled when the incremental value is calculated. Thus, if the NI value and the frequency of operation of the converter are high enough (to reduce the quantization error inherent in the digital count), the accuracy in measuring the temperature at a given reading time is basically given for thermistor tolerance. Therefore, there is no need for calibration during the calibration phase of the device.
Breve descripción de las figuras . Brief description of the figures.
La figura 1 representa un diagrama de bloques del convertidor temperatura-a-digital según una forma de realización de la presente invención. Según esta realización, el convertidor temperatura-a- digital comprende un bloque "GENERADOR DE TENSIONES DE REFERENCIA", un "GENERADOR DE FASES DE RELOJ", un bloque "NÚCLEO DE SEÑAL-MIXTA" y un "CONTROL DIGITAL". Figure 1 represents a block diagram of the temperature-to-digital converter according to an embodiment of the present invention. According to this embodiment, the digital-to-digital converter comprises a "REFERENCE VOLTAGE GENERATOR" block, a "CLOCK PHASE GENERATOR" block, a "MIXED SIGNAL CORE" block and a "DIGITAL CONTROL" block.
La figura 2 representa un diagrama de bloques del generador de tensiones de referencia según una realización de la presente invención que comprende un generador de tensión estable frente a temperatura, un divisor resistivo, tres seguidores de tensión y un conjunto de condensadores. Figure 2 depicts a block diagram of the reference voltage generator according to an embodiment of the present invention comprising a temperature stable voltage generator, a resistive divider, three voltage followers and a set of capacitors.
La figura 3 muestra un diagrama temporal de las señales de entrada/salida implicadas en el bloque de generación de fases de reloj según una realización de la presente invención. Figure 3 shows a time diagram of the input / output signals involved in the clock phase generation block according to an embodiment of the present invention.
La figura 4 muestra una forma de realización del circuito que implementa el bloque "GENERADOR DE FASES DE RELOJ". La figura 5 representa el diagrama de bloques del núcleo de procesamiento de señal mixta "NÚCLEO DE SEÑAL-MIXTA" según una forma de realización de la invención, que comprende una estructura de llaves analógicas, un amplificador de transconductancia "OTA", un comparador "COMP" y lógica de control . Figure 4 shows an embodiment of the circuit that implements the "CLOCK PHASE GENERATOR" block. Figure 5 represents the block diagram of the mixed signal processing core "SIGNAL-MIXED NUCLEUS" according to an embodiment of the invention, comprising an analog key structure, an "OTA" transconductance amplifier, a comparator " COMP "and control logic.
La figura 6 muestra un diagrama temporal de las principales señales involucradas en el núcleo de procesamiento de señal mixta "NÚCLEO DE SEÑAL-MIXTA" durante el proceso de medida del convertidor temperatura-a-digital (método para medir y digitalizar la resistencia del termistor RTH) según una forma de realización de la presente invención . Figure 6 shows a time diagram of the main signals involved in the mixed signal processing core "MIXED SIGNAL NUCLEUS" during the measurement process of the temperature-to-digital converter (method for measuring and digitizing the resistance of the RTH thermistor ) according to an embodiment of the present invention.
La figura 7 representa el diagrama de bloques del circuito de control digital "CONTROL DIGITAL" según una forma de realización de la presente invención. Figure 7 represents the block diagram of the digital control circuit "DIGITAL CONTROL" according to an embodiment of the present invention.
Descripción de un ejemplo de realización de la invención Description of an embodiment of the invention
A continuación se realiza una descripción de una forma de realización de la invención basada en las referencias utilizadas en las figuras anexas . Below is a description of an embodiment of the invention based on the references used in the attached figures.
La figura 1 representa el diagrama de bloques del convertidor temperatura-a-digital 1000 según una realización de la presente invención. Dicho convertidor 1000 comprende, como elementos activos, un generador de tensiones de referencia 1100, un generador de fases de reloj 1200, un núcleo de procesado de señal mixta 1300 y un bloque de control digital 1400. Los bloques analógicos 1100 y 1300 emplean corrientes de polarización que se sintetizan preferentemente a partir de una celda de corriente insensible frente a la temperatura con curvatura compensada y que se distribuye tantas veces como sea necesaria usando espejos de corriente. Figure 1 represents the block diagram of the temperature-to-digital converter 1000 according to an embodiment of the present invention. Said converter 1000 comprises, as active elements, a reference voltage generator 1100, a clock phase generator 1200, a mixed signal processing core 1300 and a digital control block 1400. Analog blocks 1100 and 1300 employ currents of polarization that are preferably synthesized from a temperature-insensitive current cell with compensated curvature and distributed as many times as necessary using current mirrors.
En una configuración preferente de la presente invención, los bloques activos 1100-1400 están integrados en un único microchip fabricado sobre un sustrato que se elige de entre: silicio, silicio sobre aislante, silicio-germanio , fosfuro de indio y arseniuro de galio. Preferentemente, con vistas a reducir el coste de fabricación del dispositivo, se usa substrato de silicio. In a preferred configuration of the present invention, the active blocks 1100-1400 are integrated in a single manufactured microchip on a substrate that is chosen from: silicon, silicon on insulator, silicon-germanium, indium phosphide and gallium arsenide. Preferably, in order to reduce the manufacturing cost of the device, silicon substrate is used.
Además de los bloques activos 1100-1400, el convertidor temperatura- a-digital 1000 comprende varios elementos pasivos. En concreto, dispone de un termistor 1510, cuya resistencia RTH depende con la temperatura y un conjunto de dispositivos de referencia con valores virtualmente invariables con la temperatura formado por un resistor 1520 con resistencia RS, un resistor 1530 con resistencia RP y un condensador de integración 1540 con capacidad CINT. El termistor 1510 y los resistores RS 1520 y RP 1530 satisfacen la condición RS+RTH < RP, en todo el rango de variación de temperaturas para el que se diseña el convertidor temperatura-a-digital 1000. In addition to the active blocks 1100-1400, the temperature-to-digital converter 1000 comprises several passive elements. Specifically, it has a thermistor 1510, whose resistance RTH depends on the temperature and a set of reference devices with virtually invariable values with the temperature formed by a resistor 1520 with RS resistance, a resistor 1530 with RP resistance and an integration capacitor 1540 with CINT capacity. The thermistor 1510 and the resistors RS 1520 and RP 1530 satisfy the RS + RTH <RP condition, in the entire range of temperature variation for which the 1000-to-digital converter 1000 is designed.
En una realización de la presente invención, las entradas al convertidor temperatura-a-digital 1000 son RESET y CLKTS. La señal RESET es una señal escalón empleada para iniciar el proceso de medida del convertidor temperatura-a-digital 1000 y para llevar los medios digitales de control 1400 a sus valores por defecto. De acuerdo con una posible implementación, el comienzo del proceso de medida se produce con el flanco ascendente de la señal RESET, mientras el reinicio de la lógica de control 1400 se produce con el flanco descendente de la señal RESET. El tiempo mínimo en que la señal RESET debe permanecer con valor de Λ0' lógico para reiniciar el estado de la lógica digital 1400 es de un ciclo del reloj de referencia CLKTS. Dicha señal CLKTS es un tren de pulsos periódicos con frecuencia conocida FTS, que se utiliza para la generación de las señales lógicas de control y para secuenciar el funcionamiento del bloque digital 1400. In one embodiment of the present invention, the inputs to the temperature-to-digital converter 1000 are RESET and CLKTS. The RESET signal is a step signal used to start the measurement process of the 1000 digital-to-digital converter and to bring the digital control means 1400 to their default values. According to a possible implementation, the start of the measurement process occurs with the rising edge of the RESET signal, while the reset of control logic 1400 occurs with the falling edge of the RESET signal. The minimum time in which the RESET signal must remain with a logical Λ 0 'value to reset the state of digital logic 1400 is one cycle of the CLKTS reference clock. Said CLKTS signal is a periodic pulse train with known frequency FTS, which is used for the generation of the logic control signals and for sequencing the operation of the digital block 1400.
La salida del convertidor temperatura-a-digital 1000 viene dada por dos señales que son TRDY y NTEMP< LNT-1:0>. La primera, TRDY, es una señal de control que se activa cuando los datos relativos a la medición de la temperatura corporal están disponibles y se desactiva cuando comienza un nuevo ciclo de medición. De acuerdo con ello, la señal TRDY permanece en el estado lógico Λ0' tras el reinicio del sistema y toma el valor lógico Λ1' cuando concluye el proceso de medida. La segunda, NTEMP<LNT-1 : 0>, es una representación digital serie de un número LNT de bits representativos de la medida en temperatura, de acuerdo con la presente invención. Adicionalmente, el convertidor temperatura-a-digital 1000 proporciona los terminales TRTH, TRS, VN, TRP y VO para la conexión de los dispositivos discretos 1510, 1520, 1530 y 1540 tal y como muestra la figura 1. The output of the temperature-to-digital converter 1000 is given by two signals that are TRDY and NTEMP <LNT-1: 0>. The first, TRDY, is a control signal that is activated when data related to body temperature measurement is available and deactivated when a new measurement cycle begins. Accordingly, the TRDY signal remains at logic Λ 0 'after the system reset and takes the logical value Λ 1' when the measurement process ends. The second, NTEMP <LNT-1: 0>, is a serial digital representation of an LNT number of bits representative of temperature measurement, in accordance with the present invention. Additionally, the temperature-to-digital converter 1000 provides the TRTH, TRS, VN, TRP and VO terminals for the connection of discrete devices 1510, 1520, 1530 and 1540 as shown in Figure 1.
Cada uno de los bloques incluidos en la figura 1 se describe en detalle a continuación. Each of the blocks included in Figure 1 is described in detail below.
El generador de tensiones de referencia 1100 del convertidor temperatura-a-digital 1000 se encarga de proporcionar tensiones estables y reguladas al núcleo analógico 1300, a partir de railes de alimentación estables, VDDA y VSSA. El bloque 1100 proporciona tres tensiones de salida, VCM, VREFN y VREFP. La primera (VCM) es el modo común del circuito, y las restantes (VREFN y VREFP) son tensiones de referencia negativa y positiva desplazadas por debajo y por encima del valor de modo común, respectivamente. En una posible realización, la tensión de modo común está nominalmente a mitad de los railes de alimentación, esto es, VCM = (VDDA+VSSA) /2 , y el incremento de tensión AV se toma como AV = VCM/ , aunque la presente invención no se limita a estos valores concretos de tensión. The reference voltage generator 1100 of the temperature-to-digital converter 1000 is responsible for providing stable and regulated voltages to the analog core 1300, from stable power rails, VDDA and VSSA. Block 1100 provides three output voltages, VCM, VREFN and VREFP. The first (VCM) is the common mode of the circuit, and the remaining ones (VREFN and VREFP) are negative and positive reference voltages displaced below and above the common mode value, respectively. In a possible embodiment, the common mode voltage is nominally in the middle of the supply rails, that is, VCM = (VDDA + VSSA) / 2, and the increase in AV voltage is taken as AV = VCM /, although this The invention is not limited to these specific voltage values.
La figura 2 muestra el diagrama de bloques interno de una realización particular del generador de tensiones de referencias 1100 y comprende preferentemente un bloque 1110 que proporciona una tensión estable VBG insensible con la temperatura, un divisor resistivo 1120, dispuesto entre los terminales VBG y VSSA, formado por tres resistencias insensibles con la temperatura 1121, 1122 y 1123 en cuyos nudos intermedios se generan los valores de tensión escalados VTP, VTM y VTN; tres seguidores de tensión 1130, 1140 y 1150, que obtienen las tensiones VREFP, VCM y VREFN a partir de las tensiones en los nudos intermedios de la escalera de resistencias, VTP, VTM y VTN, respectivamente; y una red capacitiva 1160 formada por los condensadores 1161, 1162 y 1163 conectados, respectivamente, entre las salidas de los seguidores de tensión 1130, 1140 y 1150 y el rail de alimentación negativa VSSA. Los seguidores 1130, 1140 y 1150 se emplean para estabilizar las tensiones de salida del generador de referencia frente a variaciones en las condiciones de carga. Los condensadores 1161, 1162 y 1163 se emplean para aumentar las constantes de tiempo de variación de los nudos correspondientes y disminuir las contribuciones de ruido térmico en las tensiones de salida VREFP, VCM y VREFN. Figure 2 shows the internal block diagram of a particular embodiment of the reference voltage generator 1100 and preferably comprises a block 1110 that provides a stable voltage-insensitive VBG voltage, a resistive divider 1120, disposed between the VBG and VSSA terminals, formed by three insensitive resistors with temperature 1121, 1122 and 1123 at whose intermediate nodes the voltage values scaled VTP, VTM and VTN are generated; three tension followers 1130, 1140 and 1150, which obtain the voltages VREFP, VCM and VREFN from the tensions in the intermediate nodes of the resistance ladder, VTP, VTM and VTN, respectively; and a capacitive network 1160 formed by capacitors 1161, 1162 and 1163 connected, respectively, between the outputs of the voltage followers 1130, 1140 and 1150 and the negative feed rail VSSA. Followers 1130, 1140 and 1150 are used to stabilize the output voltages of the reference generator against variations in load conditions. Capacitors 1161, 1162 and 1163 are used to increase the variation time constants of the corresponding nodes and decrease the contributions of thermal noise in the output voltages VREFP, VCM and VREFN.
La figura 3 muestra el diagrama temporal 1201 de las señales implicadas en el generador de fases de reloj 1200. El generador de fases de reloj 1200 recibe como entrada la señal CLKTS y produce dos salidas, CLKTSYS y STROBE . La primera, CLKTSYS, es una copia de la señal de entrada CLKTS retrasada por dos unidades de retraso, cada una de duración DEL. La segunda, STROBE, es un tren de pulsos periódicos con la misma frecuencia que la señal de entrada CLKTS. Los flancos de subida de las señales STROBE y CLKTS están alineados pero, en el caso de la señal STROBE, la duración del estado Λ1' es de tan sólo una unidad de retraso, DEL. La duración DEL de la unidad de retraso es típicamente del orden de nanosegundos y, por tanto, muy inferior a la duración de un semiperiodo de la señal CLKTS. Figure 3 shows the time diagram 1201 of the signals involved in the clock phase generator 1200. The clock phase generator 1200 receives the CLKTS signal as input and produces two outputs, CLKTSYS and STROBE. The first, CLKTSYS, is a copy of the CLKTS input signal delayed by two delay units, each of DEL duration. The second, STROBE, is a train of periodic pulses with the same frequency as the CLKTS input signal. The rising edges of the STROBE and CLKTS signals are aligned but, in the case of the STROBE signal, the duration of the state Λ 1 'is only one delay unit, DEL. The duration DEL of the delay unit is typically of the order of nanoseconds and, therefore, much less than the duration of a half-period of the CLKTS signal.
La figura 4 muestra el diagrama de bloques de una posible realización del generador de fases de reloj 1200. Las cadenas de seguidores digitales 1210 y 1220 introducen cada una de ellas un retraso DEL en la propagación de sus respectivas señales de entrada. Consecuentemente, la señal CLKTSYS acumula un retraso con respecto a la señal CLKTS. Por otro lado, el inversor 1240 junto con la puerta NAND 1230 cuyas entradas son, por un lado, la señal CLKTS y, por otro, la salida de la cadena de buffers 1210, generan la señal STROBE con las características temporales antes indicadas en la figura 3. El retraso provocado por la concatenación de la puerta NAND 1230 y el inversor 1240 es muy inferior al retraso DEL generado por las cadenas de seguidores digitales 1210 o 1220. Todas las puertas lógicas incluidas en el generador de fase de reloj usan railes alimentación digitales, VDDD y VSSD. Figure 4 shows the block diagram of a possible embodiment of the clock phase generator 1200. The digital tracker chains 1210 and 1220 each introduce a delay DEL in the propagation of their respective input signals. Consequently, the CLKTSYS signal accumulates a delay with respect to the CLKTS signal. On the other hand, the inverter 1240 together with the NAND gate 1230 whose inputs are, on the one hand, the CLKTS signal and, on the other, the output of the chain of buffers 1210, generate the STROBE signal with the temporal characteristics indicated above in the Figure 3. The delay caused by the concatenation of the NAND gate 1230 and the inverter 1240 is much less than the delay DEL generated by the digital tracker chains 1210 or 1220. All logic gates included in the clock phase generator use digital power rails, VDDD and VSSD.
El núcleo de procesamiento de señal-mixta 1300 del convertidor temperatura-a-digital 1000 genera una única salida lógica COMP que se transfiere al bloque de control digital 1400 y tiene como entradas las tensiones de referencia VREFP, VREFN y VCM obtenidas en el generador de tensiones de referencia 1100; un conjunto de dos señales lógicas SRTH y SRB procedentes del bloque de control digital 1400; y una señal lógica STROBE proporcionada por el generador de fases de reloj 1200. Adicionalmente, el núcleo 1300 dispone de los terminales TRTH, TRS, VN, TRP y VO para la conexión de los dispositivos discretos 1510, 1520, 1530 y 1540, tal como muestra la figura 1. Salvo que se indique explícitamente lo contrario, todos los elementos de circuito incluidos en el núcleo de procesamiento de señal-mixta 1300 emplean raíles de alimentación analógicos, VDDA y VSSA. The mixed-signal processing core 1300 of the temperature-to-digital converter 1000 generates a single logic output COMP that is transferred to the digital control block 1400 and has as input the reference voltages VREFP, VREFN and VCM obtained in the generator reference voltages 1100; a set of two SRTH and SRB logic signals from the digital control block 1400; and a STROBE logic signal provided by the clock phase generator 1200. Additionally, the core 1300 has the terminals TRTH, TRS, VN, TRP and VO for the connection of discrete devices 1510, 1520, 1530 and 1540, such as Figure 1 shows. Unless explicitly stated otherwise, all circuit elements included in the 1300 mixed-signal processing core employ analog, VDDA and VSSA power rails.
De acuerdo con la presente invención, el objetivo del núcleo de procesamiento de señal-mixta 1300 es realizar una transformación resistencia-a-tiempo de manera que la diferencia entre las resistencias del termistor 1510 y el resistor lineal 1530 se cuantifique mediante intervalos temporales cuya duración depende del valor de dichas resistencias. Puesto que la resistencia RTH del termistor 1510 depende con la temperatura mientras la resistencia RP del resistor 1530 es virtualmente invariable con la temperatura, la medida realizada en este bloque refleja de forma indirecta la temperatura a la que está expuesto el termistor 1510. In accordance with the present invention, the objective of the mixed signal processing core 1300 is to perform a resistance-to-time transformation so that the difference between the resistors of the thermistor 1510 and the linear resistor 1530 is quantified by time intervals whose duration It depends on the value of these resistors. Since the resistance RTH of the thermistor 1510 depends on the temperature while the resistance RP of the resistor 1530 is virtually invariable with the temperature, the measurement made in this block indirectly reflects the temperature to which the thermistor 1510 is exposed.
La figura 5 muestra el diagrama de bloques de una posible realización del núcleo de procesamiento de señal-mixta 1300 del convertidor temperatura-a-digital 1000 que comprende un amplificador operacional de transconductancia 1370, un comparador 1380 conectado a la salida VO del amplificador 1370 y un conjunto de dos inversores lógicos 1390 para obtener las señales negadas SRTHN y SRBN de las señales de control SRTH y SRB, respectivamente. Los inversores 1390 emplean raíles de alimentación digitales, VDDD y VSSD. El comparador 1380 detecta el signo de la diferencia de tensiones VO-VCM en los instantes definidos por la señal STROBE proporcionada por el generador de fases de reloj 1200. El terminal no-inversor del amplificador 1370 está conectado a la tensión de modo común VCM generada por el generador de tensiones de referencia 1100. El terminal inversor VN del amplificador 1370 está conectado al nudo común de dos ramas resistivas. Dichas ramas resistivas son reconfigurables de manera que se puede controlar tanto el valor de sus respectivas resistencias como el valor de las tensiones aplicadas en los nudos no conectados al terminal no-inversor del amplificador 1370. Una primera rama resistiva comprende las llaves analógicas 1310, 1320, 1330 y 1340, controladas por las señales lógicas SRB, SRTH, SRBN y SRTHN, respectivamente; el termistor 1510 (conectado entre los nudos TRTH y TRS); y el resistor serie 1520 (conectado entre los nudos TRS y VN) . Una segunda rama comprende las llaves analógicas 1350 y 1360, controladas por las señales lógicas SRB y SRBN, respectivamente; y el resistor paralelo 1530 (conectado entre los nudos TRP y VN) . La resistencia en ON de las llaves analógicas incluidas en el núcleo de procesamiento de señal-mixta 1300 es en todos los casos varios órdenes de magnitud inferior a las resistencias de los componentes discretos 1510, 1520 y 1530. Figure 5 shows the block diagram of a possible embodiment of the mixed-signal processing core 1300 of the temperature-to-digital converter 1000 comprising an operational transconductance amplifier 1370, a comparator 1380 connected to the VO output of the amplifier 1370 and a set of two logical inverters 1390 to obtain the denied signals SRTHN and SRBN of the control signals SRTH and SRB, respectively. 1390 inverters use digital power rails, VDDD and VSSD. The 1380 comparator detects the sign of the difference in VO-VCM voltages in the moments defined by the STROBE signal provided by the clock phase generator 1200. The non-inverting terminal of the amplifier 1370 is connected to the common mode voltage VCM generated by the generator of reference voltages 1100. The inverter terminal VN of amplifier 1370 is connected to the common node of two resistive branches. Said resistive branches are reconfigurable so that both the value of their respective resistors and the value of the voltages applied to the nodes connected to the non-inverting terminal of the amplifier 1370 can be controlled. A first resistive branch comprises the analog keys 1310, 1320 , 1330 and 1340, controlled by the logic signals SRB, SRTH, SRBN and SRTHN, respectively; thermistor 1510 (connected between nodes TRTH and TRS); and the 1520 series resistor (connected between the TRS and VN nodes). A second branch comprises analog keys 1350 and 1360, controlled by the logic signals SRB and SRBN, respectively; and parallel resistor 1530 (connected between nodes TRP and VN). The ON resistance of the analog keys included in the mixed-signal processing core 1300 is in all cases several orders of magnitude less than the resistances of the discrete components 1510, 1520 and 1530.
El amplificador operacional 1370, junto con las ramas resistivas y el condensador 1540 (conectado externamente entre los nudos VN y VO) forman un integrador Miller de doble entrada (los terminales de las ramas resistivas no conectados entre si) capaz de generar señales analógicas triangulares mediante el adecuado control de las señales lógicas generadas en el circuito de control digital 1400. The operational amplifier 1370, together with the resistive branches and the capacitor 1540 (externally connected between the VN and VO nodes) form a double-input Miller integrator (the terminals of the non-connected resistive branches) capable of generating triangular analog signals by the adequate control of the logic signals generated in the digital control circuit 1400.
La operación del núcleo de procesamiento de señal-mixta 1300 se divide en cuatro fases, denominadas AUTO-CERO 1, AUTO-CALIBRADO, AUTO-CERO 2 Y MEDIDA, que se ejemplifican en el diagrama temporal 1301 de la figura 6. The operation of the mixed-signal processing core 1300 is divided into four phases, called AUTO-ZERO 1, AUTO-CALIBRATE, AUTO-ZERO 2 AND MEASURE, which are exemplified in time diagram 1301 of Figure 6.
En una primera fase, denominada fase de AUTO-CERO 1, la señal lógica SRTH está en nivel alto Λ1' , la llave analógica 1320 está cerrada mientras la 1340 está abierta, y el termistor 1510 está aislado del resto de la circuiteria. Dependiendo del valor de la tensión VO a la salida del amplificador 1370, la señal de control SRB puede tomar uno u otro valor lógico. En un primer caso el signo de VO-VCM es positivo, la salida del comparador 1380 toma el valor Λ1' , y el bloque de control digital 1400 hace que la señal de control SRB tome el valor Λ1' con lo que las llaves 1310 y 1350 están cerradas mientras las llaves 1330 y 1360 están abiertas. En esta configuración de primer caso, el resistor paralelo 1530 está cortocircuitado y el resistor serie 1520 está conectado a la tensión de referencia positiva VREFP. El diagrama temporal de la figura 6 ilustra el estado de las señales en este primer caso. En un segundo caso el signo de VO-VCM es negativo, la salida del comparador 1380 toma el valor Λ0' , y el bloque de control digital 1400 hace que la señal de control SRB tome el valor Λ0' con lo que las llaves 1310 y 1350 están abiertas mientras las llaves 1330 y 1360 están cerradas. En esta configuración de segundo caso, el resistor paralelo 1530 está conectado a la tensión de referencia positiva VREFP mientras el resistor serie 1520 está conectado a la tensión de referencia negativa VREFN. En cualquiera de los dos casos, la tensión de salida VO del amplificador 1370 evoluciona hacia el valor de la tensión de modo común VCM, de tal manera que se reduce el valor absoluto de la diferencia VO-VCM hasta que se anula. La fase de AUTO-CERO 1 concluye cuando la salida del comparador 1380 cambia de estado. In a first phase, called the AUTO-ZERO 1 phase, the SRTH logic signal is high Λ 1 ', analog key 1320 is closed while 1340 is open, and thermistor 1510 is isolated from the rest of the circuitry. Depending on the value of the voltage VO at the output of the amplifier 1370, the control signal SRB can take one or another logical value. In a first case the VO-VCM sign is positive, the comparator output 1380 takes the value Λ 1 ', and the digital control block 1400 causes the SRB control signal to take the value Λ 1' so that the keys 1310 and 1350 are closed while keys 1330 and 1360 are open. In this first case configuration, the parallel resistor 1530 is shorted and the series resistor 1520 is connected to the positive reference voltage VREFP. The time diagram in Figure 6 illustrates the state of the signals in this first case. In a second case the VO-VCM sign is negative, the output of comparator 1380 takes the value Λ 0 ', and the digital control block 1400 causes the SRB control signal to take the value Λ 0' so that the keys 1310 and 1350 are open while keys 1330 and 1360 are closed. In this second case configuration, the parallel resistor 1530 is connected to the positive reference voltage VREFP while the series resistor 1520 is connected to the negative reference voltage VREFN. In either case, the output voltage VO of the amplifier 1370 evolves towards the value of the common mode voltage VCM, such that the absolute value of the VO-VCM difference is reduced until it is canceled. The AUTO-ZERO 1 phase concludes when the output of comparator 1380 changes state.
En una segunda fase, denominada fase de AUTO-CALIBRADO, la señal lógica SRTH está en nivel alto Λ1' , la llave analógica 1320 está cerrada mientras la 1340 está abierta, y el termistor 1510 está aislado del resto de la circuiteria. La fase de AUTO-CALIBRADO se divide en dos etapas. En una primera etapa, la señal de control SRB toma el valor Λ0' de forma que la salida VO del amplificador 1370 crece linealmente con el tiempo. El bloque de control digital 1400 mantiene la señal SRB en el estado Λ 0' durante un espacio de tiempo correspondiente a NI ciclos del reloj CLKTSYS, proporcionado por el generador de fases de reloj 1200. El condensador de integración 1540 con capacidad CINT se ha de elegir de tal modo que al cabo de los NI ciclos, la tensión VO no supere el rango de salida de salida del amplificador 1370. Los medios y procedimientos para realizar esta acción se detallarán más adelante. En una segunda etapa de la fase de AUTO-CALIBRADO, la señal de control SRB toma el valor Λ 1' de forma que la salida VO del amplificador 1370 decrece linealmente con el tiempo. Esta configuración se mantiene hasta que el comparador 1380 detecta que el signo de VO-VCM es negativo, momento en que la fase de AU O-CALIBRADO concluye. El tiempo transcurrido durante esta segunda etapa es medido en el bloque de control digital 1400 como el número de ciclos completos de reloj CLKTSYS, N2AU<LNT-1 : 0>, contados desde que la señal de control SRB toma el valor Λ 1' hasta que la salida del comparador 380 toma el valor Λ 0' . La variable LNT representa la longitud de la palabra digital N2AU y, en una realización preferente, NI = 2LNT. Los medios y procedimientos para realizar esta operación se describirán después. In a second phase, called the AUTO-CALIBRATION phase, the SRTH logic signal is high Λ 1 ', the analog key 1320 is closed while the 1340 is open, and the thermistor 1510 is isolated from the rest of the circuitry. The AUTO-CALIBRATION phase is divided into two stages. In a first stage, the control signal SRB takes the value Λ 0 'so that the VO output of the amplifier 1370 grows linearly with time. The digital control block 1400 keeps the SRB signal in the Λ 0 'state for a period of time corresponding to NI cycles of the CLKTSYS clock, provided by the clock phase generator 1200. The integration capacitor 1540 with CINT capability must be choose in such a way that after the NI cycles, the VO voltage does not exceed the output range of amplifier 1370. The means and procedures for performing this action will be detailed below. In a second stage of the AUTO-CALIBRATION phase, the SRB control signal takes the value Λ 1 'so that the VO output of amplifier 1370 decreases linearly with time. This configuration is maintained until comparator 1380 detects that the VO-VCM sign is negative, at which point the phase of O-CALIBRATED AU concludes. The time elapsed during this second stage is measured in the digital control block 1400 as the number of complete clock cycles CLKTSYS, N2AU <LNT-1: 0>, counted since the control signal SRB takes the value Λ 1 'until that the output of comparator 380 takes the value Λ 0 '. The variable LNT represents the length of the digital word N2AU and, in a preferred embodiment, NI = 2 LNT . The means and procedures for performing this operation will be described later.
En una tercera fase, denominada fase de AUTO-CERO 2, se repiten los mismos procedimientos previamente descritos para la fase de AUTO-CERO 1. Esta fase tiene como cometido fijar la tensión de salida VO del amplificador 1370 al valor de la tensión de modo común VCM antes de comenzar la fase de MEDIDA (cuarta fase en la operación del núcleo de procesamiento de señal-mixta 1300) . Hay que tener en cuenta que el comparador 1380 opera en instantes discretos de tiempo de acuerdo con los pulsos contenidos en el tren periódico STROBE . Dado que es improbable que la detección del cambio de signo de la diferencia VO- VCM, realizada al final de la fase de AUTO-CALIBRADO, coincida exactamente con un pulso de la señal STROBE, resulta necesaria una segunda fase de auto-cero que permita igualar los estados iniciales del sistema en las fases de AUTO-CALIBRADO y de MEDIDA. In a third phase, called the AUTO-ZERO 2 phase, the same procedures previously described for the AUTO-ZERO 1 phase are repeated. This phase has the task of setting the output voltage VO of the amplifier 1370 to the value of the mode voltage VCM common before beginning the MEASURE phase (fourth phase in the operation of the 1300 mixed-signal processing core). It must be taken into account that the 1380 comparator operates in discrete instants of time according to the pulses contained in the STROBE periodic train. Since it is unlikely that the detection of the change of sign of the VO-VCM difference, performed at the end of the AUTO-CALIBRATION phase, exactly coincides with a pulse of the STROBE signal, a second phase of auto-zero is necessary to allow match the initial states of the system in the AUTO-CALIBRATION and MEASURE phases.
En una cuarta y última fase, denominada fase de MEDIDA, la señal lógica SRTH está en nivel alto Λ0' , la llave analógica 1320 está abierta mientras la 1340 está cerrada, y el termistor 1510 está conectado en serie con el resistor 1520. Salvo por este cambio, los procedimientos empleados en la fase de MEDIDA son idénticos a los empleados en la fase de AUTO-CALIBRADO. En correspondencia, el número de ciclos completos de reloj CLKTSYS contados en el bloque de control digital 1400 durante la segunda etapa de la fase de MEDIDA es N2TH<LNT-1 : 0> . La longitud de la palabra digital N2TH es idéntica a la empleada por la palabra N2AU, esto es, LN . In a fourth and final phase, called the MEASURE phase, the SRTH logic signal is at a high level Λ 0 ', the analog key 1320 is open while the 1340 is closed, and the thermistor 1510 is connected in series with the resistor 1520. Except Due to this change, the procedures used in the MEASURE phase are identical to those used in the SELF-CALIBRATION phase. Correspondingly, the number of complete CLKTSYS clock cycles counted in digital control block 1400 during the second stage of the MEASURE phase is N2TH <LNT-1: 0>. The length of the digital word N2TH is identical to that used by the word N2AU, that is, LN.
De acuerdo con la presente invención, el bloque de control digital 1400 del convertidor temperatura-a-digital 1000 recibe como señales de entrada CLKTSYS, RESET y COMP; y genera las señales de salida, SRTH, SRB, TRDY y NTEMP<LNT-1 : 0> . La señal CLKTSYS temporiza la secuencia de operaciones del bloque de control digital 1400 y sincroniza el estado de las puertas digitales con sus flancos de bajada. La señal RESET reinicia el estado del bloque de control digital 1400 antes de iniciar el proceso de medida. La señal COMP es la salida del comparador 1380 y se usa como señal de control para la activación o desactivación de las señales SRTH y SRB de acuerdo al procedimiento descrito en relación a la figura 6. La señal TRDY indica cuando ha concluido el proceso de medida en cuyo caso toma el valor lógico Λ1' ; por defecto está en Λ0' lógico. Finalmente, NTEMP es el valor representativo de la temperatura medido por el convertidor temperatura-a-digital 1000. Todos los elementos de circuito incluidos en el bloque de control digital usan railes de alimentación digitales, VDDD y VSSD. In accordance with the present invention, the digital control block 1400 of the temperature-to-digital converter 1000 receives CLKTSYS, RESET and COMP signals as input signals; and generates the output signals, SRTH, SRB, TRDY and NTEMP <LNT-1: 0>. The CLKTSYS signal timing the sequence of operations of the digital control block 1400 and synchronizes the state of the digital gates with their falling edges. The RESET signal restarts the status of the digital control block 1400 before starting the measurement process. The COMP signal is the output of comparator 1380 and is used as a control signal for the activation or deactivation of the SRTH and SRB signals according to the procedure described in relation to Figure 6. The TRDY signal indicates when the measurement process has concluded in which case it takes the logical value Λ 1 '; by default it is in Λ 0 'logical. Finally, NTEMP is the representative value of the temperature measured by the 1000 digital-to-digital converter. All circuit elements included in the digital control block use digital power rails, VDDD and VSSD.
La figura 7 muestra una posible implementación de la lógica de control digital 400 que comprende un bloque de control 1410, un contador binario 1420 y un sumador combinacional 1430. En una realización particular, el bloque de control 1410 se activa con los flancos de bajada del reloj CLKTSYS y lleva a cabo cuatro operaciones básicas: primero, monitoriza el estado de la señal COMP y de acuerdo con su valor, activa o desactiva las señales SRTH y SRB tal y como se detalló en relación a la figura 6; segundo, gestiona el control del contador 1420 para poder determinar el número de ciclos transcurridos durante la generación de las rampas de subida y bajada del integrador Miller de la figura 5; tercero, almacena los números de ciclos transcurridos durante la fase de AUTO-CALIBRADO, N2AU<LNT-1 : 0>, y la fase de MEDIDA N2TH<LNT-1 : 0>; y cuarto, fija la señal TRDY a valor lógico Λ1' cuando el proceso de medida concluye. En una realización particular, el bloque de control 1410 usa el flanco de bajada de la señal de entrada RESET para reiniciar las puertas lógicas a su valor por defecto, y el flanco de subida de dicha señal para establecer el inicio del proceso de medida. En una realización particular, el contador 1420 es un contador síncrono de LNT bits activo por flancos de subida del reloj CLKTSYS. El contador 1420 tiene por entradas las señales CLKTSYS, RESET, ENABLE y CLR y genera como salida la palabra digital C<LNT-1:0> que da cuenta del número de ciclos de reloj transcurridos mientras el contador está activo. Cuando concluye la operación del contador 1420, la palabra C<LNT-1:0> se transfiere a alguno de los registros digitales disponibles en el bloque de control 1410 para su posterior procesado. En una configuración particular, la señal RESET a nivel bajo, o la señal CLR a nivel alto, reinician el contador 1420. La señal ENABLE a nivel alto, activa la operación del contador 1420 y a nivel bajo, la desactiva. En una configuración particular, durante las rampas de subida de la señal VO en las fases de AUTO-CALIBRADO y MEDIDA del núcleo de procesamiento de señal-mixta 1300, el contador 1420 está habilitado durante NI = 2LNT ciclos del reloj CLKTSYS, esto es, durante un periodo completo del contador. Durante las rampas de bajada de la señal VO, la palabra digital C<LNT-1:0> toma el valor final N2AU<LNT-1 : 0>, en la fase de AUTO- CALIBRADO, y el valor final N2TH<LNT-1 : 0>, en la fase de MEDIDA. El bloque 1430 es un sumador combinacional que obtiene la diferencia entre los valores N2AU<LNT-1 : 0> y N2TH<LNT-1 : 0> y proporciona la salida del bloque digital 1400, NTEMP<LNT-1 : 0>, esto es, Figure 7 shows a possible implementation of the digital control logic 400 comprising a control block 1410, a binary counter 1420 and a combinational adder 1430. In a particular embodiment, the control block 1410 is activated with the falling edges of the CLKTSYS clock and carries out four basic operations: first, it monitors the status of the COMP signal and according to its value, activates or deactivates the SRTH and SRB signals as detailed in relation to figure 6; second, it manages the control of the counter 1420 to be able to determine the number of cycles elapsed during the generation of the up and down ramps of the Miller integrator of Figure 5; third, it stores the numbers of cycles elapsed during the AUTO-CALIBRATION phase, N2AU <LNT-1: 0>, and the MEASURE phase N2TH <LNT-1: 0>; and fourth, set the TRDY signal to value logical Λ 1 'when the measurement process concludes. In a particular embodiment, control block 1410 uses the falling edge of the RESET input signal to reset the logic gates to its default value, and the rising edge of said signal to establish the start of the measurement process. In a particular embodiment, counter 1420 is a synchronous LNT bit counter active by rising edges of the CLKTSYS clock. Counter 1420 has the CLKTSYS, RESET, ENABLE and CLR signals as inputs and generates the digital word C <LNT-1: 0> as output, which accounts for the number of clock cycles elapsed while the counter is active. When the operation of the counter 1420 is completed, the word C <LNT-1: 0> is transferred to any of the digital registers available in the control block 1410 for further processing. In a particular configuration, the RESET signal at a low level, or the CLR signal at a high level, reset the counter 1420. The ENABLE signal at a high level activates the operation of the counter 1420 and at a low level, deactivates it. In a particular configuration, during the ramps of the VO signal phases AUTO-CALIBRATION and measurement processing core 1300-mixed signal, the counter 1420 is enabled during NI = 2 LNT clock cycles CLKTSYS, this is , for a full period of the counter. During the ramps of the VO signal down, the digital word C <LNT-1: 0> takes the final value N2AU <LNT-1: 0>, in the AUTO-CALIBRATION phase, and the final value N2TH <LNT- 1: 0>, in the MEASURE phase. Block 1430 is a combinational adder that obtains the difference between the values N2AU <LNT-1: 0> and N2TH <LNT-1: 0> and provides the output of digital block 1400, NTEMP <LNT-1: 0>, this is,
NTEMP = N2 AU - N2TH ( λ } NTEMP = N2 AU - N2TH (λ}
La palabra digital NTEMP es, de hecho, el valor representativo de la temperatura medido por el convertidor temperatura-a-digital 1000. Se puede comprobar analíticamente que el valor de la resistencia del termistor 1510 se puede aproximar por un valor RTH A que está relacionado, en primera aproximación, con el valor de NTEMP por la ecuación : NTEMP The digital word NTEMP is, in fact, the representative value of the temperature measured by the digital-to-digital converter 1000. It can be checked analytically that the resistance value of the thermistor 1510 can be approximated by an RTH A value that is related , in first approximation, with the value of NTEMP by the equation: NTEMP
RTH A= •RP (2)  RTH A = • RP (2)
Nl y puesto que los valores de RP y Nl no dependen con la temperatura, cualquier variación de la resistencia del termistor 1510 se refleja integramente en el valor de NTEMP. Más aún, los valores de RP y Nl son esencialmente invariables y, por tanto, característicos del convertidor temperatura-a-digital, de acuerdo con la presente invención. Por tanto, NTEMP determina unívocamente el valor aproximado RTH A de la resistencia del termistor 1510.  Nl and since the values of RP and Nl do not depend on the temperature, any variation of the resistance of the thermistor 1510 is fully reflected in the value of NTEMP. Moreover, the values of RP and Nl are essentially invariable and, therefore, characteristic of the temperature-to-digital converter, in accordance with the present invention. Therefore, NTEMP uniquely determines the approximate value RTH A of the resistance of thermistor 1510.
El error relativo ERR RTH cometido en la aproximación (2) como consecuencia de la discretización temporal en el proceso de medida realizado por el convertidor temperatura-a-digital 1000 viene dado por la expresión: The relative error ERR RTH committed in the approximation (2) as a consequence of the temporary discretization in the measurement process performed by the 1000 digital-to-digital converter is given by the expression:
RPRP
ERR RTH (3 ERR RTH (3
N1 RTH del reloj CLKTSYS usados en la medida de la temperatura. En la práctica, dicho número de ciclos se ha de escoger de forma que el error de discretización sea despreciable frente a las tolerancias habituales en termistores .  N1 RTH of the CLKTSYS watch used in temperature measurement. In practice, said number of cycles must be chosen so that the discretization error is negligible compared to the usual tolerances in thermistors.
Es relevante resaltar que el impacto de las imperfecciones de la circuitería analógica incluida en el núcleo de procesamiento de señal-mixta 1300 sobre el valor de NTEMP es prácticamente despreciable para valores convencionales de los parámetros implicados dado que tanto la fase de AUTO-CALIBRADO como de MEDIDA parten de las mismas condiciones iniciales y siguen el mismo protocolo de funcionamiento y, por tanto, las componentes no-ideales de los términos N2AU y N2TH (por efecto de la tensión de offset o la precisión finita de los componentes resistivos) se cancelan cuando se calcula el valor incremental, NTEMP. De este modo, si la frecuencia de operación del convertidor y la longitud del contador digital 1420 son lo suficientemente altas (para reducir el error de cuantización inherente al recuento digital), la precisión en la medida de la temperatura en un tiempo de lectura determinado viene básicamente dada por la tolerancia del termistor el cual, mediante técnicas apropiadas de calibración, puede alcanzar precisiones del orden de + 0.01°C en el rango de 0 a 70°C. It is relevant to highlight that the impact of the imperfections of the analog circuitry included in the 1300 mixed-signal processing core on the value of NTEMP is practically negligible for conventional values of the parameters involved given that both the AUTO-CALIBRATION phase and the phase of MEASURE they start from the same initial conditions and follow the same operating protocol and, therefore, the non-ideal components of the terms N2AU and N2TH (due to the effect of offset voltage or the finite precision of the resistive components) are canceled when The incremental value, NTEMP, is calculated. Thus, if the frequency of operation of the converter and the length of the digital counter 1420 are high enough (to reduce the quantization error inherent in the digital count), the precision in the measurement of the temperature in a given reading time is basically given by the tolerance of the thermistor which, by means of appropriate calibration techniques, can reach accuracies of the order of + 0.01 ° C in the range from 0 to 70 ° C.
En una de realización particular de la presente invención, el convertidor temperatura-a-digital se usa con fines clínicos para medir la temperatura corporal de pacientes. El convertidor emplea un termistor intercambiable en contacto directo con la piel del individuo y alcanza una precisión de aproximadamente + 0.1°C (limitada por la tolerancia del termistor) en un rango de temperaturas de 30-45 °C. El circuito activo de lectura y conversión puede operar con tensiones de alimentación de entono a IV y, para una frecuencia de operación FTS de alrededor de 3-4kHz, obtiene un consumo de alrededor de 4 microwatios. El tiempo empleado por el dispositivo para la medición y conversión de la temperatura corporal es del mismo orden de magnitud que los termómetros clínicos basados en detección de infrarrojos (del orden de segundos), sin embargo, aspectos tales como el coste de implementación, consumo de corriente o factor de forma son muy inferiores en este ejemplo de realización de la presente invención. In a particular embodiment of the present invention, the temperature-to-digital converter is used for clinical purposes to measure the body temperature of patients. The converter uses an interchangeable thermistor in direct contact with the individual's skin and reaches an accuracy of approximately + 0.1 ° C (limited by the thermistor tolerance) in a temperature range of 30-45 ° C. The active reading and conversion circuit can operate with intonation supply voltages to IV and, for an FTS operating frequency of around 3-4kHz, it obtains a consumption of around 4 microwatts. The time taken by the device for measuring and converting body temperature is of the same order of magnitude as clinical thermometers based on infrared detection (of the order of seconds), however, aspects such as the cost of implementation, consumption of current or form factor are much lower in this embodiment of the present invention.
En el contexto de la presente invención, los términos "aproximadamente" o "del orden de" deben entenderse como indicando valores muy próximos a los que dicho término acompañe. El experto en la técnica entenderá que una pequeña desviación de los valores indicados, dentro de unos términos razonables, es inevitable debido a imprecisiones de medida, etc. In the context of the present invention, the terms "approximately" or "of the order of" should be understood as indicating very close values to which said term accompanies. The person skilled in the art will understand that a small deviation from the indicated values, within reasonable terms, is inevitable due to measurement inaccuracies, etc.
A lo largo de esta especificación, el término "comprende" y sus derivados no debe interpretarse en un sentido excluyente o limitativo, es decir, no debe interpretarse en el sentido de excluir la posibilidad de que el elemento o concepto al que se refiere incluya elementos o etapas adicionales . Throughout this specification, the term "comprises" and its derivatives should not be construed in an exclusive or limiting sense, that is, it should not be construed to exclude the possibility that the element or concept to which it refers includes elements or additional stages.

Claims

REIVINDICACIONES
1. - Convertidor de temperatura-a-digital (1000) de alta precisión con bajo consumo de potencia caracterizado porque comprende: 1. - High precision temperature-to-digital converter (1000) with low power consumption characterized in that it comprises:
• un termistor RTH (1510) cuya resistencia depende de la  • an RTH thermistor (1510) whose resistance depends on the
temperatura;  temperature;
• un conjunto de elementos discretos invariables con la temperatura que comprende :  • a set of discrete elements invariable with the temperature comprising:
o un resistor RP (1530);  or an RP resistor (1530);
o un resistor RS (1520);  or an RS resistor (1520);
o un condensador de integración CINT (1540);  or a CINT integration capacitor (1540);
• un circuito de lectura y conversión (1300) que mide la resistencia del termistor y convierte dicho valor representativo de la temperatura, en un código digital para su posterior procesado ;  • a reading and conversion circuit (1300) that measures the resistance of the thermistor and converts said temperature representative value into a digital code for further processing;
tal que el resistor RS (1520) y el termistor RTH (1510), por un lado, y el resistor RP (1530), por otro, forman dos ramas de circuito que se conectan por un extremo a un nudo común y donde los tres terminales resultantes están conectados a otros tantos nudos del circuito de lectura y conversión. such that the resistor RS (1520) and the thermistor RTH (1510), on the one hand, and the resistor RP (1530), on the other, form two circuit branches that are connected at one end to a common node and where the three Resulting terminals are connected to as many nodes of the reading and conversion circuit.
2. - Circuito de lectura y conversión de la temperatura tal y como se encuentra definido en la reivindicación 1, en donde dicho circuito de lectura y conversión está caracterizado por que comprende: 2. - Temperature reading and conversion circuit as defined in claim 1, wherein said reading and conversion circuit is characterized in that it comprises:
• un generador de tensiones de referencia (1100);  • a reference voltage generator (1100);
• un generador de fases de reloj (1200);  • a clock phase generator (1200);
• un control digital (1400);  • a digital control (1400);
• un núcleo de procesado de señal mixta (1300) conectado con:  • a mixed signal processing core (1300) connected with:
o el generador de tensiones de referencia (1100) que envía al núcleo de procesado de señal mixta (1300) una tensión en modo común "VCM", una tensión de referencia negativa "VREFN" y una tensión de referencia positiva "VREFP";  or the reference voltage generator (1100) that sends a common mode voltage "VCM", a negative reference voltage "VREFN" and a positive reference voltage "VREFP" to the mixed signal processing core (1300);
o el generador de fases de reloj (1200), el cual recibe una señal de reloj "CLKTS" y envía al núcleo de procesado de señal mixta (1300) una señal formada por trenes de pulsos de la misma frecuencia que la señal de reloj "CLKTS" recibida; además, el generador de fases de reloj (1200) está conectado con el control digital (1400) al cual envía una señal de reloj "CLKTSYS" idéntica a la señal de reloj "CLKTS" pero con un retraso de dos unidades de retraso; el control digital (1400) al cual envía una señal lógica "COMP" y del cual recibe una señal "SRTH" y una señal "SRB"; además, el control digital (1400) tiene una entrada RESET, una salida binaria TRDY y una salida NTEMP que representa la temperatura medida de forma digital. or the clock phase generator (1200), which receives a "CLKTS" clock signal and sends to the mixed signal processing core (1300) a signal formed by pulse trains of the same frequency as the clock signal " CLKTS " received; in addition, the clock phase generator (1200) is connected to the digital control (1400) to which it sends a clock signal "CLKTSYS" identical to the clock signal "CLKTS" but with a delay of two delay units; the digital control (1400) to which it sends a logic signal "COMP" and from which it receives a signal "SRTH" and a signal "SRB"; In addition, the digital control (1400) has a RESET input, a TRDY binary output and an NTEMP output that represents the temperature measured digitally.
3. - Circuito de lectura y conversión de la temperatura según la reivindicación 2, en donde el generador de tensiones de referencia (1100) está caracterizado por que comprende: 3. - Temperature reading and conversion circuit according to claim 2, wherein the reference voltage generator (1100) is characterized in that it comprises:
• un generador de tensión (1110) que proporciona un voltaje estable "VBG", insensible con la temperatura y conectado con un raíl de alimentación negativa "VSSA" y un raíl de alimentación positiva "VDDA"; • a voltage generator (1110) that provides a stable voltage "VBG", insensitive to the temperature and connected with a negative power rail "VSSA" and a positive power rail "VDDA";
• un divisor resistivo (1120) que a su vez comprende tres resistencias insensibles con la temperatura (1121,1122,1123); • a resistive divider (1120) which in turn comprises three temperature insensitive resistors (1121,1122,1123);
• tres seguidores de tensión (1130,1140,1150) que obtienen la tensión de referencia positiva "VREFP", la tensión en modo común "VCM" y la tensión de referencia negativa "VREFN" a partir de las tensiones en los nudos intermedios de la escalera de resistencias "VTP", "VTM" y "VTN", respectivamente; y una red capacitiva (1160) formada por los condensadores (1161,1162,1163) conectados, respectivamente, entre las salidas de los tres seguidores de tensión (1130, 1140, 1150) y el raíl de alimentación negativa "VSSA". • three voltage followers (1130,1140,1150) that obtain the positive reference voltage "VREFP", the common mode voltage "VCM" and the negative reference voltage "VREFN" from the tensions in the intermediate nodes of the resistance ladder "VTP", "VTM" and "VTN", respectively; and a capacitive network (1160) formed by the capacitors (1161,1162,1163) connected, respectively, between the outputs of the three voltage followers (1130, 1140, 1150) and the negative feed rail "VSSA".
4. - Circuito de lectura y conversión de la temperatura según la reivindicación 2, en donde núcleo de procesado de señal mixta (1300) está caracterizado por que comprende: 4. - Temperature reading and conversion circuit according to claim 2, wherein the mixed signal processing core (1300) is characterized in that it comprises:
• un amplificador operacional (1370);  • an operational amplifier (1370);
• un comparador (1380) conectado a la salida del amplificador operacional (1370); • un conjunto de dos inversores lógicos (1390) que proporcionan dos señales negativas "SRTHN" y "SRBN" de las señales de control "SRTH" y "SRB", respectivamente; • a comparator (1380) connected to the output of the operational amplifier (1370); • a set of two logical inverters (1390) that provide two negative signals "SRTHN" and "SRBN" of the control signals "SRTH" and "SRB", respectively;
• un primer conjunto de llaves analógicas (1310, 1320, 1330, 1340) ;  • a first set of analog keys (1310, 1320, 1330, 1340);
• un segundo conjunto de llaves analógicas (1350, 1360);  • a second set of analog keys (1350, 1360);
donde la resistencia de cada una de las llaves analógicas es varios órdenes de magnitud inferior a las resistencias del termistor RTH (1510), del resistor RP (1530) y del resistor RS (1520) . where the resistance of each of the analog keys is several orders of magnitude lower than the resistors of the thermistor RTH (1510), resistor RP (1530) and resistor RS (1520).
5.- Método para medir y digitalizar la resistencia del termistor RTH comprendido en el convertidor temperatura-a-digital de alta precisión con bajo consumo de potencia definido en la reivindicación 1, donde el método comprende las siguientes cuatro etapas que se suceden consecutivamente : 5. Method for measuring and digitizing the resistance of the RTH thermistor comprised in the high-precision digital-to-digital converter with low power consumption defined in claim 1, wherein the method comprises the following four steps that follow one after the other:
• una primera etapa, denominada de AUTO-CERO 1, en donde se descarga el condensador de integración de forma que la tensión de salida del amplificador operacional toma el valor de modo común, VCM;  • a first stage, called AUTO-ZERO 1, where the integration capacitor is discharged so that the output voltage of the operational amplifier takes the common mode value, VCM;
• una segunda etapa, denominada de AUTO-CALIBRADO, en donde se cortocircuita el termistor externo y se generan dos rampas a la salida del amplificador operacional, una positiva y otra negativa; la primera rampa tiene una duración fija de NI ciclos de reloj con frecuencia FTS y se obtiene conectando la rama del resistor RP a una tensión VREFP y la rama del resistor RS a una tensión VREFN; la segunda rampa se genera conectando la rama del resistor RP a un nudo de tierra virtual y la rama del resistor RS a una tensión VREFP y concluye cuando el comparador detecta que la salida del amplificador operacional es inferior a la tensión de modo común; la duración de esta segunda rampa se monitoriza mediante un contador que determina el número de ciclos de reloj, N2AU, contenido en dicho intervalo, una vez concluida la etapa de auto-calibrado, el valor N2AU se guarda en una dirección del registro digital;  • a second stage, called AUTO-CALIBRATION, where the external thermistor is short-circuited and two ramps are generated at the output of the operational amplifier, one positive and the other negative; the first ramp has a fixed duration of NI clock cycles with FTS frequency and is obtained by connecting the resistor branch RP to a VREFP voltage and the resistor branch RS to a VREFN voltage; the second ramp is generated by connecting the branch of the resistor RP to a virtual ground node and the branch of the resistor RS to a VREFP voltage and concludes when the comparator detects that the output of the operational amplifier is less than the common mode voltage; the duration of this second ramp is monitored by a counter that determines the number of clock cycles, N2AU, contained in said interval, once the self-calibration stage is concluded, the N2AU value is stored in an address of the digital register;
• una tercera etapa, denominada de AUTO-CERO 2, en donde se descarga el condensador de integración de forma que la tensión de salida del amplificador operacional toma el valor de modo común, VCM; y, • a third stage, called AUTO-ZERO 2, where the integration capacitor is discharged so that the voltage Output of the operational amplifier takes the common mode value, VCM; Y,
• una cuarta etapa, denominada etapa de MEDIDA, en donde se repite la etapa de AUTO-CALIBRADO, sólo que, en este caso, el termistor RTH no está cortocircuitado y la duración de la segunda rampa durante la etapa de medida se monitoriza mediante un contador que determina el número de ciclos de reloj, N2TH, contenido en dicho intervalo; una vez concluida la etapa de medida, el valor N2TH se guarda en otra dirección del registro digital;  • a fourth stage, called the MEASURE stage, where the AUTO-CALIBRATION stage is repeated, only that, in this case, the RTH thermistor is not short-circuited and the duration of the second ramp during the measurement stage is monitored by a counter that determines the number of clock cycles, N2TH, contained in said interval; Once the measurement stage is completed, the N2TH value is stored in another address of the digital register;
tal que la resistencia del termistor RTH es proporcional al término dependiente de la temperatura NTEMP = (N2AU - N2TH) donde dicho término se calcula mediante un sumador binario a partir de los valores almacenados en las dos direcciones del registro digital. such that the resistance of the RTH thermistor is proportional to the temperature dependent term NTEMP = (N2AU - N2TH) where said term is calculated by a binary adder from the values stored in the two directions of the digital register.
PCT/ES2013/070720 2012-10-18 2013-10-18 High-precision temperature-to-digital converter with low power consumption WO2014060631A1 (en)

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US3906391A (en) * 1974-06-14 1975-09-16 Westinghouse Electric Corp Linear period thermistor temperature oscillator
US3942123A (en) * 1970-06-15 1976-03-02 Ivac Corporation Electronic measurement system
US4568913A (en) * 1980-03-25 1986-02-04 Intersil, Inc. High speed integrating analog-to-digital converter
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WO2009019632A1 (en) * 2007-08-06 2009-02-12 Nxp B.V. Signal processor comprising an integrating analog-to-digital converter

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Publication number Priority date Publication date Assignee Title
US3942123A (en) * 1970-06-15 1976-03-02 Ivac Corporation Electronic measurement system
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US4568913A (en) * 1980-03-25 1986-02-04 Intersil, Inc. High speed integrating analog-to-digital converter
US5128676A (en) * 1990-06-05 1992-07-07 Blh Electronics, Inc. Variable conversion rate analog-to-digital converter
WO2009019632A1 (en) * 2007-08-06 2009-02-12 Nxp B.V. Signal processor comprising an integrating analog-to-digital converter

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