WO2014057289A1

WO2014057289A1 - Ion-sensitive field-effect transistor

Info

Publication number: WO2014057289A1
Application number: PCT/GB2013/052676
Authority: WO
Inventors: David M. Garner
Original assignee: Dna Electronics Ltd
Priority date: 2012-10-12
Filing date: 2013-10-14
Publication date: 2014-04-17
Also published as: GB201218356D0; GB2508582A

Abstract

The invention relates to an ion-sensitive field effect transistor (ISFET), which is provided with a Ti N layer between an ion-sensitive layer and the gate of the transistor. Preferably the ISFET is provided with a well disposed over the gate of the transistor.

Description

ION-SENSITIVE FIELD-EFFECT TRANSISTOR

Technical Field

The present invention relates to an ion-sensitive field-effect transistor and is of particular use in biochemical sensors such as DNA sensor arrays.

Background

Field-effect transistors, such as ion-sensitive field-effect transistors (ISFETS), have become a common component of many biochemical sensors today. Two examples of known ISFETs are illustrated in Figure 8 and 9. Figure 9 is an example of an early ISFET made in a customised process, wherein the electrolyte 83 is exposed to the gate 16 to affect the channel between source and gate. Figure 8 is typical of more recent ISFETs made in standard CMOS processes, wherein a metal stack (18 and 20) extends the gate towards the electrolyte but is separated from it by a standard passivation layer such as Silicon Nitride.

An ISFET typically comprises a substrate 10 which has doped regions forming a source 12, a drain 14 and bulk 13. The source, drain, and bulk are each provided with electrodes 81 to make electrical connection to them. A gate insulator 21 is formed between the source 12 and the drain 14 and a gate 16 is formed between the gate insulator 21 and the metal via 20.

When a voltage is applied on the gate 16 the availability of charge within the area of the substrate 10 adjacent to the gate oxide 21 is altered. When a sufficiently large voltage is applied the availability of charge is such that a conducting channel between the source and drain is created. This conducting channel allows a current, which can be measured, to flow between the source and the drain. The size of the current conducted by the channel is proportional to the amount of charge in the channel which in turn is proportional to the voltage applied to the gate.

The polysilicon gate 16 is coupled to multiple metal layers 18 having one or more additional via layers 20 disposed between them to form a floating gate structure. The top metal layer 18 of the floating gate structure is in contact with an ion-sensitive layer 25. The ion-sensitive layer is sensitive to a change in the ion concentration within an electrolyte, reagent, or other fluid contacting this layer.. Different ion-sensitive layers can be used to detect different ions, for example Silicon Nitride, Silicon Dioxide, and Ta₂0₅ are sensitive to hydrogen ions.

When a change in the ion concentration occurs, the ion-sensitive layer will either accept/donate protons from the solution resulting in a change in the charge on the surface of the ion-sensitive layer. If the change in the charge on the ion-sensitive layer is sufficient then it will result in sufficient voltage to be applied, via the gate, to increase the channel between the source and drain changing theamount of current. In addition to the capacitance between the floating gate and source and between the floating gate and drain of the ISFET (C_isfe,) there is an additional capacitance (C_chem) which is also known as double layer capacitance which arises at the interface between the solution in the well and the ion-sensitive layer. There are also parasitic capacitances between the floating gates and conductors that might be adjacent to the floating gate in a practical realisation of the ISFET.

Summary of the Invention

In accordance with a first aspect of the present invention there is provided an ion- sensitive field-effect transistor, ISFET, comprising: a metal layer, an ion-sensitive layer; and a Titanium Nitride (TiN) layer between the metal layer and the ion-sensitive layer. The TiN layer provides an additional layer to prevent diffusion or drift under electric field of ions or electrons into the gate metal, which would lead to an electrical current passing from the fluid sitting in the well to the gate and would render the gate no longer floating. Additionally, it acts as a resistor, which in combination with C_iSfet and the floating gate's parasitic capacitances, forms a low pass filter to filter out noise generated during a chemical reaction.

The TiN layer preferably has a depth of 10 to 400nm. This depth allows the TiN to act as a stop layer when a well is etched into an insulating layer deposited over the gate of the ISFET.

The metal layer may be the gate metal layer of the ISFET or, alternatively, the ISFET gate may be coupled to a plurality of metal layers the metal layers each being separated by an oxide layer each containing a metal via layer and the metal layer is the one of the plurality of metal layers furthest from the ISFET gate. The ISFET may also include an insulating layer, the insulating layer having a well formed in it, the well being disposed above the gate of the ISFET. The ion sensitive layer may be one of Al₂0₃, Si₃N_4! Hf0₂ or Ta₂0₅ and/or the insulating layer may be one or more of TEOS-oxide, HDP-oxide, PECVD-oxide or other CVD oxide, or Si0₂.

The well may have at least one inclined wall. Additionally, the well may have a circular, rectangular, hexagonal or octagonal cross-section.

In accordance with a second aspect of the present invention there is provided a method of manufacturing an ISFET comprising the steps of: depositing a metal layer; depositing a TiN layer; applying a mask; and etching the metal layer and the TiN layer using the mask. By etching the TiN layer and metal layer using the same mask the number of masks required to produce the ISFET can be minimised.

The method may include the additional steps of: growing an insulating layer over the etched metal and TiN layer, applying a mask over the insulating layer and etching a well in the insulating layer. The TiN layer acts as a stop layer for the etching process.

An ion-sensitive layer may then be deposited over the etched insulating layer. The ion- sensitive layer is advantageously formed of a compound which is capable of Atomic Layer Deposition (ALD) at low temperature, a temperature below the CMOS thermal budget which is typically in the range 250 to 400 degrees Celsius. ALD gives a layer with low porosity which passivates the surface and prevents ingress of liquid into the chip.. Additionally, by depositing the ion-sensitive layer over the etched layers no further etching of the well is required meaning that the ion-sensitive layer provides a smooth surface to the inside of the well.

Alternatively the ion-sensitive layer may be deposited over the etched metal and TiN layers before growing the insulating layer. This method includes the further steps of growing an insulating layer over the ion sensitive layer, applying a mask over the insulating layer and etching a well in the insulating layer. In accordance with a third aspect of the present invention there is provided an ion- sensitive field-effect transistor, ISFET, comprising a gate structure and an insulating layer including a well disposed over the gate structure, the well having at least one side configured so that the cross sectional area of the well decreases towards the gate structure.

The well of the ISFET of the third aspect may preferably have at least one inclined wall. The well may have a circular, rectangular, hexagonal or octagonal cross-section. Brief Description of the Drawings

Figure 1 illustrates an ISFET;

Figure 2 is a flow diagram for a method of making an ISFET in accordance with a first embodiment of the present invention;

Figure 3 is a cross-section through the ISFET manufactured using the method of Figure 2;

Figure 4 is a flow diagram for a method of making an ISFET in accordance with a first embodiment of the present invention;

Figure 5 is a cross-section through the ISFET manufactured using the method of Figure 4;

Figure 6 is a circuit diagram of the ISFET of the present invention;

Figure 7 is a perspective view of a well;

Figure 8 is a cross-section of a known ISFET formed in a standard CMOS process; and Figure 9 is a cross-section of a known ISFET formed in a customised process. Detailed Description

One embodiment of the present invention will now be described with reference to Figures 2 and 3. An ISFET is constructed in any known manner on a substrate including a source and a drain up to and including depositing the gate metal layer (S1 ). The ISFET of the present invention is then constructed using the following steps:

52. Following the deposition of the gate metal layer 30, a layer of TiN 32 is deposited on the gate metal layer 30.

53. The mask for the gate metal layer 30 is applied to the TiN layer 32. 54. The TiN and gate metal layers are etched using any suitable method which may include plasma etch or wet chemical etch.

55. An insulating layer of High-Density Plasma (HDP) Oxide or TEOS oxide or PECVD oxide or any combination of the three is grown on the ISFET in accordance with standard CMOS procedures such as plasma deposition.

56. A mask defining a well 22 which is to be disposed over the gate is applied. S7. A well 22 is etched in the HDP oxide layer using known techniques.

S8. A layer of Ta₂0₅ is deposited over the ISFET to form the ion-sensitive layer. The resulting structure above the gate of the ISFET is illustrated in Figure 3.

Another method of forming a well in accordance with the present invention is now described with reference to Figures 5 and 6. Like features are denoted by the same reference numerals. In Figure 5, as with Figure 3, the ISFET is constructed in any known manner on a substrate including a source and a drain up to and including depositing the gate metal layer (S1 1 ). The ISFET of this embodiment is then formed by the following steps:

512. Following the deposit of the gate metal layer 30, a layer of TiN 32 is deposited on the gate metal layer 30.

513. The mask for the gate metal layer 30 is applied to the TiN layer 32.

514. The TiN and gate metal layers are etched using the mask.

515. A layer 38 of Ta₂0₅ is applied over the ISFET.

S16. An insulating layer 34 made of Silicon dioxide is grown on the ISFET over the layer of Ta₂0₅ in accordance with standard CMOS procedures such as plasma deposition S17. A mask defining a well area over the ISFET gate is applied

S17. A well is etched in the insulating layer 34 up to the Ta₂0₅ layer 38.

An illustration of a well made in accordance with this method is illustrated in Figure 5. As can be seen this provides a well which only has an ion-sensitive layer at the base of the well. This has the advantage that the binding of hydrogen ions within the well is localised to the base which may reduce the amount of buffering of the hydrogen ions within the well.

In the ISFETs of either embodiment of the present invention the metal layer 30 may be the gate metal layer of the ISFET or the top metal layer of a floating gate structure such as that illustrated in Figure 1 . The gate metal layer may be aluminium, copper, polysilicon, or any other suitable metal.

In both of the above embodiments it is preferable that the TiN layer is between 10 and 400nm. This depth enables the TiN layer to perform multiple functions. Firstly, when used in the method described with reference to Figure 2, it acts as a stop layer when the well is etched into the HDP Oxide. Secondly it acts to prevent charge in the form of both ions and electrons in the solution in the well leaking through the ion-sensitive layer and charging the top metal layer causing the gate to no longer be floating and leading to incorrect measurements. Thirdly, with reference to Figure 7 which illustrates the circuit of an ISFET including a TiN layer, the TiN layer due to having a resistivity between that of a metal and an insulator acts as a resistor between the capacitor of the field-effect transistor and the capacitor between the liquid and the ion-sensitive layer. The resistive effect of the TiN layer in combination with the capacitance of the field-effect transistor results in the action of a low pass filter to filter out any high-frequency noise.

As can be seen the TiN layer 32 is situated above the gate metal layer 30 and the gate metal layer and TiN layer form the same shape due to being etched using the same mask. The well 22 in the HDP Oxide 34 is disposed above the TiN layer 32 allowing the gate to react to any changes in ion concentrations within the well. Finally, the ion- sensitive Ta₂0₅ layer 38 covers the entirety of the ISFET.

Preferably the ion-sensitive layer has a depth of 5 to 25nm. The ion-sensitive layer may be one of Al₂0₃, Hf0₂ Si₃N₄ or Ta₂0₅ although any suitable compound may be used. It is preferable for the ion-sensitive layer to be a high-sensitivity material, capable of ALD at a low temperature. ALD makes the ion-sensitive layer more dense and less porous. Ta₂0₅ is an example of one such material. Although the above ISFET has been described using HDP oxide as an insulating layer in which a well is formed one skilled in the art will understand may be made of any suitable material. For example, as an alternative to HDP Oxide the insulating layer may be formed by Tetraethyl orthosilicate (TEOS) Oxide, PECVD oxide or Silicon dioxide.

The ion-sensitive layer may be any one of Al₂0₃, Si₃N_4! Hf0₂ or Ta₂0₅. It is preferable for the sensing layer to be Ta₂0₅ as this is capable of high density deposition at a low temperature meaning that any irregularities in the upper surface of the TiN layer caused during the etching process can be smoothed out. Preferably, the ion sensitive layer has a depth of 5 to 25nm. Ta205 is a high sensitivity material and ALD deposition makes the ion-sensitive layer formed by more dense and less porous.

It is preferable that the wells etched in the insulating layer have sides which incline so that the cross-sectional area at the bottom of the well is less than that at the top of the well. One example of such a well is illustrated in Figure 7. By tapering the sides of the walls in this manner beads having a diameter that matches the diameter of the well at an intermediate point between the top and the bottom of the well can be readily captured and held within the well. Having the beads held in tight frictional engagement with the wall of the well in this way also acts to concentrate hydrogen ions in the bottom of the well underneath the bead.

Although Figure 7 illustrates a well having a square cross-section the well may have any suitable cross-section including, but not limited to, circular, oval, rectangular, hexagonal and octagonal. Preferably the ISFET is fabricated in an 180nm CMOS process to create a semiconductor chip comprising an array of ISFETs. In one embodiment there are more than one million ISFETs. In one embodiment there are less than one million ISFETs. In one embodiment the chip shape is a rectangle measuring 25mm x 27mm.

Claims

CLAIMS:

1. An ion-sensitive field-effect transistor, ISFET, comprising:

a metal layer;

an ion-sensitive layer; and

a TiN layer between the metal layer and the ion-sensitive layer.

2. An ISFET as claimed in claim 1 wherein the TiN layer has a depth of 10 to 400nm.

3. An ISFET as claimed in claim 1 or claim 2 wherein the metal layer forms part of a floating gate of the ISFET.

4. An ISFET as claimed in claim 3 wherein a gate of the ISFET is coupled to a plurality of metal layers, the metal layers each being separated by an oxide layer and connected by a metal via, and the metal layer is the one of the plurality of metal layers furthest from the polysilicon gate.

5. An ISFET as claimed in any preceding claim wherein the ion sensitive layer comprises one of Al₂0₃, Si₃N₄ , Hf0₂ or Ta₂0₅.

6. An ISFET as claimed in any preceding claim further comprising an insulating layer, the insulating layer having a well formed in it, the well being disposed above the gate of the ISFET.

7. An ISFET as claimed in claim 6 wherein the insulating layer comprises one of TEOS-oxide, HDP-oxide, PECVD-oxide or Si0₂.

8. An ISFET as claimed in claim 6 or claim 7 wherein the well has at least one inclined wall.

9. An ISFET as claimed in any one of claims 6 to 8 wherein the well has a circular, rectangular, hexagonal or octagonal cross-section.

10. A method of manufacturing an ISFET comprising the steps of:

a) depositing a metal layer; b) depositing a TiN layer;

c) applying a mask; and

d) etching the metal layer and the TiN layer using the mask.

11 . A method of manufacturing an ISFET, as claimed in claim 10 further comprising the steps of:

depositing an insulating layer over the etched metal and TiN layer, applying a mask over the insulating layer and etching a well in the insulating layer.

12. A method of manufacturing an ISFET as claimed in claim 1 1 further comprising depositing an ion-sensitive layer over the etched insulating layer.

13. A method of manufacturing an ISFET as claimed in claim 10 further comprising the step of depositing an ion-sensitive layer over the etched metal and TiN layers.

14. A method of manufacturing an ISFET as claimed in claim 13 further comprising the step of depositing an insulating layer over the ion sensitive layer, applying a mask over the insulating layer and etching a well in the insulating layer.

15. An ISFET substantially as illustrated in and described with reference to Figures 3, 5, 6 and 7.

16. A method of manufacturing an ISFET substantially as illustrated in and described with reference to Figures 2, 4 and 6.