WO2014057106A1

WO2014057106A1 - Image sensor

Info

Publication number: WO2014057106A1
Application number: PCT/EP2013/071325
Authority: WO
Inventors: Thomas Schweiger; Harald Neubauer; Frank Wippermann; Andreas Brückner; Alexander Oberdörster
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 2012-10-12
Filing date: 2013-10-11
Publication date: 2014-04-17
Also published as: WO2014057104A1; DE102012218834B4; DE102012218835A1; DE102012218835B4; DE102012218834A1

Abstract

The invention relates to an image sensor having a plurality of pixel groups and a column ADC comprising a plurality of individual ADCs. At least one first individual ADC of the plurality of individual ADCs is located in a first gap between a first pixel group and a second pixel group of the plurality of pixel groups and at least one second individual ADC of the plurality of individual ADCs is located in a second gap between the second pixel group and a third pixel group of the plurality of pixel groups. The first individual ADC is designed to convert pixel signals of a first pixel column of the second pixel group from analogue to digital. The second individual ADC is designed to convert pixel signals of a second pixel column of the second pixel group from analogue to digital.

Description

image sensor

description

Technical area

Embodiments of the present invention relate to an image sensor. In particular, embodiments of the present invention relate to an image sensor having a plurality of pixel groups.

Background of the invention

In so-called electronic cluster images (German: group image sensors) are image sensors that have several small pixel groups instead of a single large image field. In such conventional image sensors, the analog-to-digital conversion is placed outside the image field.

Cluster imagers (German: group image sensors) are used in combination with cluster lenses. The latter are multi-channel imaging systems, which have a reduced overall height compared to conventional cameras based on a single-aperture lens. In this case, of the individual imaging channels, which are formed from one or more optical interfaces and filters, a part of the total field of view is transmitted to an associated pixel group. In this way, areas of the object can be assigned to the individual partial images, and the partial images can be combined both software-based and electronics-based to form the overall image. The object regions imaged in parallel by the various optical channels can be suitably detected and converted by the parallelized pixel groups of the cluster image. In this case, the geometric arrangement of the pixel groups is designed in accordance with the geometric arrangement of the optical channels. Optics and image converters are therefore to be understood as an overall system, with both subcomponents having to be coordinated with one another. For example, by appropriate design of the optics, the subsequent electronic image processing can be simplified, which is used inter alia for correcting distortion by field coordinate-dependent pixel shift or field coordinate-dependent deployment according to the location-dependent point image blurring function. Optimal optical imaging performance can ideally - -

From distortion. Achromasie and consistency of the Punktbildveraschungsfunktion result, which allows a trivial image post-processing and correspondingly simple electronics and software processing. Conversely, a simplified optical design can be used if both chromatic and monochromatic field-dependent aberrations are allowed since they are corrected by software or electronics-based processing.

Such image sensors with a split image field have the disadvantage that, for optomechanical reasons, gaps arise between the image fields, which increase the total area of the image sensor and thus the costs for such an image sensor.

Summary of the Invention It is therefore an object of the present invention to provide a concept for an image sensor which enables reduction of the total area of a split field image sensor.

This object is achieved by an image sensor according to independent patent claim 1 and an image sensor according to independent claim 9 and by methods according to independent claims 22 and 23.

Embodiments of the present invention provide an image sensor having a plurality of pixel groups as well as a column ADC (Analog-to-Digital Converter) having a plurality of single ADCs. At least a first single ADC of the plurality of single ADCs is disposed in a first space between a first pixel group and a second pixel group of the plurality of pixel groups, and at least a second single ADC of the plurality of single ADCs is in a second one Space between the second pixel group and a third pixel group of the plurality of pixel groups arranged. The first single ADC is configured to analog to digital convert pixel signals of a first pixel column of the second pixel group and the second single ADC is configured to analog to digital convert pixel signals of a second pixel column of the second pixel group. In the present application, a column ADC is understood to mean the entirety of the individual ADCs of the image sensor, the column ADC typically being configured to use a single (complete) pixel row of the image sensor using its individual ADCs at the same time to convert analog to digital. Each individual ADC is typically responsible for a complete (pixel) column of the image sensor.

It has been found that by using the gaps between the individual pixel groups or image fields, the total area of the image sensor is increased and thus the costs are increased. In embodiments of the present invention, to reduce the overall chip area of the image sensor again, the column ADC is placed within the image field between the pixel groups (in the spaces between the pixel groups). However, because these pixel group spaces are relatively small, there are special requirements for the architecture and layout of the column ADC.

It is now an idea of embodiments of the present invention that a column ADC can be placed in spaces between different pixel groups. However, the problem here is that a complete ADC (which converts pixel signals of all pixel columns of a pixel group analog to digital) typically does not fit in such a space between two adjacent pixel groups. According to exemplary embodiments of the present invention, the individual ADCs of the column ADC, which respectively convert pixel signals (pixel group-spanning) of a pixel column of the image sensor analog-to-digitally, are distributed over spaces between pixel groups (adjacent in the column direction) such that the number of individual pixel groups differs. ADCs per space is smaller than the number of pixel columns per pixel group of the column groups adjacent pixel groups. The total number of individual ADCs still corresponds to the number of pixel columns per pixel group. For example, when dividing into two spaces, a single ADC allows the width of two pixel columns of a group of pixels to be accommodated. Of course, splitting into more than two spaces (between pixel-adjacent pixel groups) is also possible, and as the number of spaces to which the individual ADCs are distributed increases, so does the available width for a single ADC.

A key idea of the present invention is therefore the division of the column ADC into two (or N) ADC parts, each of these ADC parts being responsible for the even and odd pixel columns (or each Nth column). One such ADC part is the individual ADCs of the column ADCs. which are arranged in the same space. As a result, there is more horizontal space for each individual ADC (namely, the width of, for example, two pixel columns instead of just one), and each single ADC can thus be made wider. Because of conservation of space, it takes up less vertical space and therefore fits in the gap between pixel groups. , ,

According to embodiments of the present invention, therefore, the column ADC is subdivided into at least two interspaces (between pixel groups adjacent in the column direction of the image sensor), in each of which at least one individual ADC is located, each of these individual ADCs each having pixel signals of a pixel column (pixel group). group across the fend) of the entire image sensor analog to digital converts. For example, a space in which such a single ADC is arranged - or a plurality of such single ADCs are arranged - may be the space between two pixel groups adjacent in the column direction.

Of course, the said principle can be extended to a field of pixel groups, the individual ADCs each being arranged in intermediate spaces between pixel groups adjacent to the column direction. At least one individual ADCs is arranged in each column of pixel groups in at least two interspaces of this column, which is designed to convert pixel signals of the same pixel column of the pixel groups arranged in this column analog to digital. Typically, the number of individual ADCs per column equals the number of pixel columns per pixel group in that column.

In other words, the column ADC is divided into individual sub-blocks (into the individual single ADCs), so that the area between the individual pixel groups can be minimized. The entire column ADC therefore requires multiple spaces to accommodate all the individual ADCs of the column ADC in the spaces between the pixel groups on the image sensor. Due to the placement of the individual ADCs of the column ADCs in the spaces between the pixel groups, it is possible to dispense with arranging the column ADC on the edge of the image sensor, thereby reducing the overall chip area of the image sensor compared to conventional image sensors in which the column ADC is located at the edge Edge is located, lets shrink significantly.

It is therefore an advantage of embodiments of the present invention over conventional split field image sensors that a split field image sensor can be fabricated which has a significantly lower overall chip area over conventional image sensors.

Further embodiments of the present invention provide an image sensor having a plurality of pixel groups and a column ADC having a plurality of single ADCs. Each individual ADC is designed to generate at least pixel signals of pixel columns of two different pixel groups from the plurality of pixel groups analog to digital to change. Further, the single ADCs of the plurality of single ADCs are arranged in spaces between adjacent pixel groups of the plurality of pixel groups.

It has also been found that, particularly with respect to image sensors having a group level ADC, an improved image sensor can be achieved by employing a column ADC whose single ADCs are arranged in spaces between adjacent pixel groups and each one ADC converts at least pixel signals from pixel columns of two different pixel groups from the plurality of pixel groups analog to digital. This has the advantage, in particular over image sensors with group-level ADCs, that, on the one hand, the individual ADCs can be made significantly smaller than a single group-level ADC and, furthermore, the advantage that the clock rate of the individual ADCs can be selected to be lower than for group-level ADCs because the number of pixels to be converted per unit of time is lower for the individual ADCs mentioned than for typical group-level ADCs. Thus, such group level ADCs typically need to convert a complete set of pixels analog to digital, while a single ADC of a column ADC typically only converts one pixel column analog-to-digital. For example, it is sufficient to provide a single ADC per pixel column of a pixel group. This individual ADC can then be designed, for example, to convert pixel signals of one pixel column (for example, in each case the same pixel column) of each pixel group of the plurality of pixel groups analog to digital. Embodiments of the present invention further provide an image sensor which has the advantage over image sensors having conventional group-level ADCs in that complexity (due to the lower required clock rate) of the ADCs on the image sensor chip becomes lower, thereby realizing an image sensor with less effort and lower cost leaves.

In summary, it was recognized that the placement of the analog-to-digital converter outside the field of view, as in conventional image sensors, in image sensors with split image field is indeed possible. However, inefficient for two reasons: On the one hand there is already space between the image fields, which should be used. On the other hand, analog-to-digital converters placed outside the image field would have to be connected to all pixels, which would require wiring between the image fields. This wiring requires extra space. Embodiments of the present invention solve these problems by dividing a column ADC into a plurality of single ADCs arranged in (any existing) spaces between adjacent pixel groups. Brief description of the figures

Exemplary embodiments of the present invention will be described in detail below with reference to the attached figures. Show it:

1a is a schematic representation of an image sensor according to an embodiment of the present invention, in which pixel signals from two different pixel columns of a pixel group of two individual ADCs arranged in different interspaces are converted analog to digital;

Fig. Lb is a schematic representation of an image sensor according to another

An embodiment of the present invention, wherein pixel signals of a first pixel column of a first pixel group and a first pixel column of a second pixel group are analog-to-digital converted from a single ADC located in a space between these two pixel groups;

FIG. 2 illustrates how a conventional single ADC may be converted such that it fits into spaces between individual pixel groups according to embodiments of the present invention.

3 shows an image sensor according to a further embodiment which combines the concepts shown in FIGS. 1a and 1b; 4 shows an image sensor according to a further exemplary embodiment of the present invention

Invention in which the memory of the individual ADCs is combed like a comb;

Fig. 5 is a schematic representation of an imaging device according to a

Embodiment of the present invention; and

6 is a flow chart of a method according to an embodiment of the present invention.

Detailed description of exemplary embodiments

of the present invention - -

Before describing embodiments of the present invention in detail below, it should be pointed out that identical elements or elements having the same function are provided with the same reference numerals. Before the exemplary embodiments are described in detail, the problems of image sensors with a split image field are again summarized. Image sensors with split image field have the problem that gaps between pixel fields are dead areas. d. H. they cause costs but no use, the price of the sensor increases approximately proportionally with the surface.

An example will be given below: area for a conventional image sensor (contiguous image field): Fs = pixel area P + logic area L

Area for a sensor with split image field:

Fm = pixel area P + logic area G + gap area L

Therefore, Fm = Fs + L. The goal is therefore to fill the gap area with logic so that L = 0 and Fm = Fs. Prerequisite for G> L. If G = L, the logic fills the gaps completely. If G> L, part of the logic still sits outside the frame; that does not matter, because Fm = Fs.

In fact, Fm = Fs is unattainable because rearranging the logic into the pixel areas adds extra wiring area V: Fm = Fs + V. Moreover, some parts of the logic are blocks of fixed minimum size or shape. The following inventions aim to minimize V and divide logic blocks.

From the above considerations, therefore, the following presets arise for image sensors with split image field:

1. Logic blocks should be made as small as possible so that they can be distributed well (or not block the distribution of other blocks and their wiring). 2. Logic blocks should be located between the image fields to minimize the area of the entire image sensor die. Ideal case: Silicon area between image fields is fully utilized. 3. Wiring between logic blocks (and pixel groups) should be minimized

Embodiments of the present invention solve this problem by arranging individual ADCs in the spaces between adjacent pixel groups of an image sensor, which together form a column ADC of the image sensor.

1 a shows a schematic representation of an image sensor 100 according to an exemplary embodiment of the present invention.

The image sensor 100 has a plurality of pixel groups 101a to 101c. Further, the image sensor 100 includes a column analog-to-digital converter (also referred to as a column ADC). This column ADC has a plurality of individual analog-to-digital converters 103a, 103b (also referred to as single ADCs 103a, 103b).

As can be seen in FIG. 1a, in the image sensor 100, a first single ADC 103a of the column ADC is arranged in a first gap 105a between a first pixel group 101a and a second pixel group 101b of the plurality of pixel groups. It is arranged a second single ADC 103 b of the column ADCs in a second intermediate space 105b between the second pixel group 101 b and a third pixel group 101 c of the plurality of pixel groups. The first single ADC 103a is configured to analog-to-digitalize pixel signals of a first pixel column 101b-1 of the second pixel group 101b, and the second single ADC 103b is configured to receive pixel signals of a second pixel column c 101b-2 of the second pixel group 101 b analog to digital to convert.

As already explained in the introductory part of this application, it is an idea of embodiments of the present invention that a column ADC is divided into a plurality of single ADCs 103a to 103b which respectively receive pixel signals of a pixel column 101,10 -2 of a pixel group 101b analog to digital, so that these individual ADCs 103a. 103 b in gaps 105 a, 105 b between pixel groups 101 a to 101 c of the image sensor 100 fit. By dividing the column ADC into the plurality of single ADCs 103a, 103b, these single ADCs 103a. 103b fit into the spaces 105a, 105b. It is therefore no longer necessary to change the column ADC on the edge of the image sensor 100 to arrange, since this fits distributed in the spaces 105a, 105b between the pixel groups 103a-103c, which can save chip area. It has therefore been recognized that the gaps between the individual pixel groups 101a to 101c may be utilized in split field image sensors to operate in these single ADCs 103a. 103b of a column ADC, in a simplest embodiment of the present invention, exactly one individual ADC of the column ADC can be arranged in each case in a space between two adjacent pixel groups. This single ADC can be designed to convert pixel signals of one pixel column of each pixel group of the image sensor 100 analog to digital. The column ADC can therefore be divided into as many individual ADCs as there are pixel columns per pixel group 101a to 101c.

According to further embodiments, also a plurality of single ADCs of the column ADCs may be located in a space between two adjacent pixel groups. This is illustrated by way of example in FIG. 1 a where, in addition to the first single ADC 103 a, a third single ADC 103 c of the column ADC and a fifth individual ADC 103 e of the column ADC are also located in the first gap 105 a. Further, in the second space 105b, further, a fourth single ADC 103d and a sixth single ADC 103f of the column ADC are arranged. The number of single ADCs located in such a gap 105a, 105b, or disposed in such a gap 105a, 105b, may vary according to some embodiments and is particularly dependent on the size of the individual ADCs as well as the size of the gaps 105a, 105b dependent. In this case, each of the individual ADCs 103c-103f may, as with the first individual ADC 103a and the second individual ADC 103b, be configured to analog pixel-to-digital pixel signals from pixel columns 101b-3 to 101b-6 of the second pixel group 101b to change.

In the exemplary embodiment shown in FIG. 1 a, the third individual ADC 103 c is designed to analogously digital-convert pixel signal c of a third pixel column 101 b-3 of the second pixel group 101 b, forming the fourth individual ADC 103 d, u pixel signals of a fourth Pixel column 101 b-4 of the second pixel group 101 b analog to digital to convert, the fifth single ADC 103 e formed to convert pixel signals of a fifth pixel column 101 b- 5 of the second pixel group 101 b analog to digital, and the sixth single ADC 103 f configured to analog to digitally convert pixel signals of a sixth pixel column 101 b-6 of the second pixel group 101 b.

As can be seen from FIG. 1a, the lines of the pixel columns 101bl can thereby be selected. 101b-6 of the second pixel group 101b are led out alternately at the top and bottom. So - -

For example, the individual ADCs 103a to 103e arranged in the first space 105a may be formed to respectively analog-to-digitally convert pixel signals of an odd pixel column 101b-1, 101b-3, 101b-5, the second pixel group 101b, and the single ADCs 103b, 103d, 103f in the second space 105b may be formed to receive pixel signals of even pixel columns 101b-2, respectively. 101b-4, 101b-6 of the second pixel group 101b analog to digital to convert.

Furthermore, the sub-numbers of individual ADCs arranged in the interspaces 105a, 105b may be selected such that a total width of the sub-plurality of individual ADCs which are each arranged in a gap 105a, 105b (for example a total width of the individual ADCs 103a, 103c, 103e and / or the individual ADCs 103b, 103d, 103f) is less than or equal to a total width of the second pixel group 101b. In other words, the individual ADCs 103a to 103f are distributed to the spaces 105a, 105b between the pixel groups 101a to 101c such that they do not laterally project beyond the widths of the pixel groups 101a to 101c.

Further, each of the single ADCs 103a to 103f may be dedicated to one pixel column 101b-l to 101b-6 of the second pixel group 101b, respectively, to pixel signals of only those dedicated pixel columns 101b-1 and 101b-6 and no other pixel column of that second pixel group 101 analog to digital to convert. Nevertheless, a single ADC may further be configured to convert pixel signals of a pixel column of another pixel group of the image sensor 100 analogously to digital (for example, the first pixel group 101a and / or the third pixel group 101c), as will be described below with reference to FIG. 1b and 3 are shown by way of example.

For example, the first single ADC 103a may further be configured to analog-to-digitally convert pixel signals of a first pixel column 101a-1 of the first pixel group 101a.

Furthermore, the second individual ADC 103b may also be designed to convert digitally analog pixel signals of a second pixel column 101a-2 of the first pixel group 101a.

The assignment of the individual ADCs 103a to 103f to the individual pixel columns of the pixel groups 101a. 101b can take place in such a way that each of the individual ADCs 103a to 103f is designed in each case to convert pixel signals of the same pixel column of the different pixel groups 101a to 101c analog to digital.

For example, the first single ADC 103a may be configured to respectively analog to digital pixel signals of the first pixel column of each pixel group of the image sensor 100 - -

The second single ADC 103b may be configured to respectively analog to digital convert pixel signals of the second pixel column of each pixel group of the image sensor 100, and so on. The column ADC is configured to simultaneously analog-to-digitally convert one complete row of a pixel group (for example, the second pixel group 101b) or even the entire image sensor 100 (using the plurality of single ADCs 103a to 103f). Although only three pixel groups 101a to 101c are shown in the exemplary embodiment shown in FIG. 1a, the image sensor 100 can also have further pixel groups. The number of pixel groups can vary and depends in particular on the chosen application. Above all, the pixel groups can be arranged in a field of pixel groups with, for example, X columns and Y rows, where X is greater than or equal to 2 and Y is greater than or equal to 2.

In this case, the individual ADCs 103a to 103f of the column ADC of the image sensor 100 can each be located at intervals of pixel groups 101a to 101c adjacent to the column direction (direction in the one column). In other words, according to embodiments of the present invention, no individual ADCs can be arranged in spaces between two image detectors adjacent in the row direction (direction in the one line).

Fig. 1b shows an image sensor 150 according to another embodiment of the present invention. The image sensor 150 has a plurality of pixel groups 101 a to 101 c. Further, the image sensor 150 has a column ADC having a plurality of single ADCs 103a. 103b on. Each of the individual ADCs 103a, 103b is designed to generate at least pixel signals from pixel columns of two different pixel groups from the plurality of pixel groups 101a, 101b. 101 c analog to digital to convert. Further, the individual ADCs 103a, 103b are arranged in spaces 105a to 105b between adjacent pixel groups 101a to 101c of the plurality of pixel groups 101a to 101c. For example, a first single ADC 103a of the column ADC is arranged in a first space 105a between a first pixel group 101a and a second pixel group 101b. A second single ADC 103b is disposed in a second space 105b between the second pixel group 101b and a third pixel group 101c. The first individual ADC 103a is designed to convert pixel signals of a first pixel column 101a-1 of the first pixel group 101a and a first pixel column 101b-l of the second pixel group 101b into analog to digital. The second single ADC 103b is designed - -

to obtain pixel signals of a second pixel column 101b-2 of the second pixel group 101b and

Pixel signals of a second pixel column 101c-2 of the third pixel group 101c analog to digital to convert. The image sensor 150 shown in FIG. 1b is based on the idea that an efficient arrangement of a column ADC on an image sensor 150 can be made possible if this column ADC is divided into individual ADCs and these individual ADCs are in spaces between adjacent ones Pixel groups are arranged. Each of the individual ADCs is designed to convert pixel signals of pixel columns of at least two different (in the column direction adjacent) pixel groups analog to digital. Thus, in particular, in comparison with group-level ADCs, it is possible to make the spacing between adjacent pixel groups smaller because the resulting individual ADCs can typically also be made smaller than a group-level ADC (which converts pixel signals of a complete pixel group analog to digital instead only from one pixel column). Furthermore, in general, the clock rate of the ADCs used on the image sensor 150 can be significantly reduced as compared to a group level ADC, since pixel signals only pixel columns of different pixel groups (and not complete pixel groups) can be converted analog to digital with the same single ADC ,

The image sensor 150 shown in FIG. 1b can also be extended by the further optional features which have been described in connection with the image sensor 100 shown in FIG. 1a. Therefore, it will not be discussed again in detail below on these further optional features.

Figure 2 illustrates the principle of reshaping a single ADC of a column ADC such that this single ADC fits into the spaces between adjacent pixel groups (as shown, for example, with reference to Figure 1a and with reference to Figure 1b). 2 shows, based on an image sensor 200 according to a further exemplary embodiment of the present invention, how a plurality of individual ADCs of the column ADC can be placed in the image field between interrupted pixel fields. The image sensor 200 shown in FIGS. 2-4 differs from the image sensor 100 shown in FIG. 1a merely in that a fourth pixel group 101b is also shown, and furthermore that each of the pixel groups 101a to lOld has eight pixel columns. Accordingly, the column ADC also has eight single ADCs 1 03a-103h. Further, four single ADCs 103a, 103c, 103c. 103g in the first gap 105a and four single ADCs 103b. 103d. 103f, 103h are arranged in the second space 105b. - -

From Fig. 2-1 it can be seen that a single ADC has a fixed area requirement. Arrange the elements so. that the single ADC has the width of a pixel column, it does not fit in the gap between two pixel fields (or between two pixel groups).

Fig. 2-2 shows how the single ADC can be reshaped. The resulting area is retained.

From Fig. 2-3 it can be seen that the single ADC now fits into the gap between the pixel fields, but every other column would be without an analog-to-digital converter (ADC) and therefore can not be read. Readable columns are right-hatched (from top left to bottom right), orphaned columns remain white.

2-4 therefore shows that according to embodiments of the present invention, a second set of ADCs (a second set of single ADCs 103b, 103d, 103f, 103h) is placed in the next gap 105b between the pixel groups 101b, 101c ( left-hatched from top right to bottom left) and with the remaining columns not already being read out by the individual ADCs 103a, 103c, 103e, 103g in the other gap 105a. Thus, all the pixels of the image sensor 100 can be read out. The remaining gaps between the other image fields (for example, further down or also laterally) remain free except for wiring.

In summary, the width of an ADC is typically limited by the width of a column (pixel pitch, or twice the pixel pitch for transistor sharing). The area is also given (capacitors, transistors etc). This results in a minimum height that is greater than the gap between image fields can be. Also, a single ADC typically also can not be split: thus, ADCs do not fit between pixel groups.

From Fig. 2, the solution to the above-mentioned problem becomes apparent that the single ADCs are reshaped and thus the column ADC is reshaped to fit in the gaps between the pixel groups. The new parts are initially too wide, so only 1 N of the columns can be read out. Therefore, according to embodiments of the present invention, further groups of individual ADCs of the column ADC are placed in the remaining gaps until all columns are readable.

This results in a significant reduction in space compared to systems in which a

Column ADC is arranged with its individual ADCs on the edge of the image sensor. - -

Furthermore, the advantage over group level image sensors is that no parallel signal lines with the pixel values are routed over the entire chip, which would additionally increase the space requirement.

In other words, in embodiments of the present invention, a column level or column level ADC is employed. Due to the limited width per ADC, the ADCs would have to be long and narrow layout. It would therefore take very large pixel group spacings to place this column level ADC in the image field. Therefore, in embodiments of the present invention, the column ADC is divided into sub-blocks (into the single ADCs) so that the area between the pixel groups can be minimized. The column ADC is therefore split into multiple pixel group gaps or spaces between pixel groups. All pixels of a line of the image sensor, across groups, get their own single ADC. For reasons of space, these single ADCs are split into multiple pixel group spaces.

FIG. 3 shows an image sensor 300 (for example, in a plan view) having a plurality of pixel groups 101 a to 101 i. The pixel groups 101a to 101i may be arranged in an NxM matrix, for example. In the embodiment shown in FIG. 3, the pixel groups 101a to 10 are arranged in a 3x3 matrix. However, the number of pixel groups per image sensor 300 may vary and, in particular, may be selected depending on the desired maximum resolution of the image sensor 300. Further, the image sensor 300 has a column ADC subdivided into a plurality of single ADCs 303-1 to 303-18. Each of the individual ADCs 303-1 to 303-18 is designed to convert pixel signals of an associated pixel column of the image sensor 300 analog to digital. In the exemplary example shown in FIG. 3, each pixel group 101a-101i has six pixel columns (and six pixel rows). The first single ADC 303-1 is therefore configured to analog-to-digitally convert pixel signals of the first pixel columns of the pixel groups 101a, 101b, and 101c. The second single ADC 303-2 is configured to receive pixel signals of the second pixel columns Pixel groups 101a, 101b and 101c to convert analog to digital and so on. The number of individual ADCs 303-1 to 303-18 of the biological sensor 300 thus corresponds (pixel group-spanning) to the number of pixel columns of the image sensor 300 (in the example 18). Each of the individual ADCs 303-1 to 303-18 is configured to analog-to-digitally convert pixel signals each of a pixel column {pixel group-spanning) of the image sensor. The numbering of the pixel columns and the single ADCs 303-1 to 303-18 in the drawing indicates which - -

Single ADCs 303-1 to 303-18 which pixel column for analogue-to-digital conversion of

Pixel signals are associated with the pixel column.

Furthermore, in the exemplary embodiment shown in FIG. 3, in each case 3 individual ADCs are arranged between two adjacent pixel groups. According to further embodiments, it is also possible that only a single ADC is arranged in each case between two adjacent pixel groups or that a larger number of individual ADCs is arranged between two adjacent pixel groups. It can also be seen from FIG. 3 that the individual ADCs 303-1 to 303-18 are each arranged in intermediate spaces between pixel groups adjacent in the column direction of the image sensor.

Further, in spaces between adjacent pixel groups in the row direction of the image sensor 300, there are no single ADCs of the column ADC. These spaces can be used for wiring, for example.

Further, also in the image sensor 300 shown in FIG. 3, it can be seen that each of the individual ADCs 303-1 to 303-18 is configured to split pixel signals from pixel groups 101a to 100c associated with the single ADC 303-1 to 303-18 To convert 10Oli from the plurality of pixel groups 101a to lOli analog to digital. In this case, each individual ADC 303-1 to 303-18 is assigned the same pixel column (for example, the first pixel column, the second pixel column, the third pixel column, etc.) of pixel fields 101a-101c, 101d-101f, 101g-101i arranged in the column direction , In other words, each individual ADC 303-1 to 303-18 is formed to receive pixel signals of the same pixel column of pixel groups 101a-101c adjacent in a column direction of the image sensor 300, respectively. l Ol d-l Ol f. l Ol g-l Ol i the various pixel groups 101 a to 101 i analog to digital to convert. Furthermore, the column ADC is designed to simultaneously convert or read out at least pixel signals of an entire (pixel) line of the image sensor analog to digital. This can be done by having pixel signals of an entire pixel row of the image sensor 300

(Across pixel group groups) at the same time of each of the associated individual ADC 303-1 to 303-18 analog to digital converted. The pixel signals can be read line by line. The individual pixel lines can be read one after the other. So z. For example, first line by line the pixel rows of the pixel groups 101a, 10U1. 101g, then the pixel groups 101b, 10e, 101h and then the - -

For example, the individual ADCs 303-1 to 303-18 are connected to the pixel rows of the different pixel groups 101a to 1011, respectively.

3 that each individual ADC 303-1 through 303-18 are each located in a space located between the columnar pixel groups whose pixel signals are from one of their pixel columns from the respective single ADC 303-1. 1 to 303-18 are analog to digital converted. In other words, each of the individual ADCs 303-1 to 303-18, together with the pixel groups 101a to lOlf whose pixel signals of one of their pixel columns are analog-to-digital converted from the respective single ADC 303-1 to 303-18, is the same column of the image sensor 300 is arranged. This avoids having to route pixel lines from the pixel columns to the individual ADCs 303-1 to 303-18 transversely (in the row direction) on the image sensor 300. This leaves free area between adjacent pixel groups in the row direction, which can be used, for example, for further logic or for wiring.

Further, the plurality of pixel groups 101a to 1091 may be disposed on the same substrate of the image sensor 300 (for example, together with the column ADC).

In the column or column level ADCs used according to embodiments of the present invention, the pixels of a pixel row are respectively converted in parallel in a single ADC per pixel column. The maximum width of the single ADCs in the layout can be doubled when two ADC banks are placed on the image sensor and the pixel columns are alternately connected to the upper and lower single ADCs, as already shown in Fig. 1a, for example.

This is also the case with the image sensor 400 shown in FIG. 4 according to a further exemplary embodiment of the present invention.

In the image sensor 400 shown in FIG. 4, four pixel groups 101 a to 101 d are shown schematically. However, this image sensor 400 typically also has further pixel groups, which may be arranged above or below the pixel groups 101a to 101d shown in FIG. 4 or also laterally next to these pixel groups 101a to 101d.

In the image sensor 400 shown in FIG. 4, the column ADC of the image sensor 400 has eight single ADCs 403a to 403h. Each of the eight single ADCs 403a to 403h is respectively configured to analog-to-digitally convert pixel signals of the same pixel span of column-adjacent pixel fields of the image sensor 400. For example, a first single ADC 403a is configured to respectively receive pixel signals of the first pixel columns - -

The second single ADC 403b is configured to analog to digitally convert pixel signals of the second pixel columns of the pixel groups 101a, 101b, etc. In other words, an n-th single ADC of the column array 101a, 101b is analog-to-digital. ADCs are designed to convert pixel signals of the n-th pixel column of the image sensor 400 analogously to digital (pixel groups over each other).

The individual ADCs 403a to 403h are respectively disposed in spaces between adjacent pixel groups of the image sensor 400 (not shown in Fig. 4, since only the four pixel groups 101a to l0ld are shown).

Further, each of the individual ADCs 403a to 403h has its own memory 41a to 41h assigned to receive the digitized signal after analog-to-digital conversion. In other words, for each of the single ADCs 403a to 403h, the column ADC has a memory 41a to 411h associated with the respective single ADC 403a to 403h for storing the digitized pixel signals. The output of the digital data (the digital pixel signals) from the chip takes place serially.

In a conventional image sensor whose column ADC is placed as a block at the edge of the frame, the pixel data may be output in a shift register. This means that the data is available line by line, pixel by pixel for further processing.

If the individual ADCs are now placed in several banks as shown in FIG. 4, the problem arises that the data is no longer output line by line, pixel by pixel (provided the respective ADC blocks receive a serial interface).

Embodiments of the present invention solve this problem by placing a plurality of single ADC banks (the single ADC blocks 403a-403h) distributed on the image sensor 400 and the single ADCs alternately up and down as shown in FIG Below are out to double the maximum ADC width in the layout, but the memory 41 1 a to 41 1 h again combed like a comb to sort the digital Pixelsignalc one line still on the chip or on the image sensor 400 again. In other words, the memories 41 la to 41 1 h are entangled such that the order of the output pixel signals corresponds to the order of the pixel columns of the image sensor 400. ,

For example, the pixel signal of each of the first pixel column is allowed to be output first, and the pixel signal of the last column is output last, or vice versa (as shown in Fig. 4). In other words, the column ADC of the image sensor 400 for each individual ADC 403a to 403h has its own memory 41a to 41h for storing the analog-to-digital converted pixel signals of pixel columns or pixel columns of the pixel groups 101a associated with the single ADCs 403a to 403h until lOld. In this case, the memories 41 1a to 41 1h are entangled with one another as a function of the pixel column or pixel columns of the pixel groups 101 a to 101 d assigned to the individual ADCs 403 a to 403 h.

The memories 41 1a to 41 1h are entangled in such a way that, in the case of a serial read-out of the memory 411a to 411h, the order of the read-out digital pixel signals of the individual ADCs 403a to 403h corresponds to an order in the row direction of the pixel columns of the image sensor 400.

4 shows the image sensor 400 in which the individual ADCs 403a to 403h are led out alternately downwards (odd pixel columns) and upwards (even pixel columns). Each of the individual ADCs 403a to 403h has its own memory 41a to 411h (which in the example has a bit width of 10 bits) which receives the converted digital signal (the respective digital pixel value in the current pixel row and the current pixel column). By comb-like entanglement of memory 411 a to 41 1h no re-sorting and thus no more wiring effort is needed to output the digital data line by line.

The concept of entanglement of the memories 41 1 a to 41 1 h shown in FIG. 4 has the advantage that resorting of the pixel data is no longer necessary. In addition, this solution variant shown in FIG. 4 with only one memory bank requires a smaller chip area than a variant with several (for example two) memory banks and corresponding sorting of the signals by means of this (two) memory banks.

Another advantage of embodiments of the present invention is. that the possible distribution of the individual ADCs on the spaces between the pixel groups, the sizing of the spaces is determined only by the optics and can be chosen independently of the sizes of the ADCs, as the number of ADCs. which are placed in a gap, can be varied. - -

In summary, in embodiments of the present invention, it has been recognized that gaps are created between the individual image fields (or between the individual pixel groups) in split field image sensors, which, if left unused, increase the overall area of each image sensor and hence the cost. In order to reduce the overall chip area of the clustered optical eye (the split-field image sensor), the analog-to-valley set (the column ADC) is placed within the image field, between the pixel groups. Since these pixel group spacings are typically relatively small, the column ADC is split into a plurality of single ADCs, each of which converts pixel signals of a pixel column of the image sensor analog to digital. These single ADCs are then arranged distributed on a chip of the image sensor in a plurality of pixel group spaces.

Embodiments of the present invention have the advantage over conventional split-field image sensors in which the ADC is located out of the frame, that the space available between the frames is used to place the individual ADCs. Further, there are no out-of-frame ADCs that need to be connected to all pixels, which would require wiring between the frames which in turn would require extra space.

Embodiments of the present invention can be used in principle in all image sensors with a split image field. In principle, these sensors can be used wherever conventional image sensors are used, especially in applications where low construction height is important. This is z. As is the case with cameras in entertainment and communications electronics (mobile phones, laptops, tablets) and in the material and component examination in tight spaces (such as in slots and holes).

Fig. 5 shows a schematic representation of an imaging device according to an embodiment of the present invention. The imaging device 500 includes an image sensor 501 according to an embodiment of the present invention

(For example, the image sensor 100 or another image field split image sensor according to an embodiment of the present invention). Furthermore, the imaging device 500 comprises a multi-channel optical system 503. Each channel of the multi-channel optical system 503 is assigned a pixel group of the image sensor 100 such that object points. which are detected by the channel to which the pixel group associated with the channel is mapped. - -

Further embodiments of the present invention therefore provide an imaging device with an image sensor according to an embodiment of the present invention, which also (optionally) has optics matched thereto and image post-processing in addition to the image sensor or image converter with corresponding arrangement of a field of pixel groups.

6 shows a flowchart of a method 600 according to an embodiment of the present invention. The method 600 includes a step 601 of providing a pixel signal of a first pixel column of a second pixel group of a plurality of pixel groups of an image sensor through a first single ADC of a column ADC of the image sensor, wherein the first single ADC is in a first space between the second Pixel group and a first pixel group of the plurality of pixel groups is arranged.

The method 600 further comprises a step 603 of providing a further pixel signal of a second pixel column of the second pixel group by a second single ADC of the column ADC, the second single ADC in a second space between the second pixel group and a third pixel group of the plurality is arranged by pixel groups.

The method 600 may be performed by an image sensor according to an embodiment of the present invention, such as the image sensor 100. Further, steps 601 and 603 may be performed simultaneously.

Although some aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or device of a device is also to be understood as a corresponding method step or feature of a method step. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation may be done using a digital storage medium, such as a floppy disk, a DVD. a Blu-Ray Disc, a CD. a ROM, a PROM, an EP ROM, an EEPROM or a FLASH memory, a hard disk or other magnetic - -

or optical memory are stored on the electronically readable control signals that can cooperate with a programmable computer system or cooperate such that the respective method is performed. Therefore, the digital storage medium can be computer readable. Thus, some embodiments of the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system to perform one of the methods described herein. In general, embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer. The program code can also be stored, for example, on a machine-readable carrier.

Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium. In other words, an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer. A further embodiment of the inventive method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program is recorded for carrying out one of the methods described herein.

A further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals, which represents or represents the computer program for performing one of the methods described herein. The data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet. Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein. - -

Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein.

In some embodiments, a programmable logic device (eg, a programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. In general, in some embodiments, the methods are performed by any hardware device. This may be a universal hardware such as a computer processor (CPU) or hardware specific to the process, such as an ASIC.

The embodiments described above are merely illustrative of the principles of the present invention. It will be understood that modifications and variations of the arrangements and details described herein will be apparent to others of ordinary skill in the art. Therefore, it is intended that the invention be limited only by the scope of the appended claims and not by the specific details presented in the description and explanation of the embodiments herein.

Claims

claims

An image sensor (100, 200, 300, 350, 400) comprising: a plurality of pixel groups (101a to l Oli); a column analog-to-digital converter having a plurality of single analog-to-digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h); wherein at least a first single analog-to-digital converter (103a) of the plurality of single analog-to-digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h) in a first space (105a) between a first pixel group (101a) and a second pixel group (101b) of the plurality of pixel groups (101a to l Oli) is arranged and at least a second single analog-to-digital converter (103b) of the plurality of single analog-to-digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h) in a second space (105b) between the second pixel group (101b) and a third pixel group (101c) the plurality of pixel groups (101a to lOli) is arranged; wherein the first single analog-to-digital converter (103 a) is configured to analog-to-digitally convert pixel signals of a first pixel column (101b-l) of the second pixel group (101b), and wherein the second single analog-to-digital converter Digital converter (103b) is adapted to analog to digital to convert pixel signals of a second pixel column (101b-2) of the second pixel group (101 b); wherein the column analog-to-digital converter for each individual analog-to-digital converter (403a to 403h) has its own memory (41 1a to 41 lh) for storing the analog-to-digital converted pixel signals of the Single analog-to-digital converter (403a to 403h) associated pixel column or pixel columns; and wherein the memories (41 1 a to 41 1 h) depending on the individual analogue to

Digital converters (403a to 403h) associated pixel column or pixel columns are entangled with each other.

Image sensor (100, 200, 300, 350, 400) according to claim 1, wherein the first single analog-to-digital converter (103a) is further adapted to analog-to-digital convert pixel signals of a first pixel column (101a-l) of the first pixel group (101a). The image sensor (100, 200, 300, 350, 400) according to any one of claims 1 to 2, wherein the second single analog-to-digital converter (103b) is further adapted to receive pixel signals of a second pixel column (101a-2 ) of the first pixel group (101a) analog to digital.

4. Image sensor (100, 200, 300, 350, 400) according to one of claims 1 to 3, wherein at least a third individual analog-to-digital converter (103c) of the plurality of individual analog-to-digital converter Converters (103a to 103f, 303-1 to 303-18, 403a to 403h) in the first space (105a) or the second space

(105b) is arranged; and wherein the third single analog-to-digital converter (103c) is adapted to analog-to-digital convert pixel signals of a third pixel column (101b-3) of the second pixel group (101b).

The image sensor (100, 200, 300, 350, 400) according to any one of claims 1 to 4, wherein in the first space (105a), a sub-plurality of individual ADCs (103a, 103b, 103e, 303-1, 303-2 303-3) of the plurality of single ADCs (103a to

1031; 303-1 to 303-18, 403a to 403h); and wherein a total width of the sub-plurality of individual ADCs (103a to 103e. 303-1 to 303-3) is less than or equal to an entire width of the second pixel group (101b).

The image sensor (100, 200, 300, 350, 400) according to any one of claims 1 to 5, wherein the column ADC for each pixel column (101b-1 to 101b-6) of the second pixel group (101b) has an in Having the first gap (105a), the second intermediate space (105b) or a further gap between two adjacent pixel groups of the plurality of pixel groups (101a to 101 i) arranged dedicated single ADC (103a to 103f) formed is to convert pixel signals of this pixel column (101 h to 101 b-6) analog to digital. An image sensor (100, 200, 300, 350, 400) according to claim 6, wherein each of the dedicated single ADCs (103a to 103f) is further adapted to receive at least pixel signals of another pixel column of another pixel group (101a, 101c to 10li). from the plurality of pixel groups (101a to lOli) analog to digital to convert.

An image sensor (100, 400) according to any of claims 1 to 7, wherein a first subset of individual analog-to-digital converters (103a, 103c, 103e) of the plurality of single analog-to-digital converters ( 103a to 103f) are disposed in the first space (105a) and a second subset of individual analog-to-digital converters (103b, 103d, 103f) of the plurality of individual analog-to-digital converters (103a to 103f) 103f) are disposed in the second space (105b); wherein each of said first sub-plurality of individual analog-to-digital converters (103a, 103c, 103e) is adapted to analogize pixel signals of each odd-numbered pixel column (101, 101b-3, 101b-5) of said second pixel group (101b) to convert to digital; and wherein each of said second sub-plurality of individual analog-to-digital converters (103b, l (), 3d, 103f) is adapted to receive pixel signals each of a straight pixel column (101b-2, 101b-4, 101b-6) second pixel group (101b) analog to digital to convert.

An image sensor (100, 150, 200, 300, 350, 400) comprising: a plurality of pixel groups (101a to 10Ii); a column analog-to-digital converter having a plurality of single analog-to-digital converters (103a to 103. 303-1 to 303-18, 403a to 403h); wherein each Emzei analog-to-digital converter (103a to 103f, 303-1 to 303-18, 403a to 403h) is adapted to analog at least pixel signals of pixel columns of two different pixel groups of the plurality of pixel groups (101a to 1011) to convert to digital; wherein the single analog to digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h) of the column analog-to-digital converter are provided in spaces (105a, 105b) between adjacent pixel groups of the plurality of pixel groups (101a to 10li); wherein the column analog-to-digital converter for each individual analog-to-digital converter (403a to 403h) own memory (41 la to 41 lh) for storing the analog-to-digital converted pixel signals of the Single analog-to-digital converter (403a to 403 h) associated pixel column or pixel columns has; and wherein the memories (41 1a to 411 h) are entangled with one another in dependence on the pixel columns or pixel columns assigned to the individual analog-to-digital converters (403 a to 403 h).

An image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 9, wherein the individual analog-to-digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h) are arranged in intermediate spaces (105a, 105b) between pixel groups which are adjacent in the column direction of the image sensor (100, 150, 200, 300, 400).

An image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 10, wherein no individual analog to. In pixel spaces in the row direction of the image sensor (100, 150, 200, 300, 400) adjacent pixel groups Column analog-to-digital converter digital converters are located.

An image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 11, wherein each of the individual analog-to-digital converters (103a to 103f, 303-1 to 303-18, 403a to 403h) is formed. pixel columns of different pixel groups (101a to 10li) of the plurality of pixel groups associated with pixel signals from the single analog-to-digital converter (103a to 103f, 303-1 to 303-18, 403a to 403h)

(101a to lOli) analog to digital to convert; and wherein each individual analog-to-digital converter is assigned to the respective pixel column of the different pixel groups (101a to 101i) for converters (103a to 103f, 303-1 to 303-1, 403a to 403h).

13. Image sensor (400) according to one of the preceding claims, wherein the memory (41 la to 411 h) are entangled such that in a serial

Reading out the memories (41 l a to 41 l h) corresponds to an order of the read-out digital pixel signals of the individual analog-to-digital converters (403a to 403h) of an order in the row direction of the pixel columns of the pixel groups (101a to 101d). The image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 13, wherein the column analog-to-digital converter is adapted to generate at least pixel signals of an entire line of the image sensor (100, 150, 200, 300 , 350, 400) at the same time to convert analog to digital.

15. An image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 14, wherein each individual analog-to-digital converter (103a to 103f, 303-1 to 303-18, 403a to 403h) is adapted to analog-to-digital conversion of pixel signals of each pixel of a pixel column associated with the single analog-to-digital converter (103a to 103f, 303-1 to 303-18, 403a to 403h).

The image sensor (300, 350, 400) according to any one of claims 1 to 15, wherein a first single analog-to-digital converter (303-1, 403a) of the plurality of single analog-to-digital converters (303-1 to 303-18, 403a to 403h) or the first individual analog-to-digital converter (303-1, 403a) is adapted to receive pixel signals of pixel columns from along a column direction of the image sensor (300, 350, 400) adjacent pixel groups (101a, 101b, 101c) analog to digital ,.

The image sensor (100, 150, 200, 300, 350, 400) according to claim 16, wherein the first one-to-one analog-to-digital converter (103a, 303-1, 403a) is adapted to receive pixel signals each of the same Pixel column of the column-adjacent pixel groups (101a, 101b, 101c) analog to digital to convert.

18. Image sensor (100, 150, 200, 300, 350, 400) according to one of claims 1 to 17, wherein each pixel group (101a to 10li) has at least 5x5 pixels.

The image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 18, wherein the pixel groups of the plurality of pixel groups (101a to 10li) are arranged on the same substrate.

The image sensor (100, 150, 200, 300, 350, 400) according to any one of claims 1 to 19, wherein the column analog-to-digital converter is disposed on the same substrate as the plurality of pixel groups (101a to 10) ,

21. An imaging apparatus (500) comprising: an image sensor (501) according to any one of claims 1 to 20, and a multi-channel optical system (503), each channel of the multi-channel optical system (501) having a pixel group of the image sensor (501) associated therewith such that object points which are detected by the channel are mapped to the pixel group associated with the channel.