WO2014049402A1

WO2014049402A1 - System and method for built-in self test (bist) in an integrated circuit

Info

Publication number: WO2014049402A1
Application number: PCT/IB2012/057462
Authority: WO
Inventors: Rajath VASUDEVAMURTHY; Bharadwaj Amrutur
Original assignee: Department of Electronics and Information Tech; Indian Institute of Science IISC
Current assignee: Department of Electronics and Information Tech; Indian Institute of Science IISC
Priority date: 2012-09-28
Filing date: 2012-12-19
Publication date: 2014-04-03
Anticipated expiration: 2015-03-28

Description

SYSTEM AND METHOD FOR BUILT-IN SELF TEST (BIST) IN AN

INTEGRATED CIRCUIT

TECHNICAL FIELD

Embodiments of the present disclosure relates to Built-in Self Test (BIST) in integrated circuits. More particularly, the embodiments relate to Built-in Self Test (BIST) of analog signals for measuring on-chip voltages.

BACKGROUND

Presently, bias variation is a common problem in analog circuits and is getting worse as the technology scales. The process variation is increasing and power supply is reducing which is causing this problem. With the increasing popularity of mixed signal integrated circuits (IC) designs in the deep sub-micron processes, it is required precisely measure analog voltages for test and debugging purposes. Such situations arise when measuring on-chip voltages for built-in-self-test (BIST) applications, voltages at the terminals of sleep transistors for power monitor applications and in measuring low bandwidth signals in sensor systems. These analog voltages could be potentially located all over the chip. It is desirable that the measurement circuitry employed in such situations occupies as less area as possible and be simple to design.

There exist few techniques of displaying analog signal waveforms using sub- sampling. These methods are well-suited for viewing waveforms in a laboratory but cannot be used directly for automated testing. An existing architecture of an Analog/RF BIST subsystem describes the maximum area permissible for the BIST subsystem for the total manufacturing and testing cost reduction. In those architectures, the DC voltages (of BIST sensors) of test nodes are all tied together to a common bus and digitized centrally through a 12-bit ADC. Even AC signals are converted to DC through an envelope detector circuit, but calibration is required in this case to map the digitized values to analog amplitudes. In such a case, one has to know the number of sensor nodes in advance or design for a worst-case scenario to ensure that the value on the bus settles within a specified time. Also, for the AC case, calibration puts a lower bound on the testing time required. It would be beneficial to have an approach where the design of driver for the bus can be made independent of the number of test nodes, and also eliminate the need for calibration in testing AC signals, which would reduce the time required for testing. Techniques of analog routing, wherein voltages and/or currents to be measured in some internal circuitry are literally "scanned" out to test pins, but analog circuits are used to route analog voltages/currents, which can themselves lead to signal distortion while propagation. It is hence desirable to have testing circuitry which is simpler than those being tested.

Another existing technique is analog routing with digital interface, where an analog voltage is digitized and the bits are scanned out through a single pin. Similarly, one can also scan in digital bits and excite circuits with analog voltages using a DAC. But with reducing power supply voltages in the deep sub micron technology nodes, leading to reduction of available voltage headroom, designing conventional ADC architectures for such applications is becoming increasingly difficult. However, in the case of time based architectures, time resolution has improved since the transition time of digital signals has reduced with technology scaling. The all-digital nature of time-based approaches offers itself for scaling and suits stringent area and power specifications.

Recent techniques are focused on designing ADCs based on the methodology of time based architectures. The two main parts of such solutions are (a) 'transducer' to convert voltages into time pulses or delays, and (b) to measure time/delays. One way of implementing the transducer is to transform the input and reference voltages into time pulses, and measuring their duration was shown to yield a 9.4 ENOB SAR ADC. An extension of this technique is used to demonstrate a 10-bit ADC, working at a low supply voltage of 0.6 V, whereas conventional ADC architectures can go up to only 9 bits of resolution for a comparator noise of standard deviation of half LSB. But both these techniques do not yield themselves well for a distributed type of measurement as desired here.

Another technique uses voltage-to-time -to-digital and voltage-to-delay-to-digital architectures providing 4 bit resolution with power consumption of less than 2.4 mW. By implementing moving average filtering, a resolution of 12 μν per LSB at a sampling rate of 10 kHz is achieved. This technique uses the delay of an inverter as LSB and their linearity is therefore limited by the matching between inverter elements. Another digital approach which is gaining popularity is the VCO based approach. In this approach, the voltage to be quantized controls the frequency of the VCO, and the count of edges of the VCO output in a certain measurement time is the quantization of the analog voltage. Also, a sigma-delta ADC with the VCO as the quantizer is used to overcome the non-linearity of the voltage to frequency transfer curve. The voltage to be measured is tied to the control voltage of VCO, and as many VCOs are needed as test nodes. However, to reduce area overhead, the number of stages in the VCO needs to be small which increases it operating frequency and hence power.

In another existing technique, a ring oscillator ADC is implemented where a differential transistor pair drives two identical ring oscillators as a matched load. The voltage difference is digitized by the difference between the counters which capture the frequencies of the two oscillators. They report a bin size of 16 mV with 80 mV range and consuming a current of 37 μΑ. However, while implementing two ring oscillators, there is a possibility of injection locking and adequate care has to be taken to avoid it.

For the task of measuring analog voltages distributed all over the chip, the techniques described above require the analog signals themselves to be routed to the measuring unit. The implementation of these techniques is costly as the analog signals will have to be shielded, which can take up considerable area.

REFERENCES

[1] G. Banerjee, M. Behera, M. A. Zeidan, R. Chen, and K. Barnett, "Analog/RF built-in- self-test subsystem for a mobile broadcast video receiver in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 46, no. 9, pp. 1998-2008, September 2011.

[2] N. A. Mehta, G. V. Naik, and B. Amrutur, "In situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits," in ISLPED Digest of Technical Papers. IEEE, 2010, pp. 259-264.

[3] C.-L. Wey and S. Krishnan, "Built-in self-test (BIST) structure for analog circuit fault diagnosis," IEEE Transactions on Instrumentation and Measurement, vol. 39, no. 3, pp. 517-521, June 1990. [4] L. S. Milor, "A tutorial introduction to research on analog and mixed signal circuit testing," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 45, no. 10, pp. 1389-1407, October 1998.

[5] R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, "All-digital Tx frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, 2004.

[6] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, "A 9.4-enob lv 3.8T W lOOks/s SAR ADC with time domain comparator," in ISSCC Digest of Technical Papers, 2008, pp. 246-247,610.

[7] S.-K. Lee, S.-J. Park, H.-J. Park, and J.-Y. Sim, "A 21 fj/conversion-step 100 ks/s 10- bit ADC with a low-noise time-domain comparator for lowpower sensor interface," IEEE Journal of Solid-State Circuits, vol. 46, no. 3, March 2011.

[8] G. Li, Y. M. Tousi, A. Hassibi, and E. Afshari, "Delay-line-based analog to- digital converters," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 56, no. 6, pp. 464-470, June 2009.

[9] T. Watanabe, T. Mizuno, and Y. Makino, "An all-digital analog-to digital converter with 12y v/lsb using moving-average filtering," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 38, no. 1, pp. 120-125, April 2004.

[10] J. Bergs, Design of a VCO based ADC in a 180 nm CMOS Process for use in Positron Emission Tomography. Master's thesis, 2010.

[11] M. Z. Straayer and M. H. Perrott, "A 12-bit, 10-mhz bandwidth, continuous-time <- adc with a 5-bit, 950-ms/s VCO-based quantizer," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 805-814, April 2008. [12] J. Xiao, A. V. Peterchev, J. Zhang, and S. R. Sanders, "A 4-j a quiescent current dual-mode digitally controlled buck converter ic for cellular phone applications," IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2342-2348, December 2004.

[13] R. Vasudevamurthy, P. K. Das, and B. Amrutur, "A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test," in ISCAS Digest of Papers, 2011, pp. 2035-2038.

[14] C. S. Taillefer and G. W. Roberts, "Delta-sigma a/d conversion via time mode signal processing," IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 56, no. 9, pp. 1908-1920, September 2009.

[15] H. Pekau, A. Yousif, and J. W. Haslett, "A CMOS integrated linear voltage-to-pulse- delay-time converter for time based analog-to-digital converters," in ISCAS Digest of Technical Papers. IEEE, 2006, pp. 2373-2376.

[16] D. Fick, N. Liu, Z. Foo, M. Fojtik, J. s. Seo, D. Sylvester, and D. Blaauw, "In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter," in ISSCC Digest of Technical Papers. IEEE, 2010, pp. 188-189.

[17] P. K. Das, B. Amrutur, J. Sridhar, and V. Visvanathan, "On-chip clock network skew measurement using sub-sampling," in IEEE ASSCC Digest of Technical Papers, November 2008, pp. 401-404.

[18] Y. Zheng and K. L. Shepard, "On-chip oscilloscopes for non invasive time-domain measurement of waveforms in digital integrated circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 336-344, June 2003.

[19] R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. Horowitz, "Applications of on-chip samplers for test and measurement of integrated circuits," in Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 138-139.

[20] T. Hashida and M. Nagata, "An on-chip waveform capturer and application to diagnosis of power delivery in soc integration," IEEE Journal of Solid-State Circuits, vol. 46, no. 4, April 2011. [21] B. Amrutur, P. K. Das, and R. Vasudevamurthy, "0.84ps resolution clock skew measurement via sub-sampling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 99, pp. 1-9, November 2010.

[22] R. J. Baker, CMOS Mixed-Signal Circuit Design. IEEE Press, 2002.

[23] J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of a/d converters," IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, December 1984.

SUMMARY

The shortcomings of the prior art are overcome and additional advantages are provided through the provision of methods and systems of the present disclosure.

The present disclosure solves limitations of existing techniques by providing a built-in-self-test (BIST) at each node in an integrated circuit.

Additional features and advantages are realized through various techniques provided in the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered as part of the claimed disclosure.

In one embodiment, the disclosure provides a system configured for built-in-self- test (BIST) at each node in an integrated circuit. The system comprises one or more nodes in the integrated circuit. The test voltage of each node is measured using BIST. Also, the system comprises one or more sampling head blocks to convert the test voltage at a node into time delay, wherein each sampling head is connected to each node. The system further comprises a control unit to control the operation of the one or more sampling head to perform the BIST corresponding to each node. Further, the system includes a delay measurement unit (DMU) to receive low-frequency signals from each sampling head block to calculate the time delay and thereby, the test voltage at each node by using interpolation on pre-computed calibration data.

In another embodiment, the disclosure provides a method to perform built-in self test (BIST) at each node of an integrated circuit. The method comprises the acts of converting test voltage of a predefined node of the integrated circuit and a reference voltage corresponding to said predefined node into time delay between a pair of low-frequency signals by sub-sampling technique. The sub-sampling technique is performed using a sampling head. Next step of the method is calculating time delay corresponding to the difference between test voltage and the reference voltage to obtain a code word. Further, the method includes converting the code word into an analog value to obtain a differential voltage. The differential voltage is the difference between node voltage and reference voltage. Further, all the above steps are repeated for each node in the integrated circuit to perform BIST.

The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The novel features and characteristic of the disclosure are set forth in the appended claims. The embodiments of the disclosure itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings. One or more embodiments are now described, by way of example only, with reference to the accompanying drawings wherein like reference numerals represent like elements and in which:

Fig. la is an exemplary block diagram of analog BIST, in accordance with one embodiment.

Fig. lb is a block diagram showing blocks of sampling head (SpH), in accordance with one embodiment.

Fig. 2 shows a schematic circuit of current-starved voltage to delay cell (V2D), in accordance with one embodiment.

Fig. 3 shows a block diagram representation of analog BIST in an integrated circuit along with delay measurement unit (DMU), in accordance with an alternate embodiment.

Fig. 4 shows a timing diagram and sub-sampling in analog BIST, in accordance with one embodiment. Fig. 5 shows a Behavioral model of voltage quantization employing the DMU, in accordance with one embodiment.

Fig. 6 shows a plot of OSR versus n, showing the existence of optimal OSR for a given f , in accordance with one embodiment.

Fig. 7 shows a plot of 'offset-canceled' differential delay versus differential voltage, in accordance with one embodiment.

Fig. 8 shows DNL and INL plots for the setting of entry 8 in Table 2, in accordance with one embodiment.

The figures depict embodiments of the disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the disclosure described herein.

DETAILED DESCRIPTION

The foregoing has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described herein after which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

Exemplary embodiments of the present disclosure provide system for performing a built-in-self-test (BIST) at each node in an integrated circuit. The system comprises one or more nodes in the integrated circuit. The test voltage of each node is measured using BIST. Also, the system comprises one or more sampling head blocks to convert the test voltage at a node into time delay, wherein each sampling head is connected to each node. The system further comprises a control unit to control the operation of the one or more sampling head to perform the BIST corresponding to each node. Further, the system includes a delay measurement unit (DMU) to receive low-frequency signals from each sampling head block to calculate the time delay and thereby, the test voltage at each node by using interpolation on pre-computed calibration data.

In one embodiment the disclosure provides a method to perform built-in self test (BIST) at each node of an integrated circuit. The method comprises the acts of converting test voltage of a predefined node of the integrated circuit and a reference voltage corresponding to said predefined node into time delay between a pair of low-frequency signals by sub-sampling technique. The sub-sampling technique is performed using a sampling head. Next step of the method is calculating time delay corresponding to the difference between test voltage and the reference voltage to obtain a code word. Further, the method includes converting the code word into an analog value to obtain a differential voltage. The differential voltage is the difference between node voltage and reference voltage. Further, all the above steps are repeated for each node in the integrated circuit to perform BIST.

In one embodiment of the present disclosure, a small part of the measuring unit called sampling head (SpH) is placed at the measurement node, avoiding the routing of analog signals over long paths, as shown in fig. la. The sampling heads are placed at each node in integrated circuit in order to minimize the routing of analog signals routed over long paths. Each sampling head consists of a pair of identical delay cells (V2D) and a pair of flip-flops (DFF), as shown in fig. lb. A clock signal is routed serially to all the sampling heads, which is fed to both the delay cells in the sampling head. The delay of one element of the pair is controlled by the analog voltage VAi, and that of the other by a reference voltage V_ref. Thus, a voltage difference between the node voltage and reference shows up as a delay difference in the clocks at the output of the delay cell pair. The pair of clocks is sampled by a slightly slower sampling clock, giving rise to a pair of beat frequency signals. The sub-sampled signals and the skew between them are amplified by the process of sub-sampling. Hence, there will be as many pairs of sub-sampled signals as there are test nodes. To measure a certain test node, the corresponding sub-sampled signal pair has to be fed to the DMU with appropriate select signal to the multiplexer. Also, the design of a sampling head does not depend upon the number of test nodes desired, giving the advantage of scalability with respect to number of test nodes.

Fig. 1 shows both the input clock (elk) and sampling clock (samp elk) which are from a single point for each sampling head. Thus, cross-talk and coupling noise which may affect the clocks do not contribute to additional noise in the sampling head circuitry. Also, the output sub-sampled signal pair of the sampling head are low-frequency signals and the skew between them is already amplified by the 'sub-sampling' process, which makes the sub-sampled signal pair also immune to cross-talk and coupling noise. Also as shown in the fig. 1, reference voltage V_ref need not be the same for all the nodes.

One embodiment of the present disclosure is about measurement procedure. The delay cells of the system are non-linear and they need to be calibrated apriori. The delay cell pair, i, corresponding to VA^ is calibrated as follows: The multiplexer (MUXcal) as shown in the Fig. lb is set high so that the calibration voltage is fed, instead of the local node voltage, to each of the delay cell pairs. The select signal MUXsel_z- of the multiplexer is set to 1 to provide this voltage to one of the delay cells in pair i. The other cell gets the reference voltage. The settling time of Veal sets a bottleneck on the testing time in this mode.

As an example in one embodiment, let g^ and g^ are the voltage to delay functions of the two delay cells respectively, then the delay difference out of this cell pair, ΔΖλ is given by

AD_rg_n(Vcal)-g_i2(VreJ)

Let, a function ΐ^·) mapping AV^ to ΔΖλ defined as

The calibration step measures the function f(-) at few points, which is used later to correct for non-linearity and bias. Calibration helps in mitigating mismatches, if any, between the delay cell pairs. The delay at the input of the delay measurement unit (DMU) is given as: ADDMU=ADj+ADresidual (2) wherein ADresidual is the delay difference in the clock pair, accrued in the rest of the path. The delay difference will be independent of the voltage at node i and hence can be easily calibrated out.

During the measurement process, the multiplexer (MUXcal) is set low. To measure VA ·, the corresponding sub-sampled signal pair is selected by the multiplexor. Thus, the delay cell pair i will create a delay differential given as :

ΔΖ⁾ _Ζ· = g_n(VAi)-g_a(VreJ) (3)

:= ffVAf-Vref) (4)

The input delay difference at the DMU is as shown in the expression 2. From the calibration data, VA_z- can be inferred directly or by interpolation. The input delay difference at the DMU as shown in expression 2, from the calibration data VAi can be inferred directly or by interpolation.

Fig. 2 shows a schematic circuit of current-starved Voltage to Delay cell (V2D). The target measurement range for BIST in an integrated circuit is 0 to 100 mV. Hence, PMOS controlled current starved inverters is used as shown in Fig. 2. However, alternative delay cell architectures may be used for other applications as the specifications desire. The area of the pair of delay cells chosen for this application and taped out is 8.2 μιη x 8.4 μιη in about 130nm UMC CMOS process, in one embodiment.

As shown in the fig. 2, the voltage influences only the delay of the rising edge, while the delay of the falling edge is uncontrolled. Hence, input clock period of T and duty ratio D provides the range of the system, i.e. the value of Yin which gives an absolute delay of D , wherein D =D^ T, the maximum rising edge delay possible. As an example for a clock period of 125 ns, duty ratio of 0.5, let 120 mV provides a delay of 62.5 ns, then the range of the system is 120 mV.

One embodiment of the present disclosure provides design considerations of the system. The sizing of the delay cell circuitry is critical, so the capacitance between the analog voltage and the input clock is about 2 fF. With a decoupling capacitor of 4 pF, the kickback will be less than 0.6 mV. For smaller kickback, either the decoupling capacitor has to be increased or cascoding has to be implemented. With a transistor of gain 20 in cascode, the decoupling capacitor can be as less as 0.1 pF.

The delay of every cell is sensitive to supply voltage, variations in supply voltage directly impacts the voltage measurement. The power supply will have a distribution profile across the chip. This profile will get calibrated out provided the power supply does not change too much with time. To combat time varying supply voltage, delay cells are used with a good power supply rejection ratio or to use regulated power supply. Placing a transistor in cascade helps to mitigate the effect of power supply noise on delay.

The measurement of bias voltages is dependent on Veal for the calibration and interpolation. Hence, the generation of Veal have to be accurate and has to be shielded well so that noise coupled onto Veal will not impact the measurement. The noisy currents of the voltage-to-delay converter contribute to jitter on the clocks. If N delay cells are used in cascade to generate the delay difference, assuming the jitter added by each to be independent of one another, the jitter grows as

while the total delay grows as N. Hence, from a noise perspective, it is advantageous to employ more delay stages. But this leads to bandwidth limitation and increased kick-back to the analog test node.

In one embodiment for a given measurement time, the resolution of measurement of delay difference that can be obtained be 6σ (where σ is the standard deviation of the measured delay values). Then, the required voltage-to-delay ratio is calculated based on the desired voltage resolution. Based on the total delay required, one can choose the number of delay stages needed.

For example, suppose that a resolution of 10 ps can be achieved in a given measurement time and the voltage resolution desired is 1 mV. Then the voltage-to-delay converter has to provide a differential delay of 10 ps/mV. Suppose a single delay cell is designed to provide this delay and If 0.1 mV resolution is desired with the available system architecture and measurement time, then ten such delay cells can be used.

Fig. 3 shows the block diagram of the system implemented to evaluate the concept. The system comprises of voltage-to-delay circuitry, an on-chip sampling head and a DMU. The system is used to measure a single analog voltage, shown as the pin named 'Vm". It is used first for calibration (by feeding known voltages) and then to measure test voltages. There is a provision to select the output of either of a single or a series of 13 voltage-to-delay cells, giving a handle on the voltage-to-delay transfer.

In one embodiment of the system, a sub-sampling based delay measurement unit (DMU) is used. The V2D cells set up a delay between the clocks at nodes D¾ and Dbi, which has to be measured. Since the objective is to measure delay digitally, the clock pair is sampled by another clock. To perform sampling, a sampling clock with a frequency which is much larger (about 100^x) that of the clock pair can be used. But, practical measurements show that the standard deviation of the measured delay, and therefore of voltage is too high. The system here uses a sampling frequency which is slightly less or slightly more than that of the clock pair which is known as sub-sampling.

The sampling rate is about 2 times lesser than Nyquist frequency, which means that the full signal cannot be reconstructed back. But, if the parameter of interest can be made periodic with a known frequency, then this technique can still be used to reconstruct the parameter of interest. For example, an on-chip analog oscilloscope where a high frequency periodic analog signal is sub-sampled and the samples are digitized. The sampling clock has a frequency which is slightly less than that of the input signal to be displayed, so that the original signal becomes time expanded, thereby significantly reduces the required bandwidth of the ADC that follows.

As shown in Fig. 3, if the frequencies of sampling clock and core clock pair are rationally related that happens when one of them is derived from the other, then the resolution of measurement is lower bounded by a non-zero quantity, determined by the parameters T and ΔΤ. This means that, in spite of increasing the measurement time, the accuracy (standard deviation) of measurement does not improve beyond a certain value. In such cases, adding some additional jitter onto the clocks, by way of frequency modulation for instance, improves the resolution.

Further, when the frequencies of sampling and core clock pair are irrationally related, there is no such fundamental limit on resolution. But, it comes with the rider that this sampling clock has to be generated from a separate crystal. For this particular application, the tester can be made to feed this second clock signal. In this setup, the jitter of the clocks comes in as a hindrance and is mitigated by averaging. Fig. 4 illustrates of timing diagram and the concept of Sub-sampling. As shown, the input clock pair Da_z- and Db_z- (of period T) is sampled by an asynchronous sampling clock of period Τ+ΔΤ. As a result, the two outputs will be beat clocks with period given as

= (Τ+ΔΤ)^χΤ/ΔΤ. The period of ideal Qa and Qb is as shown in Fig. 4. Here, there is time amplification by a factor Τ/ΔΤ. Hence, the skew δ between these two clocks which has to be measured will also be amplified by the same amount Tsk = [(Τ+ΔΤ)^χδ/ΔΤ], shown as skew between ideal Q_a and ideal Q^. Due to jitter on the clocks and meta-stability issues of the samplers, the sampled outputs will be bouncy as shown in the waveforms for Qa and Qb. Hence, the skew has to be estimated by averaging the delay difference between the two rising edges of Qa and Qb across many instances. Since Qa and Qb are synchronous to sampling clock, their delay difference will always be some multiple of sampling clock period and hence a simple up/down counter suffices to estimate this difference. Further, the same counter can be used for averaging across multiple periods of Qa and Qb. Such an averaging yields an unbiased estimate of the skew as a fraction of the clock period T [20]. The falling edge related bounces is ignored and hence the clean clocks CQa and CQb are generated which are fed to the up/down counter as shown in Fig. 4.

In one embodiment of the present disclosure, the system uses needs two clocks i.e. a core clock and a sampling clock, of slightly different frequencies. Generation and routing of such close frequency clocks is obtained using a pair of signal generators independently. In a real-world BIST scenario, one of the clocks can be provided while the other can be generated on-chip. A sub-harmonic of the sampling clock does practically no change to this system of sub-sampling and hence eliminates the issue of injection-locking.

Fig. 5 shows the behavioral model of voltage quantization employing the DMU. Let T and Τ+ΔΤ be the time periods of core clock and sampling clock respectively. Then, the duration of the beat period is given by T^ = (Τ+ΔΤ)^χΤ/ΔΤ, which will consist of Τ/ΔΤ sampling clock periods. Hence, the resolution of the quantizer in measuring time, in principle, is ΔΤ/Τ. Therefore, the maximum number of bits of this quantizer, bmax and conversion time are given by: τ

bmax ^{= lo}¾

T_b = (Γ+Δ7)^χ77ΔΓ (5)

If dmax is the maximum delay given by the voltage-to-delay converter corresponding to the maximum voltage input, then the number of bits b available is given by:

where c is the maximum delay as a fraction of the time period T.

If the total measurement time is M beat periods, the variance reduces by a factor of M, and hence the SNR increases by about 3 log2(M) dB. Hence, doubling the measurement time improves the SNR by about 3 dB. The bandwidth of measurement is 1/27^. Hence, clearly there is a bandwidth-accuracy trade-off in the choice of parameters T and ΔΤ. The overall SNR of the complete system for a sinusoidal input of amplitude V · is given by:

where A=kV ·„, _„ with k being the voltage to delay gain i.e. assuming voltage to delay conversion being linear. Thereby, assumes that sample-and-hold circuitry is available which can hold the sampled values for a period of the measurement time (t_m), given by t_m=M- ( Γ+Δ 7) x 77Δ Γ (8)

In one embodiment, let f and f be the frequencies of the core and sampling clocks respectively. Then, the frequency of the beat signal is given by ffr⁼f_c ^~f_s- The above equations can now be re -written as:

W AT= (10)

In order to simplify the design in this case of distributed voltage measurement, the use of a sample-and-hold at the voltage nodes is avoided. Hence, this renders data conversion at Nyquist rate impossible, but the methodology of over-sample-and-average can be used. Basically, the sampling rate should be high enough so that the signal of interest does not change beyond an LSB within the conversion time. Assuming an input sinusoid

the maximum change in F- within an interval of l/f^ should not exceed a, i.e.,

2nAf i,n

(13)

fb

Let

for η γ effective bits of conversion. Then, OSR sets a limit on the number of effective bits (n^) that can be obtained, as given by

wi^≤lo¾ l ^~J⁺¹ (14)

A second limit on the number of effective bits (n^) available is set by the number of bits available at each conversion, which reduces with increased oversampling. Using (11),

1

n~_> < b+ ^\og₂ (OSR)

y fin OS^Rj

The actual number of bits (n) that one can obtain is given by η=νώΆ{η γ ,η₂) (16) Fig. 6 shows a plot indicating the existence of an optimal OSR along with the optimal OSR which reduces for a higher input bandwidth and also yields lesser number of effective bits.

In one embodiment, as an example, a set of 32 measurements are taken to compute the mean and standard deviation of the delay count for each V/n value. The error-bars obtained is as shown in Fig. 7 as plots, which represents a value of ±σ on each side of the mean. The accuracy of voltage measurement is defined as the range of voltage values corresponding to ±3σ. This is obtained by the dividing standard deviation of delay by the local slope at each point in Fig. 7.

Fig. 6 is the plot of OSR versus n, showing the existence of optimal OSR for a given f The other parameters of the equations are taken from the settings described in

Table 2. The dots indicate the results summarized in Table 2. The gap between the modeled and measured behavior is because the differential delay generated is a small fraction of the clock time period, and the resolution improves as the ratio of differential delay to time period increases. Table 1 shows a summary of measured results for DC input.

Table 1

SI. VDD fc & MT DR σηιαχ Bin-size

No. (V) (MHz) (MHz) (s) (ns) (ps) (mV)

1 0.75 8.0 7.6 4.42 6.77 32.1 1.50

2 1.2 10.0 9.8 3.42 1.53 10.1 2.05

3* 1.2 8.0 7.9 4.25 11.25 30.5 0.82

4 0.75 8.0 7.99 4.20 7.80 29.0 1.60

5 0.75 8.0 7.99 16.80 7.30 15.0 0.85

6† 1.0 37.0 36.927 0.056 2.97 9.77 2.10

7† 1.1 37.0 36.927 0.056 2.13 9.92 1.03

8† 1.2 37.0 36.927 0.88 1.20 3.87 1.25 wherein * is 13 V2D cells and† is measurement time strictly integer number of beat periods, fc - Input Clock Frequency, fc - Sampling Clock Frequency, MT - Measurement Time, DR - Dynamic Range of delay, σιηαχ - Maximum standard deviation of delay values, Bin-size - Accuracy of measurement

Fig. 8 shows plots of 'offset-canceled' differential delay versus differential voltage for the settings mentioned. Refer Table 1 for the settings of #1,2,3.

Table 2: Summary of Measured Results for Sine wave input

SI. f ^J i.n f_c f_s OSR SNR ENOB

No. (Hz) (MHz) (MHz) (dB) (bits)

1 30 37 36.999 16.67 9.61 1.30

2 30 37 36.9975 41.67 17.57 2.63

3* 30 37 36.995 41.67 17.37 2.59

4* 30 37 36.9925 62.50 19.54 2.95

5* 30 37 36.99 83.33 16.51 2.45

6* 30 37 36.98 166.67 9.01 1.20

7 10 37 36.999 50.0 17.76 2.63

8* 10 37 36.927 1825 33.61 5.29 wherein * is one measurement over two beat periods; f- - Frequency of input sine wave, f - Core clock Frequency, f - Sampling Clock Frequency, OSR - Over-sampling Ratio, SNR - Signal to Noise Ratio, ENOB - Effective Number Of Bits.

Table 1 and Fig. 7 presents a summary of measured results, which shows that delay increases with reducing supply and increasing number of V2D cells. The delay versus voltage plots of Fig. 8 are for the settings presented in the rows 1, 2 and 3 of Table 1. An accuracy of about 1 mV can be obtained by proper choice of parameters and measurement time. One can easily obtain desired accuracies by suitably altering the measurement time. Except entry 3, other entries of Table 1 correspond to the single V2D case. Entries 4 and 5 show that the accuracy improves with measurement time. For a four-fold increase in measurement time, the accuracy improves by a factor of two, which goes well with the theory. Entries 6 to 8 are taken for a measurement time strictly integer number of beat periods. The bin-size obtained in lesser duration is comparable to other entries acquired over a larger measurement time. The differences in the delay ranges for the similar settings are present because they were measured on different days and hence conditions like supply voltage and temperature could be different. However, the measurements taken with the same setting about couple of hours apart (after offset-cancellation) is stable enough.

In one embodiment, a sine wave of frequency 30 Hz is applied to the system directly without sample-and-hold circuitry. A set of 16,384 data points are collected for the SNR measurements. SNR measurements are determined without calibrating the data points. The summary of results obtained is shown in Table 2. It is observed that the SNR degrades for both low and high OSR in accordance with Fig. 6. Entries number 7 and 8 of the Table 2 confirms that the SNR is higher for a lower bandwidth signal with rest of the settings being similar. Fig. 8 shows the plot of DNL and INL for setting 8 of Table 2, obtained by code density test. The maximum values of DNL and INL are found to be less than 1 LSB.

The theoretical analysis shows that a resolution of 12 bits is possible in this approach, as shown in Fig. 6, but the measured results show a maximum of 5.29 bits. The limitation in the resolution is because the delay in this case is a small fraction of the time period of core clock. So, in order to get a better resolution, a core clock of higher frequency has to be used. But the poor rise time of the presently designed voltage-to-delay (V2D) converter limits the frequency of the clock that can be used.

Also, since the oversampling rate is closely related to the difference of the core and sampling clock frequencies, both these clock frequencies need to be accurately controlled. Entries 1 and 3 of Table 2 show that the SNR drops by about 8 dB for a change in the third decimal place of the sampling clock frequency. Hence, the use of this system necessitates precise control of the sampling clock frequency. This may be achieved by deriving this sampling clock from the core clock and mimicking asynchrony by artificially introducing frequency modulation. Also, a PLL may be used to precisely control the oversampling rate or beat frequency and accordingly adjust the sampling clock frequency. The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

With respect to the use of substantially any plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

In addition, where features or aspects of the disclosure are described in terms of Markush groups, those skilled in the art will recognize that the disclosure is also thereby described in terms of any individual member or subgroup of members of the Markush group.

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

We claim:

1. A system configured for built-in-self-test (BIST) at each node of an integrated circuit comprising:

one or more nodes in the integrated circuit, wherein a predefined test voltage of each node is measured using BIST;

one or more sampling head blocks to convert the predefined test voltage at a node into time delay, wherein one sampling head is connected to each node;

a control unit to control the operation of the sampling heads to perform the BIST corresponding to each node; and

a clock module comprising two clocks, called core and sampling clocks, of slightly different frequencies, where a predefined time delay is captured between the pair of core clock signals of predefined frequency, the pair of core clocks are sampled by sampling clock to digitize the time delay to produce sub-sampled signal pairs; and delay measurement unit (DMU) to receive sub-sampled signals from each sampling head block to calculate the time delay and thereby, the test voltage at each node by using interpolation on pre-computed calibration data.

2. The system as claimed in claim 1, wherein the integrated circuit comprises sampling head blocks equal to number of nodes.

3. The system as claimed in claim 1, wherein the clock module comprises of two clocks, one clock carries the predetermined delay information and the other clock performs sampling operation to produce a pair of sub-sampled signals.

4. The system as claimed in claim 1, wherein the predetermined information is time delay information.

5. The system as claimed in claim 1, wherein each sampling head block comprises: a pair of delay cells (V2D) which takes the test voltage of the corresponding node connected to the sampling head block as input, and correspondingly delays an input clock triggering said V2D; and

a pair of flip flops connected to the pair of delay cells, each flip flop has input from the corresponding delay cell, said delay flip flops are triggered using a sampling clock to generate pair of sub-sampled signals, the delay between which carries information about the test voltage.

6. The system as claimed in claim 1, wherein the control unit supplies reference voltage, calibration voltage to each sampling head and selects one of either calibration or measurement phase via a control bus.

7. The system as claimed in claim 1, wherein the control unit determines the test node to be measured by selecting the corresponding sub-sampled output pair to be fed to the DMU using a multiplexer.

8. A method to perform built-in self test (BIST) at each node of an integrated circuit comprising:

converting test voltage of a predefined node of the integrated circuit and a reference voltage corresponding to said predefined node into time delay between a pair of low-frequency signals by sub-sampling technique, wherein said sub-sampling technique is performed using sampling head;

calculating said time delay corresponding to the difference between test voltage and the reference voltage to obtain a code word; and

converting the code word into an analog value to obtain a differential voltage, said differential voltage being the difference between node voltage and reference voltage; repeating all above step for each node in the integrated circuit to perform BIST.