WO2014036078A3 - Dynamic central cache memory - Google Patents
Dynamic central cache memory Download PDFInfo
- Publication number
- WO2014036078A3 WO2014036078A3 PCT/US2013/056980 US2013056980W WO2014036078A3 WO 2014036078 A3 WO2014036078 A3 WO 2014036078A3 US 2013056980 W US2013056980 W US 2013056980W WO 2014036078 A3 WO2014036078 A3 WO 2014036078A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- module
- memory
- resources
- new
- cache
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7207—Details relating to flash memory management management of metadata or control data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
Abstract
The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of, e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/596,480 US9116820B2 (en) | 2012-08-28 | 2012-08-28 | Dynamic central cache memory |
US13/596,480 | 2012-08-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2014036078A2 WO2014036078A2 (en) | 2014-03-06 |
WO2014036078A3 true WO2014036078A3 (en) | 2014-05-01 |
Family
ID=50184615
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2013/056980 WO2014036078A2 (en) | 2012-08-28 | 2013-08-28 | Dynamic central cache memory |
Country Status (3)
Country | Link |
---|---|
US (1) | US9116820B2 (en) |
TW (1) | TW201432452A (en) |
WO (1) | WO2014036078A2 (en) |
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US8874824B2 (en) | 2009-06-04 | 2014-10-28 | Memory Technologies, LLC | Apparatus and method to share host system RAM with mass storage memory RAM |
US9417998B2 (en) | 2012-01-26 | 2016-08-16 | Memory Technologies Llc | Apparatus and method to provide cache move with non-volatile mass memory system |
US9311226B2 (en) | 2012-04-20 | 2016-04-12 | Memory Technologies Llc | Managing operational state data of a memory module using host memory in association with state change |
US9164804B2 (en) | 2012-06-20 | 2015-10-20 | Memory Technologies Llc | Virtual memory module |
US9575884B2 (en) * | 2013-05-13 | 2017-02-21 | Qualcomm Incorporated | System and method for high performance and low cost flash translation layer |
KR20180038109A (en) * | 2016-10-05 | 2018-04-16 | 삼성전자주식회사 | Electronic device including monitoring circuit and storage device included therein |
TW201818248A (en) | 2016-11-15 | 2018-05-16 | 慧榮科技股份有限公司 | Memory managing method for data storage device |
US10754783B2 (en) * | 2018-06-29 | 2020-08-25 | Intel Corporation | Techniques to manage cache resource allocations for a processor cache |
CN111007987A (en) * | 2019-11-08 | 2020-04-14 | 苏州浪潮智能科技有限公司 | Memory management method, system, terminal and storage medium for raid io |
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2012
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2013
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Also Published As
Publication number | Publication date |
---|---|
US9116820B2 (en) | 2015-08-25 |
TW201432452A (en) | 2014-08-16 |
US20140068140A1 (en) | 2014-03-06 |
WO2014036078A2 (en) | 2014-03-06 |
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