WO2014020582A2 - Procédé permettant de fournir une puissance ajustable à partir de blocs de batteries, unité de distribution de puissance discrète pour des véhicules électriques - Google Patents

Procédé permettant de fournir une puissance ajustable à partir de blocs de batteries, unité de distribution de puissance discrète pour des véhicules électriques Download PDF

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Publication number
WO2014020582A2
WO2014020582A2 PCT/IB2013/056366 IB2013056366W WO2014020582A2 WO 2014020582 A2 WO2014020582 A2 WO 2014020582A2 IB 2013056366 W IB2013056366 W IB 2013056366W WO 2014020582 A2 WO2014020582 A2 WO 2014020582A2
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Prior art keywords
dpdu
eesu
current path
sbus
voltage
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Application number
PCT/IB2013/056366
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English (en)
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WO2014020582A3 (fr
Inventor
Suren Martirosyan
Didier Guillonnet
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Suren Martirosyan
Didier Guillonnet
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Publication of WO2014020582A2 publication Critical patent/WO2014020582A2/fr
Publication of WO2014020582A3 publication Critical patent/WO2014020582A3/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0024—Parallel/serial switching of connection of batteries to charge or load circuit
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2310/00—The network for supplying or distributing electric power characterised by its spatial reach or by the load
    • H02J2310/40—The network being an on-board power network, i.e. within a vehicle
    • H02J2310/48—The network being an on-board power network, i.e. within a vehicle for electric vehicles [EV] or hybrid vehicles [HEV]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries

Definitions

  • the present patent application discloses a method for providing adjustable power from battery packs and relates to a Discrete Power Distribution Unit (DPDU) for (i) providing regulated electricity from a multicell battery pack to a load or (ii) for recharging from a power source or even (iii) for balancing the charge of individual cells of the said battery pack; the DPDU being able to individually control the cells usage and thus optimizing the energy usage and the service life of the battery pack.
  • DPDU Discrete Power Distribution Unit
  • the present patent application also relates to electric vehicles comprising such Discrete Power Distribution Unit.
  • the DPDU uses these Current Paths to maintain balance over cells with varying characteristics during charge discharge or quietness, redistribute the charge of cells, produce one or several discrete regulated output voltage during discharge and charge and adapt to varying loads or charge sources.
  • the classic approach is that the power supply includes a switching regulator with power MOS-FET or IGBT.
  • the switching frequency is usually higher than 12-15 kHz in order to create a minimal noise.
  • this approach does not provide any cell by-pass system to minimize the cell failure impact. For example a cell with 50% capacity in Bank 4 containing 8 cells would decrease by 50% the capacity of the whole Bank 4. In consequence this approach doesn't provide no active distribution optimization of the load or charge current.
  • a classic approach is to balance individual cell usage in using a shunting current around the highest voltage cells, typically using a power transistor and a current-limiting resistor.
  • This cell balancing can be performed not only during charge, but continuously: during discharge, quiescence, and storage.
  • the aim of the present patent application is to provide a solution to improve the characteristics of such power distribution unit.
  • one stage discrete power regulation system which has the drawback of not being as precise as a double stage regulation system, turns out to be an acceptable solution for providing an adjustable output voltage from a high voltage battery pack.
  • the system includes a plurality of electric circuits allowing to individually connect or disconnect the cells from the serial chain, so that the subset of cells included in the serial chain can be any subset.
  • circuitry and switching means object of the present invention, is not limited to a substring of adjacent cells such as it is in Eaves's approach which therefore suffers "overlapping" issues.
  • Eaves or Thomasson we do not suffer these "overlapping” issues; indeed we can by-pass individually a failing or weak cell, Eaves or Thomasson cannot.
  • the said one stage DPDU object of the present invention is applicable for battery packs comprising a unique serial chain of battery units of any capacity, each battery unit comprising a unique cell or a set of cells or even an electric circuit combining different electricity storage means or generators such as battery cells, fuel cells, supercapacitors, etc.
  • the first object of the invention is a Discrete Power Distribution Unit for establishing with an external system a bi-directional transfer of energy to or from any serially connected subset of the units of a battery pack wherein said DPDU includes
  • each SBU comprising at least (i) an Electrical Energy Storage Unit (EESU), and, (ii) individually controlled Unit Switching Means (USM) allowing at least a state "Inserted” in which the EESU is inserted in the current path of the SBUS and another state "Not-Inserted” in which the current path of the SBUS doesn't include the EESU; so that any subset of EESU - from a null subset to a set including all the EESU of the said battery pack - can be included or not in the SBUS's current path; by extension we will say thereafter that a SBU is in Inserted state (resp. Not-Inserted state) when its EESU is inserted (resp. not- inserted) in the SBUS current path;
  • EESU Electrical Energy Storage Unit
  • USM individually controlled Unit Switching Means
  • a Central Processing Unit permanently selecting the most suitable subset of EESUs to be Inserted and actuating accordingly said individually controlled USMs in order (i) to regulate a target output voltage or target current to an external load, or, (ii) to regulate the receipt of electricity from an external power source while at the same time optimizing the distribution of the load or receipt of energy over the EESUs;
  • sensing means for measuring the electrical current flow into the SBUS and supplying the measurement to said CPU
  • sensing means for measuring the voltage across the poles of each individual EESU, and supplying the measurement to said CPU;
  • sensing means for measuring the voltage across the output terminals of said DPDU and supplying the measurement to said CPU
  • the SBUS can include from zero to all the available EESU and can provide a set of discrete voltages from zero to a maximum voltage obtained when all the EESU are inserted in the current path of the SBUS.
  • the said CPU regulates the output to a target voltage, target current or target power by permanently rotating the subset of EESUs inserted in the SBUS's current path whereby
  • the said EESUs are rechargeable battery cells and the SBUS can be connected to a power source, whereby the said EESUs can be recharged.
  • the said CPU regulates a target input current or terminals voltage by permanently redefining the subset of EESUs inserted in the SBUS's current path whereby
  • the number of SBUs is optimized according to the nominal output operating voltage of the DPDU and the nominal EESU's voltage discharge curve, said number of SBUs being at least the result of the division of the DPDU's nominal output operating voltage by the cut-off voltage of EESUs whereby preserving the DPDU's nominal output operating voltage till the full discharge of the pack, ie till the EESUs reach their cut-off voltage, and whereby optimizing the operating time of the pack and the total energy retrieved.
  • the said EESU are capacitors, such as electric double-layer capacitors whereby allowing a fast energy storage or retrieval and a high energy density.
  • each USM individually comprises additional means allowing at any moment the corresponding EESU to be inserted in one or several Current Paths, or not included in any Current Path at all whereby simultaneously allowing the SBUS to provide several independent Current Paths, each one with its own pair of voltage output terminals.
  • the said DPDU additionally comprises for each Current Path a Principal Switch, actuated by the said CPU, the said Principal Switch being able to interrupt the current in the Current Path the time the USMs are actuated to redefine new subsets of Inserted EESUs whereby the USMs are positioned while no current is passing through, thus extending the USMs' service life.
  • the said USMs are low resistivity electric switches, such are relays whereby the electric current flows in the Current Path with a minimal loss of energy, eventually leading to enhanced overall characteristics of the DPDU.
  • the USMs are low consumption type, such as bi-stable relays, whereby maintaining the state of
  • the time between two subset selections by the CPU is between 0.1 second and 10 minutes whereby
  • the switching duration is minimal in comparison with operating duration while current is flowing, and
  • the said CPU includes means for determining for each EESU the energy to be delivered or received considering parameters of the EESUs in the list of cycling number, internal resistivity, state of charge, state of aging, temperature, nominal capacity and historical data on the same, whereby optimizing individual EESU discharging or charging and enhancing overall battery pack characteristics.
  • the DPDU comprises additional switches in order reconfigure the Current Paths into n aliquots connected in parallel whereby the DPDU can be configured to deliver or accept a voltage n times lower with a current n times higher.
  • This additional switching system to manage aliquots can be comparable to the one described in US Pat. 7,516, 726 (Esaka et al.
  • the method of using such DPDU object of the present invention for providing an adjustable power from battery packs is especially suitable for Electric Vehicles.
  • the present patent application relates to Electric Vehicles comprising at least one DPDU of the present patent application.
  • a one stage DPDU is provided allowing to
  • the present patent application offers voltage or current regulation with individual optimization of battery units' usage while avoiding the loss of energy inherent to a second stage DC/DC or DC/AC regulation.
  • the DPDUs object of this patent application are particularly suitable for high power battery adjustable power supply when large cells such as lead-acid, zinc-air, lithium-air, fuel cells or other power sources can be used, especially for stationery applications or electric vehicles such as e-cars, e-autobuses, e-trucks, e-bicycles, etc.
  • FIG. 1 a is a schematic circuit diagram of a Switchable Battery Unit comprising battery cells connected in parallel.
  • FIG.1 b is a schematic circuit diagram of a Switchable Battery Unit comprising battery cells connected in serial.
  • FIG. 2 is a schematic circuit diagram of a DPDU.
  • FIG. 3a is a time chart showing a selecting sequence of SBUs and Principal Switch
  • FIG. 3b is a time chart showing the details of a selecting sequence of SBU
  • FIG. 4a is a schematic circuit diagram of a Switchable Battery Unit suitable for a DPDU with 2 Current Paths in the state of EESU Inserted in Current Path A, Not-Inserted in Current Path B;
  • FIG. 4b is a schematic circuit diagram of a Switchable Battery Unit suitable for a DPDU with 2 Current Paths in the state of EESU Not- Inserted in Current Path A, Inserted in Current Path B;
  • FIG. 4c is a schematic circuit diagram of a Switchable Battery Unit suitable for a DPDU with 2 Current Paths in the state of EESU Not- Inserted in Current Path A, Not-Inserted in Current Path B;
  • FIG. 4d is a schematic circuit diagram of a Switchable Battery Unit suitable for a DPDU with 2 Current Paths in the state of EESU Inserted in Current Path A, Inserted in Current Path B;
  • FIG. 5 is a schematic circuit diagram of a DPDU with 2 Current Paths.
  • FIG. 6 is a schematic circuit diagram of the Principal Switch including an additional relay in parallel to the IGBT.
  • FIG. 7 is a schematic circuit diagram of an EESU comprising an intermediary supercapacitor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments will be described in detail on the basis of examples and with reference to the drawings. In the drawings the same or corresponding parts are designated by the same reference numerals.
  • a DPDU of 210V 9.6kWh nominal capacity, able to discharge at C/3 in average with 10kW peaks is prepared.
  • the DPDU includes SBUs (10) such as illustrated by FIG. 1a in which:
  • the EESU (1 1 ) is composed of 3 rechargeable battery cells of 3.2V 10Ah (used with a 2.4V cut-off voltage, 3.6V charging voltage) such as LiFeP04 O'CELL OLS8081230FP, each connected in parallel giving globally 3.2V 96Wh nominal characteristics,
  • the Unit Switching Means (12) comprises 2 magnetic latching SPST relays such as type 80A HW80 from HWE (Yueqing Hengwei Electronics Co., Ltd. ) with its signal command input (13), preferably it would be substituted by a single SPDT relay with similar characteristics (2mOhm contacts resistance with at least 50A max current) as symbolized on FIG. 1 ;
  • FIG. 2 is a schematic circuit diagram that illustrates the DPDU of Example 1.
  • SBUs (21 .1 ) ... (21 .100) are connected in serial, the pole T+ of SBU, connected to the pole T- of SBU i+ i , and form the SBUs String (22) of a total of 9.6kWh nominal capacity with termination poles S+ and S-.
  • the Voltage Sensor Controller (23) is a system assessing the voltage of each EESU such as the one described in Hitachi - Kinoshita - US6157165 (1999). It is accessing independently all the EESUs from their lines (14) whenever the EESU is in inserted or not- inserted state.
  • a Current Sensor (24) such as a 2mOhm shunt is measuring the current flowing through the SBUS, on a range from -100A to +100A.
  • the Voltage Sensor Controller (23) transmits to the CPU the voltage at the terminals of the SBUS, between S+ and S-, on a range from 0 to 400V, and the current in the SBUS from Current Sensor (24).
  • the Principal Switch (26) is a 600V 100A IGBT such as PDMB100A6 from NIEC [Nihon Inter Electronics Corporation, Japan] or QIC0610001 from Powerex, for which, in both cases, the Collector-Emitter voltage drop is below 2.0V for a 50A current.
  • the CPU (28) of this example is a small linux computer with all necessary input-output lines, such as a FriendlyARM Mini6410.
  • This CPU is receiving current & voltage information from sensors (14) (24) and (S+,S- lines) with the help of an A/D adaptation & conversion unit included in the Voltage Sensor Controller (23).
  • the CPU (i) scans in permanence the actual parameters of the EESUs, (ii) keeps a history of their usage and their evolution of characteristics, and (iii) considers the input parameters defining for our example the required voltage Vout. Another input parameter of the CPU could also be the required supplied or received Current or Power. From all this information the CPU decides what SBUs to insert in the Current Path and drives accordingly the USMs and Principal Switch through an interface (29).
  • a modification of the selection set is performed in less than 0.1 sec if Vout is no longer corresponding to the input parameters. If Vout is above the required voltage some SBUs are removed from the selection set, if Vout is below the required voltage some SBUs are added to the selection set, this comparison is done with some tolerance, in this example +-1.6V which represents half a EESU nominal voltage and less than 1 % of nominal output voltage.
  • a PID controller regulation algorithm helps to smoothen and average Vout to the required value. This CPU system and algorithm present no difficulty for the one skilled in the art.
  • the USMs are activated only twice: one time to Inserted state, the second time to Not-Inserted state. This leads to very small activation power requirements and increases the lifetime of the USMs.
  • the minimal source voltage can be as low as the charging voltage of a single EESU.
  • the level of breaking is regulated by the CPU by removing or adding EESUs into the current path.
  • FIG. 3a is a time chart showing the signals sent from the CPU (28) through the SBUS interface (29) to the SBUs in order to Insert or Not-lnsert their EESU in the current path.
  • FIG. 3a depicts the situation when 5 SBUs are with EESU Inserted at the same time and the selection of Inserted EESUs is rotating:
  • SBUs 1 -2-4-99-100 are in Inserted state demonstrating the case that the CPU can decide not to Insert EESU of SBU 21.3 in the current path, for example if it is out of order or below cut-off voltage.
  • SBUs 1 -2-4-5-99-100 are in Inserted state demonstrating the case that the CPU can decide to increase the number of EESUs Inserted in the current path, for example to adjust to an increase of the input parameter specifying the required voltage Vout.
  • FIG. 3b is a time chart showing the synchronization of the Principal Switch (26) with the command signal to change the state of the SBUs. From t01 to W2 the Principal Switch (26) is opened so that no current flows in the SBUS Current Path, then from t1 1 to t12 the CPU through the Interface (29) is setting the USMs (12) state as needed, then from t21 to t22 the Principal Switch (26) is close to reestablish the SBUS Current Path. In this way the USMs are opened or closed only while no current is flowing through them and their lifetime is prolonged significantly.
  • t01 -t02 duration is 1 ms
  • t02-t1 1 is 1 ms
  • t1 1 -t12 is 2x30ms for the 2 SPST relays (t1 1 -t12 would be 30ms in case of a unique SPDT relay)
  • t12-t21 and t21 -22 are ms.
  • the total duration (td) for selecting a set of SBUs to be inserted is less than 65ms (35ms in case of SPDT).
  • Table 1 is giving some characteristics of the DPDU of Example 1 , especially it shows the losses and the global efficiency of the DPDU during different discharge regimes and in average, the load being a 10kW 210V dc brush motor for electric car. TABLE 1
  • the DPDU switching circuitry is using 69W at average output power which is less than 3% of the DPDU output power.
  • This second example is a DPDU comprising SBUs of another embodiment, allowing 2 current paths, these SBUs being illustrated by the schematic circuit diagrams of FIGs 4a, 4b, 4c and 4d.
  • the SBU (40) comprises a EESU (42) of the same type as in Example 1 , but the Unit Switching Means comprises 2 SPDT latching relays (41 A) (41 B) connected to the Termination Poles A+, A-, B+, B-.
  • the command line (43) plays a similar role as the signal command input (13) to the SBU of Example 1 and allows the CPU to activate independently the 2 relays (41 A) and (41 B) through the Interface (29).
  • Paths B+B- and A+A- are both a bypass circuit.
  • FIG. 5 is a schematic circuit diagram of the DPDU of Example 2.
  • This second example allows retrieving energy from the SBUS with a first selection of EESUs inserted in Current Path A, with poles (51 a) and (51 b) connected to a motor-generator (not represented) while at the same moment:
  • This second example allows also retrieving electricity from a set of EESUs through Current Path A to charge another distinct set of EESUs through Current Path B while switches (54a) and (54b) are closed whereby performing an equalizing of charges among the EESUs.
  • This second example is especially suitable for an Electric Car, such as one comprising a 10kW DC brush motor (that can also be used as generator during regenerative braking) and a second 100Wh 350V Supercapacitors DPDU.
  • this second example allows the Voltage Sensor Controller to access the voltage of any EESU through Current Path B while Current Path A is in use, whenever the EESU is in use or not (in this case its open voltage).
  • the CPU will place all SBUs but the one it want to measure voltage in a B-B+ bypass position (i.e. in the cases of FIG. 4a or FIG. 4c) so that the voltage to be measured will be present at the end of the SBUS between points (55a) and (55b) that are connected to the Voltage Sensor Controller (23).
  • a DPDU was obtained as in Example 1 except that, as illustrated by FIG. 6, the Principal Switch (26) comprises in addition to the IGBT a 100A SPST latch relay (61 ) connected in parallel to the IGBT (62) so that the CPU can close this relay when the IGBT is passing in order to diminish the global internal resistance of the Principal Switch.
  • the Principal Switch (26) comprises in addition to the IGBT a 100A SPST latch relay (61 ) connected in parallel to the IGBT (62) so that the CPU can close this relay when the IGBT is passing in order to diminish the global internal resistance of the Principal Switch.
  • Table 2 is showing a comparison of power losses incumbent to the Principal Switch in case it is comprising an IGBT only (case of Example 1 ) or it is comprising IGBT and latch relay (case of this Example 3). Considering that the CPU activates the additional relay 90% of the time the IGBT is conducting, the use of this additional relay (61 ) is reducing the average loss from 25W to 5W.
  • each EESU (71 ) comprises in addition a supercapacitor (72), made of 2 supercapacitors KAMCAP 400F 2.7V model HP-2R7- J407UY LR connected in serial, connected in parallel to the LJFEP04 cells (73).
  • This configuration is globally reducing the energy losses in EESUs due to internal resistance of the battery cells.
  • each SBU (10b) comprises EESU (1 1 b) including 3 NiMH cells, battery F 13000mAh from [Guangzhou Great Power Energy & Technology Co., China] (1.0V cut-off voltage), connected in serial.
  • This serial configuration of the battery cells is preferred for EESUs than a parallel configuration because cell failures are predominantly internal short circuits, and in this case the EESU is still able to operate with the remaining other cells.
  • the DDPU can very well detect internal short-circuit of cells and continue using the remaining capacity of concerned EESUs.
  • the DPDU of this example presents 4.7kWh 270V nominal characteristics.

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  • Power Engineering (AREA)
  • Secondary Cells (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

La présente invention se rapporte à une unité de distribution de puissance discrète (DPDU pour Discrete Power Distribution Unit) destinée à établir avec un système externe un transfert d'énergie bidirectionnel vers un sous-ensemble d'unités d'un bloc de batteries qui est raccordé en série, ou à partir de ce dernier, ladite unité DPDU comprenant au moins une pluralité d'unités de batterie commutables (SBU pour Switchable Battery Unit) raccordées en série, formant une série d'unités de batterie commutables (SBUS pour Switchable Battery Units String) permettant un trajet de courant avec une paire de bornes de sortie de tension, chaque unité SBU comprenant au moins une unité de stockage d'énergie électrique (EESU pour Electrical Energy Storage Unit) et des moyens de commutation d'unité (USM pour Unit Switching Means) commandés individuellement qui permettent un état « inséré » dans lequel l'unité EESU est insérée dans le trajet de courant de la série SBUS, et un autre état « non inséré » dans lequel le trajet de courant de la série SBUS ne comprend pas l'unité EESU; et une unité centrale de traitement qui sélectionne en permanence le sous-ensemble d'unités EESU le plus approprié qui doit être inséré et active, par conséquent, ledit moyen USM commandé individuellement.
PCT/IB2013/056366 2012-08-03 2013-08-03 Procédé permettant de fournir une puissance ajustable à partir de blocs de batteries, unité de distribution de puissance discrète pour des véhicules électriques WO2014020582A2 (fr)

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WO2016005108A1 (fr) * 2014-07-07 2016-01-14 Robert Bosch Gmbh Procédé de régulation d'une tension de sortie d'un système de batterie et système de batterie conçu pour mettre en œuvre le procédé
WO2017114802A1 (fr) * 2015-12-29 2017-07-06 Vito Nv Dispositif et procédé de reconfiguration d'un dispositif de stockage d'énergie rechargeable en chaînes de connexion de batteries séparées
DE102017112387A1 (de) * 2017-06-06 2018-12-06 Dr. Ing. H.C. F. Porsche Aktiengesellschaft Batterie, Verwendung derer und Kraftfahrzeug
CN110597127A (zh) * 2019-09-20 2019-12-20 深圳市易马智行科技有限公司 一种带有激活功能的电动车控制系统
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