WO2014014652A1 - Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods - Google Patents
Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods Download PDFInfo
- Publication number
- WO2014014652A1 WO2014014652A1 PCT/US2013/049021 US2013049021W WO2014014652A1 WO 2014014652 A1 WO2014014652 A1 WO 2014014652A1 US 2013049021 W US2013049021 W US 2013049021W WO 2014014652 A1 WO2014014652 A1 WO 2014014652A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- photodefinable
- thickness
- photodefinable material
- over
- radiant energy
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/1191—Forming a passivation layer after forming the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/36—Material effects
- H01L2924/365—Metallurgical effects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/36—Material effects
- H01L2924/365—Metallurgical effects
- H01L2924/3651—Formation of intermetallics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/381—Pitch distance
Definitions
- Embodiments of the present disclosure relate to pillar on pad interconnect structures for semiconductor dice, semiconductor dice and die assemblies including such interconnect structures, and to related methods.
- One long-favored configuration is an assembly of vertically stacked semiconductor dice, at least some of which are interconnected electrically and the stacked die assembly being mechanically and electrically connected to higher level packaging, such as an interposer or other substrate bearing conductive traces.
- MPGA Micropillar Grid Array Package
- Such a package comprises a stack of a plurality (for example four (4)) of dynamic random access (DRAM) semiconductor memory dice vertically interconnected from an uppermost die to a lowermost die, and a plurality of electrically conductive pillars extending from the underside of the lowermost memory die for connection to a logic die or a System on a Chip (SoC) die.
- DRAM dynamic random access
- SoC System on a Chip
- the provider of the logic die or the SoC die conventionally mounts their device to an interposer, such as a ball grid array (BGA) substrate, the logic or SoC die including conductive through vias for connection to the conductive pillars on the underside of the MPGA.
- BGA ball grid array
- the MPGA is mounted to the logic die or SoC die on the interposer and the assembly is then overmolded with an encapsulant into a finished Ball Grid Array (BGA) package.
- BGA Ball Grid Array
- the aforementioned configuration implemented as a so-called “Wide I/O" memory device, enables fast memory access, and reduces power requirements.
- MPGA One particularly promising configuration of an MPGA is a die assembly, which incorporates a high-speed logic die below a vertical stack of DRAM dice interconnected with through-silicon vias (TSVs).
- the DRAM dice are configured specifically to only handle data, while the logic die provides all DRAM control within the die assembly.
- the design is expected to reduce latency, and greatly improve bandwidth and speed, while offering significantly reduced power demand and physical space requirements and providing flexibility for multiple platforms and application through use of different logic dice.
- MCDRAM Memory Cube DRAM
- HMC Hybrid Memory Cube
- End products of the above designs will find a wide variety of applications including, among others, in mobile electronic devices such as so-called “smart phones,” laptop and notebook computers, supercomputers, BLACKBERRY® devices, iPHONE® and iPAD® devices, and DROID® devices.
- mobile electronic devices such as so-called “smart phones,” laptop and notebook computers, supercomputers, BLACKBERRY® devices, iPHONE® and iPAD® devices, and DROID® devices.
- One significant concern with regard to implementation of the above-referenced designs is providing good adhesion, sufficient to withstand reliability stress testing, between bond pads of a semiconductor die and small diameter pillars at tight pitches employed to provide reliable electrical connections to another semiconductor die, interposer or other substrate above or below the semiconductor die in a stack.
- a conventional pillar on pad interconnect structure 100 for a semiconductor die 102 comprises an electrically conductive elementl04 in the form of a pillar including a copper material 106 of about 30 ⁇ diameter, a nickel material 108 thereover, and a solder material 1 10, such as a SnAg solder, over nickel material 108.
- Bond pad 112 on active surface 114 of semiconductor die 102 is surrounded by passivation material 1 16, for example of at least one of SiN x and SiO x .
- a polymer repassivation material 1 18 is located over passivation material 1 16, extending over bond pad 112 and leaving about a 9 ⁇ diameter opening for contact of bond pad 1 12 with 30 ⁇ diameter copper material 106.
- thermocompression bonding employed to reflow solder material 110 to attach and electrically connect semiconductor die 102 to another component.
- FIG. 1 is a schematic side sectional elevation of a portion of a semiconductor die having a conventional interconnect structure thereon;
- FIG. 2 is a section of a 25,000X photomicrograph of a failed interconnect structure of the type of FIG. 1 after reliability stress testing of a semiconductor die;
- FIGS. 3A through 3C are schematic side sectional elevations of a portion of a method for fabricating an interconnect structure according to embodiments of the disclosure; and FIGS. 4 A through 4C are schematic side sectional elevations of a remaining portion of a method for fabricating an interconnect structure according to some embodiments of the disclosure;
- FIGS. 5 A and 5B are schematic side sectional elevations of a remaining portion of a method for fabricating an interconnect structure according to other embodiments of the disclosure.
- FIGS. 6 A through 6C are sectional photomicrographs of portions of a semiconductor die having interconnect structures formed thereon according to an embodiment of the disclosure
- FIG. 6D is a perspective photomicrograph of a semiconductor die having interconnect structures formed thereon according to an embodiment of the disclosure.
- FIG. 7 is a schematic side sectional elevation of a die assembly employing interconnect structures according to embodiments of the disclosure.
- interconnect structures means and includes bond pads and conductive elements formed thereon for electrical connection to other components, and associated materials and structures.
- wafer means and includes a volume of a semiconductor material in the form of a bulk semiconductor substrate, and is not limited to conventional, substantially circular wafers.
- wafer means and includes a volume of a semiconductor material in the form of a bulk semiconductor substrate, and is not limited to conventional, substantially circular wafers.
- semiconductor material means and includes silicon, germanium, gallium arsenide, indium phosphide, and other III-V or II-VI type semiconductor materials.
- semiconductor substrate means and includes a segment or segments of semiconductor material bearing integrated circuitry and singulated from a bulk semiconductor substrate.
- memory die and plural forms thereof means and includes all forms of integrated circuit memory, including, by way of non-limiting example including DRAM, SRAM, Flash memory, and other memory forms.
- major surface means and includes one of an active surface and a back side of a wafer, a semiconductor substrate or a semiconductor die.
- photodefinable material means and includes materials formulated to alter one or more material characteristics responsive to exposure to radiant energy. Such material characteristics include, but are not limited to, material chemistry and structural characteristics, and specifically include relative solubility or lack thereof in a selected solvent. Examples of photodefinable materials include commercially available positive tone and negative tone photoresists, as well as materials in solution or suspension in carrier fluids as used to provide the
- solvents include developers employed in conjunction with photoresists after exposure to radiant energy.
- the terms "about” and “substantially,” as used in connection with a given parameter each mean and include variances from the designated value referenced for that particular parameter within normal manufacturing tolerances, material variations, accuracy of measuring instrumentation, consistency of controls, etc., as the case may be and as recognized by those of ordinary skill in the art.
- a method of forming at least one interconnect structure comprises applying a photodefmable material to a first thickness on the surface of a semiconductor substrate surrounding a periphery of at least one conductive element protruding from the surface of the semiconductor substrate and to a second, lesser thickness over at least a top surface of the at least one conductive element, exposing the at least a top surface of the at least one conductive element to a dose of radiant energy sufficient to penetrate the second thickness of photodefmable material, and removing the second thickness of photodefmable material.
- a method of forming interconnect structures on an active surface of a semiconductor substrate comprises forming pillars comprising copper and a solder material on bond pads in contact with the bond pads over a full diameter of the pillars, spin coating a photodefmable material to a thickness over the active surface and to another, lesser thickness over the solder material of the pillars, and exposing the photodefmable material over the solder material to a dose of radiant energy substantially sufficient to penetrate the another thickness thereof.
- a method of forming at least one interconnect structure comprises applying a photodefmable material to the surface of a
- semiconductor substrate surrounding a periphery of at least one conductive element protruding from the surface of the semiconductor substrate and over the at least one conductive element, exposing the surface of the semiconductor substrate to a dose of radiant energy sufficient to penetrate the photodefmable material while masking the photodefmable material over at top surface of the at least one conductive element, and removing the photodefmable material over the top surface of the at least one conductive element.
- FIGS. 3 A through 5B of the drawings embodiments of a method for fabricating an interconnect structure for a semiconductor die, and the resulting structure, is described.
- a semiconductor die 102 comprises a bond pad 112 on active surface 114 surrounded by passivation material 116.
- Bond pad 112 may comprise a copper material and passivation material 116 may comprise, for example, at least one of SiN x ,SiO x and SiO x N y .
- passivation material 116 may comprise Si0 2 and Si 3 N 4 , applied by a chemical vapor deposition (CVD) technique.
- CVD chemical vapor deposition
- passivation material 116 may extend over a lateral periphery 1 13 of bond pad 112 a short distance, for example about 5 ⁇ , leaving a substantial majority of the bond pad 112 exposed for formation of an electrically conductive element 104 (see FIG. 3B).
- electrically conductive element 104 may be formed by sequentially depositing copper material 106, optionally nickel material 108, and solder material 110 (e.g., SnAg) or other electroplatable material (e.g., Sn, SnCu) directly on bond pad 1 12, with a full conductive element lateral extent (e.g., diameter) of about 5 ⁇ to about 70 ⁇ , for example about 30 ⁇ , of copper material 106 in contact with the material of bond pad 112.
- solder material 110 e.g., SnAg
- other electroplatable material e.g., Sn, SnCu
- an annular area of 111 of bond pad 112 remains exposed between conductive element 104 and an inner boundary 115 of passivation
- Electroplated copper material 106 may, for example, comprise a height of between about 5 ⁇ and about 15 ⁇ .
- Electroplated nickel material 108 may, in some embodiments, be employed as a barrier layer to prevent formational of intermetallic compounds between copper material 106 and the tin of solder material 110.
- Nickel material 108 may comprise a thickness, for example, of about 3 ⁇ .
- Electroplated solder material 110 may comprise a thickness, for example, of about 15 ⁇ . As is clear from a review of FIGS. 6A through 6D, all material thicknesses for conductive element are approximate as the electroplated copper material 106, nickel material 108 and solder material 110 may, in practice, exhibit nonlinear (e.g., arcuate) boundaries between adjacent materials. After the electroplating processes are completed, photoresist 122 and the seed layer are then removed from active surface 114.
- a photodefmable material 218 exhibiting dielectric (i.e., electrically insulative) properties and comprising, by way of non-limiting example, a positive tone photodefmable material, such as a photoresist is nonselectively applied over active surfaces 114, including any exposed area 11 1 of bond pad 112, to a first thickness of about 5 ⁇ , also covering conductive element 104 to a second, lesser thickness t 2 of, for example, about 1 ⁇ or less.
- Spin coating may be used to apply photodefmable material 218 over active surface, as the combination of centrifugal and gravitational forces may be used to reduce the thickness photodefmable material 218 over conductive element 104.
- a relatively viscous photodefmable material 218 enables thinning over conductive element 104 while ensuring a sufficient thickness of photodefmable material 218 over active surface 114.
- the photodefmable material 218 may also be applied as a dry film using vacuum lamination, which technique also facilitates thinning of photodefmable material 218 over conductive element 104.
- Suitable dielectric materials for use in photodefmable materials include, for example, polyimides, epoxies, polybenzoxazole, and bezocyclobutene. Specific products, which may be employed in an embodiment include, for example, WPR-5070 offered by JSR Micro, Inc.
- the photodefinable material 218 is exposed to a selected dose of broadband radiant energy RS D (for example) a mercury arc light source.
- the selected dose magnitude may be referred to as a "sub dose,” and comprise a power magnitude of, for example, about twenty-five percent to about fifty percent of E 0 , a radiant energy dose required to substantially completely remove a thickness of photodefinable material 218 from over active surface 114 by rendering it soluble in a developer.
- the broadband radiant energy may comprise G-H-I ultraviolet broadband exposure at wavelength peaks of 436, 405 and 365 nm, respectively.
- an energy source such as the abovementioned mercury arc light source, may be used to produce a full dose of radiant energy R F D with a partially optically transmissive photomask 130, termed a "leaky chrome" mask in the art, employed with a stepper to expose photodefinable material 218 on a group of semiconductor dice 102 to a reduced dose of radiant energy R S D- Chrome is conventionally employed as a mask material to block transmission of light, and a leaky chrome mask comprises a checkerboard pattern of chrome or other mask material and open areas at extremely small resolution, for example, less than 1 ⁇ , such as 0.5 ⁇ or even 0.25 ⁇ resolution.
- the coverage of semiconductor die 102 with a partially optically transmissive photomask 130 can be used to reduce the full dose of radiant energy RFD to a suitable sub dose RSD by limiting radiant energy transmission using characteristic of the photomask to effect the desired energy reduction.
- a selected sub dose of broadband radiant energy R S D less than Eoresults in penetration of only part of the thickness ti of photodefinable material 218, rendering only the penetrated portion soluble in and therefore removable by, a developer.
- FIG. 4C after exposure to the sub dose of radiant energy, positive photodefinable material 218 is developed.
- the photodefinable material 218 over and adjacent conductive element 104 is exposed through an aperture 134 in an opaque mask 132 to a sub dose of broadband radiant energy R S D from (for example) a mercury arc light source sufficient to remove a thickness t 2 of photodefinable material 218 from the top of conductive element 104.
- the selected sub dose of radiant energy RSD results in penetration and exposure of only part of the thickness t ⁇ of photodefinable material 218.
- a full dose of radiant energy RFD may also be employed if a dimension and alignment of aperture 134 with conductive element sufficiently blocks exposure of surrounding photodefinable material 218.
- a full dose of radiant energy RFD may be employed with an opaque mask 132 having a partially optically transmissive portion aligned over conductive element 104, or a partially optically transmissive mask 130 (FIG. 4B) with an aperture 134 aligned over conductive element may be employed.
- Radiant energy power employed, as well as the mask maybe selected to remove photodefinable material 218 from over conductive element 104 while providing desired remaining thickness of photodefinable material 218 surrounding and in contact with conductive element 104.
- photodefinable material 218 is developed.
- the thickness t 2 of photodefinable material 218 over and about the side of conductive element 104, having been substantially completely exposed, is then removed.
- the full thickness ti of polymide material 218 over active surface 114 and surrounding conductive element 104 has not been exposed except immediately adjacent conductive element 104.
- photodefinable material 218 is developed, an unexposed thickness t 3 remains, surrounding and in contact with conductive element 104, while the full thickness t ⁇ of masked photodefinable material 218 resides over a remainder of active surface 114.
- one embodiment comprises an interconnect structure for a semiconductor substrate, comprising a bond pad, a conductive element comprising a pillar on and in direct contact with the bond pad over a full diameter of the pillar, a solder material on an end of the pillar opposite the bond pad, and a photodefinable material over a portion of the bond pad around and in contact with the pillar.
- FIG. 6A depicts several conductive elements 104 processed according to the embodiment of FIGS. 4A and 4B on a semiconductor die 102 residing on bond pads 112 in communication with TSVs 120 and with passivation material 116 between bond pads 112 and photodefinable material 218 surrounding and adjacent conductive elements 104.
- FIG. 6B is an enlargement of FIG. 6 A and depicts portions of two adjacent conductive elements 104
- FIG. 6C is an enlarged view of a single conductive element 104 showing copper material 106, nickel material 108 and solder material 110 surrounded by photodefinable material 218 surrounding conductive element 104 to a height above a boundary of nickel material 108 with solder material 110.
- FIG. 6D is a perspective view of a row of conductive elements 104 surrounded by photodefinable material 218.
- a semiconductor substrate comprises
- semiconductor material comprising integrated circuitry and having bond pads on an active surface thereof, conductive elements comprising metal pillars on and in direct contact with the bond pads over a full diameter of the pillars, a solder material on each metal pillar, and a photodefinable material over the active surface surrounding and at least in contact with the metal pillars.
- FIG. 7 depicts a die assembly formed by connection of mutually adjacent semiconductor dice 102a 102b and 102c after inversion of semiconductor die 102a and semiconductor die 102b for so-called "flip chip” bonding by reflow of solder material 110 of conductive elements 104 to respectively connect to landing pads 140 on back sides 142 of semiconductor dice 102b and 102c using thermocompression bonding.
- solder material 110 i.e., melting
- the solder material 110 is formed by reflowing (i.e., melting) the solder material 110 at a temperature, for example, of about 250°C to bond the copper material 106 of conductive elements 104 to the landing pads 140.
- solder material 110 of conductive elements 104 may be dipped in flux and placed in contact with landing pads 140 and the die assembly placed in an oven for reflow.
- a dielectric underfill material 150 is located between semiconductor dice 102a, 102b and 102c, surrounding conductive elements 104 and primarily solder material 110, as photodefinable material 218 surrounds at least copper material 106 of conductive elements 104.
- An embodiment as described above may be characterized as a semiconductor die assembly comprising a semiconductor die having bond pads on a major surface thereof, and conductive pillars located on the bond pads, another semiconductor die having landing pads on a major surface thereof, and landing pads connected to the conductive pillars with a solder material, a dielectric photodefinable material over the major surface of the semiconductor die and surrounding and in contact with the conductive pillars, and a dielectric material over the major surface of the another semiconductor die, in contact with the photodefinable material and laterally surrounding at least a portion of the solder material connecting the conductive pillars to the landing pads.
- Photodefinable material comprising, for example, a photoresist has been described herein to be a so-called "positive" tone material which, when exposed to radiant energy of one or more suitable wavelengths and then developed, may be removed.
- the inventors herein contemplate that the techniques described herein may also be implemented using a "negative" tone photodefinable material in conjunction with a skeleton mask to cover primarily the tops of pillar-type conductive elements during exposure of a wafer comprising photodefinable material-coated semiconductor dice to radiant energy, such exposure being followed by developing using a positive developer.
- the unexposed photodefinable material covering the tops of the conductive elements is removed, leaving the exposed, developed photodefinable material over at least portions of the sides of the conductive elements as well as the bond pads and surrounding passivation material.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015523108A JP6163550B2 (en) | 2012-07-16 | 2013-07-02 | Pillar-on-pad interconnect structure, semiconductor die and die assembly including the interconnect structure, and related methods |
EP13819215.8A EP2873091A4 (en) | 2012-07-16 | 2013-07-02 | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
CN201380038241.9A CN104471680B (en) | 2012-07-16 | 2013-07-02 | Pad column body interconnection structure, semiconductor die, die assemblies and correlation technique |
KR1020157000897A KR101650670B1 (en) | 2012-07-16 | 2013-07-02 | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/550,225 US8659153B2 (en) | 2012-07-16 | 2012-07-16 | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
US13/550,225 | 2012-07-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014014652A1 true WO2014014652A1 (en) | 2014-01-23 |
Family
ID=49913299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2013/049021 WO2014014652A1 (en) | 2012-07-16 | 2013-07-02 | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
Country Status (7)
Country | Link |
---|---|
US (2) | US8659153B2 (en) |
EP (1) | EP2873091A4 (en) |
JP (1) | JP6163550B2 (en) |
KR (1) | KR101650670B1 (en) |
CN (1) | CN104471680B (en) |
TW (1) | TWI603445B (en) |
WO (1) | WO2014014652A1 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
MY149251A (en) * | 2008-10-23 | 2013-07-31 | Carsem M Sdn Bhd | Wafer-level package using stud bump coated with solder |
US9583425B2 (en) * | 2012-02-15 | 2017-02-28 | Maxim Integrated Products, Inc. | Solder fatigue arrest for wafer level package |
US8659153B2 (en) | 2012-07-16 | 2014-02-25 | Micron Technology, Inc. | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US9603283B1 (en) | 2015-10-09 | 2017-03-21 | Raytheon Company | Electronic module with free-formed self-supported vertical interconnects |
US10103069B2 (en) | 2016-04-01 | 2018-10-16 | X-Celeprint Limited | Pressure-activated electrical interconnection by micro-transfer printing |
JP2018006391A (en) | 2016-06-28 | 2018-01-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
US10242926B2 (en) * | 2016-06-29 | 2019-03-26 | Alpha And Omega Semiconductor (Cayman) Ltd. | Wafer level chip scale package structure and manufacturing method thereof |
US10222698B2 (en) | 2016-07-28 | 2019-03-05 | X-Celeprint Limited | Chiplets with wicking posts |
US11064609B2 (en) | 2016-08-04 | 2021-07-13 | X Display Company Technology Limited | Printable 3D electronic structure |
IT201700055983A1 (en) | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | PROCEDURE FOR PRODUCING SEMICONDUCTOR, SEMICONDUCTOR AND CORRESPONDENT CIRCUIT DEVICES |
US10734269B1 (en) | 2017-06-07 | 2020-08-04 | Apple Inc. | Micro device metal joint process |
US10903151B2 (en) * | 2018-05-23 | 2021-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US10790251B2 (en) * | 2018-06-20 | 2020-09-29 | Micron Technology, Inc. | Methods for enhancing adhesion of three-dimensional structures to substrates |
US11869841B2 (en) * | 2020-11-19 | 2024-01-09 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems |
TWI811133B (en) * | 2022-10-12 | 2023-08-01 | 友達光電股份有限公司 | Display panel |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10321630A (en) * | 1997-05-16 | 1998-12-04 | Matsushita Electric Ind Co Ltd | Bump formation |
KR19990060346A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Method of manufacturing protective film for semiconductor device |
JP2001168129A (en) * | 1999-12-10 | 2001-06-22 | Sony Chem Corp | Method for producing contact structure |
US20060094224A1 (en) * | 2004-11-03 | 2006-05-04 | Advanced Semiconductor Engineering, Inc. | Bumping process and structure thereof |
JP4324572B2 (en) * | 2005-03-03 | 2009-09-02 | カシオマイクロニクス株式会社 | Bump formation method |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6072236A (en) | 1996-03-07 | 2000-06-06 | Micron Technology, Inc. | Micromachined chip scale package |
TW480636B (en) * | 1996-12-04 | 2002-03-21 | Seiko Epson Corp | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
CN100474544C (en) * | 1996-12-04 | 2009-04-01 | 精工爱普生株式会社 | Semiconductor device and method of making the same |
US6566016B1 (en) * | 2000-06-28 | 2003-05-20 | Koninklijke Philips Electronics N.V. | Apparatus and method for compensating critical dimension deviations across photomask |
KR100440507B1 (en) * | 2000-03-23 | 2004-07-15 | 세이코 엡슨 가부시키가이샤 | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US20030059718A1 (en) | 2001-09-24 | 2003-03-27 | Koninklijke Philips Electronics N.V. | Method for forming a contact window in a semiconductor device |
JP2004193518A (en) * | 2002-12-13 | 2004-07-08 | Seiko Epson Corp | Method for manufacturing and mounting semiconductor chip, semiconductor chip, semiconductor mounted board, electronic device and electronic apparatus |
US7276801B2 (en) | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
JP2006040955A (en) * | 2004-07-22 | 2006-02-09 | Fuji Photo Film Co Ltd | Forming method of image pattern and manufacturing method of printed wiring board |
JP2006245289A (en) * | 2005-03-03 | 2006-09-14 | Casio Micronics Co Ltd | Semiconductor device and packaging structure |
JP2007103571A (en) * | 2005-10-03 | 2007-04-19 | Tokai Rika Co Ltd | Manufacturing method of semiconductor device |
JP2007305667A (en) * | 2006-05-09 | 2007-11-22 | Toshiba Corp | Semiconductor device and its manufacturing method |
JP5017930B2 (en) * | 2006-06-01 | 2012-09-05 | 富士通株式会社 | Semiconductor device, method for manufacturing solder bump connecting substrate, and method for manufacturing semiconductor device |
WO2009122867A1 (en) * | 2008-03-31 | 2009-10-08 | 日本電気株式会社 | Semiconductor device, composite circuit device, and methods for manufacturing semiconductor device and composite circuit device |
WO2010046408A2 (en) * | 2008-10-22 | 2010-04-29 | Micronic Laser Systems Ab | Method of iterative compensation for non-linear effects in three-dimensional exposure of resist |
US7642128B1 (en) | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
JP2010147252A (en) * | 2008-12-18 | 2010-07-01 | Sharp Corp | Ion implantation method and method of manufacturing semiconductor device |
JP2011009363A (en) * | 2009-06-24 | 2011-01-13 | Nec Corp | Semiconductor device, method of manufacturing the same, and composite circuit device using the same |
US20110285013A1 (en) * | 2010-05-20 | 2011-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists |
US20110291263A1 (en) * | 2010-05-28 | 2011-12-01 | Texas Instruments Incorporated | Ic having dielectric polymeric coated protruding features having wet etched exposed tips |
US9484259B2 (en) * | 2011-09-21 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9082832B2 (en) * | 2011-09-21 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US8659153B2 (en) | 2012-07-16 | 2014-02-25 | Micron Technology, Inc. | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
-
2012
- 2012-07-16 US US13/550,225 patent/US8659153B2/en active Active
-
2013
- 2013-07-02 WO PCT/US2013/049021 patent/WO2014014652A1/en active Application Filing
- 2013-07-02 KR KR1020157000897A patent/KR101650670B1/en active IP Right Grant
- 2013-07-02 EP EP13819215.8A patent/EP2873091A4/en not_active Ceased
- 2013-07-02 CN CN201380038241.9A patent/CN104471680B/en active Active
- 2013-07-02 JP JP2015523108A patent/JP6163550B2/en active Active
- 2013-07-16 TW TW102125422A patent/TWI603445B/en active
-
2014
- 2014-02-21 US US14/186,869 patent/US9129869B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10321630A (en) * | 1997-05-16 | 1998-12-04 | Matsushita Electric Ind Co Ltd | Bump formation |
KR19990060346A (en) * | 1997-12-31 | 1999-07-26 | 윤종용 | Method of manufacturing protective film for semiconductor device |
JP2001168129A (en) * | 1999-12-10 | 2001-06-22 | Sony Chem Corp | Method for producing contact structure |
US20060094224A1 (en) * | 2004-11-03 | 2006-05-04 | Advanced Semiconductor Engineering, Inc. | Bumping process and structure thereof |
JP4324572B2 (en) * | 2005-03-03 | 2009-09-02 | カシオマイクロニクス株式会社 | Bump formation method |
Non-Patent Citations (1)
Title |
---|
See also references of EP2873091A4 * |
Also Published As
Publication number | Publication date |
---|---|
KR101650670B1 (en) | 2016-08-23 |
CN104471680A (en) | 2015-03-25 |
US20140015124A1 (en) | 2014-01-16 |
CN104471680B (en) | 2018-02-16 |
EP2873091A1 (en) | 2015-05-20 |
JP6163550B2 (en) | 2017-07-12 |
TWI603445B (en) | 2017-10-21 |
US8659153B2 (en) | 2014-02-25 |
US20140167259A1 (en) | 2014-06-19 |
KR20150030722A (en) | 2015-03-20 |
TW201411796A (en) | 2014-03-16 |
JP2015526899A (en) | 2015-09-10 |
US9129869B2 (en) | 2015-09-08 |
EP2873091A4 (en) | 2016-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9129869B2 (en) | Pillar on pad interconnect structures, semiconductor devices including same and related methods | |
US10867976B2 (en) | Semiconductor packages having dummy connectors and methods of forming same | |
US20200251463A1 (en) | Packaging Mechanisms for Dies With Different Sizes of Connectors | |
TWI501327B (en) | Three dimensional integrated circuit and method of fabricating the same | |
US11600575B2 (en) | Method for forming chip package structure | |
KR102386542B1 (en) | Semiconductor device and method of manufacture | |
US20230384684A1 (en) | Method for removing resistor layer, and method of manufacturing semiconductor | |
US20240128232A1 (en) | Semiconductor package | |
US11276658B2 (en) | Devices with three-dimensional structures and support elements to increase adhesion to substrates | |
US20230215831A1 (en) | Semiconductor Device and Methods of Manufacture | |
CN218996710U (en) | Semiconductor package | |
TWI834033B (en) | Method for removing resist layer, and method of manufacturing semiconductor structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13819215 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2015523108 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20157000897 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2013819215 Country of ref document: EP |