WO2014007845A1 - Eléments de stockage configurables - Google Patents

Eléments de stockage configurables Download PDF

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Publication number
WO2014007845A1
WO2014007845A1 PCT/US2013/026398 US2013026398W WO2014007845A1 WO 2014007845 A1 WO2014007845 A1 WO 2014007845A1 US 2013026398 W US2013026398 W US 2013026398W WO 2014007845 A1 WO2014007845 A1 WO 2014007845A1
Authority
WO
WIPO (PCT)
Prior art keywords
configurable
circuit
routing
output
circuits
Prior art date
Application number
PCT/US2013/026398
Other languages
English (en)
Inventor
Steven Teig
Christopher D. Ebeling
Martin Voogel
Andrew Caldwell
Trevis Chandler
Thomas S. CHANACK
Que-Won Rhee
Jung Ko
Original Assignee
Tabula, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/540,591 external-priority patent/US8760193B2/en
Priority claimed from US13/549,405 external-priority patent/US9148151B2/en
Application filed by Tabula, Inc. filed Critical Tabula, Inc.
Publication of WO2014007845A1 publication Critical patent/WO2014007845A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

Selon certains modes de réalisation, l'invention concerne un circuit intégré (IC) configurable comprenant un tissu de routage qui comprend un élément de stockage configurable dans le tissu de routage. Dans certains modes de réalisation, l'élément de stockage configurable comprend un trajet distribué parallèle afin de fournir de manière configurée une paire d'éléments de stockage transparents. La paire d'éléments de stockage configurables peut agir de manière configurable comme des éléments de stockage non transparents (commandés par horloge), ou comme des éléments de stockage configurables transparents. Dans certains modes de réalisation, l'élément de stockage configurable dans le tissu de routage effectue à la fois des opérations de routage et de stockage par un trajet distribué parallèle qui comprend un élément de stockage commandé par horloge et une connexion de dérivation. Dans certains modes de réalisation, l'élément de stockage configurable effectuer à la fois des opérations de routage et de stockage via une paire de verrous maîtres-esclaves sans connexion de dérivation.
PCT/US2013/026398 2012-07-02 2013-02-15 Eléments de stockage configurables WO2014007845A1 (fr)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201261667411P 2012-07-02 2012-07-02
US13/540,591 US8760193B2 (en) 2011-07-01 2012-07-02 Configurable storage elements
US61/667,411 2012-07-02
US13/540,596 2012-07-02
US13/540,591 2012-07-02
US13/540,596 US8941409B2 (en) 2011-07-01 2012-07-02 Configurable storage elements
US201261671665P 2012-07-13 2012-07-13
US61/671,665 2012-07-13
US13/549,405 2012-07-13
US13/549,405 US9148151B2 (en) 2011-07-13 2012-07-13 Configurable storage elements

Publications (1)

Publication Number Publication Date
WO2014007845A1 true WO2014007845A1 (fr) 2014-01-09

Family

ID=49882402

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/026398 WO2014007845A1 (fr) 2012-07-02 2013-02-15 Eléments de stockage configurables

Country Status (1)

Country Link
WO (1) WO2014007845A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
CN111668232A (zh) * 2020-06-19 2020-09-15 成都华微电子科技有限公司 集成电路芯片
WO2020183396A1 (fr) * 2019-03-11 2020-09-17 Untether Ai Corporation Mémoire de calcul
US11342944B2 (en) 2019-09-23 2022-05-24 Untether Ai Corporation Computational memory with zero disable and error detection
US11468002B2 (en) 2020-02-28 2022-10-11 Untether Ai Corporation Computational memory with cooperation among rows of processing elements and memory thereof
US11934482B2 (en) 2019-03-11 2024-03-19 Untether Ai Corporation Computational memory

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US20040123167A1 (en) * 2002-12-23 2004-06-24 Power -One Limited System and method for interleaving point-of-load regulators
US20080231314A1 (en) * 2007-03-20 2008-09-25 Steven Teig Configurable IC Having A Routing Fabric With Storage Elements
US20100194429A1 (en) * 2004-11-08 2010-08-05 Steven Teig Reconfigurable ic that has sections running at different reconfiguration rates
US20110031999A1 (en) * 2008-02-27 2011-02-10 Silicon Basis Ltd Programmable logic fabric
US7917559B2 (en) * 2004-11-08 2011-03-29 Tabula, Inc. Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
US20110133777A1 (en) * 2004-02-14 2011-06-09 Herman Schmit Configurable Circuits, IC's, and Systems
US20110154278A1 (en) * 2008-05-24 2011-06-23 Andrew Caldwell Decision modules
US20110221471A1 (en) * 2008-09-17 2011-09-15 Jason Redgrave Controllable storage elements for an ic
US20120098568A1 (en) * 2007-03-22 2012-04-26 Jason Redgrave Method and apparatus for performing an operation with a plurality of sub-operations in a configurable ic
US20120117525A1 (en) * 2007-06-27 2012-05-10 Brad Hutchings Translating a User Design in A Configurable IC for Debugging the User Design

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421784B1 (en) * 1999-03-05 2002-07-16 International Business Machines Corporation Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element
US20040123167A1 (en) * 2002-12-23 2004-06-24 Power -One Limited System and method for interleaving point-of-load regulators
US20110133777A1 (en) * 2004-02-14 2011-06-09 Herman Schmit Configurable Circuits, IC's, and Systems
US20100194429A1 (en) * 2004-11-08 2010-08-05 Steven Teig Reconfigurable ic that has sections running at different reconfiguration rates
US7917559B2 (en) * 2004-11-08 2011-03-29 Tabula, Inc. Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
US20080231314A1 (en) * 2007-03-20 2008-09-25 Steven Teig Configurable IC Having A Routing Fabric With Storage Elements
US20120098568A1 (en) * 2007-03-22 2012-04-26 Jason Redgrave Method and apparatus for performing an operation with a plurality of sub-operations in a configurable ic
US20120117525A1 (en) * 2007-06-27 2012-05-10 Brad Hutchings Translating a User Design in A Configurable IC for Debugging the User Design
US20110031999A1 (en) * 2008-02-27 2011-02-10 Silicon Basis Ltd Programmable logic fabric
US20110154278A1 (en) * 2008-05-24 2011-06-23 Andrew Caldwell Decision modules
US20110221471A1 (en) * 2008-09-17 2011-09-15 Jason Redgrave Controllable storage elements for an ic

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
WO2020183396A1 (fr) * 2019-03-11 2020-09-17 Untether Ai Corporation Mémoire de calcul
US11256503B2 (en) 2019-03-11 2022-02-22 Untether Ai Corporation Computational memory
US11934482B2 (en) 2019-03-11 2024-03-19 Untether Ai Corporation Computational memory
US11342944B2 (en) 2019-09-23 2022-05-24 Untether Ai Corporation Computational memory with zero disable and error detection
US11881872B2 (en) 2019-09-23 2024-01-23 Untether Ai Corporation Computational memory with zero disable and error detection
US11468002B2 (en) 2020-02-28 2022-10-11 Untether Ai Corporation Computational memory with cooperation among rows of processing elements and memory thereof
CN111668232A (zh) * 2020-06-19 2020-09-15 成都华微电子科技有限公司 集成电路芯片

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