WO2013179402A1

WO2013179402A1 - Control system, control method, and program

Info

Publication number: WO2013179402A1
Application number: PCT/JP2012/063821
Authority: WO
Inventors: 森政仁
Original assignee: 富士通株式会社
Priority date: 2012-05-29
Filing date: 2012-05-29
Publication date: 2013-12-05

Abstract

An objective of the present invention is, even if a plurality of process commencement instructions are transmitted from a first device to a second device, to transfer the process commencement instructions, a process termination notification, and an asynchronous notification, without carrying out an exclusivity control between the first device and the second device. A first upper bound value regulates the number of connections which are employed in communication between the first device and the second device. The first device controls the number of process commencement instructions among the process commencement instructions which are transmitted from the first device to the second device for which a process termination notification with respect to the process commencement instruction is not received from the second device to be less than or equal to the first upper bound. The second device controls the sum of the number of the process commencement instructions corresponding to the process termination instructions which are not transmitted from the second device to the first device and the number of the asynchronous notifications which are transmitted from the second device to the first device to less than or equal to a second upper bound value which is greater than the first upper bound value.

Description

Control system, control method, and program

The present invention relates to a control system, a control method, and a program.

FIG. 1 shows the first input / output control in the conventional information processing system. The control system 101 includes an input / output processor (IOP) 111, a channel device (CHU) 112, and an interface 121 between the IOP 111 and the CHU 112.

The IOP 111 performs input / output processing for the input / output devices (Input / Output / Device, IO) 103-1 to IO 103-3 to the input / output control device (Input / Output / Controller, IOC) 102 via the CHU 112. A start instruction START_IO is transmitted. IO 103-1 to IO 103-3 (IO # A to IO # C) are three logically identifiable IOs, and their identification information (ID) is #A to #C, respectively. The IOs 103-1 to IO103-3 may represent three physical IOs or may represent three logical IOs.

The IOC 102 transmits notifications indicating the states of the IO 103-1 to IO 103-3 to the IOP 111 via the CHU 112, and the IOP 111 transmits a response ACC_STS to the notification to the IOC 102 via the CHU 112.

The notification transmitted from the IOC 102 to the IOP 111 includes a processing end notification OPTERM_STS, an asynchronous notification ASYNC_STS, and a busy notification BUSY_STS. The process end notification OPTERM_STS is a notification indicating the end of input / output processing for START_IO, and the asynchronous notification ASYNC_STS is a notification indicating a change in IO state independent of START_IO. The busy notification BUSY_STS is a notification indicating that the input / output process cannot be started because the START_IO is received while attempting to transmit the asynchronous notification ASYNC_STS.

Thus, since communication between the IOP 111 and the IOC 102 is performed via the CHU 112, the START_IO from the IOP 111 and the ASYNC_STS from the IOC 102 may be different in the CHU 112. However, in the communication protocol between the CHU 112 and the IOC 102, since the number of IOs that can be operated during connection is defined as 1, for example, the following exclusive control is performed.

First, the IOP 111 reserves the interface 121 to transmit the START_IO for IO # A (procedure 131), and when the reservation is successful (RSV_SUCC), transmits the START_IO to the CHU 112 (procedure 133). Then, the CHU 112 transmits the START_IO to the IOC 102 (procedure 153).

When the I / O processing of IO # A for START_IO is completed, the IOC 102 transmits OPTERM_STS to the CHU 112 (procedure 154), and the CHU 112 transmits the OPTERM_STS to the IOP 111 (procedure 134). Then, the IOP 111 transmits a response ACC_STS indicating that the OPTERM_STS has been received to the CHU 112 (procedure 135), and releases the reservation of the interface 121 (RLS) (procedure 136). The CHU 112 transmits the received ACC_STS to the IOC 102 (procedure 155).

Meanwhile, the IOC 102 transmits a connection request REQ_CNCT to the CHU 112 in order to transmit ASYNC_STS indicating the state of IO # B (procedure 151). When receiving the REQ_CNCT, the CHU 112 reserves the interface 121 (procedure 132). However, since the interface 121 is being used for communication related to IO # A, the CHU 112 fails to make a reservation (RSV_FAIL), and transmits a connection rejection response DNY_CNCT to the IOC 102 (procedure 152). In this case, the IOC 102 cannot transmit ASYNC_STS to the CHU 112.

After receiving ACC_STS from the CHU 112, the IOC 102 transmits REQ_CNCT to the CHU 112 again (procedure 156), and when receiving the REQ_CNCT, the CHU 112 reserves the interface 121 (procedure 137). At this time, since the reservation of the interface 121 has been released, the CHU 112 succeeds in the reservation (RSV_SUCC), and transmits a connection acceptance response ACC_CNCT to the IOC 102 (procedure 157).

Therefore, the IOC 102 transmits ASYNC_STS indicating the state of IO # B to the CHU 112 (procedure 158), and the CHU 112 transmits the ASYNC_STS to the IOP 111 (procedure 139). Then, the IOP 111 transmits a response ACC_STS indicating that the ASYNC_STS has been received to the CHU 112 (procedure 140). The CHU 112 transmits the received ACC_STS to the IOC 102 (procedure 159), and releases the reservation of the interface 121 (procedure 141).

On the other hand, the IOP 111 reserves the interface 121 to transmit START_IO targeted for IO # C (procedure 138). However, since the interface 121 is being used for communication related to IO # B, the IOP 111 fails to reserve the interface 121 (RSV_FAIL) and cannot transmit START_IO to the CHU 112.

The IOP 111 reserves the interface 121 again after transmitting ACC_STS to the CHU 112 (procedure 142). At this time, since the reservation of the interface 121 is cancelled, the IOP 111 succeeds in the reservation (RSV_SUCC), and transmits START_IO for IO # C to the CHU 112 (procedure 143). Then, the CHU 112 transmits the START_IO to the IOC 102 (procedure 160).

In the input / output control of FIG. 1, since the number of the interfaces 121 that are communication resources between the IOP 111 and the CHU 112 is one, interlock is performed as exclusive control for the interface 121.

In this interlock, communication related to any one of IO # A to IO # C cannot be performed while communication related to any one of IO # A to IO # C is being performed. If either the IOP 111 or the CHU 112 successfully reserves the interface 121 for communication related to one IO, the interface 121 is exclusively used for communication related to that IO until the reservation is released.

For example, in steps 131 to 136, START_IO, OPTERM_STS, and ACC_STS related to IO # A are transmitted and received between the IOP 111 and the CHU 112. Next, in steps 137 to 141, ASYNC_STS and ACC_STS related to IO # B are transmitted / received, and in

steps

142 and 143, START_IO related to IO # C are transmitted / received.

Recently, a communication protocol capable of operating a plurality of IOs during connection has been adopted between the CHU 112 and the IOC 102, and exclusive control such as a connection request from the IOC 102 to the CHU 112 has been abolished. However, since the number of communication resources between the IOP 111 and the CHU 112 is still one, exclusive control for the interface 121 has not been abolished.

FIG. 2 shows such second input / output control. The CHU 112 in FIG. 2 includes a buffer 201 for temporarily storing the notification received from the IOC 102.

First, the IOP 111 reserves the interface 121 for transmitting START_IO for IO # A (procedure 211), and when the reservation is successful (RSV_SUCC), transmits the START_IO to the CHU 112 (procedure 213). Then, the CHU 112 transmits the START_IO to the IOC 102 (procedure 232), and releases the reservation of the interface 121 by the IOP 111 (RLS) (procedure 214).

Meanwhile, the IOC 102 transmits ASYNC_STS indicating the state of IO # B to the CHU 112 (procedure 231). The CHU 112 stores the received ASYNC_STS in the buffer 201 and reserves the interface 121 (procedure 212). However, since the interface 121 is being used for communication related to IO # A, the CHU 112 fails to make a reservation (RSV_FAIL) and suspends transmission of ASYNC_STS.

After canceling the reservation of the interface 121, the CHU 112 reserves the interface 121 again (procedure 215) and succeeds in the reservation (RSV_SUCC). Therefore, the CHU 112 transmits ASYNC_STS stored in the buffer 201 to the IOP 111 (procedure 217). Then, the IOP 111 transmits a response ACC_STS indicating that the ASYNC_STS has been received to the CHU 112 (procedure 218). The CHU 112 transmits the received ACC_STS to the IOC 102 (procedure 234), and releases the reservation of the interface 121 (procedure 219).

The IOP 111 reserves the interface 121 to transmit START_IO targeted for IO # C (procedure 216). However, since the interface 121 is being used for communication related to IO # B, the IOP 111 fails to reserve the interface 121 (RSV_FAIL) and cannot transmit START_IO to the CHU 112.

When the IO # A input / output processing for START_IO is completed, the IOC 102 transmits OPTERM_STS to the CHU 112 (procedure 233). The CHU 112 stores the received OPTERM_STS in the buffer 201.

After canceling the reservation of the interface 121, the CHU 112 reserves the interface 121 again (procedure 220) and succeeds in the reservation (RSV_SUCC). Therefore, the CHU 112 transmits OPTERM_STS stored in the buffer 201 to the IOP 111 (procedure 221). Then, the IOP 111 transmits a response ACC_STS indicating that the OPTERM_STS has been received to the CHU 112 (procedure 222). The CHU 112 transmits the received ACC_STS to the IOC 102 (procedure 235), and releases the reservation of the interface 121 (RLS) (procedure 223).

The IOP 111 reserves the interface 121 again after transmitting ACC_STS to the CHU 112 (procedure 224). At this time, since the reservation of the interface 121 is released, the IOP 111 succeeds in the reservation (RSV_SUCC), and transmits START_IO targeted for IO # C to the CHU 112 (procedure 225). Then, the CHU 112 transmits the START_IO to the IOC 102 (procedure 236), and releases the reservation of the interface 121 by the IOP 111 (RLS) (procedure 226).

According to such input / output control, there is no need to transmit / receive control information for exclusive control such as a connection request, a connection rejection response, and a connection acceptance response between the CHU 112 and the IOC 102.

Regarding the conventional channel device, a technique for reducing the communication amount between the computer system and the input / output control device and reducing the load on the computer system and the input / output control device is also known. This channel device notifies a start instruction issued from the channel control adapter to the input / output control device, and the input / output control device notifies the channel device of busy when the input / output device is busy. When the channel device is notified of the busy status, it notifies the channel control adapter of the initial status indicating that the start instruction has been accepted. When the channel device is notified of the busy release, the input / output control device Is notified of the start instruction.

Further, when the channel device is notified of the status from the input / output control device, the channel device temporarily holds the status, and when the channel control adapter is in a state where it cannot receive the status, Notify the stack. When the channel device is notified of the stack, the channel device notifies the input / output control device that the status notification has been accepted, and executes a process of notifying the status according to a specified period until the channel control adapter receives it.

In addition, in an I / O control method in which an I / O processor queues I / O requests and executes I / O processing while dequeuing, a technique for reducing the scope of influence due to changes in I / O configuration is also known. Yes. In this technology, a unit for creating an input / output request queue is a collection of input / output control devices, and all input / output control devices connected to one input / output device belong to the same creation unit. An upper limit is set for the number of connected channels. When the input / output request is dequeued from the queue, the input / output path is selected based on the status information of the corresponding input / output control device.

JP-A-8-123748 Japanese Patent Laid-Open No. 2-113356

The conventional input / output control described above has the following problems.
As the transfer rate of input / output processing in the information processing system increases, the proportion of time required for exclusive control between the IOP 111 and the CHU 112 increases, and the influence of exclusive control on the input / output processing capability increases. For this reason, it is considered that the throughput of the input / output processing, which has been improved by eliminating the exclusive control between the CHU 112 and the IOC 102, is lowered.

Such a problem occurs not only in input / output control in an information processing system, but also in other control systems that transfer processing start instructions, processing end notifications, and asynchronous notifications between the first device and the second device. Is.

In one aspect, the present invention does not perform exclusive control between the first device and the second device even when a large number of processing start instructions are transmitted from the first device to the second device. It is intended to transfer a processing start instruction, a processing end notification, and an asynchronous notification.

In one scheme, the control system includes a first device and a second device. The first device includes a first communication unit, a first storage unit, and a first control unit. The first communication unit transmits a process start instruction to the second device, and receives a process end notification and an asynchronous notification for the process start instruction from the second device. The first storage unit stores a first upper limit value that defines the number of connections used for communication between the first device and the second device. The first control unit controls the number of processing start instructions corresponding to processing end notifications not received from the second device to a number equal to or less than the first upper limit value.

The second device includes a second communication unit, a second storage unit, and a second control unit. The second communication unit receives a processing start instruction from the first device, and transmits a processing end notification and an asynchronous notification to the first device. The second storage unit stores a second upper limit value that is larger than the first upper limit value. The second control unit determines the total number of processing start instructions corresponding to processing end notifications not yet transmitted to the first device and the number of asynchronous notifications transmitted to the first device as a second upper limit value. Control to the following number.

According to the control system in the embodiment, even when a large number of processing start instructions are transmitted from the first device to the second device, without performing exclusive control between the first device and the second device, A process start instruction, a process end notification, and an asynchronous notification can be transferred.

It is a figure which shows the 1st input / output control in the conventional information processing system. It is a figure which shows the 2nd input / output control in the conventional information processing system. It is a figure which shows the influence of the exclusive control in the conventional 2nd input / output control. It is a block diagram of the control system of embodiment. It is a flowchart of the control which a 1st apparatus performs. It is a flowchart of the control which a 2nd apparatus performs. It is a figure which shows the input / output control in the information processing system of embodiment. It is a block diagram of the information processing system of embodiment. It is a flowchart of the process performed when IOP receives IO process command. It is a flowchart of the process performed when IOP receives OPTERM_STS or BUSY_STS. It is a flowchart of the process performed when IOP receives ASYNC_STS. It is a flowchart of the process performed when IOP receives BUSY. It is a flowchart of the process which IOP dequeues a CHU transmission queue. It is a flowchart of the process which IOP dequeues an execution queue. It is a flowchart of the process performed when CHU receives START_IO. It is a flowchart of the process performed when CHU receives OPTERM_STS or BUSY_STS. It is a flowchart of the process performed when CHU receives ASYNC_STS. It is a flowchart of the process performed when CHU receives ACC_STS. It is a flowchart of the process which CHU dequeues an IOC transmission queue. It is a flowchart of the process which CHU dequeues an IOP transmission queue. FIG. 6 is a diagram (part 1) illustrating a sequence of input / output control. FIG. 5 is a diagram (part 2) illustrating a sequence of input / output control. FIG. 10 is a third diagram illustrating the sequence of input / output control. FIG. 10 is a diagram (part 4) illustrating the sequence of input / output control. It is FIG. (5) which shows the sequence of input / output control. It is FIG. (6) which shows the sequence of input / output control. It is a figure which shows the input / output capability improved by the input / output control of embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings.
FIG. 3 shows the influence of exclusive control in the input / output control of FIG. The horizontal axis of FIG. 3 represents the transfer rate of input / output processing (megabytes / second, MB / S), and the vertical axis represents the frequency of IO instruction execution of a central processing unit (CPU) in one second. A broken line 301 represents the target value of the CPU IO instruction execution frequency with respect to the transfer rate, and a solid line 302 represents the actual CPU IO instruction execution frequency when there is exclusive control between the IOP 111 and the CHU 112.

In this case, it takes about 15 μs for the exclusive processing for performing the reservation of the interface 121 or the cancellation of the reservation in one input / output processing.

For example, while the target value of the CPU IO instruction execution frequency corresponding to the transfer rate of 17 MB / S is 850, the actual CPU IO instruction execution frequency when performing the input / output control of FIG. 3. Therefore, the frequency of IO instruction execution by the CPU decreases by about 10.7 (about 1.3%) due to the influence of the exclusive control in FIG.

On the other hand, when the input / output control of FIG. 2 is performed, the target value of the CPU IO instruction execution frequency at the point 321 on the broken line 301 corresponding to the transfer rate of 320 MB / S is 16000, whereas At point 322, the actual CPU IO instruction execution frequency is about 12900. Accordingly, the frequency of IO instruction execution by the CPU is reduced by about 3100 (about 19.4%) due to the influence of the exclusive control of FIG. 2, and the influence is greater than that of the exclusive control of FIG.

As can be seen from FIG. 2, the transfer rate increases, and the CPU IO instruction execution frequency decreases greatly due to the influence of exclusive control between the IOP 111 and the CHU 112. For this reason, there is a tendency that the throughput of the input / output processing, which has been improved by eliminating the exclusive control between the CHU 112 and the IOC 102, is lowered. Therefore, it is desirable to eliminate exclusive control between the IOP 111 and the CHU 112.

In the control system of the embodiment, instead of abolishing exclusive control between the first device corresponding to the IOP 111 and the second device corresponding to the CHU 112, communication is performed between the first device and the second device. An upper limit is set for the number of connections used for the.

After the process start instruction is transmitted from the first device to the second device, the process is regarded as being connected until the process end notification is returned from the second device to the first device. Therefore, after the first device transmits the maximum number of processing start instructions corresponding to the upper limit value to the second device, the first device starts a new processing start instruction until receiving a processing end notification for any of the processing start instructions. Suspend sending On the other hand, the second device can start a new connection for transmitting an asynchronous notification to the first device while the number of processing start instructions received from the first device has not reached the upper limit.

However, when a large number of process start instructions exceeding the upper limit value are generated, the first apparatus transmits a next process start instruction as soon as a process end notification is received from the second apparatus. The number of processing start instructions always seems to reach the upper limit. Thus, when the upper limit value used for controlling the number of connections in the first device and the upper limit value used for controlling the number of connections in the second device are set to the same value, the second device sends the asynchronous notification to the first device. May not be able to be transmitted to other devices.

Therefore, it is desirable to set the upper limit value used for controlling the number of connections in the second device to a value larger than the upper limit value used for controlling the number of connections in the first device. Specifically, the first device transmits one or more processing start instructions within a range equal to or smaller than the first upper limit value to the second device, and the second device has a first value greater than the first upper limit value. In a range equal to or less than the upper limit of 2, a process end notification and an asynchronous notification in response to the process start instruction are transmitted to the first device.

According to such control, after the first apparatus transmits the maximum number of process start instructions corresponding to the first upper limit value to the second apparatus, the first apparatus sends a process end notification for any of the process start instructions. Until it is received, transmission of a new process start instruction is suspended. On the other hand, the second device starts a new connection for transmitting an asynchronous notification to the first device even when the number of processing start instructions received from the first device reaches the first upper limit value. can do.

FIG. 4 shows a configuration example of a control system that performs such control. The control system of FIG. 4 includes a first device 401 and a second device 402. The first device 401 includes a first communication unit 411, a first storage unit 412, and a first control unit 413. The first communication unit 411 transmits a process start instruction to the second device 402, and receives a process end notification and an asynchronous notification for the process start instruction from the second device 402. The first storage unit 412 stores a first upper limit value 414 that defines the number of connections used for communication between the first device 401 and the second device 402.

The second device 402 includes a second communication unit 421, a second storage unit 422, and a second control unit 423. The second communication unit 421 receives a processing start instruction from the first device 401 and transmits a processing end notification and an asynchronous notification to the first device 401. The second storage unit 422 stores a second upper limit value 424 that is larger than the first upper limit value 414.

5 and 6 are flowcharts showing examples of control performed by the first control unit 413 and the second control unit 423, respectively. The first control unit 413 controls the number of processing start instructions corresponding to processing end notifications not received from the second device 402 to a number equal to or less than the first upper limit value 414 (step 501 in FIG. 5).

The second control unit 423 includes the number of processing start instructions corresponding to the processing end notification not transmitted from the second device 402 to the first device 401, and the number of asynchronous notifications transmitted to the first device 401. Is controlled to a number equal to or less than the second upper limit value 424 (step 601 in FIG. 6).

According to such a control system, even when a large number of processing start instructions are transmitted from the first device 401 to the second device 402, exclusive control is performed between the first device 401 and the second device 402. The processing start instruction, the processing end notification, and the asynchronous notification can be transferred without performing them. Hereinafter, the first upper limit value may be written as N, and the second upper limit value may be written as M.

FIG. 7 shows an example of input / output control in the information processing system of the embodiment. The control system 701 includes an IOP 711 and a CHU 712. The IOP 711 and the CHU 712 respectively correspond to the first device 401 and the second device 402 in FIG.

The IOP 711 transmits an input / output processing start instruction START_IO for the IO 703-1 to IO 703-5 to the IOC 702 via the CHU 712. IO703-1 to IO703-5 (IO # A to IO # E) are five logically identifiable IOs, and their IDs are #A to #E, respectively. IO703-1 to IO703-5 may represent five physical IOs or may represent five logical IOs.

Examples of physical IO include input devices such as a keyboard and pointing device, display devices, output devices such as printers and speakers, external storage devices such as disk devices and semiconductor memories. A logical IO corresponds to, for example, one of a plurality of virtual IOs realized as a plurality of virtual machines using one or more physical IOs.

In FIG. 7, START_IO is a processing start instruction for input / output processing from the IOP 711 to the IOC 702, and OPTERM_STS is a processing end notification for the START_IO. ASYNC_STS is an asynchronous notification indicating a change in the IO state from the IOC 702 to the IOP 711, and ACC_STS is a response to notifications such as OPTERM_STS, ASYNC_STS, and BUSY_STS.

BUSY_STS is a busy notification indicating that the input / output process cannot be started because the START_IO is received from the IOP 711 instead of the ACC_STS after the ASYNC_STS is transmitted from the IOC 702 to the IOP 711. BUSY is a busy notification indicating that when the number of connections in the CHU 712 is equal to or greater than the first upper limit value N, a new START_IO has been received from the IOP 711 and the START_IO cannot be accepted.

7, the first upper limit value N used for control by the IOP 711 is 3, and the second upper limit value M used by the CHU 712 for control is 4.

First, the IOP 711 transmits START_IO targeted for IO # A to the CHU 712 (procedure 721), and the CHU 712 transmits the START_IO to the IOC 702 (procedure 742). Next, the IOP 711 transmits START_IO targeted for IO # B to the CHU 712 (procedure 722), and the CHU 712 transmits the START_IO to the IOC 702 (procedure 743).

On the other hand, the IOC 702 transmits ASYNC_STS indicating the state of IO # B to the CHU 712 (procedure 741), and the CHU 712 transmits the ASYNC_STS to the IOP 711 (procedure 723). In this case, the IOP 711 discards the ASYNC_STS because it has received the ASYNC_STS related to the same IO after receiving the START_IO for the START_IO after transmitting the START_IO for the IO # B. The reason why the IOP 711 may discard the ASYNC_STS is as follows.

In the communication protocol between the CHU 712 and the IOC 702, when START_IO and ASYNC_STS related to the same IO pass each other, control is performed to disable ASYNC_STS and enable START_IO. In this case, the IOC 702 can notify the IO state to be notified by ASYNC_STS again as a response to START_IO.

On the other hand, when START_IO and ASYNC_STS related to the same IO pass between the IOP 711 and the CHU 712, the IOP 711 discards the ASYNC_STS, and the CHU 712 can perform control to transmit the START_IO to the IOC 702. According to such control, when viewed from the IOC 702, the state is the same as when START_IO and ASYNC_STS pass between the CHU 712 and the IOC 702. Therefore, the communication protocol between the CHU 712 and the IOC 702 is not violated.

Next, the IOC 702 transmits ASYNC_STS indicating the state of IO # C to the CHU 712 (procedure 744), and the CHU 712 transmits the ASYNC_STS to the IOP 711 (procedure 725). Further, the IOC 702 transmits ASYNC_STS indicating the state of IO # D to the CHU 712 (procedure 745), and the CHU 712 transmits the ASYNC_STS to the IOP 711 (procedure 727).

At this time, the number of START_IO corresponding to the OPTERM_STS not transmitted from the CHU 712 is 2, and the number of ASYNC_STS transmitted by the CHU 712 is 2, so the number of connections between the IOP 711 and the CHU 712 is 4. The number of connections 4 is equal to the second upper limit value M in the CHU 712.

On the other hand, since the number of START_IO corresponding to the OPTERM_STS that has not been received from the CHU 712 is 2, and the IOP 711 has not reached the first upper limit N of 3, the new START_IO for IO # E is sent to the CHU 712. Transmit (procedure 724). However, since the number of connections in the CHU 712 is equal to or greater than the first upper limit value N, the CHU 712 returns BUSY to the IOP 711 in order to suppress an increase in the number of connections (procedure 729).

Next, the IOP 711 transmits ACC_STS indicating that ASYNC_STS related to IO # C has been received to the CHU 712 (procedure 726), and the CHU 712 transmits the ACC_STS to the IOC 702 (procedure 746). Further, the IOP 711 transmits ACC_STS indicating that the ASYNC_STS related to IO # D has been received to the CHU 712 (procedure 728), and the CHU 712 transmits the ACC_STS to the IOC 702 (procedure 747).

When the I / O processing of IO # A for START_IO is completed, the IOC 702 transmits OPTERM_STS to the CHU 712 (procedure 748), and the CHU 712 transmits the OPTERM_STS to the IOP 711 (procedure 730). Since the IOC 702 receives the START_IO related to the same IO after transmitting the ASYNC_STS related to the IOSYNC B and before receiving the ACC_STS corresponding to the ASYNC_STS, the IOC 702 returns the BUSY_STS to the CHU 712 (step 749).

Next, the IOP 711 transmits ACC_STS indicating that OPTERM_STS related to IO # A has been received to the CHU 712 (procedure 732), and the CHU 712 transmits the ACC_STS to the IOC 702 (procedure 750). Also, the IOP 711 transmits ACC_STS indicating that BUSY_STS related to IO # B has been received to the CHU 712 (procedure 733), and the CHU 712 transmits the ACC_STS to the IOC 702 (procedure 751).

In this way, the IOP 711 transmits one or more START_IOs to the CHU 112 within the range of the first upper limit value N or less, and the CHU 712 transmits OPTERM_STS and ASYNC_STS to the IOP 711 within the range of the second upper limit value M or less. To do.

START_IO is an instruction based on an instruction from a central processing unit (CPU) in the information processing system. Therefore, if the CHU 712 does not process the START_IO received from the IOP 711 with priority, the processing efficiency of the entire information processing system decreases. Here, when the second upper limit value M is set to be equal to or lower than the first upper limit value N, only START_IO and OPTERM_STS may be transferred between the IOP 711 and the CHU 712, and other notifications such as ASYNC_STS may not be transferred. .

As an example of ASYNC_STS, an attention to notify a screen input when the Enter key of the keyboard is pressed is known. If this attention cannot be notified to the CPU, the operator cannot operate the information processing system.

However, if the second upper limit value M is set to a value larger than the first upper limit value N, the CHU 712 transmits ASYNC_STS to the IOP 711 even when the number of START_IO received from the IOP 711 reaches N. A new connection can be started. Therefore, it becomes possible to transmit the attention to the IOP 711.

Next, the configuration and operation of the information processing system including the control system 701 and the IOC 702 will be described in more detail with reference to FIGS.

FIG. 8 shows a configuration example of the information processing system. 8 includes a control system 701, an IOC 702, a CPU 801, a memory control unit (Memory 制御 Control Unit, MCU) 802, a main storage unit (Main Storage Unit, MSU) 803, and IO804-1 to IO804-9. . The control system 701 includes an IOP 711 and a CHU 712.

The MSU 803 includes a main memory 811. The main memory 811 stores a system program 812 and has a hardware system area (Hardware System Area, HSA) 813. The system program 812 includes an operating system (OS).

The CPU 801 reads the system program 812 stored in the main memory 811 via the MCU 802, interprets the system program 812, and executes it. The CPU 801 transmits an IO processing instruction for instructing the start of input / output processing to the IOP 711 according to an instruction described in the system program 812 and receives an IO processing result from the IOP 711. Further, the CPU 801 receives asynchronous interrupts from the IOs 804-1 to IO804-9 via the IOP 711.

The MCU 802 controls access from the CPU 801 and the IOP 711 to the MSU 803. The HSA 813 in the main memory 811 of the MSU 803 is an area used by the CPU 801 and the IOP 711 to perform input / output operations. The HSA 813 stores an execution queue 814 for controlling the execution of input / output processing, and a flag 815 indicating whether the input / output processing related to each IO is being activated.

The IOP 711 includes a control processor 821, a memory 822, an MSU access unit 823, and a CHU communication unit 824. The memory 822 stores a control program 825, an active IO counter 826, and a CHU transmission queue 828, and has a CHU reception buffer area 827. The CHU reception buffer area 827 stores N−1 reception buffers.

The control processor 821 reads the control program 825 in the memory 822, interprets the control program 825, and executes it. The MSU access unit 823 accesses the main memory 811 in the MSU 803 via the MCU 802 according to an instruction from the control processor 821, and performs reading from the HSA 813 and writing to the HSA 813. The CHU communication unit 824 communicates with the CHU 712 according to a command from the control processor 821.

When the IOP 711 receives an IO processing command from the CPU 801, the IOP 711 transmits START_IO to the CHU 712, and transmits notification contents such as OPTERM_STS, ASYNC_STS, and BUSY_STS received from the CHU 712 to the CPU 801. The active IO counter 826 is a count value indicating the number of IOs connected between the IOP 711 and the CHU 712, and the maximum value is N. By providing the active IO counter 826, the IOP 711 can check whether or not the number of connections in the IOP 711 has reached the maximum value N.

The CHU 712 includes a control processor 831, a memory 832, an IOP communication unit 833, and an IOC communication unit 834. The memory 832 stores an IOP transmission queue 835, a control program 837, a connect IO counter 838, and an IOC transmission queue 840, and has an IOP reception buffer area 836 and an IOC reception buffer area 839. The IOP receive buffer area 836 stores N−1 receive buffers, and the IOC receive buffer area 839 stores M−1 receive buffers.

The control processor 831 reads the control program 837 in the memory 832 and interprets and executes the control program 837. The IOP communication unit 833 communicates with the IOP 711 according to a command from the control processor 831. The IOC communication unit 834 communicates with the IOC 702 according to a command from the control processor 831.

The CHU 712 transmits START_IO received from the IOP 711 to the IOC 702, and transmits OPTERM_STS, ASYNC_STS, BUSY_STS, etc. received from the IOC 702 to the IOP 711. The connect IO counter 838 is a count value indicating the number of IOs connected between the IOP 711 and the CHU 712, and the maximum value is M. By providing the connect IO counter 838, the CHU 712 can check whether or not the number of connections in the CHU 712 has reached the maximum value M.

The IOC 702 includes a CHU communication unit 841 and a CHU reception buffer area 842. The CHU communication unit 841 communicates with the CHU 712. The CHU reception buffer area 842 stores M−1 reception buffers. The IOC 702 transmits the START_IO received from the CHU 712 to the IOs 804-1 to IO804-9. Further, the IOC 702 transmits notifications such as OPTERM_STS indicating the processing results of the input / output processing received from the IOs 804-1 to IO804-9 and ASYNC_STS indicating the asynchronous interrupts received from the IOs 804-1 to IO804-9 to the CHU 712.

IO804-1 to IO804-9 (IO # 01 to IO # 09) are nine logically identifiable IOs, and their IDs are # 01 to IO # 09, respectively. The IOs 804-1 to IO804-9 may represent nine physical IOs and may represent nine logical IOs. The IOs 804-1 to IO804-9 execute input / output processing according to START_IO received from the IOC 702, and transmit the processing result to the IOC 702. Further, the IOs 804-1 to IO804-9 transmit an asynchronous interrupt or the like indicating a change in the IO state to the IOC 702.

Note that the number of IOs connected to the IOC 702 is not limited to nine and may be an integer of 1 or more. The first upper limit value N may be an integer equal to or greater than 1, and the second upper limit value M may be an integer equal to or greater than 2. When a virtual computer that is a plurality of virtual machines is operated by the system program 812, N is preferably equal to or greater than the number of virtual computers, and the difference M−N between M and N is preferably equal to or greater than the number of virtual computers. .

The main memory 811, the memory 822, and the memory 832 are semiconductor memories such as Random Access Memory (RAM), for example. The system program 812, the control program 825, and the control program 837 may be stored in a Read Only Memory (ROM) instead of being stored in the RAM.

In addition, the information processing system transmits a system program 812, a control program 825, or a control program 837 stored in an external storage device or a portable recording medium via the IO 804-1 to IO 804-9 to the main memory 811, the memory 822, And can be loaded into memory 832.

The external storage device is, for example, a magnetic disk device, an optical disk device, a magneto-optical disk device, a tape device, or the like. The external storage device also includes a hard disk drive. The portable recording medium is, for example, a memory device, a flexible disk, an optical disk, a magneto-optical disk, or the like. The portable recording medium includes Compact Disk Read Only Memory (CD-ROM), Digital Versatile Disk (DVD), flash memory, Universal Serial Bus (USB) memory, and the like.

As described above, the computer-readable recording medium storing the system program 812, the control program 825, or the control program 837 includes physical (non-volatile) such as a RAM, a ROM, an external storage device, and a portable recording medium. Temporary recording media are included.

9 to 14 are flowcharts showing examples of processing performed by the IOP 711. 9 to 14, “IDLE” indicates that the IOP 711 is idling.

The IOP 711 turns on the corresponding IO flag 815 of the HSA 813 when adding 1 to the active IO counter 826, and turns off the corresponding IO flag 815 when subtracting 1 from the active IO counter 826.

First, the process of FIG. 9 will be described. When the IOP 711 receives an IO processing command from the CPU 801 (step 901), the IOP 711 checks the active IO counter 826 (step 902). If the active IO counter 826 is smaller than N (step 902, YES), the IOP 711 adds 1 to the active IO counter 826 (step 903), and checks whether the CHU transmission queue 828 is empty (step 904).

If the CHU transmission queue 828 is empty (step 904, YES), the IOP 711 checks whether or not there is an empty space in the IOP reception buffer area 836 of the CHU 712 (step 905). If there is a free space in the IOP reception buffer area 836 (step 905, YES), the IOP 711 transmits START_IO to the CHU 712 (step 906).

On the other hand, if the active IO counter 826 has reached N (step 902, NO), the IOP 711 enqueues START_IO into the execution queue 814 of the HSA 813 (step 907), and performs another process. By enqueueing START_IO into the execution queue 814, the IOP 711 suspends transmission of START_IO to the CHU 712.

If the CHU transmission queue 828 is not empty (step 904, NO), the IOP 711 enqueues START_IO into the CHU transmission queue 828 (step 908). If there is no free space in the IOP reception buffer area 836 (NO in step 905), the IOP 711 performs the processing in step 908.

Next, the process of FIG. 10 will be described. When the IOP 711 receives OPTERM_STS or BUSY_STS from the CHU 712 (step 1001), the IOP 711 checks whether or not the CHU transmission queue 828 is empty (step 1002). If the CHU transmission queue 828 is empty (step 1002, YES), the IOP 711 checks whether or not there is an empty space in the IOP reception buffer area 836 of the CHU 712 (step 1003).

If there is an empty IOP reception buffer area 836 (step 1003, YES), the IOP 711 transmits ACC_STS to the CHU 712 (step 1004). Then, the IOP 711 transmits an IO processing result indicating the received notification content to the CPU 801 (step 1005), and subtracts 1 from the active IO counter 826 (step 1006).

On the other hand, if the CHU transmission queue 828 is not empty (step 1002, NO), the IOP 711 enqueues ACC_STS into the CHU transmission queue 828 (step 1007). If there is no free space in the IOP reception buffer area 836 (step 1003, NO), the IOP 711 performs the process of step 1007.

Next, the process of FIG. 11 will be described. When the IOP 711 receives ASYNC_STS from the CHU 712 (step 1101), the IOP 711 refers to the flag 815 of the HSA 813 and checks whether an input / output process related to the same IO is being activated (step 1102). If the input / output processing related to the same IO is being activated (step 1101, YES), the IOP 711 discards ASYNC_STS (step 1107).

If the input / output processing related to the same IO is not active (step 1101, NO), the IOP 711 checks whether or not the CHU transmission queue 828 is empty (step 1103). If the CHU transmission queue 828 is empty (step 1103, YES), the IOP 711 checks whether or not there is an empty space in the IOP reception buffer area 836 of the CHU 712 (step 1104). If there is an empty IOP reception buffer area 836 (step 1104, YES), the IOP 711 transmits ACC_STS to the CHU 712 (step 1105), and transmits an asynchronous interrupt indicating the notification content of ASYNC_STS to the CPU 801 (step 1106).

On the other hand, if the CHU transmission queue 828 is not empty (step 1103, NO), the IOP 711 adds 1 to the active IO counter 826 (step 1108), and enqueues ACC_STS into the CHU transmission queue 828 (step 1109). If there is no free space in the IOP reception buffer area 836 (step 1104, NO), the IOP 711 performs the processing from step 1108 onward.

Next, the process of FIG. 12 will be described. When the IOP 711 receives BUSY from the CHU 712 (step 1201), it subtracts 1 from the active IO counter 826 (step 1202) and enqueues START_IO into the execution queue 814 of the HSA 813 (step 1203).

Next, the process of FIG. 13 will be described. The IOP 711 checks whether or not the CHU transmission queue 828 is empty at a predetermined timing (step 1301). If the CHU transmission queue 828 is not empty (step 1301, NO), the IOP 711 checks whether or not there is an empty space in the IOP reception buffer area 836 of the CHU 712 (step 1302).

If there is an empty IOP reception buffer area 836 (step 1302, YES), the IOP 711 dequeues the head information from the CHU transmission queue 828 (step 1303) and checks whether the information is START_IO (step 1304). .

If the top information is START_IO (step 1304, YES), the IOP 711 transmits the START_IO to the CHU 712 (step 1305).

If the head information is not START_IO but ACC_STS (step 1304, NO), the IOP 711 subtracts 1 from the active IO counter 826 (step 1306), and transmits the ACC_STS to the CHU 712 (step 1307). Then, the IOP 711 checks whether or not the transmitted ACC_STS is a response to the ASYNC_STS (step 1308).

If ACC_STS is not a response to ASYNC_STS but a response to OPTERM_STS or BUSY_STS (step 1308, NO), IOP 711 transmits the IO processing result to CPU 801 (step 1309).

If ACC_STS is a response to ASYNC_STS (step 1308, YES), the IOP 711 transmits an asynchronous interrupt to the CPU 801 (step 1310).

On the other hand, if the CHU transmission queue 828 is empty (step 1301, YES), the IOP 711 performs another process. If there is no free space in IOP reception buffer area 836 (step 1003, NO), IOP 711 performs another process.

Next, the process of FIG. 14 will be described. The IOP 711 checks whether or not the execution queue 814 of the HSA 813 is empty at a predetermined timing (step 1401). If the execution queue 814 is not empty (step 1401, NO), the IOP 711 checks the active IO counter 826 (step 1402).

If the active IO counter 826 is smaller than N (step 1402, YES), the IOP 711 dequeues the first START_IO from the execution queue 814 (step 1403). The IOP 711 adds 1 to the active IO counter 826 (step 1404) and checks whether the CHU transmission queue 828 is empty (step 1405). If the CHU transmission queue 828 is empty (step 1405, YES), the IOP 711 checks whether or not there is an empty space in the IOP reception buffer area 836 of the CHU 712 (step 1406).

If there is an empty IOP reception buffer area 836 (step 1406, YES), the IOP 711 transmits START_IO to the CHU 712 (step 1407).

On the other hand, if the execution queue 814 is empty (step 1401, YES), the IOP 711 performs another process. If the active IO counter 826 has reached N (step 1402, NO), the IOP 711 performs another process.

If the CHU transmission queue 828 is not empty (step 1405, NO), the IOP 711 enqueues START_IO into the CHU transmission queue 828 (step 1408). If there is no free space in the IOP reception buffer area 836 (step 1406, NO), the IOP 711 performs the processing of step 1408.

15 to 20 are flowcharts showing examples of processing performed by the CHU 712. 15 to 20, “IDLE” indicates that the CHU 712 is in an idling state.

First, the processing of FIG. 15 will be described. When the CHU 712 receives START_IO from the IOP 711 (step 1501), the CHU 712 transmits an ASYNC_STS related to the same IO to the IOP 711 and checks whether or not it is waiting for a response (step 1502). If not waiting for a response (step 1502, NO), the CHU 712 checks the connect IO counter 838 (step 1503).

If the connect IO counter 838 is smaller than N (step 1503, YES), the CHU 712 adds 1 to the connect IO counter 838 (step 1404) and checks whether the IOC transmission queue 840 is empty (step 1505). If the IOC transmission queue 840 is empty (step 1505, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 842 of the IOC 702 (step 1506).

If there is an empty space in the CHU reception buffer area 842 (step 1506, YES), the CHU 712 transmits START_IO to the IOC 702 (step 1507).

On the other hand, if the IOC transmission queue 840 is not empty (step 1505, NO), the CHU 712 enqueues START_IO into the IOC transmission queue 840 (step 1509). If there is no free space in the CHU reception buffer area 842 (step 1506, NO), the CHU 712 performs the processing of step 1509.

If it is waiting for a response to ASYNC_STS (step 1502, YES), the CHU 712 cancels the response waiting (step 1508) and performs the processing from step 1505 onward.

If the connect IO counter 838 is greater than or equal to N (step 1503, NO), the CHU 712 checks whether or not the IOP transmission queue 835 is empty (step 1510). If the IOP transmission queue 835 is empty (step 1510, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 827 of the IOP 711 (step 1511).

If there is an empty space in the CHU reception buffer area 827 (step 1511, YES), the CHU 712 transmits BUSY to the IOP 711 (step 1512). If the IOP transmission queue 835 is not empty (NO in step 1510), the CHU 712 enqueues BUSY in the IOP transmission queue 835 (step 1513). If there is no free space in the CHU reception buffer area 827 (step 1511, NO), the CHU 712 performs the process of step 1513.

Next, the process of FIG. 16 will be described. When the CHU 712 receives OPTERM_STS or BUSY_STS from the IOC 702 (step 1601), the CHU 712 checks whether or not the IOP transmission queue 835 is empty (step 1602). If the IOP transmission queue 835 is empty (step 1602, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 827 of the IOP 711 (step 1603).

If there is an empty space in the CHU reception buffer area 827 (step 1603, YES), the CHU 712 transmits the received notification to the IOP 711 (step 1604). If the IOP transmission queue 835 is not empty (step 1602, NO), the CHU 712 enqueues the received notification in the IOP transmission queue 835 (step 1605). If there is no free space in the CHU reception buffer area 827 (step 1603, NO), the CHU 712 performs the process of step 1605.

Next, the process of FIG. 17 will be described. When the CHU 712 receives the ASYNC_STS from the IOC 702 (step 1701), the CHU 712 transmits a START_IO related to the same IO to the IOC 702 to check whether it is waiting for a response (step 1702). If not waiting for a response (step 1702, NO), the CHU 712 checks the connect IO counter 838 (step 1703).

If the connect IO counter 838 is smaller than M (step 1703, YES), the CHU 712 adds 1 to the connect IO counter 838 (step 1704) and checks whether the IOP transmission queue 835 is empty (step 1705). If the IOP transmission queue 835 is empty (step 1705, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 827 of the IOP 711 (step 1706).

If there is an empty space in the CHU reception buffer area 827 (step 1706, YES), the CHU 712 transmits ASYNC_STS to the IOP 711 (step 1707). If the IOP transmission queue 835 is not empty (step 1705, NO), the CHU 712 enqueues ASYNC_STS into the IOP transmission queue 835 (step 1709). If there is no free space in the CHU reception buffer area 827 (step 1706, NO), the CHU 712 performs the processing of step 1709.

If waiting for a response to START_IO (step 1702, YES), the CHU 712 discards the received ASYNC_STS and cancels waiting for a response to the ASYNC_STS (step 1708).

If the connect IO counter 838 has reached M (step 1703, NO), the CHU 712 checks whether or not the IOC transmission queue 840 is empty (step 1710). If the IOC transmission queue 840 is empty (step 1710, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 842 of the IOC 702 (step 1711).

If there is an empty space in the CHU reception buffer area 842 (step 1711, YES), the CHU 712 transmits BUSY to the IOC 702 (step 1712). This BUSY is a busy notification indicating that the ASYNC_STS cannot be accepted because a new ASYNC_STS is received from the IOC 702 when the connect IO counter 838 is equal to or greater than M. The CHU 712 suppresses transmission of ASYNC_STS to the IOP 711 by transmitting BUSY to the IOC 702.

On the other hand, if the IOC transmission queue 840 is not empty (NO at step 1710), the CHU 712 enqueues BUSY into the IOC transmission queue 840 (step 1713). If there is no free space in the CHU reception buffer area 842 (step 1711, NO), the CHU 712 performs the process of step 1713.

Next, the process of FIG. 18 will be described. When the CHU 712 receives ACC_STS from the IOP 711 (step 1801), the CHU 712 checks whether or not the IOC transmission queue 840 is empty (step 1802). If the IOC transmission queue 840 is empty (step 1802, YES), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 842 of the IOC 702 (step 1803).

If there is an empty space in the CHU reception buffer area 842 (step 1803, YES), the CHU 712 transmits ACC_STS to the IOC 702 (step 1804) and subtracts 1 from the connect IO counter 838 (step 1805).

On the other hand, if the IOC transmission queue 840 is not empty (step 1802, NO), the CHU 712 enqueues ACC_STS into the IOC transmission queue 840 (step 1806). If there is no free space in the CHU reception buffer area 842 (step 1803, NO), the CHU 712 performs the process of step 1806.

Next, the process of FIG. 19 will be described. The CHU 712 checks whether or not the IOC transmission queue 840 is empty at a predetermined timing (step 1901). If the IOC transmission queue 840 is not empty (NO in step 1901), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 842 of the IOC 702 (step 1902).

If there is an empty space in the CHU reception buffer area 842 (step 1902, YES), the CHU 712 dequeues the top information from the IOC transmission queue 840 (step 1903) and checks whether the information is START_IO (step 1904). .

If the head information is START_IO (step 1904, YES), the CHU 712 transmits the START_IO to the IOC 702 (step 1905).

If the head information is not START_IO (step 1904, NO), the CHU 712 checks whether the information is ACC_STS (step 1906). If the head information is ACC_STS (step 1906, YES), the CHU 712 subtracts 1 from the connect IO counter 838 (step 1907) and transmits the ACC_STS to the IOC 702 (step 1908).

If the head information is not ACC_STS but BUSY (step 1906, NO), the CHU 712 transmits the BUSY to the IOC 702 (step 1909).

On the other hand, if the IOC transmission queue 840 is empty (step 1901, YES), the CHU 712 performs another process. If there is no free space in the CHU reception buffer area 842 (step 1902, NO), the CHU 712 performs another process.

Next, the process of FIG. 20 will be described. The CHU 712 checks whether or not the IOP transmission queue 835 is empty at a predetermined timing (step 2001). If the IOP transmission queue 835 is not empty (step 2001, NO), the CHU 712 checks whether or not there is an empty space in the CHU reception buffer area 827 of the IOP 711 (step 2002).

If there is a free space in the CHU reception buffer area 827 (step 2002, YES), the CHU 712 dequeues the head information from the IOP transmission queue 835 (step 2003). Then, the CHU 712 checks whether or not the information is one of OPTERM_STS or BUSY_STS (step 2004).

If the head information is one of OPTERM_STS or BUSY_STS (step 2004, YES), the CHU 712 transmits the notification to the IOP 711 (step 2005).

If the top information is neither OPTERM_STS nor BUSY_STS (step 2004, NO), the CHU 712 checks whether the information is ASYNC_STS (step 2006). If the head information is ASYNC_STS (step 2006, YES), the CHU 712 transmits the ASYNC_STS to the IOP 711 (step 2007).

If the head information is not ASYNC_STS but BUSY (step 2006, NO), the CHU 712 transmits the BUSY to the IOP 711 (step 2008).

On the other hand, if the IOP transmission queue 835 is empty (step 2001, YES), the CHU 712 performs another process. If there is no free space in the CHU reception buffer area 827 (step 2002, NO), the CHU 712 performs another process.

9 to 20 are merely examples, and some processes may be omitted or changed according to the configuration and conditions of the information processing system, and the order of steps may be changed.

For example, in FIG. 9, the counter addition processing in step 903 may be moved after step 906 or step 908. In FIG. 10, the counter subtraction process in step 1006 may be moved before or after step 1004. In FIG. 11, the counter addition process in step 1108 may be moved after step 1109. In FIG. 12, the counter subtraction process in step 1202 may be moved after step 1203.

In FIG. 13, the counter subtraction process in step 1306 may be moved after step 1307, or may be moved after step 1309 or step 1310. In FIG. 14, the counter addition process in step 1404 may be moved before step 1403 or may be moved after step 1407 or step 1408.

In FIG. 17, the counter addition process in step 1704 may be moved after step 1707 or step 1709. In FIG. 18, the counter subtraction process in step 1805 may be moved before step 1804. In FIG. 19, the counter subtraction process in step 1907 may be moved after step 1908.

Further, in step 1503 of FIG. 15, an integer greater than N and equal to or less than M may be used instead of the threshold value N compared with the connect IO counter 838.

21 to 26 show the input / output control sequence of FIG. 7 in the information processing system of FIG. However, in FIGS. 21 to 26, IO703-1 to IO703-5 of FIG. 7 are used instead of IO804-1 to IO804-9 of FIG. The order of procedures in FIGS. 21 to 26 may be different from the order of steps in the flowcharts of FIGS. 9 to 20.

The first upper limit value N is 3, and the second upper limit value M is 4. Therefore, each of the CHU reception buffer area 827 and the IOP reception buffer area 836 has two reception buffers, and each of the IOC reception buffer area 839 and the CHU reception buffer area 842 has three reception buffers.

First, the sequence of FIGS. 21 and 22 will be described. Procedures 2102 to 2113 correspond to the process of FIG. 9, and procedures 2114 to 2115 correspond to the process of FIG. Procedures 2122 to 2128 correspond to the process of FIG. 17, and procedures 2129 to 2140 correspond to the process of FIG.

The control processor 821 of the IOP 711 sets an initial value 0 to the active IO counter 826 (procedure 2101).

Next, when an IO processing instruction targeted for IO # A is received from the CPU 801 (procedure 2102), the control processor 821 checks the active IO counter 826 (procedure 2103). Since the active IO counter 826 is 0 and smaller than N, the control processor 821 adds 1 to the active IO counter 826 (procedure 2104) and checks the CHU transmission queue 828 (procedure 2105).

Since the CHU transmission queue 828 is empty, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2107). Since there are two empty reception buffers in the IOP reception buffer area 836, the control processor 821 transmits START_IO to the CHU 712 (procedure 2108).

The control processor 831 of the CHU 712 sets an initial value 0 to the connect IO counter 838 (procedure 2121).

The IOC 702 checks the IOC reception buffer area 839 of the CHU 712 (procedure 2151). Since there are three empty reception buffers in the IOC reception buffer area 839, the IOC 702 transmits ASYNC_STS indicating the state of IO # B to the CHU 712 (procedure 2152).

Next, the control processor 831 of the CHU 712 refers to the IOC reception buffer area 839 and detects reception of ASYNC_STS related to IO # B (procedure 2122). Therefore, the control processor 831 checks whether it is waiting for a response to START_IO related to IO # B (step 2123).

Since it is not waiting for a response, the control processor 831 checks the connect IO counter 838 (procedure 2124). Since the connect IO counter 838 is 0 and smaller than M, the control processor 831 adds 1 to the connect IO counter 838 (procedure 2125) and checks the IOP transmission queue 835 (procedure 2126).

Since the IOP transmission queue 835 is empty, the control processor 831 checks the CHU reception buffer area 827 of the IOP 711 (procedure 2127). Since there are two empty reception buffers in the CHU reception buffer area 827, the control processor 831 transmits ASYNC_STS to the IOP 711 (step 2128).

Next, the control processor 831 refers to the IOP reception buffer area 836 and detects reception of START_IO related to IO # A (step 2129). Therefore, the control processor 831 checks whether or not it is waiting for a response to ASYNC_STS regarding IO # A (step 2130).

Since it is not waiting for a response, the control processor 831 checks the connect IO counter 838 (procedure 2131). Since the connect IO counter 838 is 1 and smaller than N, the control processor 831 adds 1 to the connect IO counter 838 (procedure 2132) and checks the IOC transmission queue 840 (procedure 2133).

Since the IOC transmission queue 840 is empty, the control processor 831 checks the CHU reception buffer area 842 of the IOC 702 (procedure 2134). Since there are three empty reception buffers in the CHU reception buffer area 842, the control processor 831 transmits START_IO to the IOC 702 (procedure 2135).

When the control processor 821 of the IOP 711 receives an IO processing instruction for IO # B from the CPU 801 (procedure 2106), it checks the active IO counter 826 (procedure 2109). Since the active IO counter 826 is 1 and smaller than N, the control processor 821 adds 1 to the active IO counter 826 (procedure 2110) and checks the CHU transmission queue 828 (procedure 2111).

Since the CHU transmission queue 828 is empty, the control processor 821 checks the IOP reception buffer area 836 (procedure 2112). Since there are two empty reception buffers in the IOP reception buffer area 836, the control processor 821 transmits START_IO to the CHU 712 (procedure 2113).

Next, the control processor 821 refers to the CHU reception buffer area 827 and detects reception of ASYNC_STS related to IO # B (procedure 2114). Therefore, the control processor 821 checks whether or not the input / output processing related to IO # B is being activated (procedure 2115). Since the input / output processing related to IO # B is being activated, the control processor 821 discards ASYNC_STS.

The IOC 702 checks the IOC reception buffer area 839 of the CHU 712 (procedure 2153). Since there are three empty reception buffers in the IOC reception buffer area 839, the IOC 702 transmits ASYNC_STS indicating the state of IO # C to the CHU 712 (procedure 2154).

The control processor 831 of the CHU 712 refers to the IOP reception buffer area 836 and detects reception of START_IO related to IO # B (step 2136). Therefore, the control processor 831 checks whether or not it is waiting for a response to ASYNC_STS regarding IO # B (step 2137).

Since it is waiting for a response, the control processor 831 releases the response wait and checks the IOC transmission queue 840 (step 2138). Since the IOC transmission queue 840 is empty, the control processor 831 checks the CHU reception buffer area 842 of the IOC 702 (procedure 2139). Since there are two empty reception buffers in the CHU reception buffer area 842, the control processor 831 transmits START_IO to the IOC 702 (procedure 2140).

Meanwhile, the IOC 702 checks the IOC reception buffer area 839 of the CHU 712 (procedure 2155). Since there are two empty reception buffers in the IOC reception buffer area 839, the IOC 702 transmits ASYNC_STS indicating the state of IO # D to the CHU 712 (procedure 2156).

Next, the sequence of FIG. 23 will be described. Procedures 2201 to 2214 correspond to the processing of FIG. 17, and procedures 2221 to 2226 correspond to the processing of FIG.

The control processor 831 of the CHU 712 refers to the IOC reception buffer area 839 and detects reception of ASYNC_STS related to IO # C (procedure 2201). Therefore, the control processor 831 checks whether it is waiting for a response to START_IO related to IO # C (step 2202).

Since it is not waiting for a response, the control processor 831 checks the connect IO counter 838 (procedure 2203). Since the connect IO counter 838 is 2 and smaller than M, the control processor 831 adds 1 to the connect IO counter 838 (procedure 2204) and checks the IOP transmission queue 835 (procedure 2205).

Since the IOP transmission queue 835 is empty, the control processor 831 checks the CHU reception buffer area 827 of the IOP 711 (procedure 2206). Since there are two empty reception buffers in the CHU reception buffer area 827, the control processor 831 transmits ASYNC_STS to the IOP 711 (step 2207).

Next, the control processor 831 refers to the IOC reception buffer area 839 and detects reception of ASYNC_STS related to IO # D (procedure 2208). Therefore, the control processor 831 checks whether it is waiting for a response to START_IO related to IO # D (step 2209).

Since it is not waiting for a response, the control processor 831 checks the connect IO counter 838 (procedure 2210). Since the connect IO counter 838 is 3 and smaller than M, the control processor 831 adds 1 to the connect IO counter 838 (procedure 2211) and checks the IOP transmission queue 835 (procedure 2212).

Since the IOP transmission queue 835 is empty, the control processor 831 checks the CHU reception buffer area 827 of the IOP 711 (procedure 2213). Since there is one empty reception buffer in the CHU reception buffer area 827, the control processor 831 transmits ASYNC_STS to the IOP 711 (step 2214).

On the other hand, when the control processor 821 of the IOP 711 receives an IO processing instruction for IO # E from the CPU 801 (procedure 2221), it checks the active IO counter 826 (procedure 2222). Since the active IO counter 826 is 2 and smaller than N, the control processor 821 adds 1 to the active IO counter 826 (procedure 2223) and checks the CHU transmission queue 828 (procedure 2224).

Since the CHU transmission queue 828 is empty, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2225). Since there are two empty reception buffers in the IOP reception buffer area 836, the control processor 821 transmits START_IO to the CHU 712 (step 2226).

Next, the sequence of FIG. 24 will be described. Procedures 2301 to 2310 correspond to the process of FIG. 11, and procedures 2311 to 2313 correspond to the process of FIG. Procedures 2321 to 2325 correspond to the process of FIG. 15, and procedures 2326 to 2333 correspond to the process of FIG.

The control processor 821 of the IOP 711 refers to the CHU reception buffer area 827 and detects reception of ASYNC_STS related to IO # C (procedure 2301). Accordingly, the control processor 821 checks whether or not the input / output processing related to IO # C is being activated (procedure 2302).

Since the input / output processing related to IO # C is not activated, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2303). Since there is one empty reception buffer in the IOP reception buffer area 836, the control processor 821 transmits ACC_STS for ASYNC_STS to the CHU 712 (procedure 2304). Then, the control processor 821 transmits an asynchronous interrupt indicating the notification content of ASYNC_STS to the CPU 801 (procedure 2305).

On the other hand, the control processor 831 of the CHU 712 refers to the IOP reception buffer area 836 and detects reception of START_IO related to IO # E (procedure 2321). Therefore, the control processor 831 checks whether or not it is waiting for a response to ASYNC_STS related to IO # E (step 2322).

Since it is not waiting for a response, the control processor 831 checks the connect IO counter 838 (procedure 2323). Since the connect IO counter 838 is 4 and is equal to or greater than N, the control processor 831 checks whether or not there is a free space in the CHU reception buffer area 827 of the IOP 711 (step 2324).

Since there are two empty reception buffers in the CHU reception buffer area 827, the control processor 831 transmits BUSY indicating that START_IO related to IO # E cannot be accepted to the IOP 711 (step 2325).

Meanwhile, the control processor 821 of the IOP 711 refers to the CHU reception buffer area 827 and detects reception of ASYNC_STS related to IO # D (procedure 2306). Therefore, the control processor 821 checks whether the input / output processing relating to IO # D is being activated (step 2307).

Since the input / output processing related to IO # D is not activated, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2308). Since there is one empty reception buffer in the IOP reception buffer area 836, the control processor 821 transmits ACC_STS for ASYNC_STS to the CHU 712 (step 2309). Then, the control processor 821 transmits an asynchronous interrupt indicating the notification content of ASYNC_STS to the CPU 801 (procedure 2310).

Next, the control processor 821 refers to the CHU reception buffer area 827 and detects the reception of BUSY related to IO # E (procedure 2311). Therefore, the control processor 821 enqueues START_IO related to IO # E into the execution queue 814 of the HSA 813 (procedure 2312), and subtracts 1 from the active IO counter 826 (procedure 2313).

Meanwhile, the IOC 702 refers to the CHU reception buffer area 842 and detects reception of START_IO related to IO # A (procedure 2341). Therefore, the IOC 702 transmits the START_IO to the IO # A.

The control processor 831 of the CHU 712 refers to the IOP reception buffer area 836 and detects reception of ACC_STS related to IO # C (procedure 2326). Therefore, the control processor 831 subtracts 1 from the connect IO counter 838 (procedure 2327), and checks the CHU reception buffer area 842 of the IOC 702 (procedure 2328). Since there are two empty reception buffers in the CHU reception buffer area 842, the control processor 831 transmits ACC_STS to the IOC 702 (step 2329).

Next, the IOC 702 refers to the CHU reception buffer area 842 to detect reception of START_IO related to IO # B (procedure 2342). Therefore, the IOC 702 transmits the START_IO to the IO # B.

Next, the control processor 831 refers to the IOP reception buffer area 836 and detects reception of ACC_STS related to IO # D (procedure 2330). Therefore, the control processor 831 subtracts 1 from the connect IO counter 838 (procedure 2331), and checks the CHU reception buffer area 842 of the IOC 702 (procedure 2332). Since there are two empty reception buffers in the CHU reception buffer area 842, the control processor 831 transmits ACC_STS to the IOC 702 (procedure 2333).

Next, the sequence of FIGS. 25 and 26 will be described. Procedures 2411 to 2416 correspond to the process of FIG. 16, procedures 2417 to 2424 correspond to the process of FIG. 18, and procedures 2431 to 2440 correspond to the process of FIG.

The IOC 702 checks the IOC reception buffer area 839 of the CHU 712 (procedure 2401). Since there are three empty reception buffers in the IOC reception buffer area 839, the IOC 702 transmits OPTERM_STS indicating the result of IO # A input / output processing to the CHU 712 (procedure 2402).

Next, the control processor 831 of the CHU 712 refers to the IOC reception buffer area 839 and detects reception of OPTERM_STS related to IO # A (procedure 2411). Therefore, the control processor 831 checks the CHU reception buffer area 827 of the IOP 711 (procedure 2412). Since there are two free reception buffers in the CHU reception buffer area 827, the control processor 831 transmits OPTERM_STS to the IOP 711 (step 2413).

Since the IOC 702 receives the START_IO related to the IO # B after transmitting the ASYNC_STS related to the IO # B, the IOC 702 cannot start the input / output processing of the IO # B. Therefore, the IOC 702 checks the IOC reception buffer area 839 of the CHU 712 in order to transmit BUSY_STS as a response to START_IO (procedure 2403). Since there are three empty reception buffers in the IOC reception buffer area 839, BUSY_STS related to IO # B is transmitted to the CHU 712 (procedure 2404).

Next, the control processor 831 of the CHU 712 refers to the IOC reception buffer area 839 and detects reception of BUSY_STS related to IO # B (procedure 2414). Therefore, the control processor 831 checks the CHU reception buffer area 827 of the IOP 711 (procedure 2415). Since there is one empty reception buffer in the CHU reception buffer area 827, the control processor 831 transmits BUSY_STS to the IOP 711 (step 2416).

The IOC 702 refers to the CHU reception buffer area 842 to detect reception of ACC_STS related to IO # C (procedure 2405). Next, the IOC 702 refers to the CHU reception buffer area 842 and detects reception of ACC_STS related to IO # D (procedure 2406).

Meanwhile, the control processor 821 of the IOP 711 refers to the CHU reception buffer area 827 and detects reception of OPTERM_STS related to IO # A (procedure 2431). Therefore, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2432).

Since there are two empty reception buffers in the IOP reception buffer area 836, the control processor 821 transmits ACC_STS for OPTERM_STS to the CHU 712 (procedure 2433). Then, the control processor 821 transmits an IO processing result indicating the notification contents of OPTERM_STS to the CPU 801 (procedure 2434), and subtracts 1 from the active IO counter 826 (procedure 2435).

The control processor 831 of the CHU 712 refers to the IOP reception buffer area 836 and detects reception of ACC_STS related to IO # A (procedure 2417). Therefore, the control processor 831 subtracts 1 from the connect IO counter 838 (procedure 2418), and checks the CHU reception buffer area 842 of the IOC 702 (procedure 2419). Since there are three empty reception buffers in the CHU reception buffer area 842, the control processor 831 transmits ACC_STS to the IOC 702 (procedure 2420).

Next, the IOC 702 refers to the CHU reception buffer area 842 and detects reception of ACC_STS related to IO # A (procedure 2407).

The control processor 821 of the IOP 711 refers to the CHU reception buffer area 827 and detects reception of BUSY_STS related to IO # B (procedure 2436). Therefore, the control processor 821 checks the IOP reception buffer area 836 of the CHU 712 (procedure 2437).

Since there are two empty reception buffers in the IOP reception buffer area 836, the control processor 821 transmits ACC_STS for BUSY_STS to the CHU 712 (procedure 2438). Then, the control processor 821 transmits a busy notification indicating the notification content of BUSY_STS to the CPU 801 (procedure 2439), and subtracts 1 from the active IO counter 826 (procedure 2440).

The control processor 831 of the CHU 712 refers to the IOP reception buffer area 836 and detects reception of ACC_STS related to IO # B (procedure 2421). Therefore, the control processor 831 subtracts 1 from the connect IO counter 838 (procedure 2422), and checks the CHU reception buffer area 842 of the IOC 702 (procedure 2423). Since there are three free reception buffers in the CHU reception buffer area 842, the control processor 831 transmits ACC_STS to the IOC 702 (step 2424).

Next, the IOC 702 refers to the CHU reception buffer area 842 to detect reception of ACC_STS related to IO # B (procedure 2408).

Next, an example of input / output control for IO804-1 to IO804-9 (IO # 01 to IO # 09) in FIG. 8 will be described. In this example, it is assumed that the CPU 801 receives an asynchronous interrupt from IO # 02 and IO # 05 to IO # 09 at the timing when the IO processing instruction for IO # 01 to IO # 04 is issued.

(1) The IOP 711 receives an IO processing instruction related to IO # 01 to IO # 04 from the CPU 801, and performs the following processing corresponding to FIG.

When the IOP 711 receives an IO processing instruction related to IO # 01 to IO # 03, since the active IO counter 826 is smaller than N, the IOP 711 adds 1 to the active IO counter 826.

When the IOP 711 receives an IO processing instruction related to IO # 01 and IO # 02, the IOP 711 transmits START_IO to the CHU 712 because there is an empty reception buffer in the IOP reception buffer area 836 of the CHU 712.

When the IOP 711 receives an IO processing instruction related to IO # 03, the IOP 711 enqueues START_IO into the CHU transmission queue 828 because there is no empty reception buffer in the IOP reception buffer area 836.

The IOP 711 enqueues START_IO into the execution queue 814 of the HSA 813 when the I / O processing instruction related to the IO # 04 is received because the active IO counter 826 reaches N.

At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 0, and the active IO counter 826 is 3.

(2) The IOC 702 receives asynchronous interrupts from IO # 02 and IO # 05 to IO # 09, respectively. The IOC 702 transmits ASYNC_STS to the CHU 712 for three asynchronous interrupts corresponding to the number of reception buffers included in the IOC reception buffer area 839 of the CHU 712 among the six asynchronous interrupts received. In this case, the IOC 702 transmits ASYNC_STS to the CHU 712 for the three asynchronous interrupts from IO # 02, IO # 05, and IO # 06.
At this time, the number of empty reception buffers in the IOC reception buffer area 839 is zero.

(3) The CHU 712 performs the following processing corresponding to FIGS. 15 and 17.
When receiving the START_IO related to IO # 01 from the IOP 711, the CHU 712 adds 1 to the connect IO counter 838 because the connect IO counter 838 is smaller than N, and transmits the START_IO to the IOC 702. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 1, and the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 2.

When the CHU 712 receives the ASYNC_STS related to IO # 02 from the IOC 702, the CHIO 712 adds 1 to the connect IO counter 838 because the connect IO counter 838 is smaller than M, and transmits the ASYNC_STS to the IOP 711. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 1, and the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 1.

When the CHU 712 receives the START_IO related to the IO # 02 from the IOP 711, the CHU 712 transmits the ASYNC_STS related to the same IO to the IOP 711 and waits for a response. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, and the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 1.

When the CHU 712 receives the ASYNC_STS related to IO # 05 from the IOC 702, the CHIO 712 adds 1 to the connect IO counter 838 because the connect IO counter 838 is smaller than M, and transmits the ASYNC_STS to the IOP 711. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 2, and the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 0.

When receiving the ASYNC_STS related to IO # 06 from the IOC 702, the CHU 712 adds 1 to the connect IO counter 838 because the connect IO counter 838 is smaller than M. However, since there is no empty reception buffer in the CHU reception buffer area 827 of the IOP 711, the CHU 712 enqueues ASYNC_STS related to IO # 06 into the IOP transmission queue 835.

At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 3, and the connect IO counter 838 is 4.

(4) The IOP 711 performs the following processing corresponding to FIG.
Since the IOP 711 has a free reception buffer in the IOP reception buffer area 836 of the CHU 712, the IOP 711 transmits START_IO related to IO # 03 to the CHU 712. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 1.

Also, the IOP 711 receives ASYNC_STS related to IO # 02 and IO # 05, and performs the following processing corresponding to FIG.

When the IOP 711 receives the ASYNC_STS related to the IO # 02, the IOP 711 discards the ASYNC_STS because the input / output processing related to the same IO is being activated. At this time, the number of empty reception buffers in the CHU reception buffer area 827 is 1.

When the IOP 711 receives ASYNC_STS related to IO # 05, the CHU transmission queue 828 is empty, and there is an empty reception buffer in the IOP reception buffer area 836 of the CHU 712. Therefore, the IOP 711 transmits ACC_STS to the CHU 712 and transmits an asynchronous interrupt to the CPU 801.

At this time, the number of empty reception buffers in the CHU reception buffer area 827 is 2, the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 0, and the active IO counter 826 is 3.

(5) The IOC 702 transmits an ASYNC_STS regarding IO # 07, IO # 08, and IO # 09 to the CHU 712 because an empty reception buffer has been created in the IOC reception buffer area 839 of the CHU 712. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is zero.

The IOC 702 receives START_IO related to IO # 01 and IO # 02, and transmits these START_IO to IO # 01 and IO # 02. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is three.

(6) The CHU 712 performs the following processing corresponding to FIG.
Since the CHU 712 has an empty reception buffer in the CHU reception buffer area 827 of the IOP 712, the CHU 712 transmits ASYNC_STS related to IO # 06 to the IOP 711. At this time, the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 712 is 1.

Further, the CHU 712 performs the following processing corresponding to FIG. 15, FIG. 17, and FIG.
When receiving START_IO related to IO # 03 from the IOP 711, the CHU 712 transmits BUSY to the IOP 711 because the connect IO counter 838 has reached N. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 1, and the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 0.

When the CHU 712 receives ASYNC_STS related to IO # 07, IO # 08, and IO # 09 from the IOC 702, the connect IO counter 838 reaches M, and the CHU reception buffer area 842 of the IOC 702 has an empty reception buffer. Therefore, the CHU 712 transmits BUSY to the IOC 702. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 3, and the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 0.

When receiving the ACC_STS related to IO # 05 from the IOP 711, the CHU 712 enqueues the ACC_STS in the IOC transmission queue 840 because there is no empty reception buffer in the CHU reception buffer area 842 of the IOC 702. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, and the connect IO counter 838 is 4.

(7) The IOP 711 performs the following processing corresponding to FIG.
When the IOP 711 receives ASYNC_STS related to IO # 06, the CHU transmission queue 828 is empty, and there is an empty reception buffer in the IOP reception buffer area 836 of the CHU 712. Therefore, the IOP 711 transmits ACC_STS to the CHU 712 and transmits an asynchronous interrupt to the CPU 801. At this time, the number of empty reception buffers in the CHU reception buffer area 827 is 1, and the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 1.

Further, the IOP 711 performs the following processing corresponding to FIG.
When the IOP 711 receives BUSY from the CHU 712 for the START_IO related to the IO # 03, the IOP 711 subtracts 1 from the active IO counter 826 and enqueues the START_IO into the execution queue 814 of the HSA 813. At this time, the number of empty reception buffers in the CHU reception buffer area 827 is two.

Further, the IOP 711 performs the following processing corresponding to FIG.
START_IO related to IO # 04 is enqueued in the execution queue 814, the active IO counter 826 is smaller than N, and there is an empty reception buffer in the IOP reception buffer area 836 of the CHU 712. Therefore, the IOP 711 adds 1 to the active IO counter 826 and transmits START_IO related to IO # 04 to the CHU 712.

At this time, the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 0 and the active IO counter 826 is 3.

(8) The IOC 702 receives BUSY from the CHU 712 to the ASYNC_STS related to the IO # 07, IO # 08, and IO # 09, and notifies the IO # 07, IO # 08, Send to IO # 09.

Also, the IOC 702 receives the processing results from the IO # 01 and the IO # 02 and transmits OPTERM_STS regarding the IO # 01 and the IO # 02 to the CHU 712. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is 3, and the number of empty reception buffers in the IOC reception buffer area 839 of the CHU 712 is 1.

(9) The CHU 712 performs the following processing corresponding to FIG.
Since the CHU 712 has an empty reception buffer in the CHU reception buffer area 842 of the IOC 702, the CHU 712 subtracts 1 from the connect IO counter 838 and transmits ACC_STS related to IO # 05 to the IOC 702. At this time, the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is two.

Further, the CHU 712 performs the following processing corresponding to FIG. 18, FIG. 16, and FIG.
When the CHU 712 receives the ACC_STS related to the IO # 06 from the IOP 711, the CHU 712 transmits the ACC_STS to the IOC 702 and subtracts 1 from the connect IO counter 838. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 1, the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 1, and the connect IO counter 838 is 2.

When the CHU 712 receives the OPTERM_STS related to the IO # 01 and IO # 02 from the IOC 702, the CHU712 transmits the OPTERM_STS to the IOP711. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 3, and the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 0.

When receiving the START_IO related to IO # 04 from the IOP 711, the CHU 712 adds 1 to the connect IO counter 838 because the connect IO counter 838 is smaller than N. The CHU 712 transmits START_IO related to IO # 04 to the IOC 702 because there is an empty reception buffer in the CHU reception buffer area 842 of the IOC 702.

At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 0, and the connect IO counter 838 is 3.

(10) The IOP 711 performs the following processing corresponding to FIG.
When the IOP 711 receives OPTERM_STS related to IO # 01 and IO # 02, the CHU transmission queue 828 is empty, and the IOP reception buffer area 836 of the CHU 712 has an empty reception buffer. Therefore, the IOP 711 transmits ACC_STS for the received OPTERM_STS to the CHU 712, transmits the IO processing result indicated by the received OPTERM_STS to the CPU 801, and subtracts 1 from the active IO counter 826.

At this time, the number of empty reception buffers in the CHU reception buffer area 827 is 2, the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 0, and the active IO counter 826 is 1.

Further, the IOP 711 performs the following processing corresponding to FIG.
Since START_IO related to IO # 03 is enqueued in the execution queue 814 and the active IO counter 826 is smaller than N, the IOP 711 adds 1 to the active IO counter 826. However, since there is no empty reception buffer in the IOP reception buffer area 836 of the CHU 712, the IOP 711 enqueues START_IO related to IO # 03 to the CHU transmission queue 828. At this point, the active IO counter 826 is 2.

(11) The IOC 702 receives the ACC_STS related to the IO # 05 and the IO # 06, and transmits a notification indicating that the asynchronous interrupt is accepted to the IO # 05 and the IO # 06.

Further, the IOC 702 receives the START_IO related to the IO # 04 and transmits the START_IO to the IO # 04. Then, the IOC 702 receives the processing result from the IO # 04 and transmits OPTERM_STS related to the IO # 04 to the CHU 712. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is 3, and the number of empty reception buffers in the IOC reception buffer area 839 of the CHU 712 is 2.

(12) The CHU 712 performs the following processing corresponding to FIG.
When the CHU 712 receives the ACC_STS related to IO # 01 and IO # 02 from the IOP 711, the CHU 712 transmits the received ACC_STS to the IOC 702 and subtracts 1 from the connect IO counter 838. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, and the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 1.

Further, the CHU 712 performs the following processing corresponding to FIG.
When the CHU 712 receives the OPTERM_STS related to the IO # 04 from the IOC 702, the CHU 712 transmits the OPTERM_STS to the IOP 711. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 3, the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 1, and the connect IO counter 838 is 1.

(13) The IOP 711 performs the following processing corresponding to FIG.
Since the IOP 711 has a free reception buffer in the IOP reception buffer area 836 of the CHU 712, the IOP 711 transmits START_IO related to IO # 03 to the CHU 712. At this time, the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 1.

The IOP 711 performs the following processing corresponding to FIG.
When the IOP 711 receives OPTERM_STS related to IO # 04, the CHU transmission queue 828 is empty, and the IOP reception buffer area 836 of the CHU 712 has an empty reception buffer. Therefore, the IOP 711 transmits ACC_STS regarding IO # 04 to the CHU 712, transmits the IO processing result regarding IO # 04 to the CPU 801, and subtracts 1 from the active IO counter 826.

(14) The IOC 702 receives the ACC_STS related to the IO # 01 and the IO # 02, and transmits a notification indicating that the processing result is accepted to the IO # 01 and the IO # 02. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is three.

(15) The CHU 712 performs the following processing corresponding to FIG.
When the CHU 712 receives START_IO related to IO # 03 from the IOP 711, the connect IO counter 838 is smaller than N, and thus 1 is added to the connect IO counter 838. The CHU 712 transmits START_IO related to IO # 03 to the IOC 702 because there is an empty reception buffer in the CHU reception buffer area 842 of the IOC 702.

At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 1, and the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is two.

Further, the CHU 712 performs the following processing corresponding to FIG.
When the CHU 712 receives the ACC_STS related to the IO # 04 from the IOP 711, the CHU 712 transmits the ACC_STS to the IOC 702 and subtracts 1 from the connect IO counter 838. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 1, and the connect IO counter 838 is 1.

(16) The IOC 702 receives START_IO related to IO # 03 and transmits the START_IO to IO # 03. Then, the IOC 702 receives the processing result from the IO # 03 and transmits OPTERM_STS related to the IO # 03 to the CHU 712. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is two, and the number of empty reception buffers in the IOC reception buffer area 839 of the CHU 712 is two.

Also, the IOC 702 receives the ACC_STS related to the IO # 04 and transmits a notification indicating that the processing result has been accepted to the IO # 04. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is three.

(17) The CHU 712 performs the following processing corresponding to FIG.
When the CHU 712 receives OPTERM_STS related to IO # 03 from the IOC 702, the CHU 712 transmits the OPTERM_STS to the IOP 711. At this time, the number of empty reception buffers in the IOC reception buffer area 839 is 3, the number of empty reception buffers in the CHU reception buffer area 827 of the IOP 711 is 1, and the connect IO counter 838 is 1.

(18) The IOP 711 performs the following processing corresponding to FIG.
When the IOP 711 receives OPTERM_STS related to IO # 03, the CHU transmission queue 828 is empty, and there is an empty reception buffer in the IOP reception buffer area 836 of the CHU 712. Therefore, the IOP 711 transmits ACC_STS related to IO # 03 to the CHU 712, transmits the IO processing result related to IO # 03 to the CPU 801, and subtracts 1 from the active IO counter 826.

At this time, the number of empty reception buffers in the CHU reception buffer area 827 is 2, the number of empty reception buffers in the IOP reception buffer area 836 of the CHU 712 is 1, and the active IO counter 826 is 0.

(19) When receiving the ACC_STS related to IO # 03 from the IOP 711, the CHU 712 transmits the ACC_STS to the IOC 702 and subtracts 1 from the connect IO counter 838. At this time, the number of empty reception buffers in the IOP reception buffer area 836 is 2, the number of empty reception buffers in the CHU reception buffer area 842 of the IOC 702 is 2, and the connect IO counter 838 is 0.

(20) The IOC 702 receives the ACC_STS related to the IO # 03 and transmits a notification indicating that the processing result has been accepted to the IO # 03. At this time, the number of empty reception buffers in the CHU reception buffer area 842 is three.

FIG. 27 shows the input / output capability improved by the input / output control of the embodiment. The horizontal and vertical axes in FIG. 27 represent the transfer rate and the CPU instruction execution frequency, as in FIG. A broken line 2501 represents the target value of the CPU IO instruction execution frequency with respect to the transfer rate, and a solid line 2502 represents the actual CPU IO instruction execution frequency by the input / output control of the embodiment.

At the point 2521 on the broken line 2501 corresponding to the transfer rate of 320 MB / S, the target value of the CPU IO instruction execution frequency is 16000, whereas at the point 2522 on the solid line 2502, the actual CPU IO instruction execution frequency is About 15500. Therefore, according to the input / output control of the embodiment, the decrease of the CPU IO instruction execution frequency is about 500, which is improved by about 2600 compared with the decrease of the CPU IO instruction execution frequency by the exclusive control of FIG. I understand that In terms of the time required for control per input / output process, this corresponds to a reduction from about 15 μs to 2 μs.

As described above, according to the input / output control of the embodiment, it is possible to prevent the throughput of the input / output processing, which has been improved by eliminating the exclusive control between the CHU and the IOC, from being lowered.

Although the disclosed embodiment and its advantages have been described in detail above, those skilled in the art can make various modifications, additions and omissions without departing from the scope of the present invention clearly described in the claims. Will.

Claims

A control system including a first device and a second device,
The first device includes:
A first communication unit that transmits a process start instruction to the second apparatus and receives a process end notification and an asynchronous notification for the process start instruction from the second apparatus;
A first storage that stores a first upper limit value that defines the number of connections used for communication between the first device and the second device;
A first control unit that controls the number of processing start instructions corresponding to the processing end notification not received from the second device to a number equal to or less than the first upper limit value;
With
The second device includes:
A second communication unit that receives the processing start instruction from the first device and transmits the processing end notification and the asynchronous notification to the first device;
A second storage unit for storing a second upper limit value larger than the first upper limit value;
The total of the number of processing start instructions corresponding to the processing end notification not transmitted to the first device and the number of asynchronous notifications transmitted to the first device is equal to or less than the second upper limit value. A second control unit that controls the number of
A control system comprising:
The first storage unit stores a first count value indicating the number of processing start instructions corresponding to the processing end notification not received from the second device, and the first control unit When a process start instruction is transmitted to the second apparatus, 1 is added to the first count value, and when a process end notification or a busy notification for the process start instruction is received from the second apparatus, 1 is subtracted from the first count value, the second storage unit stores a second count value indicating the total number, and the second control unit sends the processing start instruction to the first device. 1 is added to the second count value when the asynchronous notification is transmitted to the first device, and either the processing end notification, the asynchronous notification, or the busy notification is notified. A response is received from the first device. The control system of claim 1, wherein the subtracting 1 from the second count value when.
The first control unit starts a new process for the second device when the number of the process start instructions corresponding to the unprocessed process end notification reaches the first upper limit value. The transmission of the instruction is suspended, and the second control unit suppresses transmission of a new asynchronous notification to the first device when the total reaches the second upper limit value. The control system according to claim 1 or 2.
The second communication unit is configured to display the processing result when the second device transmits the processing start instruction to the input / output device and receives the processing result of the input / output processing from the input / output device. The end notification is transmitted to the first device, and the asynchronous notification is transmitted to the first device when an asynchronous interrupt indicating a state change is received from the input / output device. 4. The control system according to any one of 3.
A control method for controlling communication between a first device and a second device, comprising:
Among the process start instructions transmitted from the first apparatus to the second apparatus, the number of the process start instructions that have not received a process end notification for the process start instruction from the second apparatus Control to a number equal to or less than a first upper limit value that defines the number of connections used for communication between the second device and the second device;
The number of processing start instructions corresponding to the processing end notification not transmitted from the second device to the first device, and the number of asynchronous notifications transmitted from the second device to the first device; To a number equal to or less than a second upper limit value greater than the first upper limit value,
A control method characterized by that.
A program for causing a processor included in the first device to execute processing for controlling communication between the first device and the second device,
Among the process start instructions transmitted from the first apparatus to the second apparatus by the processor, the number of process start instructions that have not been received from the second apparatus is a process end notification for the process start instruction. , Controlling the number of connections used for communication between the first device and the second device to a number equal to or less than a first upper limit value that defines the number of connections,
The number of processing start instructions corresponding to the processing end notification that has not been transmitted from the second device to the first device by the second device, and transmission from the second device to the first device. Controlling the total number of asynchronous notifications to be made to a number equal to or less than a second upper limit value greater than the first upper limit value,
A program characterized by that.
A program for causing a processor included in the second device to execute processing for controlling communication between the first device and the second device,
Of the process start instructions transmitted from the first apparatus to the second apparatus by the first apparatus, the process start instruction that has not received a process end notification for the process start instruction from the second apparatus And the number of connections to a number equal to or less than a first upper limit value that defines the number of connections used for communication between the first device and the second device;
The number of processing start instructions corresponding to the processing end notification not transmitted from the second device to the first device by the processor, and the asynchronous transmitted from the second device to the first device Controlling the total number of notifications to a number equal to or less than a second upper limit value greater than the first upper limit value,
A program characterized by that.