WO2013176305A1 - Architecture de système basée sur une mémoire ddr - Google Patents

Architecture de système basée sur une mémoire ddr Download PDF

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Publication number
WO2013176305A1
WO2013176305A1 PCT/KR2012/004044 KR2012004044W WO2013176305A1 WO 2013176305 A1 WO2013176305 A1 WO 2013176305A1 KR 2012004044 W KR2012004044 W KR 2012004044W WO 2013176305 A1 WO2013176305 A1 WO 2013176305A1
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WO
WIPO (PCT)
Prior art keywords
coupled
raid
chip
ddr
controller
Prior art date
Application number
PCT/KR2012/004044
Other languages
English (en)
Inventor
Byungcheol Cho
Original Assignee
Taejin Info Tech Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taejin Info Tech Co., Ltd. filed Critical Taejin Info Tech Co., Ltd.
Priority to PCT/KR2012/004044 priority Critical patent/WO2013176305A1/fr
Publication of WO2013176305A1 publication Critical patent/WO2013176305A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Definitions

  • the present invention relates to an SSD system architecture based on DDR memory.
  • Embodiments of the present invention provide an SSD system architecture based on DDR memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. Coupled to each SSD RAID controller is a set of DDR memory control units, each of the set of DDR memory control units include an SSD controller and a set of DRAM memory units.
  • a first aspect of the present invention provides an SSD system architecture based on DDR memory, comprising: a set of SSD RAID controllers coupled to a system control board; a fibre channel chip coupled to the system control board; and a set of memory control units coupled to each of the set of SSD RAID controllers, each of the set of memory control units comprising an SSD controller and a set of DRAM memory units.
  • a second aspect of the present invention provides a method for providing an SSD system architecture based on DDR memory, comprising: coupling a set of SSD RAID controllers to a system control board; coupling a fibre channel chip to the system control board; and coupling a set of memory control units to each of the set of SSD RAID controllers, each of the set of memory control units comprising an SSD controller and a set of DRAM memory units.
  • a third aspect of the present invention provides an SSD system architecture based on DDR memory, comprising: a processor; a chip coupled to the processor; a set of SSD RAID controllers coupled to the chip; a fibre channel chip coupled to the chip; and a set of memory control units coupled to each of the set of SSD RAID controllers, each of the set of memory control units comprising an SSD controller and a set of DRAM memory units.
  • a fourth aspect of the present invention provides a method for providing an SSD system architecture based on DDR memory, comprising: a processor; coupling a chip to a processor; coupling a set of SSD RAID controllers to the chip; coupling a fibre channel chip to the chip; and coupling a set of memory control units to each of the set of SSD RAID controllers, each of the set of memory control units comprising an SSD controller and a set of DRAM memory units.
  • a fifth aspect of the present invention provides a DDR memory system for a multi-level RAID architecture, comprising: a main RAID controller coupled to a system control board; a set of DDR RAID controllers coupled to the main RAID controller; and a set of DDR RAID control blocks coupled to each of the set of DDR RAID controllers, each of the set of DDR RAID control blocks comprising a set of DDR memory disks.
  • a sixth aspect of the present invention provides a DDR memory system for a multi-level RAID architecture, comprising: a main RAID controller coupled to a system control board; a set of DDR RAID controllers coupled to the main RAID controller; and a set of DDR RAID control blocks coupled to each of the set of DDR RAID controllers, each of the set of DDR RAID control blocks comprising a set of DDR memory disks and a PCI-Express RAID controller.
  • a seventh aspect of the present invention provides a method for providing a DDR memory system for a multi-level RAID architecture, comprising: coupling a main RAID controller to a system control board; coupling a set of DDR RAID controllers to the main RAID controller; and coupling a set of DDR RAID control blocks to each of the set of DDR RAID controllers, each of the set of DDR RAID control blocks comprising a set of DDR memory disks.
  • Fig. 1 is a diagram schematically illustrating a configuration of a RAID controlled storage device of a PCI-Express (PCI-e) type according to an embodiment of the present invention.
  • PCI-e PCI-Express
  • Fig. 2 is a more specific diagram of a RAID controller coupled to a set of SSDs.
  • Fig. 3 is a diagram schematically illustrating a configuration of the highspeed SSD of Fig. 1.
  • Figs. 4A and 4B are diagrams schematically illustrating DDR memory systems.
  • Fig. 5 is an SSD unit block diagram illustrating the memory components.
  • Fig. 6 is a diagram schematically illustrating the SSD unit architecture.
  • Fig. 7 is a diagram schematically illustrating an SSD multi-RAID system architecture based on DDR memory.
  • RAID means redundant array of independent disks (originally redundant array of inexpensive disks).
  • RAID technology is a way of storing the same data in different places (thus, redundantly) on multiple hard disks. By placing data on multiple disks, I/O (input/output) operations can overlap in a balanced way, improving performance. Since multiple disks increase the mean time between failures (MTBF), storing data redundantly also increases fault tolerance.
  • SSD means semiconductor storage device.
  • DDR means double data rate.
  • HDD means hard disk drive.
  • embodiments of the present invention provide a DDR memory system for a multi-level RAID architecture.
  • embodiments of this invention provide a main RAID controller coupled to a system control board.
  • Main RAID controller 802 is self-contained, meaning it has its own firmware to enable booting from an SSD. Coupled to the main RAID controller is a set of double data rate (DDR) RAID subcontrollers.
  • DDR double data rate
  • a set of DDR RAID control blocks is coupled to each of the set of DDR RAID controllers, each of the set of DDR RAID control blocks include a set of DDR memory disks.
  • the storage device of an I/O standard such as a serial attached small computer system interface (SAS) serial advanced technology attachment (SATA) type supports a low-speed data processing speed for a host by adjusting synchronization of a data signal transmitted/received between the host and a memory disk during data communications between the host and the memory disk through a PCI-Express interface, and simultaneously supports a high-speed data processing speed for the memory disk, thereby supporting the performance of the memory to enable high-speed data processing in an existing interface environment at the maximum.
  • SAS serial attached small computer system interface
  • SATA serial advanced technology attachment
  • FIG. 1 a diagram schematically illustrating a configuration of a PCI-Express type, RAID controlled storage device (e.g., for providing storage for a serially attached computer device) according to an embodiment of the invention is shown. As depicted, Fig.
  • FIG. 1 shows a RAID controlled PCI-Express type storage device according to an embodiment of the invention which includes a memory disk unit 100 comprising: a plurality of memory disks having a plurality of volatile semiconductor memories (also referred to herein as high-speed SSDs 100); a RAID controller 800 coupled to SSDs 100; an interface unit 200 (e.g., PCI-Express host) which interfaces between the memory disk unit and a host; a controller unit 300; an auxiliary power source unit 400 that is charged to maintain a predetermined power using the power transferred from the host through the PCI-Express host interface unit; a power source control unit 500 that supplies the power transferred from the host through the PCI-Express host interface unit to the controller unit, the memory disk unit, the backup storage unit, and the backup control unit which, when the power transferred from the host through the PCI-Express host interface unit is blocked or an error occurs in the power transferred from the host, receives power from the auxiliary power source unit and supplies the power to the memory disk unit through the controller unit; a
  • the memory disk unit 100 includes a plurality of memory disks provided with a plurality of volatile semiconductor memories for high-speed data input/output (for example, DDR, DDR2, DDR3, SDRAM, and the like), and inputs and outputs data according to the control of the controller unit 300.
  • the memory disk unit 100 may have a configuration in which the memory disks are arrayed in parallel.
  • the PCI-Express host interface unit 200 interfaces between a host and the memory disk unit 100.
  • the host may be a computer system or the like, which is provided with a PCI-Express interface and a power source supply device.
  • the controller unit 300 adjusts synchronization of data signals transmitted/received between the PCI-Express host interface unit 200 and the memory disk unit 100 to control a data transmission/reception speed between the PCI-Express host interface unit 200 and the memory disk unit 100.
  • a PCI-e type RAID controller 800 can be directly coupled to any quantity of SSDs 100. Among other things, this allows for optimum control of SSDs 100. Among other things, the use of a RAID controller 800:
  • the internal backup controller determines the backup (user's request order or the status monitor detects power supply problems);
  • the internal backup controller requests a data backup to SSDs
  • the internal backup controller determines the restore (user's request order or the status monitor detects power supply problems);
  • the internal backup controller requests a data restore to the SSDs
  • SSD/memory disk unit 100 comprises: a host interface 202 (e.g., PCI-Express host) (which can be interface 200 of Fig. 1, or a separate interface as shown); a DMA controller 302 interfacing with a backup control module 700; an ECC controller 304; and a memory controller 306 for controlling one or more blocks 604 of memory 602 that are used as high-speed storage.
  • a host interface 202 e.g., PCI-Express host
  • DMA controller 302 interfacing with a backup control module 700
  • ECC controller 304 e.g., ECC controller 304
  • memory controller 306 for controlling one or more blocks 604 of memory 602 that are used as high-speed storage.
  • the controller unit 300 of Fig. 1 is shown as comprising: a memory control module 310 which controls data input/output of the SSD memory disk unit 100; a DMA control module 320 which controls the memory control module 310 to store the data in the SSD memory disk unit 100, or reads data from the SSD memory disk unit 100 to provide the data to the host, according to an instruction from the host received through the PCI-Express host interface unit 200; a buffer 330 which buffers data according to the control of the DMA control module 320; a synchronization control module 340 which, when receiving a data signal corresponding to the data read from the SSD memory disk unit 100 by the control of the DMA control module 320 through the DMA control module 320 and the memory control module 310, adjusts synchronization of a data signal so as to have a communication speed corresponding to a PCI-Express communications protocol to transmit the synchronized data signal to the PCI-Express host interface unit 200, and when receiving a data signal from the host through the PCI
  • the high-speed interface module 350 includes a buffer having a double buffer structure and a buffer having a circular queue structure, and processes the data transmitted/received between the synchronization control module 340 and the DMA control module 320 without loss at high speed by buffering the data and adjusting data clocks.
  • Fig. 4A is a diagram schematically illustrating the semiconductor storage device (SSD) system architecture based on double data rate (DDR) memory.
  • the DDR memory system comprises a set of SSD RAID controllers 368A-N coupled to system control board 360.
  • Fibre channel chip 370 is coupled to system control board 360.
  • Fibre channel is a technology for transmitting data between computer devices.
  • System control board 360 generally comprises CPU 362 and IOH 366.
  • QPI QualityPath Interconnect
  • HT HyperTransport
  • a set of memory control units 376A-N is coupled to each of the set of SSD RAID controllers 368A-N, each of the set of memory control units comprising an SSD controller 374A-N and a set of DRAM memory units 378A-N.
  • Fig. 4B is a diagram schematically illustrating an alternate DDR memory system.
  • CPU 380 is coupled to IOH 384 using QPI or HT.
  • IOH 384 is coupled to a set of SSD RAID controllers (for example SSD RAID 386) and fibre channel 388.
  • Each of the set of SSD RAID controllers is coupled to a DDR unit (for example, DDR 398).
  • Each DDR unit comprises SSD controller 392 coupled to a set of DRAM memory units (for example, DRAM 396).
  • Fig. 5 depicts an SSD block diagram illustrating a detailed view of the memory components.
  • SSD controller 502 is coupled to a SATA3 device, NAND flash 504 and HDD 506 using SATA, memory controller 508, and memory controller 510.
  • SSD controller 502 is coupled to each memory controller via a PCI-Express interface (PCIe).
  • PCIe PCI-Express interface
  • Memory controller 508 is coupled to a set of DRAM memory units 512A-N using DDR connections.
  • Memory controller 510 is coupled to a set of DRAM units 514A-N using DDR connections.
  • SSD unit 408 includes main controller 404, SSD subcontroller 406, and a set of DRAM memory units 410A-N.
  • Main controller 404 is coupled to SSD subcontroller 406 using a PCI-Express interface.
  • Subcontroller 406 is coupled to the set of DRAM units 410A-N using DDR2.
  • the architecture includes a main RAID controller 802 coupled to a system control board 810. Coupled to the main RAID controller 802 is data backup unit 808, and a set (at least one) of DDR RAID controllers 824A-N. Focusing on DDR RAID controller 824A for illustrative purposes, a data backup unit 828A and a set (at least one) of DDR RAID control blocks 842A are coupled to DDR RAID controllers 824A.
  • each DDR RAID control block 842A comprises: a set of DDR memory disks 844A; a hot spare disk 846A coupled to the set of DDR memory disks; a (PCI-E to PCI-E) RAID controller 840A coupled to the set of DDR memory disks 844A; a RAID fail component 836A coupled to the RAID controller 840A; and a data backup component 838A coupled to the RAID controller 840A.
  • Each of the remaining DDR RAID controllers 824B-N and DDR RAID control blocks 842B-N making up the system architecture has a similar configuration as described above.
  • main RAID controller 802 comprises: a high-speed data controller 804; a middle-speed data controller 805, and a low-speed data controller 806.
  • a data backup component 808 is shown coupled to main RAID controller 802.
  • System control board 810 generally comprises: a chip (e.g., IOH) 816; a high-speed data controller 812 coupled to the chip 816; a middle speed data controller 813 coupled to the chip 816, a low-speed data controller 814 coupled to the chip 816; a fibre channel chip 818 coupled to the chip 816; a processor 820 coupled to the chip 816; and cache memory 822 coupled to the processor 820.
  • a chip e.g., IOH
  • processor 820 coupled to the chip 816
  • cache memory 822 coupled to the processor 820.
  • auxiliary power source unit 400 may be configured as a rechargeable battery or the like, so that it is normally charged to maintain a predetermined power using power transferred from the host through the PCI-Express host interface unit 200 and supplies the charged power to the power source control unit 500 according to the control of the power source control unit 500.
  • the power source control unit 500 supplies the power transferred from the host through the PCI-Express host interface unit 200 to the controller unit 300, the memory disk unit 100, the backup storage unit 600, and the backup control unit 700.
  • the power source control unit 500 receives power from the auxiliary power source unit 400 and supplies the power to the memory disk unit 100 through the controller unit 300.
  • the backup storage unit 600A-B is configured as a low-speed non-volatile storage device such as a hard disk and stores data of the memory disk unit 100.
  • the backup control unit 700 backs up data stored in the memory disk unit 100 in the backup storage unit 600 by controlling the data input/output of the backup storage unit 600 and backs up the data stored in the memory disk unit 100 in the backup storage unit 600 according to an instruction from the host, or when an error occurs in the power source of the host due to a deviation of the power transmitted from the host deviates from the threshold value.
  • the present invention supports a low-speed data processing speed for a host by adjusting synchronization of a data signal transmitted/received between the host and a memory disk during data communications between the host and the memory disk through a PCI-Express interface and simultaneously supports a high-speed data processing speed for the memory disk, thereby supporting the performance of the memory to enable high-speed data processing in an existing interface environment at the maximum.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Des modes de réalisation de la présente invention concernent une architecture de système SSD basée sur une mémoire DDR. Pour être plus précis, des modes de réalisation de la présente invention concernent un ensemble de contrôleurs SSD RAID couplé à un tableau de commande de système. Un ensemble d'unités de contrôle de mémoire est couplé à chaque contrôleur SSD RAID. Chaque unité de l'ensemble d'unités de contrôle de mémoire comprend un contrôleur SSD et un ensemble d'unités de mémoire DRAM.
PCT/KR2012/004044 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire ddr WO2013176305A1 (fr)

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PCT/KR2012/004044 WO2013176305A1 (fr) 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire ddr

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PCT/KR2012/004044 WO2013176305A1 (fr) 2012-05-23 2012-05-23 Architecture de système basée sur une mémoire ddr

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020058511A (ko) * 2000-12-30 2002-07-12 오길록 복수 개의 레이드를 구비한 계층적 레이드 시스템 및 그제어 방법
KR20110110720A (ko) * 2010-04-01 2011-10-07 인텔 코오퍼레이션 고체 상태 드라이브에서의 웨어 레벨링을 위한 방법 및 시스템
KR20110124711A (ko) * 2010-05-11 2011-11-17 주식회사 태진인포텍 멀티레벨 알에이아이디 아키텍처용 하이브리드 저장 시스템
KR20120010150A (ko) * 2010-07-19 2012-02-02 주식회사 태진인포텍 멀티 레벨 ｒａｉｄ 구조를 위한 하이브리드 저장 시스템

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020058511A (ko) * 2000-12-30 2002-07-12 오길록 복수 개의 레이드를 구비한 계층적 레이드 시스템 및 그제어 방법
KR20110110720A (ko) * 2010-04-01 2011-10-07 인텔 코오퍼레이션 고체 상태 드라이브에서의 웨어 레벨링을 위한 방법 및 시스템
KR20110124711A (ko) * 2010-05-11 2011-11-17 주식회사 태진인포텍 멀티레벨 알에이아이디 아키텍처용 하이브리드 저장 시스템
KR20120010150A (ko) * 2010-07-19 2012-02-02 주식회사 태진인포텍 멀티 레벨 ｒａｉｄ 구조를 위한 하이브리드 저장 시스템

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