WO2013174528A2

WO2013174528A2 - Gate driver for a power converter

Info

Publication number: WO2013174528A2
Application number: PCT/EP2013/052805
Authority: WO
Inventors: Philip Perry Waite
Original assignee: Siemens Aktiengesellschaft
Priority date: 2012-05-24
Filing date: 2013-02-13
Publication date: 2013-11-28
Also published as: CN104303405B; EP2815491A2; CN104303405A; WO2013174528A3

Abstract

A gate driver for a power converter is provided, wherein the gate driver comprises a low side circuit and a high side circuit coupled to the low side circuit, wherein the high side circuit comprises a detection circuitry which is adapted to provide an error signal which is indicative of a fault condition of the low side circuit.

Description

DESCRIPTION

Gate Driver for a Power Converter

Field of the Invention

The present invention relates to the field of gate drivers for power converters in particular to gate drivers for power converters having a plurality of power converter modules.

Moreover, the present invention relates to a power converter comprising a gate driver. Furthermore, the present invention relates to a method of operating a gate driver.

Art Background

Multi-megawatt power electronic converters typically adopt a modular approach, using multiple inverter modules connected in soft parallel. In such systems the output of each module is connected via a balancing reactor to the common load. The primary purpose of the balancing reactor is to accommodate the inevitable timing and voltage differences between inverter modules and then provides an important part of the facility by which active current balance is achieved between the inverter modules.

Fig. 1 schematically shows the electrical system of a wind turbine 100. The blades 101 of the wind turbine are coupled to a generator 102 which is coupled to the electrical system via a generator circuit breaker (GCB) 103. The electrical system comprises a plurality of balancing reactors 104 which are coupled to the GCB and are used to divert the power generated by the generator into a plurality of inverter or power converters modules 105 connected in parallel so that high power outputs, e.g. in the range of several megawatt, can be handled by the electrical system of the wind turbine. The power converters are only schematically depicted in

Fig. 1 and each comprise a generator bridge 106, a voltage clamp 107 and a network bridge 108. The output of the

inverters or power converters is coupled to further balancing reactors 109 which are used to perform inevitable timing and handle voltage differences between inverter modules. The output of the further balancing reactors is connected to a network circuit breaker (NCB) 110 via an inductivity (LN) 111 and a pulse width modulation filter (PWM) 112. The output of the NCB is in turn coupled to a wind turbine transformer 113 and via a further circuit breaker (MVCN) 114, which serves for the self-protection of the network, to a wind farm collector network 115 which serves for conducting of the generated electrical power of the wind farm. Furthermore, the electrical system comprises a wind turbine controller 116 and a controller 117 which are both used to control the inverter or power converter modules.

In typical LV power converters, the controller, which

operates at ground potential, generates turn-on and turn-off command signals for each insulated-gate bipolar transistor (IGBT) gate of the balancing reactors. The IGBT gates operate at potentials several hundred volts from ground potential and so the low voltage command signals must be galvanicaly isolated from the IGBT gate. This signal conditioning and isolation is performed by a gate-drive circuit or gate driver. The gate-drive circuit board has a "low-side" circuit which transmits signals to and from the "high-side" circuit using a pulse transformer.

For certain internal component fault conditions the IGBT turn-off signal from the controller cannot be transmitted via the pulse transformer to the high-side in order to turn-off an IGBT of the balancing reactor. This represents a temporary loss of control of the conduction state of the IGBT which may result in a failure of the power converter or inverter.

Thus, there may be a need to provide a method which may avoid or at least reduces the probability of such a loss of control .

Summary

This need may be met by the subject matter according to the independent claims. Advantageous embodiments are described by the dependent claims.

According to an exemplary aspect a gate driver for a power converter is provided, wherein the gate driver comprises a low side circuit and a high side circuit coupled to the low side circuit, wherein the high side circuit comprises a detection circuitry which is adapted to provide an error signal which is indicative of a fault condition of the low side circuit. In particular, the low side circuit and the high side circuit may be coupled to each other by a coupling element which is adapted to transmit signals, e.g. electrical signals or optical signals, and/or AC current but blocks DC current. Thus, the low side circuit and the high side circuit may be isolated from each other with respect to a DC current. For example, the coupling element may be a transformer or a capacitor. However, the coupling element may be an opto-fiber or opto-coupler which both are suitable to transmit signals but to block electrical current.

It should be noted that the term "gate driver" is not

restricted to a device adapted to drive the gate of a

transistor but has to be understand in a broader sense. In particular any device adapted or suitable to drive or control a switching element by providing a drive, control or

switching signal to an input terminal of the switching element may be regarded as a gate driver.

The term "detection circuitry" may particular denote any arrangement of electronic circuits which is suitable and/or adapted to detect a faulty condition of the low side circuit and based on this detection provide and/or generate a

detection and/or error signal which is indicative of the faulty condition.

According to an exemplary aspect an electronic converter is provided which comprises a gate driver according to an exemplary aspect and a switching element having an input terminal coupled to an output terminal of the gate driver.

According to an exemplary aspect a method of operating a gate driver according to any an exemplary aspect is provided, wherein the method comprises detecting an error condition of the low side circuit at the high side circuit generating an error signal upon detection of the error condition, and providing the error signal to a switching element. According to an exemplary aspect a computer program is provided which, when being executed by a processor, is adapted for controlling the method according to an exemplary aspect.

As used herein, reference to a computer program is intended to be equivalent to a reference to a program element and/or to a computer readable medium containing instructions for controlling a processor or computer system to coordinate the performance of the method of operating a gate driver. The computer program element may be implemented as computer readable instruction code in any suitable programming language, such as, for example, JAVA, C++, and may be stored on a computer-readable medium (removable disk, volatile or non-volatile memory, embedded memory/processor, etc.). The instruction code is operable to program a computer or any other programmable device to carry out the intended

functions. The computer program may be available from a network, such as the World Wide Web, from which it may be downloaded .

In particular, the switching element may be a transistor of the electronic converter. In particular, the electronic converter may comprise a plurality of converter stages or modules each comprising at least one gate driver and coupled in parallel so that the amount of current and/or power providable by the electronic converter is increased. The electronic converter, which may be a multi-megawatt power electronic converter, may comprise a balancing reactor adapted to provide a timing and/or voltage adaption or matching for different converter stages of the electronic converter . By providing a gate driver adapted to provide an error signal indicative of a fault or faulty condition of the low side circuit of the gate driver it may be possible to reduce the possibility of an inverter or power converter failure. This may be true in particular for certain internal component fault conditions, e.g. a sudden loss of power on the "low- side" circuit due to short-circuit component and/or loss of gate drive clock signal. In such cases turn-off signals for a switching element, e.g. a transistor (like an IGBT) , may be transmitted fast enough from the controller so that the switching element can be turned-off. Thus, a temporary loss of control of the conduction state of the switching element may be avoided. In particular, it may be possible to avoid the situation that, if the switching element is in a turned- on state and conducting current at the instant of the fault, it will remain turned-on and conducting current until the power supply fails of the "high-side" electronics (held up by high- side local reservoir capacitor) collapses to its

undervoltage lockout threshold.

Next further embodiments of the gate driver are described. However the respective features may also be combined with the electronic converter, the method of operating a gate driver, and the computer program.

According to an exemplary embodiment of the gate driver the low side circuit and the high side circuit are galvanicaly separated from each other. In particular, the separation or isolation may be performed by providing a transformer, by an opto-fiber or opto-coupler . According to an exemplary embodiment the gate driver further comprises a pulse transformer, wherein the pulse transformer is adapted to couple the low side circuit to the high side circuit .

Compared to an opto-fiber or an opto-coupler, the use of a pulse transformer as the means of coupling or isolation may provide for an optimisation of signal latency (and variation of latency) , skew (and variation of skew) , voltage isolation capability, lifetime/performance degradation, and cost. The pulse transformer may use a form of voltage pulse, to turn-on and a pulse to turn-off, which is latched by the high-side.

According to an exemplary embodiment the gate driver further comprises an output terminal which is adapted to be coupled to a switching element in such a way that the error signal is provided at a switching input terminal of the switching element . In particular, the switching element may be a transistor, preferably a power transistor, and may be an IGBT, a MOSFET, a BPT, GTO or IGCT.

According to an exemplary embodiment of the gate driver the fault condition is a loss of a low side power supply and/or a loss of a clock signal of the low side circuit.

For example, the loss of the low side power supply may be caused by a short-circuit component.

According to an exemplary embodiment of the gate driver the detection circuitry is adapted to provide the error signal in a time span which is lower than a predetermined limit. In particular, a predetermined limit may be defined as a time span which is sufficient short to protect a switching element when coupled to the gate driver. Examples for the

predetermined limit may be 1 millisecond, 100 microseconds, 50 microseconds or even 10 microseconds.

According to an exemplary embodiment of the gate driver the high side circuit comprises a top part and a bottom part.

According to an exemplary embodiment of the gate driver the high side circuit comprises a power supply circuitry and a logic circuitry wherein the high side power supply circuitry is coupled to a low side power supply circuitry.

In particular, the detection circuitry may be a part of the logic circuitry or at least some parts or components of the detection circuitry may be part of the logic circuitry.

However, the detection circuitry or at least some parts or components of the detection circuitry may be part of the power supply circuitry.

According to an exemplary embodiment of the gate driver the detection circuitry comprises a pair of diodes and an RC filter coupled to each other in such a way that a detection signal is generatable.

In particular, the detection circuitry may be part of the high side power supply circuitry and the pair of diodes and the RC filter are coupled to each other in such a way that the detection signal is supplied to the logic circuitry. The detection signal may be used to generate the error signal or may itself be the error signal depending on the specific implementation of the detection circuitry.

Alternatively or additionally to the provision of a pair of diodes and an RC filter it is possible to use any other configuration adapted to provide a fast, e.g. faster than 1 millisecond or even faster than 100 microseconds, logic signal suitable for providing an error signal. For example another number of diodes may be used and may thus form at least a part of the detection circuitry. Likewise a detection circuitry or logic circuitry may be used which is adapted to detect a square wave carrier or square wave signal modulated onto the power supply. In such a case an edge triggered timer/monostable or phase-locked loop may be used to provide a high speed signal as the detection signal and/or error signal based on the detection of the presence of the square wave carrier, which error signal may then be used to switch- off switching elements of a corresponding balancing reactor. According to an exemplary embodiment of the gate driver the logic signal is supplied to an AND and/or NAND element having an output terminal wherein the AND and/or NAND element is adapted to provide the error signal at an output terminal Summarizing a gist of an exemplary embodiment may be seen in providing or generating a detection or error signal which is indicative of a faulty condition and which is generated at the high side, i.e. the high side circuit of a gate driver. This has to be distinguished from a measurement of phase current (for closed-loop current control, current balancing, and over-current protection) performed on the low side circuit. However, the detection on the low side may have some disadvantages in specific cases which disadvantages may be avoided when the error signal is generated at the high side. For example, the disadvantages, that in certain internal component fault conditions (e.g. a sudden loss of power on the "low-side" circuit due to short-circuit component or loss of gate drive clock signal) the transistor (e.g. an IGBT) turn-off signal from the controller cannot be transmitted via the pulse transformer to the high-side in order to turn-off the respective transistor, may be avoided, since the error signal is already generated on the high side.

The generation of the error signal on the high side may avoid a temporary loss of control of the conduction state of the transistor which loss of control would, if the IGBT is in a turned-on state and conducting current at the instant of the fault, lead to the fact that it will remain turned-on and conducting current until the power supply fails of the "high- side" electronics (held up by high- side local reservoir capacitor) collapses to its undervoltage lockout threshold. At this point in time (possibly several milliseconds after the fault occurred) the transistor gate will be turned off. However, this delay of turn-off of the transistor, which may cause damage to the transistor, may be avoided in case the error signal is already generated on the high side circuit. The using of a gate driver according to an exemplary

embodiment may be in particular useful for situations where: a) inverter modules or power converter modules operating in parallel (e.g. in multi-megawatt inverters) and/or

b) inverter modules connected to a load that is a voltage source for extended period (e.g. large induction/PM

motor/generator or supply network, since then additional more serious consequences may occur that require the transistor to be turned off in a much shorter time, below a millisecond, (e.g. a few microseconds) otherwise transistor destruction may occur.

Thus, according to an exemplary embodiment a simple facility on the high side of the gate driver or gate drive electronics may be provided that monitors the health of the low side of the gate driver electronics and possibly autonomously turn- off the transistor within a very short time (a few

microseconds rather than milliseconds) , which is short enough prevent buildup of current to a destructive level during some fault conditions specific to paralleled inverters and for connected to AC voltage sources.

Furthermore, an inventive idea may be seen in the utilization of high speed monitoring of the existing high frequency

(circa 500 kHz) power supply (generated by the low side circuit) as a means of sufficiently rapid detection of failure of the low side circuit, thereby not requiring additional complex circuits or additional signals to be transmitted across the isolation barrier.

It has to be noted that embodiments have been described with reference to different subject matters. In particular, some embodiments have been described with reference to method type claims whereas other embodiments have been described with reference to apparatus type claims. However, a person skilled in the art will gather from the above and the following description that, unless other notified, in addition to any combination of features belonging to one type of subject matter also any combination between features relating to different subject matters, in particular between features of the method type claims and features of the apparatus type claims is considered as to be disclosed with this application .

The aspects defined above and further aspects are apparent from the example of embodiment to be described hereinafter and are explained with reference to the example of

embodiment. The invention will be described in more detail hereinafter with reference to an example of embodiment but to which the invention is not limited.

Brief Description of the Drawings

Figure 1 schematically shows a wind turbine

Figure 2 schematically shows a principle layout of a gate driver .

Figure 3 schematically shows a layout of a gate driver according to an exemplary embodiment.

Figure 4 schematically shows a circuit used to explain a fault condition. Figure 5 schematically shows an example of a specific fault.

Detailed Description The illustration in the drawing is schematically. It is noted that in different figures, similar or identical elements may be provided with the same reference signs or with reference signs, which are different from the corresponding reference signs only within the first digit.

Figure 2 schematically shows a principle layout of a gate driver 200. In particular, Fig. 2 shows a low side circuit 201 and a high side circuit 202 which comprises a top part 203 and a symmetric bottom part 204. The low side circuit and the high side circuit are coupled to each other via a phase transformer or power supply transformer 205 which provides the power supply for the high side circuit. Furthermore, additional transformers 206 and 207 are provided which couple the low side circuit with the top part and the bottom part of the high side circuit, respectively. Furthermore, the high side circuit comprises a power supply circuitry 208 coupled to the power supply transformer 205 and providing the high side circuit with power. In particular, the power supply circuitry 208 comprises two parts 209 and 210 forming the power supply for the top part and the bottom part of the high side circuit, respectively. Each of the two parts of the power supply circuitry 208 comprises diodes and a capacitor, e.g. a local reservoir capacitor, and is

connected to a logic part of the top part of the high side circuit 211 and the bottom part of the high side circuit 212, respectively.

The logic part of the top part of the high side circuit 211 comprises a control logic 213 coupled on the one side to a signal conditioning unit 214 which is then coupled to a first terminal 215 of the gate driver. On the other side the control logic 213 is coupled to one of the additional

transformers 206. Similar, the logic part of the bottom part of the high side circuit 212 comprises a control logic 216 coupled on the one side to a signal conditioning unit 217 which is then coupled to a second terminal 218 of the gate driver. On the other side the control logic 216 is coupled to the other one of the additional transformers 207. Via the additional transformers a top command signal or top control signal and a bottom command signal or bottom control signal are provided to the top part and the bottom part of the high side circuit, respectively. The first terminal 215 and the second terminal 218 are coupled to a phase connection element 219 comprising a first transistor 220 coupled in parallel with a diode 221, wherein the first terminal 215 is connected to the gate of the first transistor 220. A second transistor 222 of the phase

connection element 219 is coupled to the second terminal 218 and is connected in parallel to a second diode 223. A source of the transistor 220 is coupled to a voltage DC+ while the source of the transistor 222 is coupled to a voltage DC-. The drains of the transistors each are coupled to a phase

connection which is then coupled to a balancing reactor 224.

Figure 3 schematically shows a layout of a gate driver according to an exemplary embodiment. The gate driver of Figure 3 is substantial identical to the one depicted in Figure 2 so that only the differences are described in the following. In particular, the power supply circuitry of the gate driver according to Figure 3 comprises detection

circuitries or elements, wherein one detection circuitry 330 is provided for the top part of the power supply circuitry and a second detection circuitry 331 is provided for the bottom part of the power supply circuitry. In particular, each of the first and second detection circuitries 330 and 331 comprises a pair of diodes 332 and 333 and 334 and 335, -Ir^¬ respectively and a RC filter 336 and 337 having a time constant in the range of microseconds, e.g. less than

100 microseconds, e.g. about 2 microseconds. The additional diodes, combined with very short time constant RC filter for small discontinuities that appear in the rectified 500 kHz square wave) provide a signal that rapidly falls if the low side power supply is lost or if clock signal is lost (which would result in freezing of command signal in current state) . Thus, the detection circuitries provide a function which is effectively an " IGBT TURN-ON ENABLE" signal. The respective signal is ANDed, by AND or NAND elements 338 and 339,

respectively, with an existing "high side" gate command signal provided by the control logic. The resulted ANDed signals are provided to the signal conditioning units and switch off the IGBT within a few microseconds of the fault occurring on the low-side thereby preventing destructive current developing.

Alternative solutions include any method of rapidly detecting (< 10 microseconds) the loss of the voltage and absence of switching of the power supply, whilst retaining high-side power supply for sufficient time (stored energy in reservoir capacitance) to turn off the IGBT in a controlled manner. These alternative solutions include:

Alternative diode arrangements that result in the same effective (fast) error signal being generated;

Detection of the presence of the square wave carrier using edge triggered timer/monostable or phase-locked-loop from which a high speed signal can be used to turn-off the IGBT.

In the following some specific fault conditions which may occur are described in greater detail. Firstly consequences of a fault condition will be explained which may occur when inverter modules operate in parallel. At any given instant, the total load current on a particular phase is shared equally between "n" soft-paralleled inverter modules, such that the current rating of each inverter module is not exceeded. However, if fault condition (e.g. power supply loss or clock signal loss) happened - causing a single IGBT to remain erroneously in a turned-on state for an extended period - on one of the paralleled inverter modules, and a resulting command is issued to turn-off the IGBTs, then n-1 IGBTs will switch off instantly followed by the IGBT with the fault on its gate drive switching off milliseconds later.

The consequence of this is that the prevailing phase current of the n paralleled inverter modules (at the instant of the failure) will be diverted into the single IGBT that has remained turned-on, at a rate determined only by the

inductance of the balancing reactors. Within a few

microseconds the total prevailing phase current is

transferred to a single IGBT. If the prevailing phase current (for the n paralleled inverter modules) is greater than the current commutation limit of the single IGBT, this will result in the IGBT exceeding its maximum commutation limit and resulting destruction. The maximum acceptable delay time to switch off safely following this fault condition is therefore : t_max = L*I/V wherein L = L_bai_aricirig + L_bai_aricirig/ (n-1 ) , n = number of inverter modules, I = IGBT commutation limit current - instantaneous inverter module phase current prior to trip, and V = DC link voltage . Figure 4 schematically shows a circuit used to explain a fault condition. Figure 4 schematically shows a plurality of inverter modules 440, 441 and 442. For clarity reasons for each inverter module only the two transistors connected to the balancing reactors via the phase connection (cf. Figure 2 and 3) are shown.

In the following the different fault example is explained in some keywords

• Initial condition: AC current waveform is negative whilst operating at load. Bottom IGBTs (T_liX(B) to Tn, x (B) ) are m turned-on state and, due to the negative polarity of the current, are therefore conducting the prevailing phase current. (Over the short time interval being considered below (a few microseconds) , and the relatively large supply

inductance the AC current can be considered as a constant negative current source)

• Fault occurs on low-side of gate driver of Ti,_x(B) as above described such that Ti_iX(B) is unable to follow a turn-off command .

• A turn-off command is sent to ΤΊ,_Χ(Β) to T_n,_X(_B), either a) as a result of the fault initiating a trip, or b) a normal turn- off event.

· Result: ΤΊ,_Χ(Β) to T_niX(B) are turned-off and Ti,_x(B) remains conducting

• Instantly, the respective share of total phase current flowing in T₂,_X(_B) to T_niX(B) is commutated to respective top diodes D₂ , _X ( T> to D_N, _X ( T ) , whilst the share of current being conducted by Ti,_x(B) remains conducting in ΪΊ_ίΧ(Β) (and not commutated to Di_iX(T) .

• The resulting applied voltage across L_2x to L_nx is now in opposition to the current, resulting in reducing current, whilst the applied voltage across L_ix is in the same polarity as the current, causing corresponding increase in current. The rate of change of current is determined by the DC link voltage and the value of L_2x to L_nx . (as previously described) · Current eventually (after a few microseconds) decreases to zero in L_2x to L_nx (and therefore D_2iX(T) to D_n,_X(T)) at which point D₂,_X(T₎ to D_niX(T) are no longer forward biased, and so applied voltage across _lK and L_2x to L_nx becomes zero,

resulting in (near) zero further change of current (over the microseconds time frame being considered in this scenario)

• The total prevailing phase current is now flowing in Ti_iX(B)

• If immediately prior to the fault, the prevailing total phase current for the n paralleled inverters is greater than the peak current commutation limit of T_liX(B) then T_liX(B) can no longer turn off without destruction, nor can it remain turned on without destruction.

In the following another situation corresponding to a case in which single/paralleled inverters or power converters are connected to an AC voltage source is described.

If a single IGBT remains erroneously conducting for an extended period (several milliseconds) , then during one half- cycle of the AC voltage source, there exists a short circuit via:

• the load reactance (main reactor (LN) for network inverter; or generator leakage inductance for generator inverter)

• The erroneously conducting IGBT

• The diode in an adjacent phase to the erroneously

conducting IGBT

Figure 5 schematically shows an example of a specific fault. In particular, Figure 5 shows one example of a short circuit path (in bold) resulting from a single IGBT (T_X,₂(_B>)

(remaining in conduction) . As in Figure 4 only three

transistors pairs 550, 551 and 552 connected to the balancing reactor 553 are shown of a given inverter module. The three pairs correspond to the different phases of the AC current. Additionally, Figure 5 shows an AC voltage source 554 to which the balancing reactors are coupled.

During the conducting half cycle (this could be multiple cycles depending on how long the IGBT takes to switch off) , there will be an increase in IGBT/diode current determined by the I = JE/L dt wherein E is the EMF of the voltage source and L is the total loop inductance. Depending on the inductance and voltage of the supply, the failure mode of the IGBT may be either:

i) Current in excess of maximum commutation current.

ii) Destruction due to excessive junction temperature (Tj) caused by the heating effect of a lesser current over (but still excessive) an extended time (several milliseconds) .

Additionally, the both situations described above may be combined in one situation, leading to a superposition of the consequences described in the context of Figure 4 and the one described in context of Figure 5:

The prevailing phase current of all paralleled inverters will be transferred to the erroneously conducting IGBT at a

(rapid) rate determined by the balancing reactor.

Simultaneously, the total prevailing current will further increase at a (less rapid) rate determined by the

instantaneous supply EMF and supply/generator impedance. It should be noted that the term "comprising" does not exclude other elements or steps and "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

List of reference signs:

100 wind turbine

101 blades

102 generator

103 generator circuit breaker

104 balancing reactors

105 inverter modules

106 generator bridge

107 voltage clamp

108 network bridge

109 balancing reactor

110 network circuit breaker

111 inductivity

112 PWM filter

113 transformer

114 MVCN

115 collector network 200 gate driver

201 low side circuit

202 high side circuit

203 top part of high side circuit

204 bottom part of high side circuit

205 power supply transformer

206 additional transformer

207 additional transformer

208 power supply circuitry

209 top part of power supply circuitry

210 bottom part of power supply circuitry

211 logic part of top part of high side circuit 212 logic part of bottom part of high side circuit 213 control logic 214 signal conditioning unit 215 first terminal

216 control logic

217 signal conditioning unit 218 second terminal

219 phase connecting element 220 first transistor

221 first diode

222 second transistor

223 second diode

224 balancing reactor

330 first detection circuitry 331 second detection circuitry 332-335 diodes

336 first RC filter

337 second RC filter

338 AND/NAND element

339 AND/NAND element

440-442 inverter modules

550-552 pairs of transistors 553 balancing reactor

554 AC voltage source

Claims

CLAIMS :

1. A gate driver (200) for a power converter, the gate driver comprising:

a low side circuit (201),

a high side circuit (202) coupled to the low side circuit (201) ,

wherein the high side circuit (202) comprises a

detection circuitry (330, 331) which is adapted to provide an error signal which is indicative of a fault condition of the low side circuit (201) .

2. The gate driver (200) according to claim 1, wherein the low side circuit (201) and the high side circuit (202) are galvanicaly separated from each other.

3. The gate driver (200) according to claim 1 or 2, wherein the gate driver (200) further comprises a pulse transformer (205) , wherein the pulse transformer (205) is adapted to couple the low side circuit (201) to the high side circuit (202) .

4. The gate driver (200) according to any one of the claims 1 to 3, wherein the gate driver (200) further comprises an output terminal (215, 218) which is adapted to be coupled to a switching element (220, 222) in such a way that the error signal is provided at a switching input terminal of the switching element (220, 222) .

5. The gate driver (200) according to any one of the claims 1 to 4, wherein the fault condition is a loss of a low side power supply and/or loss of a clock signal of the low side circuit .

6. The gate driver (200) according to any one of the claims 1 to 5, wherein the detection circuitry (330, 331) is adapted to provide the error signal in a time span which is lower than a predetermined limit.

7. The gate driver (200) according to any one of the claims 1 to 6, wherein the high side circuit (202) comprises a top part (203) and a bottom part (204) .

8. The gate driver (200) according to any one of the claims 1 to 7, wherein the high side circuit (202) comprises a power supply circuitry (209) and a logic circuitry (211) wherein the high side power supply circuitry (209) is coupled to a low side power supply circuitry.

9. The gate driver (200) according to any one of the claims 1 to 8, wherein the detection circuitry (330, 331) comprises a pair of diodes (332, 333, 334, 335) and an RC filter (336, 337) coupled to each other in such a way that a detection signal is generatable.

10. The gate driver (200) according to any one of the claims 1 to 8, wherein the logic signal is supplied to an AND and/or NAND element (338, 339) having an output terminal wherein the AND and/or NAND element is adapted to provide the error signal at an output terminal.

11. An electronic converter comprising:

a gate driver (200) according to any one of the claims 1 to 10, a switching element (220, 221) having an input terminal coupled to an output terminal (215, 218) of the gate driver

(200) .

12. A method of operating a gate driver (200) according to any one of the claims 1 to 10, comprising the steps of:

detecting an error condition of the low side circuit

(201) at the high side circuit (202);

generating an error signal upon detection of the error condition; and

providing the error signal to a switching element (220,

222) .

13. A computer program for operating a drive circuit, the computer program, when being executed by a processor, is adapted for controlling the method as set forth in claim 12.