CN101064432B - Voltage dynamic adjustment circuit of power factor corrector - Google Patents

Abstract

The invention discloses a voltage dynamic adjustment circuit of a power factor corrector that comprises at least two class RC filter circuit which receives voltage input, the first switch circuit and the second switch circuit, the first and the second switch circuit possess preset starting voltage, and one end of the first and the second switch circuit are connected with the RC filter circuit, the another end of the first and the second switch circuit are all connected with the voltage output, when the input voltage is added to make the difference of voltages of the first switch circuit bigger than the starting voltage, the first switch circuit is conducted to make output voltage increased; when the input voltage is decreased to make the potential difference between the two ends of the second switch circuit bigger than the starting voltage, the second switch circuit is conducted to make output voltage decreased. by setting of the first and the second switch circuit, the input voltage is changed, the output voltage can response actively to increase the active performance of the power factor corrector.

Description

Voltage dynamic adjustment circuit of power factor corrector

technical field

The invention relates to the field of control circuits of power factor correctors.

Background technique

At present, in the PFC control circuit using L4981, UC3854 or similar PFC (Power Factor Corrector, the English name is Power Factor Corrector) control chip, in order to obtain a better THD (Total Harmonic Distortion Rate, the English name is Total Harmonic Distortion) , In the input AC voltage RMS filtering branch, only multi-stage RC filtering is used to obtain a sufficiently flat voltage. Although this circuit can effectively reduce THD, when the input voltage changes rapidly, the branch cannot respond to the dynamic change of the input voltage in time, which will cause the PFC bus voltage to overshoot or drop. In addition, in the current PFC control circuit, the input of the bus voltage control circuit (voltage loop) is simply divided by the bus voltage and then directly input to the voltage loop. In order to obtain better steady-state performance, the corresponding parameters can be determined, but these parameters are very inappropriate in dynamic conditions, that is, when the load is suddenly increased or unloaded, the response speed of the voltage loop is very limited, so it is possible Bus voltage overshoot or undervoltage occurs. Generally speaking, the current PFC control circuits using L4981, UC3854 or similar PFC control chips have contradictions between THD and input dynamic performance, as well as contradictions between output steady state and dynamic performance.

Contents of the invention

The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide an adjustment circuit capable of improving the dynamic performance of the power factor corrector.

The technical solution adopted by the present invention to solve the technical problem is: the voltage dynamic adjustment circuit of the power factor corrector includes at least two stages of RC filter circuits accepting voltage input, a first switch circuit and a second switch circuit, the first and second The two switch circuits have a preset turn-on voltage, and one end of the first and second switch circuits are connected to the RC filter circuit, and the other ends of the first and second switch circuits are connected to the voltage output terminal, when the input voltage When the sudden increase makes the potential difference between the two ends of the first switch circuit greater than its turn-on voltage, the first switch circuit is turned on and the output voltage increases accordingly; when the input voltage suddenly drops, the potential difference between the two ends of the second switch circuit is greater than its turn-on voltage When , the second switch circuit is turned on so that the output voltage decreases accordingly.

The first and second switch circuits are connected in parallel between the first ends of the two filter capacitors of the RC filter circuit, and the second ends of the two filter capacitors are grounded.

The first switch circuit includes a first operational amplifier, a first diode and a fifth resistor, the second switch circuit includes a second operational amplifier, a second diode and a sixth resistor, and the first operational amplifier The non-inverting input terminal of the device is connected to the RC filter circuit, the output terminal is connected to the cathode of the first diode, the anode of the first diode is connected to one end of the fifth resistor and the inverting input terminal of the first operational amplifier, and the first op amp is connected to the negative input terminal. The other end of the five resistors is connected to the voltage output end, the positive phase input end of the second operational amplifier is connected to the RC filter circuit, the output end is connected to the anode of the second diode, and the cathode of the second diode is connected to the sixth resistor One end is connected to the inverting input end of the second operational amplifier, the other end of the sixth resistor is connected to the voltage output end, and the potential of the non-inverting input end of the first operational amplifier is higher than the potential of the non-inverting input end of the second operational amplifier.

The voltage dynamic adjustment circuit of the power factor corrector includes a voltage divider circuit, a first switch circuit and a second switch circuit, the voltage divider circuit has first, second and third voltage divider points, one end of the fifth resistor is connected to the The first voltage dividing point is connected, the other end of which is connected to the voltage output terminal, the first switch circuit and a resistor are connected in series between the first or second voltage dividing point and the voltage output terminal, the second switch circuit is connected to a resistor Connected in series between the first or third voltage dividing point and the voltage output terminal, when the input voltage suddenly increases, the first switch circuit is turned on, and the current flows into the voltage output terminal through the fifth resistor and the resistor connected to the first switch circuit , when the input voltage suddenly drops, the second switch circuit is turned on, and the current flows from the voltage output terminal into the fifth resistor and the resistor connected to the second switch circuit.

The first switch circuit includes a first operational amplifier and a first diode, the second switch circuit includes a second operational amplifier and a second diode, and the non-inverting input terminal of the first operational amplifier is connected to the first Two voltage divider points, the output end of which is connected to the cathode of the first diode, the anode of the first diode is connected to one end of the sixth resistor and the inverting input end of the first operational amplifier, and the other end of the sixth resistor is connected to the voltage output terminal, the positive phase input terminal of the second operational amplifier is connected to the third voltage dividing point, its output terminal is connected to the anode of the second diode, and the cathode of the second diode is connected to one end of the seventh resistor and the second operational amplifier The inverting input terminal of the amplifier, and the other end of the sixth resistor is connected to the voltage output terminal.

The first and second diodes are single diodes or pairs of diodes connected in parallel.

The first switch circuit is a first diode, the second switch circuit is a second diode, the cathode of the first diode is connected to the second voltage dividing point, and its anode is connected to one end of the sixth resistor. The other end of the resistor is connected to the voltage output end, the anode of the second diode is connected to the third voltage dividing point, the cathode thereof is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the voltage output end.

The first and second switch circuits are anti-parallel first and second diodes, wherein the cathode of the first diode and the anode of the second diode are connected to the first voltage dividing point, and the first diode The anode of the tube and the cathode of the second diode are connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the voltage output end.

The beneficial effect of the present invention is that, through the arrangement of the first and second switch circuits, when the input voltage changes, the output voltage can respond in time and be dynamically adjusted, thereby improving the dynamic performance of the power factor corrector.

Description of drawings

FIG. 1 is a schematic circuit diagram of a first embodiment of a voltage dynamic adjustment circuit of a power factor corrector of the present invention.

Fig. 2 is a schematic circuit diagram of a second embodiment of the voltage dynamic adjustment circuit of the power factor corrector of the present invention.

Fig. 3 is a schematic circuit diagram of a third embodiment of the voltage dynamic adjustment circuit of the power factor corrector of the present invention.

Fig. 4 is a schematic circuit diagram of a fourth embodiment of the voltage dynamic adjustment circuit of the power factor corrector of the present invention.

Fig. 5 is a schematic circuit diagram of a fifth embodiment of the voltage dynamic adjustment circuit of the power factor corrector of the present invention.

FIG. 6 is a schematic circuit diagram of a sixth embodiment of the voltage dynamic adjustment circuit of the power factor corrector of the present invention.

Detailed ways

Referring to Fig. 1, the control circuit of the PFC circuit of the present invention includes a three-stage filter circuit and first and second switch circuits, and the three-stage filter circuit includes a first-stage filter circuit composed of a first resistor R1 and a first capacitor C1, The second-stage filter circuit composed of the second resistor R2 and the second capacitor C2 and the third-stage filter circuit composed of the fourth resistor R4 and the third capacitor C3, the first and second switch circuits are a pair of anti-parallel Diode D1. One end of the first resistor R1 is connected to the input rectified voltage signal Vac, the other end is connected to one end of the first capacitor C1 and one end of the second resistor R2, the other end of the first capacitor C1 is grounded, and the other end of the second resistor R2 Connect one end of the second capacitor C2, one end of the third resistor R3 and one end of the fourth resistor R4, the other end of the second capacitor C2 and the other end of the third resistor R3 are grounded, and the other end of the fourth resistor R4 is connected to the output voltage Vrms and one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded. The pair of anti-parallel diodes D1 is connected in parallel with both ends of the fourth resistor R4.

The working principle of the circuit is as follows: In the steady state, the diode D1 will not conduct due to the small voltage difference between the two ends, and the three-stage RC filter circuit composed of R1C1, R2C2 and R4C3 can make the input rectified voltage signal Vac Filter straight enough so that the THD is small. When the input voltage suddenly fluctuates in a large range, when the voltage difference between the two ends of the diode D1 exceeds the conduction voltage of the diode D1, the diode D1 is turned on, so that the third capacitor C3 is directly connected in parallel with the second capacitor C2, and the filter circuit is equivalent to two stage RC filter circuit, so it can respond to the change of the input voltage Vac faster than the existing situation without the parallel diode D1, thereby improving the input dynamic response performance of the power factor corrector.

In this embodiment, since the Vac signal is a high-voltage signal, the third resistor R3 is arranged as a voltage dividing resistor to obtain a signal of an appropriate potential; the pair of anti-parallel diodes D1 can also be connected in parallel to the resistor R1 or R2, and its working The principle is as mentioned above, and the purpose of reducing one level of filtering is achieved by connecting two sets of capacitors in parallel, thereby speeding up the response speed of Vrms to Vac.

Please refer to FIG. 2 , which is a second specific embodiment of the present invention. The three-stage filter circuit of the dynamic adjustment circuit includes a first-stage filter circuit composed of a first resistor R1 and a first capacitor C1, a second-stage filter circuit composed of resistors R21, R22 and a second capacitor C2, and a fourth stage filter circuit composed of a fourth resistor A third-stage filter circuit formed by R4 and the third capacitor C3. The first switch circuit includes a first operational amplifier A1, a first diode D1 and a fifth resistor R5, and the second switch circuit includes a second operational amplifier A2, a second diode D2 and a sixth resistor R6. One end of the first resistor R1 is connected to one end of the first capacitor C1 and one end of the resistor R21, the other end of the first capacitor C1 is grounded, the other end of the resistor R21 is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to the second One end of the capacitor C2, one end of the resistor R31 and one end of the fourth resistor R4, the other end of the second capacitor C2 is grounded, the other end of the resistor R31 is connected to one end of the resistor R32, the other end of the resistor R32 is grounded, and the resistor R4 The other end of Vrms is connected to the output voltage Vrms and one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded. The positive phase input terminal of the first operational amplifier A1 is connected to the junction of resistors R21 and R22, its output terminal is connected to the cathode of the first diode D1, its inverting input terminal is connected to the anode of the first diode D1, and the fifth resistor One end of R5 is connected to the anode of the first diode D1, and the other end is connected to the voltage output Vrms. The positive-phase input terminal of the second operational amplifier A2 is connected to the junction of resistors R31 and R32, its output terminal is connected to the anode of the second diode D2, its inverting input terminal is connected to the cathode of the second diode D2, and the sixth resistor One end of R6 is connected to the cathode of the second diode D2, and the other end is connected to the voltage output Vrms.

The working principle of this circuit is as follows: the resistance values of resistors R5 and R6 are much smaller than the resistance value of resistor R4; resistors R22 and R31 determine the limit value of the sudden change of input voltage that the dynamic circuit works, and its derivation process is as follows

，那么Vrms为Assuming that the input voltage is V _AC1 in a certain steady state, its average value is

, then Vrms is

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; rmsl</span>}<span\; class="notranslate">\; =</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; AC</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 32</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 32</span>}}}$

At this time, due to the blocking of diodes D1 and D2, the voltage relationship of each point in the circuit is

V2=V4=V5=V _rms1 , V1>V5, V3<V5. In the steady state, the voltage at V1 is greater than V5 due to the relationship of voltage division, and the output of A1 is the positive saturation voltage of the op amp, which is greater than Vrms (generally, the positive saturation voltage of the op amp is close to the power supply voltage), so D1 is cut off, and Vrms passes through R5. The ground is the inverting terminal of A1, and the input of the operational amplifier is high impedance, so the voltage of V2 is equal to Vrms; at the same time, in the steady state, V3<Vrms, so the output of the A2 operational amplifier is low saturation, which is close to the negative power supply of the operational amplifier, so the output voltage of the operational amplifier is <Vrms, D2 is cut off, similarly, Vrms is grounded through R6 and the high-impedance input of A2, V4=Vrms.

)，Vrms还来不及立刻变化而保持原来的值V_rms1，而V1的电压可以立刻按比例反应出输入电压的降低，When the input voltage suddenly drops to V _AC2 (the average value is

), Vrms has no time to change immediately and maintains the original value V _rms1 , and the voltage of V1 can immediately reflect the decrease of the input voltage proportionally,

Right now ${\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_1=\stackrel{\&OverBar;}{V_{\mathrm{AC}2}}*\frac{R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_{\mathrm{twenty\; one}}+R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}$

When V1<V2, that is, V1<V _rms1 , the output terminal of the first operational amplifier A1 recirculates the current, and the first diode D1 is turned on. After the first diode D1 is turned on, V2 follows V1, that is, V2=V1 , and because V1<V _rms1 , the third capacitor C3 discharges to the first operational amplifier A1 through the fifth resistor R5. In this way, the third capacitor C3 has two discharge paths, one is to discharge through the resistors R4, R31, R32, and the other is to discharge to the first operational amplifier A1 through the resistor R5. Since the impedance of the resistor R5 is much smaller than the impedance of the branches R4, R31, and R32, the discharge speed of the third capacitor C3 is greatly increased compared with the case where the dynamic circuit is not added, so that Vrms can respond to the input voltage faster fall.

From the above analysis, we can know that the condition for branch A1, D1, R5 to work is V1<V _rms1 that is $\stackrel{\&OverBar;}{V_{\mathrm{AC}2}}*\frac{R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_{\mathrm{twenty\; one}}+R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}<\stackrel{\&OverBar;}{V_{\mathrm{AC}1}}*\frac{R_{31}+R_{32}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_{\mathrm{twenty\; one}}+R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}$

can be obtained from the above formula $\frac{V_{\mathrm{AC}2}}{V_{\mathrm{AC}1}}=\frac{\stackrel{\&OverBar;}{V_{\mathrm{AC}2}}}{\stackrel{\&OverBar;}{V_{\mathrm{AC}1}}}<\frac{R_{31}+R_{32}}{R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}=1-\frac{R_{\mathrm{twenty\; two}}}{R_{\mathrm{twenty\; two}}+R_{31}+R_{32}}$

时，动态支路A1D1R5将起作用。That is, when the input voltage drops suddenly and the change exceeds

, the dynamic branch A1D1R5 will work.

In the same way, it can be analyzed that the conditions for the dynamic branches A2, D2, and R6 to work are

$\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; AC</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 32</span>}}}<span\; class="notranslate">\; ></span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; AC</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 32</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 31</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 32</span>}}}$

Right now $\frac{V_{\mathrm{AC}2}}{V_{\mathrm{AC}1}}=\frac{\stackrel{\&OverBar;}{V_{\mathrm{AC}2}}}{\stackrel{\&OverBar;}{V_{\mathrm{AC}1}}}>\frac{R_{31}+R_{32}}{R_{31}}=1+\frac{R_{32}}{R_{31}}$

时，动态支路运放器A2、二极管D2、电阻R6起作用，其结果是除了通过电阻R4给电容C3充电外，还有运放支路运放器A2、二极管D2、电阻R6给电容C3充电，从而使Vrms能更快的反应出输入电压的增加。That is, when the input voltage suddenly increases and the change exceeds

At this time, the dynamic branch op amp A2, diode D2, and resistor R6 work. As a result, in addition to charging the capacitor C3 through the resistor R4, there are also op amp A2, diode D2, and resistor R6 charging the capacitor C3. Charge, so that Vrms can respond to the increase of input voltage faster.

In this embodiment, it is sufficient to ensure that V1>V5>V3 in the steady state; the non-inverting input terminal of the first operational amplifier A1 may also be connected to the junction of the resistor R1 and the resistor R21; for A1, D1, R5 For the branch composed of A2, D2 and R6, it is also possible not to set the operational amplifier A1, A2 but only to set the diode and the resistor, and only need to ensure the difference between V1 and V3 and V3 in the steady state The difference between V5 and V5 should be less than the turn-on voltage drop of diodes D1 and D2.

Please refer to FIG. 3 , which is a third embodiment of the present invention. The dynamic adjustment circuit is a voltage feedback circuit in the bus control circuit, which includes a voltage divider circuit composed of resistors R1, R2, R3 and R4, and first and second switch circuits. The first switch circuit includes a first operational amplifier A1 and a first diode D1, and the second switch circuit includes a second amplifier A2 and a second diode D2.

Between the DC voltage input terminal Vpfc and the ground, resistors R1, R2, R3 and R4 are serially connected in series. One end of the resistor R5 is connected to the junction of the resistors R2 and R3, and the other end of the resistor R5 is connected to the voltage output Vfeed. The non-inverting input terminal of the first operational amplifier A1 is connected to the junction of the resistor R1 and the resistor R2, its output terminal is connected to the cathode of the first diode D1, and its inverting input terminal is connected to the anode of the first diode D1 , one end of the sixth resistor R6 is connected to the anode of the first diode D1, and the other end is connected to the output voltage Vfeed. The non-inverting input terminal of the second operational amplifier A2 is connected to the junction of the third resistor R3 and the fourth resistor R4, its output terminal is connected to the anode of the second diode D2, and its inverting input terminal is connected to the second diode D2 The cathode of D2 is connected, one end of the seventh resistor R7 is connected to the cathode of the second diode D2, and the other end is connected to the output voltage Vfeed.

The working principle of the circuit is as follows: the Vfeed voltage is stabilized at a reference voltage Vref by the operational amplifier of the PFC voltage loop and remains unchanged. Assuming that the PFC voltage is Vpfc1 under stable conditions, then

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="5"\; label="V"\; filenames="H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; feed</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}$

At the same time, V ₂ ＝V ₄ ＝V _feed (the principle is as follows: in the steady state, the voltage at V1 is greater than V5 due to the relationship of voltage division, and the output of A1 is the positive saturation voltage of the op amp, which is greater than Vfeed (generally, the positive saturation of the op amp The voltage is close to the power supply voltage), so D1 is cut off, Vfeed is the inverting terminal of A1 through R6, and the op amp input is high impedance, so the voltage of V2 is equal to Vfeed; at the same time, V3<Vfeed in the steady state, so A2 op amp The output is low saturation, close to the negative power supply of the operational amplifier, so the output voltage of the operational amplifier is <Vfeed, and D2 is cut off. Similarly, Vfeed is grounded through the high-impedance input of R7 and A2, V4=Vfeed), because V1>V5>V3, so V1> V2, V3<V4, at this time, D1 blocks the high output of A1, D2 blocks the low output of A2, and the dynamic circuit does not work.

When the PFC voltage has an overshoot and reaches Vpfc2 (Vpfc2>Vpfc1),

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="5"\; label="V"\; filenames="H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="V"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}$

V1 must be greater than Vfeed, that is, V1>V2, so the branch circuit of operational amplifier A1, diode D1, and resistor R6 still does not work, but with the increase of Vpfc2, V3 will be greater than Vfeed, that is, greater than V4. Amplifier A2 will output high level, and diode D2 will be turned on. Therefore, in addition to V5 injecting current into Vfeed, the branch circuit of op amp A2, diode D2, and resistor R7 also injects current into Vfeed, so that the voltage loop op amp (Vfeed is connected to the input of the voltage loop op amp) will be lower The output of the PFC speeds up the adjustment of the PFC voltage (that is, the final output voltage of the power factor regulator).

From the above analysis, it can be seen that the condition for the A2, D2, and R7 branches to work is V3>Vfeed

Right now ${\mathrm{<figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{pfc}}*\frac{R_4}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}>V_{\mathrm{feed}}$

again $V_{\mathrm{feed}}={\mathrm{<figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{pfc}}*\frac{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+R_4}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}$

therefore ${\mathrm{<figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{pfc}}*\frac{R_4}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}>{\mathrm{<figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{pfc}}*\frac{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+R_4}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}$

Right now $\frac{V_{\mathrm{pfc}2}}{{\mathrm{<figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{pfc}}}>\frac{{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+R_4}{{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}=1+\frac{R_3}{{\mathrm{<figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_4}$

时，A2、D2、R7支路将起作用，降低PFC电压环的输出，从而加快PFC电压的调节。That is, if the PFC voltage overshoot exceeds

When , the A2, D2, R7 branches will work to reduce the output of the PFC voltage loop, thereby speeding up the regulation of the PFC voltage.

Similarly, when the PFC voltage drops and reaches Vpfc2 (Vpfc2<Vpfc1), V3 must be smaller than V4, so D2 blocks the current recharge of A2, and the branch A2D2R7 does not work; on the other hand, when V1<V2, The output of the operational amplifier A1 is low level, and the diode D1 is turned on. As a result, in addition to the resistor R5 branch drawing current from Vfeed, the A1, D1, and R6 branches also draw current from Vfeed, so that the output of the PFC voltage loop is higher to adjust the PFC voltage faster.

The condition for A1, D1, and R6 branches to work is that V1<V2, that is

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="2"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; *</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; pfc</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; pfc"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}<span\; class="notranslate">\; <</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="4"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000022.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="H06180000220060526E000021.png,H06180000220060526E000031.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}}$

时，A1、D1、R6支路起作用。That is to say, when the PFC bus voltage drop exceeds

, A1, D1, R6 branches work.

Please refer to FIG. 4 , which is a fourth embodiment of the present invention. The dynamic adjustment circuit includes a voltage divider circuit composed of resistors R1, R2, R3 and R4. The first switch circuit includes a first operational amplifier A1 and a pair of diodes D1 connected in parallel in the same direction, and the second switch circuit includes a second operational amplifier A2 and a pair of diodes D2 connected in parallel in the same direction. Resistors R1, R2, R3 and R4 are connected in series between the input voltage Vpfc and the ground. One end of the fifth resistor R5 is connected to the junction of the resistors R2 and R3, and the other end of the fifth resistor R5 is connected to the output voltage Vfeed. The non-inverting input terminal of the first operational amplifier A1 is connected to the junction of the first resistor R1 and the second resistor R2, its output terminal is connected to the cathode of the pair of diodes D1, its inverting input terminal is connected to the anode of the pair of diodes D1, and the The anode of the diode D1 is also connected to one end of a sixth resistor R6, and the other end of the sixth resistor R6 is connected to the output voltage Vfeed. The non-inverting input terminal of the second operational amplifier A2 is connected to the junction of the third resistor R3 and the fourth resistor R4, its output terminal is connected to the anode of the pair of diodes D2, and its inverting input terminal is connected to the cathode of the pair of diodes D2, and the The cathode of the diode D2 is also connected to one end of a seventh resistor R7, and the other end of the seventh resistor R7 is connected to the output voltage Vfeed.

The working principle of the adjustment circuit is the same as that of the third embodiment. In the steady state, the first and second switching circuits do not work, and only work when the PFC voltage fluctuates to a certain extent. The first branch circuit composed of the first op amp tube A1, diode D1 and resistor R6 It works only when the PFC voltage drops, and the second branch composed of the second op amp tube A2, diode D2 and resistor R7 only works when the PFC voltage overshoots. Resistors R2 and R3 respectively determine the magnitude of PFC voltage drop and overshoot, and these two groups of branches will work only when the change of PFC voltage exceeds the limit value. Specifically, when the PFC bus voltage suddenly rises above the voltage limit determined by the resistor R3, the second branch composed of the second op amp tube A2, diode D2 and resistor R7 will work, and the result is that except for R5 In addition to the feedback voltage of this branch, the second branch is added as a voltage feedback branch, that is, two currents are injected into the Vfeed point, so that the PFC voltage loop can have a lower output to speed up the reduction of the PFC voltage. In the same way, when the PFC bus voltage suddenly drops beyond the voltage limit determined by resistor R3, the first branch composed of the first op amp tube A1, diode D1 and resistor R6 will work, and the result is that except R5 In addition to the branch feedback voltage, the first branch is added as a voltage feedback branch, that is, there are two ways to draw current from the Vfeed point, so that the PFC voltage loop can have a higher output to speed up the PFC voltage increase.

Please refer to FIG. 5 , which is a fifth embodiment of the present invention. The dynamic adjustment circuit includes a voltage divider circuit composed of resistors R1, R2, R3 and R4. The first switch circuit includes a first diode D1, and the second switch circuit includes a second diode D2. Between the input voltage Vpfc and the ground, resistors R1, R2, R3 and R4 are serially connected in series. One end of the resistor R5 is connected to the junction of the resistors R2 and R3, and the other end of the resistor R5 is connected to the output voltage Vfeed. The cathode of the diode D1 is connected to the junction of the resistors R1 and R2, its anode is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the voltage output Vfeed. The anode of the diode D2 is connected to the junction of the resistors R3 and R4, the cathode thereof is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the voltage output Vfeed.

The working principle of this circuit is as described in the third embodiment. It is assumed that both the conduction voltage drops of the first diode D1 and the second diode D2 are Vf. Then when the PFC voltage has an overshoot, so that V3 is greater than (Vfeed+Vf), the second diode D2 is turned on, so that there is one path formed by the fifth resistor R5 and another path composed of D1 and R6 to inject current into Vfeed. The input of the PFC voltage loop will be lower; and when the PFC voltage is undervoltage and V1 is less than (Vfeed-Vf), the first diode D1 is turned on, so that the circuit formed by the fifth resistor R5 and the circuit formed by D1 , R6 constitutes another way to extract current from Vfeed, and the output of the PFC voltage loop is higher, thereby adjusting the PFC voltage faster.

Please refer to FIG. 6 , which is the sixth specific implementation manner of this embodiment. The dynamic adjustment circuit includes a voltage divider circuit composed of resistors R1, R2, R3 and R4. The first and second switch circuits are a pair of anti-parallel diodes D1. Between the input voltage Vpfc and the ground, resistors R1, R2, R3 and R4 are serially connected in series. One end of the resistor R5 is connected to the junction of the resistors R2 and R3, and the other end of the resistor is connected to the output voltage Vfeed. One end of the diode D1 is connected to the junction of the resistor R3 and the resistor R5, the other end of the diode D1 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the voltage output Vfeed. Wherein, the resistance value of the resistor R6 is much smaller than the resistance value of the R5.

The working principle of the control circuit is as follows: in a steady state, the pfc voltage is Vpfc1, and the Vfeed voltage is stabilized at a reference voltage Vref by the operational amplifier of the PFC voltage loop, and V5=Vfeed. When the pfc voltage overshoots, V5 will rise immediately. When the voltage difference between V5 and Vfeed exceeds the conduction voltage drop Vf of the diode D1, the forward diode conducts, and the impedance between V5 and Vrms changes from R5 to R5 and R6 in parallel. Since R6 is much smaller than R5, Therefore, the parallel impedance is very small, and the current injected into Vfeed by V5 increases significantly, so that the output of the PFC voltage loop is lower, thereby speeding up the adjustment of the PFC voltage. Similarly, when the PFC voltage suddenly undervoltage, V5 will drop immediately, and when the voltage difference between V5 and Vfeed exceeds the conduction voltage drop Vf of the diode D1, the backward diode conducts, and the impedance between V5 and Vrms becomes R5 and R6 are connected in parallel, so that V5 draws a larger current from Vfeed, so the voltage loop will have a higher output voltage to adjust the PFC voltage faster.

In this circuit, the overshoot and undervoltage, the action voltage of the dynamic circuit are the same, both are

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时，动态电路起作用。That is, when the PFC voltage overshoot value exceeds

, the dynamic circuit works.

时，动态电路起作用。PFC voltage undervoltage exceeds

, the dynamic circuit works.

In this embodiment, the pair of anti-parallel diodes (ie, a single dual diode) can also be regarded as composed of anti-parallel first and second diodes.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, they can also make some simple deduction or replacement, which should be regarded as belonging to the patent of the present invention determined by the submitted claims. protected range.

Claims (1)

1. A voltage dynamic adjustment circuit of a power factor corrector, comprising at least two stages of RC filter circuits accepting voltage input, characterized in that: it also includes first and second switch circuits, and the first and second switch circuits have preset The opening voltage is set, and one end of the first and second switching circuits is connected to the RC filter circuit, and the other end of the first and second switching circuits is connected to the voltage output end. When the input voltage suddenly increases, the first When the potential difference between the two ends of the switch circuit is greater than its turn-on voltage, the first switch circuit is turned on and the output voltage increases accordingly; when the input voltage suddenly drops so that the potential difference between the two ends of the second switch circuit is greater than its turn-on voltage, the second switch circuit The circuit is turned on and the output voltage decreases accordingly; The first switch circuit includes a first operational amplifier, a first diode and a fifth resistor, the second switch circuit includes a second operational amplifier, a second diode and a sixth resistor, and the first operational amplifier The non-inverting input terminal of the device is connected to the RC filter circuit, the output terminal is connected to the cathode of the first diode, the anode of the first diode is connected to one end of the fifth resistor and the inverting input terminal of the first operational amplifier, and the first op amp is connected to the negative input terminal. The other end of the five resistors is connected to the voltage output end, the positive phase input end of the second operational amplifier is connected to the RC filter circuit, the output end is connected to the anode of the second diode, and the cathode of the second diode is connected to the sixth resistor One end and the inverting input end of the second operational amplifier, the other end of the sixth resistor is connected to the voltage output end, and the potential of the positive phase input end of the first operational amplifier is higher than the potential of the voltage output end, the second operational amplifier The potential of the non-inverting input terminal is lower than the potential of the voltage output terminal.

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