WO2013158088A1 - Circuit fournissant des tensions continues à des lignes de signal différentiel par l'intermédiaire d'une impulsion de restauration - Google Patents

Circuit fournissant des tensions continues à des lignes de signal différentiel par l'intermédiaire d'une impulsion de restauration Download PDF

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Publication number
WO2013158088A1
WO2013158088A1 PCT/US2012/034043 US2012034043W WO2013158088A1 WO 2013158088 A1 WO2013158088 A1 WO 2013158088A1 US 2012034043 W US2012034043 W US 2012034043W WO 2013158088 A1 WO2013158088 A1 WO 2013158088A1
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WIPO (PCT)
Prior art keywords
differential signal
voltage
differential
restore pulse
logic
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Application number
PCT/US2012/034043
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English (en)
Inventor
Jose Miguel Rodriguez
Original Assignee
Hewlett-Packard Development Company, L.P.
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Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2012/034043 priority Critical patent/WO2013158088A1/fr
Publication of WO2013158088A1 publication Critical patent/WO2013158088A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541—Specific driving circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04555—Control methods or devices therefor, e.g. driver circuits, control circuits detecting current
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/015—Ink jet characterised by the jet generation process
    • B41J2/04—Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045—Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501—Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0458—Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on heating elements forming bubbles
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H04L25/0274—Arrangements for ensuring balanced coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H04L25/0296—Arrangements to ensure DC-balance

Definitions

  • printers include high voltage supply lines, where the coexistence of different voltages in the same integrated circuit die and interconnect poses a challenge to printer electronics. If printhead contacts are exposed to ink droplets, the contacts build up conductive paths between them, shorting the contacts together. The chance of ink shorts increases with the amount of ink consumed. Also, die failure may short a high voltage supply line to the low voltage communication channels.
  • Fault protection is often achieved by specialized protection circuits based on series metal oxide semiconductor field effect transistors (MOSFETs) or clamping diodes on the communication channels. These circuits are integrated into application specific integrated circuits (ASICs) or implemented with discrete components. Either way, valuable real estate is used on the die or printed circuit board.
  • MOSFETs series metal oxide semiconductor field effect transistors
  • ASICs application specific integrated circuits
  • Figure 1 is a diagram illustrating one example of an Inkjet printing system that includes a fault protection system.
  • Figure 2 is a diagram illustrating a portion of one example of a printhead die for ejecting ink.
  • Figure 3 is a diagram illustrating a fault protection system.
  • Figure 4 is a timing diagram illustrating DC level restoration in a fault protection system.
  • Figure 5 is a diagram illustrating one example of DC level restoration in a prototype circuit that includes a fault protection system.
  • Figure 6 is a diagram illustrating one example of a restoration window and a restore pulse in a prototype circuit that includes a fault protection system.
  • Some printers such as inkjet printers, include inkjet printheads that receive higher voltages on voltage supply lines. These voltages are used for ejecting ink from the printheads and are higher than the voltages in
  • LVDS low voltage differential signaling
  • Fault protection is built into the communication channels to enable the die to survive high voltage events.
  • Series capacitors in the communication channels can be used to block DC voltages while transmitting a data stream.
  • the data stream is DC balanced.
  • Line coding techniques such as 8b/10b or 64b/66b, can be used to DC balance the data stream. However, these line coding techniques decrease the effective bandwidth of the channel, and the hardware for encoding and decoding takes up real estate on the die.
  • Figure 1 is a diagram illustrating one example of an inkjet printing system
  • Inkjet printing system 20 that includes a fault protection system that provides DC balance on a communications channel, such as an LVDS communications channel, and enables inkjet printing system 20 to survive high voltage events on the communications channel.
  • Inkjet printing system 20 is one example of a fluid ejection system that includes a fluid ejection device, such as inkjet printhead assembly or module 22, and a fluid supply assembly, such as ink supply assembly 24.
  • Inkjet printing system 20 also includes mounting assembly 26, media transport assembly 28, and electronic controller 30. At least one power supply 32 provides power to the various electrical components of inkjet printing system 20.
  • Inkjet printhead assembly 22 includes at least one printhead or printhead die 40 that ejects drops of ink through a plurality of orifices or nozzles 34 toward a print medium 36 so as to print onto the print medium 36.
  • Printhead 40 is one example of a fluid ejection device.
  • Printhead 40 receives data in differential signals on differential signal lines and provides DC voltages to the differential signal lines to maintain DC balance in the differential signal lines.
  • Printhead 40 provides a restore pulse based on detecting a change of state in the differential signals and, in response to the restore pulse, printhead 40 provides the DC voltages to the differential signal lines.
  • Print medium 36 can be any type of suitable sheet material, such as paper, card stock, transparencies, Mylar, fabric, and the like.
  • Nozzles 34 are arranged in one or more columns or arrays such that properly sequenced ejection of ink from nozzles 34 causes characters, symbols, and/or other graphics or images to be printed upon print medium 36 as inkjet printhead assembly 22 and print medium 36 are moved relative to each other. While the following description refers to the ejection of ink from printhead assembly 22, it is understood that other liquids, fluids or flowable materials, including clear fluid, may be ejected from printhead assembly 22.
  • Ink supply assembly 24 provides ink to printhead assembly 22 and includes a reservoir 38 for storing ink. As such, ink flows from reservoir 38 to inkjet printhead assembly 22. Ink supply assembly 24 and inkjet printhead assembly 22 can form either a one-way ink delivery system or a recirculating ink delivery system. In a one-way ink delivery system, substantially all of the ink provided to inkjet printhead assembly 22 is consumed during printing. In a recirculating ink delivery system, only a portion of the ink provided to printhead assembly 22 is consumed during printing. As such, ink not consumed during printing is returned to ink supply assembly 24.
  • inkjet printhead assembly 22 and ink supply assembly 24 are housed together in an inkjet cartridge or pen.
  • the inkjet cartridge or pen is one example of a fluid ejection device.
  • ink supply assembly 24 is separate from inkjet printhead assembly 22 and provides ink to inkjet printhead assembly 22 through an interface connection, such as a supply tube (not shown).
  • reservoir 38 of ink supply assembly 24 can be removed, replaced, and/or refilled.
  • reservoir 38 includes a local reservoir located within the cartridge and can also include a larger reservoir located separately from the cartridge. As such, the separate, larger reservoir serves to refill the local reservoir.
  • the separate, larger reservoir and/or the local reservoir can be removed, replaced, and/or refilled.
  • Mounting assembly 26 positions inkjet printhead assembly 22 relative to media transport assembly 28 and media transport assembly 28 positions print medium 36 relative to inkjet printhead assembly 22.
  • a print zone 37 is defined adjacent to nozzles 34 in an area between inkjet printhead assembly 22 and print medium 36.
  • inkjet printhead assembly 22 is a scanning type printhead assembly.
  • mounting assembly 26 includes a carriage (not shown) for moving inkjet printhead assembly 22 relative to media transport assembly 28 to scan print medium 36.
  • inkjet printhead assembly 22 is a non-scanning type printhead assembly. As such, mounting assembly 26 fixes inkjet printhead assembly 22 at a prescribed position relative to media transport assembly 28.
  • media transport assembly 28 positions print medium 36 relative to inkjet printhead assembly 22.
  • Electronic controller or printer controller 30 includes a processor, firmware, and other electronics, or any combination thereof, for communicating with and controlling inkjet printhead assembly 22, mounting assembly 26, and media transport assembly 28.
  • Electronic controller 30 receives data 39 from a host system, such as a computer, and usually includes memory for temporarily storing data 39.
  • Data 39 is sent to inkjet printing system 20 along an electronic, infrared, optical, or other information transfer path.
  • Data 39 represents, for example, a document and/or file to be printed. As such, data 39 forms a print job for inkjet printing system 20 and includes one or more print job commands and/or command parameters.
  • electronic controller 30 controls inkjet printhead assembly 22 for ejection of ink drops from nozzles 34.
  • electronic controller 30 defines a pattern of ejected ink drops that form characters, symbols, and/or other graphics or images on print medium 36. The pattern of ejected ink drops is determined by the print job commands and/or command parameters.
  • inkjet printhead assembly 22 includes one printhead 40.
  • inkjet printhead assembly 22 is a wide-array or multi-head printhead assembly.
  • inkjet printhead assembly 22 includes a carrier, which carries printhead dies 40, provides electrical communication between printhead dies 40 and electronic controller 30, and provides fluidic communication between printhead dies 40 and ink supply assembly 24.
  • Figure 2 is a diagram illustrating a portion of one example of a printhead die 40 for ejecting ink.
  • Printhead 40 includes an array of printing or fluid ejecting elements 42, formed on a substrate 44, which has an ink feed slot 46 formed therein.
  • ink feed slot 46 provides a supply of liquid ink to printing elements 42.
  • Ink feed slot 46 is one example of a fluid feed source.
  • Other examples of fluid feed sources include corresponding individual ink feed holes feeding corresponding vaporization chambers and multiple shorter ink feed trenches that each feed corresponding groups of fluid ejecting elements.
  • a thin-film structure 48 has an ink feed channel 54 formed therein which communicates with ink feed slot 46 formed in substrate 44.
  • An orifice layer 50 has a front face 50a and a nozzle opening 34 formed in front face 50a. Orifice layer 50 also has a nozzle chamber or vaporization chamber 56 formed therein which communicates with nozzle opening 34 and ink feed channel 54 of thin-film structure 48.
  • a firing resistor 52 is positioned within vaporization chamber 56 and leads 58 electrically couple firing resistor 52 to circuitry controlling the application of electrical current through selected firing resistors.
  • a drop generator 60 as referred to herein includes firing resistor 52, nozzle chamber or vaporization chamber 56 and nozzle opening 34.
  • Nozzle opening 34 is operatively associated with firing resistor 52 such that droplets of ink within vaporization chamber 56 are ejected through nozzle opening 34 (e.g., substantially normal to the plane of firing resistor 52) and toward print medium 36 upon energizing of firing resistor 52.
  • Examples of printhead die 40 include a thermal printhead, a piezoelectric printhead, an electrostatic printhead, or any other type of fluid ejection device known in the art that can be integrated into a multi-layer structure.
  • FIG. 3 is a diagram illustrating a fault protection system 100 that provides DC balance on a communications channel 102 and isolates high voltage faults from electronics in the communications channel 102.
  • Fault protection system 100 uses AC coupling to isolate the high voltage faults from electronics in communications channel 102, and DC level restore to maintain data integrity in communications channel 102.
  • Fault protection system 100 provides up to 99.7% of maximum bandwidth.
  • fault protection system 100 is in a fluid ejection device.
  • fault protection system 100 is in an inkjet printhead assembly or module, such as inkjet printhead assembly 22.
  • Fault protection system 100 includes integrated circuit 104, a first capacitor 106, a second capacitor 108, and a resistor 110.
  • integrated circuit 104 is in a printhead die, such as printhead die 40. In one example, integrated circuit 104 is in a thermal inkjet printhead die. In one example, one or more of first capacitor 106, second capacitor 108, and resistor 110 are discrete components. In one example, first capacitor 106, second capacitor 108, and resistor 110 are in a fluid ejection device. In one example, first capacitor 106, second capacitor 108, and resistor 110 are in an inkjet printhead assembly or module, such as inkjet printhead assembly 22.
  • Communications channel 102 is a differential signaling communications channel that receives a pair of differential signals.
  • Communications channel 102 includes a pair of differential signal paths 112 and 114.
  • One of the differential signal paths 112 and 114 such as first signal path 112, receives the non-inverted signal and the other, such as second signal path 114, receives the inverted signal.
  • Communications channel 102 including signal paths 112 and 114, communicates information, such as image data, addresses,
  • communications channel 102 is a high speed, differential signaling
  • communications channel 102 is a LVDS communications channel.
  • Capacitors 106 and 108 are AC coupling capacitors and DC blocking capacitors that pass high speed, low voltage differential signals and block DC voltages, such as voltages used for ejecting ink from a printhead. Capacitors 106 and 108 are electrically coupled to integrated circuit 104 via a pair of differential signal lines 116 and 118. One side of first capacitor 106 is electrically coupled to first signal path 112 and the other side of first capacitor 106 is electrically coupled to integrated circuit 104 via first differential signal line 116. One side of second capacitor 108 is electrically coupled to second signal path 114 and the other side of second capacitor 108 is electrically coupled to integrated circuit 104 via second differential signal line 118.
  • each of the capacitors 106 and 108 blocks a DC voltage of 30 volts or more.
  • Resistor 110 is a termination resistor that terminates the differential signal pair on differential signal paths 112 and 114. One side of resistor 110 is electrically coupled to one side of first capacitor 106 via first signal path 112, and the other side of resistor 110 is electrically coupled to one side of second capacitor 108 via second signal path 114. In one example, resistor 110 is 100 ohms.
  • Integrated circuit 104 addresses DC balance on differential signal lines 116 and 118 via DC level restore of coupling capacitors 106 and 108. If DC balance is not addressed, long strings of 1 's or O's on signal paths 112 and 114 result in the differential signals on differential signal lines 116 and 118 drifting toward each other, which can result in communication errors. For example, a long string of logic 1 voltage levels on signal paths 112 and 114 creates DC levels that charge capacitors 106 and 108. The voltages of the signals transmitted through capacitors 106 and 108 drift toward each other, resulting in a smaller difference between the differential signals.
  • Integrated circuit 104 compensates for this drift in the differential signals on differential signal lines 116 and 118 by providing DC level restore voltages to differential signal lines 116 and 118. In one example, integrated circuit 104 provides DC level restore voltages in every data frame.
  • Integrated circuit 104 receives differential signals on differential signal lines 116 and 118 and includes differential receiver 120 that is electrically coupled to each of the differential signal lines 116 and 118.
  • Differential receiver 120 receives the differential signals on differential signal lines 116 and 118 and provides an output signal at 122.
  • differential receiver 120 includes a minimum high threshold level VIH for a logic 1 and a maximum low threshold level VIL for a logic 0, for determining the output signal at 122.
  • Integrated circuit 104 includes a timing block 124, a first switch 126, a second switch 128, a differential voltage source reference 130, a DC bias voltage source 132, and resistors 134 and 136.
  • Differential voltage source reference 130 includes a first voltage source 138 and a second voltage source 140, where first voltage source 138 provides a first DC level restore voltage V1 and second voltage source 140 provides a second DC level restore voltage V2.
  • Timing block 124 is electrically coupled to each of the differential signal lines 116 and 118, and timing block 124 is electrically coupled to the control input of first switch 126 and the control input of second switch 128 via restore pulse path 142.
  • One side of first switch 126 is electrically coupled to first differential signal line 116 and the other side of first switch 126 is electrically coupled to first voltage source 138 via first voltage path 144.
  • One side of second switch 128 is electrically coupled to second differential signal line 118 and the other side of second switch 128 is electrically coupled to second voltage source 140 via second voltage path 146.
  • first switch 126 is an NMOS transistor and second switch 128 is an NMOS transistor.
  • First switch 26 is electrically coupled on one side of its drain-source path to first differential signal line 116 and on the other side to first voltage source 138 via first voltage path 144.
  • Second switch 128 is electrically coupled on one side of its drain-source path to second differential signal line 118 and on the other side to second voltage source 140 via second voltage path 146.
  • Timing block 124 is electrically coupled to the gate of first switch 122 and to the gate of second switch 124 via restore pulse path 142.
  • First voltage source 138 is electrically coupled to second voltage source 140 and to one side of DC bias voltage source 132 via voltage source path 148.
  • One side of resistor 134 is electrically coupled to first differential signal line 116, and one side of resistor 136 is electrically coupled to second differential signal line 118.
  • the other sides of resistors 134 and 136 are electrically coupled to DC bias voltage source 132 via voltage source path 148, and the other side of DC bias voltage source 132 is electrically coupled to a reference, such as ground, at 150.
  • DC bias voltage source 132 provides DC bias voltage Vb to first voltage source 138 and second voltage source 140.
  • DC bias voltage source 132 also provides DC bias voltage Vb to resistors 134 and 136, which are coupled to differential signal lines 116 and 118, respectively.
  • First voltage source 138 receives DC bias voltage Vb and provides first DC restore voltage V1 , such that the voltage provided to first switch is Vb+V1.
  • First DC level restore voltage V1 is a negative voltage that lowers the DC level on first differential signal line 116 below DC bias voltage Vb.
  • Second voltage source 140 receives DC bias voltage Vb and provides a second DC level restore voltage V2, such that the voltage provided to second switch 128 is Vb+V2.
  • Second DC level restore voltage V2 is a positive voltage that raises the DC level on second differential signal line 118 above DC bias voltage Vb.
  • Timing block 124 is a pulse generator synchronized to the data frame frequency. Timing block 124 detects a transition in differential signals on differential signal lines 116 and 118 and provides a restore pulse based on the detected transition. Timing block 124 provides the restore pulse to the control inputs of first switch 126 and second switch 128, which biases on first switch 126 and second switch 128 such that the voltage Vb+V1 is provided to first differential signal line 116 and the voltage Vb+V2 is provided to second differential signal line 118. This restores the DC levels on differential signal lines 116 and 118 and maintains DC balance. In one example, timing block 124 detects a transition in differential signals on differential signal lines 116 and 118 and provides a restore pulse at the end of each data frame.
  • a system such as a printer, includes fault protection system 100.
  • the system and integrated circuit 104 are configured to use the same bit frequency and the same number of bits N per data frame.
  • the data frame period is chosen such that N bits of one logic value do not cross a high or low threshold in a given data frame and capacitance values of capacitors 106 and 108 are chosen large enough to pass information and small enough to be discharged during the restoration window.
  • the system At the end of a data frame, the system provides a logic 0 on first and second signal paths 112 and 114. While the system provides the logic 0 at the end of a data frame, timing block 124 provides the restore pulse on restore pulse path 142. This restores the DC levels on differential signal lines 116 and 118 and maintains DC balance.
  • the logic 0 time period at the end of the data frame is a DC voltage level restoration window for restoring DC voltage levels on differential signal lines 116 and 118.
  • Timing block 124 senses or detects a transition, such as a transition from logic 0 to logic 1 , in the differential signals on differential signal lines 116 and 118. In response to detecting the transition, timing block 124 starts a timer that counts to the restoration window. Timing block 124 generates the DC restore pulse synchronized with the restoration window based on the timer. In one example, timing block 124 resets the timer after providing the restore pulse. In one example, timing block 124 provides the restore pulse during the restoration window of every data frame. In other examples, timing block 124 provides the restore pulse during the restoration window of other suitable data frames, such as during the restoration window of every other data frame or every third data frame.
  • Timing block 124 provides the restore pulse on restore pulse path 142 to the control inputs of first switch 126 and second switch 128.
  • the restore pulse activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch 128 provides the voltage Vb+V2 to second differential signal line 118.
  • This restores the DC levels on differential signal lines 116 and 118 and prevents the differential signal voltages from drifting together and causing a communication error.
  • Differential receiver 120 receives the differential signals on differential signal lines 116 and 118 and provides the output signal at 122.
  • Fault protection system 100 includes less hardware than systems based on specialized protection circuits, such as MOSFETs or clamping diodes on the communication channels. Also, fault protection system 100 maintains DC balance without line coding techniques, such as 8b/10b or 64b/66b, which decrease the effective bandwidth of the channel. In addition, fault protection system 100 includes less hardware than systems that include the hardware for encoding and decoding. Fault protection system 100 maintains the reliability level of the communications channel and reduces the cost of the system for the customer.
  • Figure 4 is a timing diagram illustrating DC level restoration in fault protection system 100. Input signals Vin+ at 200 and Vin- at 202 are a differential pair of input signals on communications channel 102.
  • Input signal Vin+ at 200 is on first signal path 112 and input signal Vin- at 202 is on second signal path 114.
  • input signals Vin+ and Vin- transition to a logic 1 and, at 206, input signals Vin+ and Vin- provide a series of logic 1 bits in a data frame of N bits.
  • input signals Vin+ and Vin- transition to a logic 0 state, which is the restoration window.
  • Input signals Vin+ and Vin- transition to a logic 1 at 210 and provide another series of logic 1 bits in another data frame of N bits at 212.
  • input signals Vin+ and Vin- transition to a logic 0 state, and provide the restoration window at the end of the second data frame.
  • input signals Vin+ and Vin- transition to a logic 1 and provide another series of logic 1 bits in another data frame of N bits at 218.
  • Differential signal Vd+ at 220 and differential signal Vd- at 222 are a differential pair of signals on differential signal lines 116 and 118 when timing block 124 does not provide a restore pulse and no DC restoration is provided by fault protection system 100.
  • Differential signal Vd+ at 220 is on first differential signal line 116 and differential signal Vd- at 222 is on second differential signal line 118.
  • Input signal Vin+ is transmitted through first capacitor 106 to provide differential signal Vd+ and input signal Vin- is transmitted through second capacitor 108 to provide differential signal Vd-, such that differential signal Vd+ corresponds to input signal Vin+ and differential signal Vd- corresponds to input signal Vin-.
  • differential signal Vd+ transitions to a high voltage for a logic 1 and, at 226, differential signal Vd- transitions to a low voltage for the logic 1.
  • differential signal Vd+ drifts to a lower voltage level at 228 and differential signal Vd- drifts to a higher voltage level at 230.
  • the difference in voltages Vd+ and Vd- remains above the minimum high threshold level VIH, indicated at 232 and 234.
  • the drift in differential signal Vd+ is due to charging of first capacitor 06 and the drift in differential signal Vd- is due to charging of second capacitor 108.
  • differential signal Vd+ transitions to a low voltage level and drifts higher during the logic 0 restoration window and, at 238, differential signal Vd- transitions to a high voltage level and drifts lower during the logic 0 restoration window.
  • the difference in the voltages Vd+ and Vd- remains below (more negative) than the maximum (more positive) low threshold level VI L (not shown for clarity), i.e., the absolute value of the difference in the voltages Vd+ and Vd- remains above a minimum low threshold level VIL
  • differential signal Vd+ transitions to a high voltage for the logic 1 and, at 242, differential signal Vd- transitions to a low voltage for the logic 1.
  • differential signal Vd+ drifts to a lower voltage level at 244 and differential signal Vd- drifts to a higher voltage level at 246.
  • the difference in the voltages Vd+ and Vd- remains above the minimum high threshold level VIH, indicated at 232 and 234.
  • differential signal Vd+ transitions to a low voltage level and drifts higher during the logic 0 restoration window and, at 250, differential signal Vd- transitions to a high voltage level and drifts lower during the logic 0 restoration window.
  • the difference in the voltages Vd+ and Vd- remains below (more negative) than the maximum (more positive) low threshold level VIL (not shown for clarity).
  • differential signal Vd+ transitions to a high voltage for the logic 1 and, at 254, differential signal Vd- transitions to a low voltage for the logic 1.
  • differential signal Vd+ drifts to a lower voltage level at 256 and differential signal Vd- drifts to a higher voltage level at 258.
  • differential signals Vd+ and Vd- drift below the minimum high threshold level VIH, indicated at 232 and 234, which results in a communications error.
  • timing block 124 does not provide a restore pulse and no DC restoration is provided by fault protection system 100, communications channel 102 provides communication errors.
  • Differential signal Vd+ at 264 and differential signal Vd- at 266 are signals on differential signal lines 116 and 118 when timing block 124 provides a restore pulse in restore pulse signal Vr at 268 and DC restoration is provided by fault protection system 100.
  • Differential signal Vd+ at 264 is on first differential signal line 116 and differential signal Vd- at 266 is on second differential signal line 118.
  • Input signal Vin+ is transmitted through first capacitor 106 to provide differential signal Vd+ and input signal Vin- is transmitted through second capacitor 108 to provide differential signal Vd-, such that differential signal Vd+ corresponds to input signal Vin+ and differential signal Vd- corresponds to input signal Vin-.
  • differential signal Vd+ transitions to a high voltage for the logic 1 and, at 272, differential signal Vd- transitions to a low voltage for the logic 1.
  • differential signal Vd+ drifts to a lower voltage level at 274 and differential signal Vd- drifts to a higher voltage level at 276.
  • the difference in voltages Vd+ and Vd- remains above the minimum high threshold level VI H, indicated at 278 and 280.
  • the drift in differential signal Vd+ is due to charging of first capacitor 106 and the drift in differential signal Vd- is due to charging of second capacitor 108.
  • differential signal Vd+ transitions to a low voltage level for the logic 0 restoration window and, at 284, differential signal Vd- transitions to a high voltage level for the logic 0 restoration window.
  • Timing block 124 receives differential signal Vd+ at 264 and differential signal Vd- at 266 and detects the transition to logic 1 at 270 and 272. In response to detecting the transition, timing block 124 starts a counter, counts a time period Trestore, and provides a restore pulse at 286 during the restoration window. The restore pulse at 286 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch 128 provides the voltage Vb+V2 to second differential signal line 118.
  • differential signal Vd+ transitions to a high voltage for the logic 1 and, at 294, differential signal Vd- transitions to a low voltage for the logic 1.
  • input signals Vin+ and Vin- providing the second series of logic 1 bits at 212, differential signal Vd+ drifts to a lower voltage level at 296 and differential signal Vd- drifts to a higher voltage level at 298.
  • differential signal Vd+ transitions to a low voltage level for the logic 0 restoration window and, at 302, differential signal Vd- transitions to a high voltage level for the logic 0 restoration window.
  • Timing block 124 receives differential signal Vd+ at 264 and differential signal Vd- at 266 and detects the transition to logic 1 at 292 and 294. In response to detecting the transition, timing block 124 starts a counter, counts the time period Trestore, and provides a restore pulse at 304 during the restoration window.
  • the restore pulse at 304 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch 128 provides the voltage Vb+V2 to second differential signal line 118.
  • Vd+ at 306 increases Vd+ at 306 to a higher voltage level and decreases Vd- at 308 to a lower voltage level, restoring the DC levels on differential signal lines 116 and 118, which prevents the difference in Vd+ at 264 and Vd- at 266 from drifting below the minimum high threshold VIH, indicated at 278 and 280.
  • differential signal Vd+ transitions to a high voltage for the logic 1 and, at 312, differential signal Vd- transitions to a low voltage for the logic 1.
  • differential signal Vd+ drifts to a lower voltage level at 314 and differential signal Vd- drifts to a higher voltage level at 316.
  • the difference in differential signals Vd+ at 264 and Vd- at 266 remains above the minimum high threshold level VIH, indicated at 278 and 280, maintaining the integrity of communications on communication channel 102.
  • the process repeats in other data frames, such that fault protection system 100 with DC restoration provides reliable
  • FIG. 5 is diagram illustrating one example of DC level restoration in a prototype circuit that includes fault protection system 100.
  • Input signal Vin(diff) at 400 is the difference in the voltages of the differential pair of input signals Vin+ and Vin- on first signal path 112 and second signal path 114.
  • input signal Vin(diff) provides a series of logic 1 bits in a data frame of N bits.
  • input signal Vin(diff) transitions to a logic 0 state, which is the restoration window.
  • Input signal Vin(diff) transitions to a logic 1 and provides another series of logic 1 bits in another data frame of N bits at 406.
  • input signal Vin(diff) transitions to a logic 0 state and provides the restoration window at the end of the second data frame.
  • input signal Vin(diff) transitions to a logic 1 and provides another series of logic 1 bits in another data frame of N bits.
  • input signal Vin(diff) transitions to a logic 0 state and provides the restoration window at the end of the third data frame.
  • input signal Vin(diff) transitions to a logic 1 and provides another series of logic 1 bits in another data frame of N bits.
  • Differential signal Vd(diff) at 416 is the difference in voltages of the differential pair of signals Vd+ and Vd- on differential signal lines 116 and 118, where timing block 124 provides a restore pulse in restore pulse signal Vr at 418.
  • Differential signal Vd(diff) at 416 transitions to a logic 1 and with input signal Vin(diff) providing the series of logic 1 bits at 402, differential signal Vd(diff) drifts to a lower voltage value at 420, but remains above the minimum high threshold level VIH.
  • the drift in differential signal Vd(diff) is due to the charging of first capacitor 106 and second capacitor 108.
  • differential signal Vd(diff) transitions to a logic 0 for the restoration window.
  • Timing block 124 receives differential signal Vd(diff) at 400 and detects a transition to the logic 1. In response to detecting the transition, timing block 124 starts a counter, counts a time period Trestore, and provides a restore pulse at 424 during the restoration window. The restore pulse at 424 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch 128 provides the voltage Vb+V2 to second differential signal line 118. This increases Vd(diff) at 426 to a higher voltage value, restoring the DC levels on differential signal line 116 and differential signal line 118 and preventing Vd(diff) from drifting below VIH.
  • Vd(diff) transitions to a logic 1 and with input signal
  • differential signal Vd(diff) drifts to a lower voltage level at 428, but remains above the minimum high threshold level VIH.
  • differential signal Vd(diff) transitions to the logic 0 restoration window.
  • Timing block 124 receives differential signal Vd(diff) at 400 and detects the transition to the logic 1. In response to detecting the transition, timing block 124 starts a counter, counts the time period Trestore, and provides a restore pulse at 432 during the restoration window. The restore pulse at 432 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch
  • Vd(diff) at 434 provides the voltage Vb+V2 to second differential signal line 118. This increases Vd(diff) at 434 to a higher voltage level, restoring the DC levels on differential signal line 116 and differential signal line 118 and preventing Vd(diff) at 416 from drifting below VIH.
  • Vd(diff) transitions to a logic 1 and with input signal
  • differential signal Vd(diff) drifts to a lower voltage level at 436, but remains above the minimum high threshold level VIH.
  • differential signal Vd(diff) transitions to the logic 0 restoration window.
  • Timing block 124 receives differential signal Vd(diff) at 400 and detects the transition to a logic 1. In response to detecting the transition, timing block 124 starts a counter, counts the time period Trestore, and provides a restore pulse at 440 during the restoration window. The restore pulse at 440 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch
  • Vd(diff) transitions to a logic 1 and with input signal Vin(diff) providing the fourth series of logic 1 bits at 414, differential signal , Vd(diff) drifts to a lower voltage level at 444, but remains above the minimum high threshold level VIH. This process continues without limit, maintaining the integrity and reliability of communications channel 102.
  • Figure 6 is a diagram illustrating one example of a restoration window and a restore pulse in a prototype circuit that includes fault protection system 100.
  • Input signal Vin(diff) at 500 is the difference in voltages of the differential pair of input signals Vin+ and Vin- on first signal path 112 and second signal path 114.
  • input signal Vin(diff) provides a series of logic 1 bits in a data frame of N bits.
  • input signal Vin(diff) transitions to a logic 0 state, which is the restoration window.
  • Input signal Vin(diff) transitions to a logic 1 at 506 and provides another series of logic 1 bits in another data frame of N bits at 508.
  • Differential signal Vd(diff) at 510 is the difference in voltages of the differential pair of signals Vd+ and Vd- on differential signal lines 116 and 118, where timing block 124 provides a restore pulse in restore pulse signal Vr at 512.
  • Differential signal Vd(diff) at 510 transitions to a logic 1 and with input signal Vin(diff) providing the series of logic 1 bits at 502, differential signal Vd(diff) drifts to a lower voltage value at 514, but remains above the minimum high threshold level VIH.
  • the drift in differential signal Vd(diff) is due to charging of first capacitor 106 and second capacitor 108.
  • differential signal Vd(diff) transitions to a logic 0 for the restoration window.
  • Timing block 124 receives differential signal Vd(diff) at 510 and detects a transition to a logic 1. In response to detecting the transition, timing block 124 starts a counter, counts a time period Trestore, and provides a restore pulse at 518 during the restoration window. The restore pulse at 518 activates or biases on first switch 126 and second switch 128, such that first switch 126 provides the voltage Vb+V1 to first differential signal line 116 and second switch 128 provides the voltage Vb+V2 to second differential signal line 118. This increases Vd(diff) at 520 to a higher voltage value, restoring the DC levels on differential signal line 116 and differential signal line 118 and preventing Vd(diff) from drifting below VIH.
  • Differential signal Vd(diff) transitions to a logic 1 and with input signal Vin(diff) providing the series of logic 1 bits at 508, differential signal Vd(diff) drifts to a lower voltage value at 522, but remains above the minimum high threshold level VIH.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un système qui comprend un circuit configuré pour recevoir des signaux différentiels sur des lignes de signal différentiel et pour fournir des tensions continues aux lignes de signal différentiel en réponse à une impulsion de restauration.
PCT/US2012/034043 2012-04-18 2012-04-18 Circuit fournissant des tensions continues à des lignes de signal différentiel par l'intermédiaire d'une impulsion de restauration WO2013158088A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/US2012/034043 WO2013158088A1 (fr) 2012-04-18 2012-04-18 Circuit fournissant des tensions continues à des lignes de signal différentiel par l'intermédiaire d'une impulsion de restauration

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2840746A1 (fr) * 2013-08-22 2015-02-25 Analog Devices, Inc. Rétablissement de courant continu pour signaux de synchronisation
US11331911B2 (en) 2019-02-06 2022-05-17 Hewlett-Packard Development Company, L.P. Die for a printhead
EP4116100A1 (fr) * 2021-07-08 2023-01-11 Seiko Epson Corporation Circuit de commande de tête d'impression et appareil d'éjection de liquide
EP4116101A1 (fr) * 2021-07-08 2023-01-11 Seiko Epson Corporation Tête d'impression et procédé d'inspection de tête d'impression

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Publication number Priority date Publication date Assignee Title
US4112512A (en) * 1977-03-23 1978-09-05 International Business Machines Corporation Semiconductor memory read/write access circuit and method
US5587681A (en) * 1993-10-29 1996-12-24 Plessey Semiconductors Limited DC restoration circuit
US6459447B1 (en) * 1998-09-30 2002-10-01 Fuji Photo Optical Co., Ltd. Video signal transmission device
US20090160522A1 (en) * 2007-12-19 2009-06-25 Van Den Brande Koen Dc restoration circuit allowing sparse data patterns
US7586329B2 (en) * 2004-08-31 2009-09-08 Micron Technology, Inc. Capacitively-coupled level restore circuits for low voltage swing logic circuits

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112512A (en) * 1977-03-23 1978-09-05 International Business Machines Corporation Semiconductor memory read/write access circuit and method
US5587681A (en) * 1993-10-29 1996-12-24 Plessey Semiconductors Limited DC restoration circuit
US6459447B1 (en) * 1998-09-30 2002-10-01 Fuji Photo Optical Co., Ltd. Video signal transmission device
US7586329B2 (en) * 2004-08-31 2009-09-08 Micron Technology, Inc. Capacitively-coupled level restore circuits for low voltage swing logic circuits
US20090160522A1 (en) * 2007-12-19 2009-06-25 Van Den Brande Koen Dc restoration circuit allowing sparse data patterns

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2840746A1 (fr) * 2013-08-22 2015-02-25 Analog Devices, Inc. Rétablissement de courant continu pour signaux de synchronisation
US9118305B2 (en) 2013-08-22 2015-08-25 Analog Devices, Inc. DC restoration for synchronization signals
US11331911B2 (en) 2019-02-06 2022-05-17 Hewlett-Packard Development Company, L.P. Die for a printhead
EP4116100A1 (fr) * 2021-07-08 2023-01-11 Seiko Epson Corporation Circuit de commande de tête d'impression et appareil d'éjection de liquide
EP4116101A1 (fr) * 2021-07-08 2023-01-11 Seiko Epson Corporation Tête d'impression et procédé d'inspection de tête d'impression
CN115593110A (zh) * 2021-07-08 2023-01-13 精工爱普生株式会社（Jp） 打印头以及打印头的检查方法

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