WO2013146035A1 - Semiconductor device and method for manufacturing same, display device, and electronic equipment - Google Patents

Semiconductor device and method for manufacturing same, display device, and electronic equipment Download PDF

Info

Publication number
WO2013146035A1
WO2013146035A1 PCT/JP2013/055090 JP2013055090W WO2013146035A1 WO 2013146035 A1 WO2013146035 A1 WO 2013146035A1 JP 2013055090 W JP2013055090 W JP 2013055090W WO 2013146035 A1 WO2013146035 A1 WO 2013146035A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
layer
electrodes
electrode
semiconductor device
Prior art date
Application number
PCT/JP2013/055090
Other languages
French (fr)
Japanese (ja)
Inventor
和雄 桧森
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Publication of WO2013146035A1 publication Critical patent/WO2013146035A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/88—Passivation; Containers; Encapsulations

Definitions

  • the present disclosure relates to a semiconductor device having a semiconductor element such as a thin film transistor (TFT), a manufacturing method thereof, and a display device and an electronic apparatus including such a semiconductor device.
  • a semiconductor element such as a thin film transistor (TFT)
  • TFT thin film transistor
  • Patent Document 1 In recent years, development of semiconductor elements using organic semiconductors such as organic TFTs has been promoted (see, for example, Patent Document 1).
  • the semiconductor element using the organic semiconductor is assumed to be applied to a display device such as a flexible organic EL (Electro Luminescence) display or flexible electronic paper, or an electronic device such as a flexible printed circuit board, an organic thin film solar cell, and a touch panel. .
  • a display device such as a flexible organic EL (Electro Luminescence) display or flexible electronic paper
  • an electronic device such as a flexible printed circuit board, an organic thin film solar cell, and a touch panel.
  • the semiconductor element semiconductor device
  • a semiconductor such as the above-described organic semiconductor
  • reliability of the element can be improved by suppressing deterioration of element characteristics or preventing a short circuit between electrodes. Improvement is required.
  • a semiconductor device includes one or a plurality of semiconductor elements.
  • This semiconductor element has a semiconductor layer, a plurality of electrodes electrically connected to the semiconductor layer, and an electrode separation layer disposed between the plurality of electrodes.
  • a display device includes the semiconductor device according to the embodiment of the present disclosure and a display unit.
  • An electronic apparatus includes the display device according to the embodiment of the present disclosure.
  • an electrode separation layer is provided between a plurality of electrodes electrically connected to the semiconductor layer in the semiconductor element.
  • the distance between the electrodes for example, the channel length in the channel region
  • the variation (variation) in the distance (channel length) at the time of electrode formation is increased. It can be suppressed.
  • a method of manufacturing a semiconductor device includes forming one or a plurality of semiconductor elements on a substrate, and forming the semiconductor element includes forming a semiconductor on the substrate. Forming a layer and a plurality of electrodes electrically connected to the semiconductor layer. In forming a plurality of electrodes, after forming an electrode separation layer having a predetermined pattern, a plurality of electrodes are formed by using a printing process on at least a part of the non-formation region of the electrode separation layer.
  • the method of manufacturing a semiconductor device when forming a semiconductor element, after an electrode separation layer having a predetermined pattern is formed, at least a part of the non-formation region of the electrode separation layer is formed.
  • a printing process By using a printing process, a plurality of electrodes electrically connected to the semiconductor layer are formed.
  • the distance between the electrodes for example, the channel length in the channel region
  • the distance (channel length) in the electrode formation using the printing process is Variation (variation) is suppressed.
  • the electrode separation layer is provided between the plurality of electrodes electrically connected to the semiconductor layer in the semiconductor element.
  • variation in the distance between the electrodes can be suppressed. Therefore, for example, it is possible to suppress deterioration of the characteristics of the element, to prevent a short circuit between electrodes, and to improve reliability.
  • the method for manufacturing a semiconductor device of one embodiment of the present disclosure when forming a semiconductor element, after forming an electrode separation layer having a predetermined pattern, at least a part of the non-formation region of the electrode separation layer is formed. Since the plurality of electrodes electrically connected to the semiconductor layer are formed by using the printing process, it is possible to suppress variations in the distance between the electrodes when forming the electrodes using the printing process. Therefore, for example, it is possible to suppress deterioration of the characteristics of the element, to prevent a short circuit between electrodes, and to improve reliability.
  • FIG. 3A is a cross-sectional diagram illustrating a process following the process in FIG. 3B.
  • FIG. 3C is a cross-sectional diagram illustrating a process following the process in FIG. 3C. It is sectional drawing showing the process of following FIG.
  • FIG. 4A It is sectional drawing showing the process of following FIG. 4A.
  • FIG. 4B is a cross-sectional diagram illustrating a process following the process in FIG. 4B.
  • FIG. 4D is a cross-sectional diagram illustrating a process following the process in FIG. 4C.
  • FIG. 7A It is sectional drawing showing the process of following FIG. 7B.
  • FIG. 7C It is sectional drawing showing the process of following FIG.
  • FIG. 7D It is sectional drawing showing the process of following FIG. 7D. It is sectional drawing showing the process of following FIG. 8A. It is sectional drawing showing the process of following FIG. 8B. It is sectional drawing showing the process of following FIG. 8C. It is sectional drawing showing the process of following FIG. 8D. It is sectional drawing showing the process of following FIG. 9A. It is sectional drawing showing the process of following FIG. 9B. It is sectional drawing showing the process of following FIG. 9C. It is sectional drawing showing the structural example of the thin-film transistor which concerns on 3rd Embodiment. It is sectional drawing showing the other structural example of the thin-film transistor which concerns on 3rd Embodiment. FIG.
  • FIG. 10 is a cross-sectional view illustrating an application example of a thin film transistor of each embodiment to a display device. It is a top view showing the application example shown to FIG. 12A.
  • FIG. 12B is a plan view schematically illustrating an arrangement example of electrode separation layers in the TFT layer illustrated in FIG. 12A.
  • FIG. 12B is a plan view schematically showing another arrangement example of the electrode separation layer in the TFT layer shown in FIG. 12A.
  • 13A is a perspective view illustrating an appearance of an application example 1 of the display device illustrated in FIGS. 12A and 12B to an electronic device.
  • FIG. 12A is a perspective view illustrating another appearance of application example 1 of the display device illustrated in FIGS. 12A and 12B to an electronic device.
  • FIG. 12A is a perspective view illustrating another appearance of application example 1 of the display device illustrated in FIGS. 12A and 12B to an electronic device.
  • FIG. 12 is a perspective view illustrating an appearance of application example 2.
  • FIG. 14 is a perspective view illustrating an appearance of Application Example 3 viewed from the front side.
  • FIG. 14 is a perspective view illustrating an appearance of Application Example 3 viewed from the back side.
  • FIG. 14 is a perspective view illustrating an appearance of application example 4.
  • FIG. 14 is a perspective view illustrating an appearance of application example 5.
  • FIG. (A) is a front view of the application example 6 in an open state
  • (B) is a side view thereof
  • (C) is a front view in a closed state
  • D) is a left side view
  • (E) is a right side view
  • (F) is a top view
  • (G) is a bottom view.
  • FIG. 1 schematically shows a schematic configuration example of the semiconductor element (thin film transistor 1) according to the first embodiment of the present disclosure in a cross-sectional view.
  • the thin film transistor 1 is of a top contact / bottom gate type used in, for example, an active matrix circuit of a display device.
  • the thin film transistor 1 includes, for example, a gate electrode 12, a gate insulating film 13, an organic semiconductor layer 14 (semiconductor layer), a pair of source / drain electrodes 15A and 15B (a plurality of electrodes), and an electrode separation layer (channel region) on a substrate 11.
  • the control layer 16 and the protective film 17 are stacked in this order. That is, the thin film transistor 1 is an organic TFT using an organic semiconductor.
  • the substrate 11 is made of, for example, an inorganic material such as glass, quartz, silicon, gallium arsenide, a metal material, or a plastic material.
  • the metal material include aluminum (Al), nickel (Ni), and stainless steel.
  • Plastic materials include polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), polyethyl ether ketone (PEEK), aromatic polyester ( Liquid crystal polymer).
  • the substrate 11 may be a rigid substrate such as a wafer, or may be a flexible substrate (flexible substrate) such as a thin glass layer, a film, or paper (general paper).
  • the surface of the substrate 11 may be provided with various layers such as a buffer layer for ensuring adhesion and a gas barrier layer for preventing gas release.
  • the gate electrode 12 functions as a gate electrode of the thin film transistor 1.
  • the gate electrode 12 is provided on the substrate 11 and is made of, for example, one or more of a metal material, an inorganic conductive material, an organic conductive material, and a carbon material.
  • the metal material include aluminum, copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel, palladium (Pd), gold (Au), silver (Ag), platinum (Pt), or An alloy containing them.
  • the inorganic conductive material include indium oxide (In 2 O 3 ), indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO).
  • the organic conductive material is, for example, polyethylene dioxythiophene (PEDOT) or polystyrene sulfonic acid (PSS).
  • the carbon material is, for example, graphite. Note that the gate electrode 12 may be formed by stacking two or more layers of the various materials described above.
  • the gate insulating film 13 is formed so as to cover the gate electrode 12, and is made of, for example, one or more of an inorganic insulating material and an organic insulating material.
  • the inorganic insulating material include silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), hafnium oxide (HfO x ), and barium titanate (BaTiO 3 ). 3 ).
  • the organic insulating material include polyvinylphenol (PVP), polyimide, polymethacrylic acid acrylate, photosensitive polyimide, photosensitive novolak resin, and polyparaxylylene. Note that the gate insulating film 13 may be formed by stacking two or more layers of the various materials described above.
  • the organic semiconductor layer 14 is formed in an island shape in the region where the thin film transistor 1 is formed, and is made of, for example, a PXX (peri-xanthenoxanthene) derivative.
  • the organic semiconductor layer 14 may be made of other organic semiconductor materials such as pentacene (C 22 H 14 ), Triisopropylsilylethynyl (TIPS) pentacene, polythiophene, and the like.
  • the source / drain electrodes 15 ⁇ / b> A and 15 ⁇ / b> B are electrodes disposed on the organic semiconductor layer 14 so as to be in contact with (electrically connected to) the organic semiconductor layer 14.
  • These source / drain electrodes 15A and 15B are each preferably made of a conductive material, in particular, a metal, a metal oxide, a conductive polymer, carbon, or the like that can provide ohmic contact with the organic semiconductor layer 14 as it is.
  • Examples of such a metal include gold (Au), copper (Cu), silver (Ag), nickel (Ni), and titanium (Ti).
  • a stacked structure in which a titanium (Ti) layer having a thickness of 20 nm, an aluminum (Al) layer having a thickness of 200 nm, and a titanium (Ti) layer having a thickness of 20 nm are stacked in this order may be employed.
  • the metal oxide include CuO x , NiO x , TiO x , ITO (Indium Tin Oxide), MoO x , and WO x .
  • the conductive polymer include water-soluble PEDOT-PSS.
  • the electrode isolation layer 16 is disposed on the gate insulating film 13 and the organic semiconductor layer 14 so as to surround the source / drain electrodes 15A and 15B, including between the source / drain electrodes 15A and 15B.
  • the electrode separation layer 16 is for controlling (defining) a channel region in the organic semiconductor layer 14, specifically, a channel length L (see FIG. 1) (channel region control layer).
  • the electrode separation layer 16 is continuously formed along the channel width direction at least on the region corresponding to the channel region in the organic semiconductor layer 14 with a length substantially the same as the channel length L (preferably the same).
  • Such an electrode separation layer 16 is made of an insulating material, and a material that does not damage the channel in the organic semiconductor layer 14 (a material that protects the channel), particularly a composition that includes a solvent that does not damage is used.
  • a composition formed by dissolving a fluorine-based resin or the like in a fluorine-based solvent, a composition formed by dissolving polyvinyl alcohol, ethyl cellulose or the like in water can be preferably exemplified.
  • a composition using a solvent such as alcohol or ether may be used.
  • the protective film 17 is disposed so as to cover at least a part of the source / drain electrodes 15 ⁇ / b> A and 15 ⁇ / b> B and the electrode separation layer 16.
  • This protective film 17 may be made of the same material as the electrode separation layer 16 described above, or may be made of a different material.
  • the protective film 17 can be formed using a technique such as coating or vapor deposition.
  • the protective film 17 is preferably a resin dissolved in a solvent that does not damage the organic semiconductor layer 14.
  • a fluororesin such as (C 6 F 10 ) n .
  • PVA polyvinyl alcohol; water-soluble
  • etc. other than the above-mentioned fluororesin can be illustrated.
  • the thin film transistor 1 can be manufactured, for example, as follows.
  • 2A to 4D are cross-sectional views showing main process examples in the method of manufacturing the thin film transistor 1 in order of processes.
  • the gate electrode 12 is formed on the substrate 11 as shown in FIGS. 2A to 2C.
  • a substrate 11 made of the above-described material is prepared.
  • the substrate 11 is made of the above-described metal material by, for example, a vacuum film forming method, a coating method, or a plating method.
  • An electrode film 120 is formed.
  • the vacuum film forming method include a vacuum deposition method, a flash deposition method, a sputtering method, a physical vapor deposition method (PVD), a chemical vapor deposition method (CVD), a pulse laser deposition method (PLD), or an arc discharge method.
  • the coating method include spin coating, slit coating, bar coating, and spray coating.
  • the plating method include an electrolytic plating method and an electroless plating method.
  • a resist film 81 (photoresist film) made of a predetermined mask pattern (resist pattern) is formed on the electrode film 120.
  • the resist film 81 is removed using an ashing method or an etching method.
  • the gate electrode 12 is formed on the substrate 11 as shown in FIG. 2C.
  • a photolithography method, a laser drawing method, an electron beam drawing method, an X-ray drawing method, or the like is used. To pattern the photoresist film.
  • the resist pattern may be formed using a resist transfer method or the like.
  • the etching method of the electrode film 120 is, for example, a dry etching method or a wet etching method using an etchant solution, and the dry etching method is, for example, ion milling or reactive ion etching (RIE).
  • RIE reactive ion etching
  • the formation method of the gate electrode 12 may be a printing method such as an inkjet method, a screen printing method, a gravure printing method, or a gravure offset printing method.
  • a metal pattern may be formed instead of the resist pattern as a mask using a laser ablation method, a mask vapor deposition method, a laser transfer method, or the like.
  • the above-described inorganic conductive material, organic conductive material, or carbon material can be used instead of the metal material.
  • a gate insulating film 13 is formed so as to cover the gate electrode 12.
  • the formation procedure of the gate insulating film 13 differs depending on, for example, the formation material.
  • the formation procedure in the case of using an inorganic insulating material is the same as that for forming the gate electrode 12 except that, for example, the coating method may be a sol-gel method.
  • the formation procedure in the case of using the organic insulating material is the same as that in the case of forming the gate electrode 12 except that the photosensitive material may be patterned using, for example, a photolithography method.
  • An example of a method for forming the gate insulating film 13 is a method in which a mixed solution of, for example, PVP (polyvinylphenol) and a curing agent (for example, melamine resin) is applied and baked by, for example, a spin coating method. Can be mentioned.
  • PVP polyvinylphenol
  • a curing agent for example, melamine resin
  • the organic semiconductor layer 14 is formed on the gate insulating film 13 by using, for example, a coating method or a vapor deposition method.
  • a solution (mixed solution) in which the above-described organic semiconductor material, for example, a PXX derivative is dispersed or dissolved in a solvent such as an organic solvent is prepared, and this mixed solution is applied to the upper surface of the gate insulating film 13. And heating (firing).
  • the coating method include spin coating, slit coating, cap coating, printing, and inkjet, but are not particularly limited.
  • the organic semiconductor layer 14 made of the above-described organic semiconductor material, for example, a PXX derivative is formed on the gate insulating film 13.
  • the solvent for example, toluene, xylene, mesitylene, tetralin, or the like can be used.
  • the organic semiconductor layer 14 is formed by, for example, RIE or wet etching using a resist film 82 (photoresist film) made of a predetermined mask pattern (resist pattern). Patterning is performed.
  • the element isolation method is not limited to this, and for example, laser ablation may be used.
  • the organic semiconductor layer 14 can be directly patterned using a printing method such as a reverse offset printing method.
  • Source / drain electrodes 15A and 15B are formed on the organic semiconductor layer 14 so as to be in contact with the organic semiconductor layer 14 (so as to be electrically connected).
  • the source / drain electrodes 15A and 15B are formed by using a printing method (printing process). Further, after the electrode separation layer 16 having the predetermined pattern is formed, the source / drain electrodes 15A and 15B are formed by using a printing method on at least a part of the non-formation region of the electrode separation layer 16. That is, here, the electrode / separation layer 16 is used to form the source / drain electrodes 15A and 15B. At this time, the electrode separation layer 16 can also be formed using a printing method. Examples of the printing method for forming the source / drain electrodes 15A and 15B and the electrode separation layer 16 in this way include a transfer printing method such as a reverse printing method, a gravure offset method, and an inkjet method. There is no limitation. Hereinafter, in the present embodiment, a case where the source / drain electrodes 15A and 15B and the electrode separation layer 16 are formed by using the reverse printing method will be described.
  • the electrode separation layer 16 having the predetermined pattern described above is formed on the transfer plate 91.
  • the electrode separation layer 16 on the transfer plate 91 is transferred to the above-mentioned positions on the gate insulating film 13 and the organic semiconductor layer 14, and then the electrode separation layer 16 is dried. And firing. Thereby, an electrode isolation layer 16 having a predetermined pattern is formed on the gate insulating film 13 and the organic semiconductor layer 14.
  • source / drain electrodes 15 A and 15 B having a predetermined pattern are formed on the transfer plate 92.
  • the source / drain electrodes 15A and 15B on the transfer plate 92 are formed on at least a part of a region where the electrode isolation layer 16 is not formed on the gate insulating film 13 and the organic semiconductor layer 14 ( It is transferred to the gaps of the electrode separation layer 16.
  • a pair of source / drain electrodes 15A and 15B are formed on the gate insulating film 13 and the organic semiconductor layer.
  • the protective film 17 made of the above-described material is formed on the electrode isolation layer 16 and the source / drain electrodes 15A and 15B.
  • a fluororesin such as (C 6 F 10 ) n
  • a general resist film photoresist film
  • the protective film 17 is formed.
  • the fluororesin film is dry-etched using, for example, oxygen plasma. Then, after the etching process, the photoresist film is removed.
  • the printing method is a suitable method as a method of forming the source / drain electrodes when manufacturing the top contact type organic TFT.
  • the electrode forming techniques based on the printing method the wiring forming technique based on the reverse offset printing method has achieved excellent results in definition.
  • the fine pattern formation by the printing method has a high hurdle from the viewpoint of dimensional reproducibility, and in particular, the source / drain electrodes in the short channel device in which the channel length L is about 10 ⁇ m or less are formed by the printing method. Extremely difficult. Specifically, when the source / drain electrodes are formed by printing, since the ink is in a paste form, dripping occurs before firing and the electrode shape easily changes, and the channel length L varies. . Further, the source / drain electrodes are likely to contact (short) due to the pressing pressure during printing.
  • the distance (channel length L) between the source / drain electrodes 15A and 15B may vary (fluctuate).
  • the characteristics of the thin film transistor 101 are deteriorated, the source / drain electrodes 15A and 15B are short-circuited, and the reliability of the device is lowered.
  • the electrode separation layer 16 (for controlling the channel region (channel length L) in the organic semiconductor layer 14 between the pair of source / drain electrodes 15A and 15B ( A channel region control layer) is provided.
  • a printing method is used for at least a part of the non-formation region of the electrode separation layer 16 to form a pair.
  • Source / drain electrodes 15A and 15B are formed.
  • the distance (channel length L) between the source / drain electrodes 15A and 15B is controlled (defined) by the pattern of the electrode separation layer 16.
  • the variation (variation) in the channel length L when the source / drain electrodes 15A and 15B are formed using the printing method is suppressed.
  • the electrode separation layer 16 is provided between the pair of source / drain electrodes 15A and 15B electrically connected to the organic semiconductor layer 14.
  • a pair of source / drain electrodes 15A and 15B are formed by using a printing method on at least a part of the non-formation region of the electrode separation layer 16. To do.
  • the channel length L can be formed with good reproducibility regardless of the dimensional reproducibility during printing and the viscosity of the ink. Therefore, the reliability of the element can be improved.
  • FIG. 6 schematically shows a schematic configuration example of the semiconductor element (thin film transistor 1A) according to the second embodiment in a cross-sectional view.
  • the thin film transistor 1A of the present embodiment is a top contact / top gate type organic TFT.
  • the thin film transistor 1A includes, for example, an insulating film 18, an organic semiconductor layer 14, a pair of source / drain electrodes 15A and 15B and an electrode separation layer 16, a gate insulating film 13, a gate electrode 12, and a protective film on a substrate 11. 17 has a structure laminated in this order. That is, the configuration is basically the same as that of the thin film transistor 1 except that the stacked positions (formation order) of the gate electrode 12 and the gate insulating film 13 are different and the insulating film 18 is further provided. It has become.
  • the insulating film 18 is provided between the substrate 11, the organic semiconductor layer 14, the source / drain electrodes 15 ⁇ / b> A and 15 ⁇ / b> B, and the electrode separation layer 16.
  • the insulating film 18 is made of the same insulating material as the gate insulating film 13 described above. .
  • the thin film transistor 1A can be manufactured, for example, as follows.
  • FIG. 7A to FIG. 9D show main process examples in the manufacturing method of the thin film transistor 1A in cross-sectional views in the order of the processes.
  • an insulating film 18 is formed on the substrate 11 as shown in FIG. 7A.
  • the formation method (film formation method) of the insulating film 18 is basically the same as that of the gate insulating film 13 described above.
  • the organic semiconductor layer 14 having the island shape described above is formed on the insulating film 18 by using the same method as in the first embodiment. That is, after the organic semiconductor layer 14 is formed on the insulating film 18, the organic semiconductor layer 14 is patterned (element isolation) using a resist film 83 (photoresist film) made of a predetermined mask pattern (resist pattern). Do.
  • the source / drain electrodes 15A and 15B are formed using the electrode separation layer 16 having a predetermined pattern. At this time, the source / drain electrodes 15A and 15B and the electrode separation layer 16 are formed using a printing method such as a reverse printing method.
  • the gate insulating film 13 is formed so as to cover the source / drain electrodes 15A and 15B and the electrode isolation layer 16 by using the same method as in the first embodiment. .
  • the gate electrode 12 is formed on the gate insulating film 13 by using the same method as in the first embodiment. That is, after the electrode film 120 is formed on the gate insulating film 13, the electrode film 120 is patterned using a resist film 84 (photoresist film) made of a predetermined mask pattern (resist pattern). The electrode 12 is formed.
  • a resist film 84 photoresist film
  • an electrode isolation layer 16 for controlling a channel region (channel length L) in the organic semiconductor layer 14 is interposed between the pair of source / drain electrodes 15A and 15B. (Region control layer) is provided.
  • the printing method is used for at least a part of the non-formation region of the electrode separation layer 16 to form a pair.
  • Source / drain electrodes 15A and 15B are formed.
  • FIG. 10 and FIG. 11 schematically show schematic configuration examples of semiconductor elements (thin film transistors 1B and 1C) according to the third embodiment in cross-sectional views.
  • the thin film transistors 1B and 1C of the present embodiment are bottom contact type organic TFTs, respectively.
  • the source / drain electrodes 15A and 15B are in contact (electrically connected) with the organic semiconductor layer 14 below the organic semiconductor layer 14.
  • the thin film transistor 1B shown in FIG. 10 is a bottom contact / bottom gate type organic TFT. That is, the thin film transistor 1B includes, for example, a gate electrode 12, a gate insulating film 13, a pair of source / drain electrodes 15A and 15B, an electrode separation layer 16, an organic semiconductor layer 14, and a protective film 17 in this order on a substrate 11. It has a laminated structure.
  • the thin film transistor 1C shown in FIG. 11 is a bottom contact / top gate type organic TFT. That is, the thin film transistor 1C includes, for example, an insulating film 18, a pair of source / drain electrodes 15A and 15B and an electrode separation layer 16, an organic semiconductor layer 14, a gate insulating film 13, a gate electrode 12, and a protective film on a substrate 11. 17 has a structure laminated in this order.
  • Electrodes and effects of thin film transistors 1B and 1C similarly to the thin film transistors 1 and 1A, electrode separation for controlling the channel region (channel length L) in the organic semiconductor layer 14 is performed between the pair of source / drain electrodes 15A and 15B.
  • a layer 16 channel region control layer
  • a printing method is used for at least a part of the non-formation region of the electrode separation layer 16.
  • a pair of source / drain electrodes 15A and 15B is formed.
  • Display device 12A and 12B schematically show a schematic configuration of a display device (display device 2) including the semiconductor elements (thin film transistors 1, 1A to 1C) of the above-described embodiments.
  • FIG. 12B shows a planar configuration (XY planar configuration)
  • FIG. 12A shows an arrow sectional configuration (ZX sectional configuration) along the line II-II in FIG. 12B. .
  • This display device 2 is obtained by laminating a substrate 11, a TFT layer 22 (semiconductor device), a display layer 23 (display portion), and a transparent substrate 24 in this order. Specifically, the TFT layer 22, the display layer 23, and the transparent substrate 24 are stacked on the display region 20 ⁇ / b> A in the substrate 11, while these TFTs are formed on the frame region (non-display region) 20 ⁇ / b> B in the substrate 11. The layer 22, the display layer 23, and the transparent substrate 24 are not laminated.
  • the TFT layer 22 is a layer including a plurality of devices including a thin film (a conductive film such as a metal film or an insulating film). Examples of this device include a TFT as a switching element for selecting a pixel, a capacitor element (such as a storage capacitor element), a wiring (such as a scanning line or a signal line), and an electrode (such as a pixel electrode).
  • a TFT as a switching element for selecting a pixel
  • a capacitor element such as a storage capacitor element
  • a wiring such as a scanning line or a signal line
  • an electrode such as a pixel electrode
  • the above-described TFT is constituted by the thin film transistor (organic TFT) of each of the above embodiments. That is, the TFT layer 22 corresponds to a specific example of “semiconductor device” of the present disclosure including one or a plurality of semiconductor elements (the thin film transistors of the above embodiments).
  • the display layer 23 includes, for example, an electrophoretic particle, a liquid crystal layer, an organic EL (Electro-Luminescence) layer, or an inorganic EL layer between the pixel electrode and the common electrode. That is, the display layer 23 is configured using an electrophoretic element, a liquid crystal element, an organic EL element, an inorganic EL element, or the like. Note that the pixel electrode is provided for each pixel in the TFT layer 22, and the common electrode is provided over one surface of the transparent substrate 24.
  • the transparent substrate 24 is configured using, for example, the same material as the substrate 11.
  • a moisture-proof film for preventing moisture from entering the display layer 23 and an optical function film for preventing external light from being reflected on the display surface may be provided on the transparent substrate 24.
  • the thin film transistor 1 (1A to 1C) described so far is formed as follows, for example. Specifically, for example, as shown in FIGS. 13A and 13B, a plurality of thin film transistors 1 (1A to 1C) are arranged along the Y-axis direction. A signal line 22S (wiring) extending along the Y-axis direction is commonly connected to one source / drain electrode 15B (drain electrode) in each thin film transistor 1 (1A to 1C). An electrode separation layer 16 is formed at least in a region between the signal line 22S and the other source / drain electrode 15A (source electrode) in each thin film transistor 1 (1A to 1C).
  • An electrode isolation layer 16 is also formed in a region between the source / drain electrodes 15A. Accordingly, in the example of FIG. 13A, the electrode separation layer 16 is formed so as to surround the other source / drain electrode 15A of each thin film transistor 1 (1A to 1C).
  • the electrode separation layer 16 is not formed in the region between the other source / drain electrodes 15A in each thin film transistor 1 (1A to 1C).
  • the display device 2 can be applied to electronic devices in various fields such as television devices, digital cameras, notebook personal computers, portable terminal devices such as mobile phones, and video cameras.
  • the display device 2 can be applied to electronic devices in various fields that display a video signal input from the outside or a video signal generated inside as an image or video.
  • the electronic book has, for example, a display unit 210 and a non-display unit 220, and the display unit 210 is configured by the display device 2.
  • FIG. 15 illustrates an appearance of a television device to which the display device 2 is applied.
  • This television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is configured by the display device 2.
  • 16A and 16B show the appearance of a digital camera to which the display device 2 is applied.
  • the digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440, and the display unit 420 includes the display device 2.
  • FIG. 17 shows the appearance of a notebook personal computer to which the display device 2 is applied.
  • the notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image.
  • the display unit 530 is configured by the display device 2.
  • FIG. 18 shows the appearance of a video camera to which the display device 2 is applied.
  • This video camera includes, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640.
  • the display unit 640 includes the display device 2.
  • FIG. 19 shows an appearance of a mobile phone to which the display device 2 is applied.
  • the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes.
  • the display 740 or the sub-display 750 is constituted by the display device 2.
  • each layer described in the above embodiment and the like, or the film formation method and film formation conditions are not limited, and other materials and thicknesses may be used. It is good also as film
  • the electrode separation layer channel region control layer
  • this electrode separation layer may be used as a sacrificial layer when forming a plurality of electrodes so that it does not remain in the finally manufactured semiconductor device.
  • the configuration of the display device has been specifically described, but it is not necessary to include all layers, and other layers may be further included.
  • the semiconductor layer in the semiconductor element is an organic semiconductor layer (in the case of an organic TFT) has been described as an example, but the present invention is not limited thereto. That is, the semiconductor layer may be an inorganic semiconductor (for example, silicon (Si), a compound semiconductor, an oxide semiconductor, etc.) (may be an inorganic TFT).
  • the semiconductor layer may be an inorganic semiconductor (for example, silicon (Si), a compound semiconductor, an oxide semiconductor, etc.) (may be an inorganic TFT).
  • a thin film transistor including an organic semiconductor layer, a gate electrode, a pair of source / drain electrodes, and a wiring layer
  • organic TFT organic TFT
  • the present technology can also be applied to other semiconductor elements such as an organic semiconductor layer, a pair of electrodes (anode electrode and cathode electrode), and a diode (rectifier element) including a wiring layer.
  • semiconductor element semiconductor device
  • the semiconductor element is not limited to the display device described in the above embodiment and the like, for example, other devices such as a light receiving element (sensor) and a solar battery, and those devices.
  • the present invention can also be applied to electronic devices provided.
  • this technique can also take the following structures.
  • the semiconductor element is A semiconductor layer; A plurality of electrodes electrically connected to the semiconductor layer; A semiconductor device comprising: an electrode separation layer disposed between the plurality of electrodes.
  • the semiconductor element is a thin film transistor including the semiconductor layer, a gate electrode, a pair of source / drain electrodes as the plurality of electrodes, and the electrode separation layer.
  • the electrode separation layer controls a channel region in the semiconductor layer.
  • the electrode separation layer controls a channel length in the channel region.
  • a plurality of the semiconductor elements are provided, and a wiring commonly connected to one of the pair of source / drain electrodes in each semiconductor element is provided, The semiconductor device according to any one of (2) to (4), wherein the electrode isolation layer is formed at least in a region between the wiring and the other electrode of each semiconductor element.
  • the electrode separation layer is also formed in a region between the other electrodes in each semiconductor element.
  • the electrode separation layer is formed so as to surround a periphery of the other electrode in each semiconductor element.
  • the plurality of electrodes are electrically connected to the semiconductor layer on the semiconductor layer.
  • the thin film transistor includes a gate insulating film and a protective film, The semiconductor device according to (8), wherein the gate electrode, the gate insulating film, the semiconductor layer, the pair of source / drain electrodes, and the protective film are stacked in this order on a substrate. (10) The semiconductor device according to any one of (1) to (9), wherein the semiconductor layer is an organic semiconductor layer. (11) A semiconductor device having one or more semiconductor elements and a display unit; The semiconductor element is A semiconductor layer; A plurality of electrodes electrically connected to the semiconductor layer; A display device comprising: an electrode separation layer disposed between the plurality of electrodes.
  • a display device includes a semiconductor device having one or a plurality of semiconductor elements and a display unit,
  • the semiconductor element is A semiconductor layer; A plurality of electrodes electrically connected to the semiconductor layer; And an electrode separation layer disposed between the plurality of electrodes.
  • the step of forming the semiconductor element includes a step of forming a semiconductor layer and a plurality of electrodes electrically connected to the semiconductor layer on the substrate, In the step of forming the plurality of electrodes, after forming an electrode separation layer having a predetermined pattern, the plurality of electrodes are formed by using a printing process on at least a part of the non-formation region of the electrode separation layer.
  • the step of forming the semiconductor element includes a step of removing the electrode separation layer after forming the plurality of electrodes. The method for manufacturing a semiconductor device according to any one of (13) to (15).

Abstract

A semiconductor device, provided with one or more semiconductor elements. The semiconductor element has: a semiconductor layer; a plurality of electrodes electrically connected to the semiconductor layer; and an electrode separation layer provided between the electrodes. The method for manufacturing a semiconductor device includes forming one or more semiconductor elements on a substrate, and the forming of the semiconductor element includes forming a semiconductor layer and a plurality of electrodes electrically connected to the semiconductor layer on the substrate. With regards to forming the electrodes, after the electrode separation layer comprising a predetermined pattern is formed, a print process is applied to at least a part of a region in which the electrode separation layer is not formed, whereby the electrodes are formed.

Description

半導体装置およびその製造方法、表示装置ならびに電子機器Semiconductor device, manufacturing method thereof, display device, and electronic device
　本開示は、薄膜トランジスタ（Thin Film Transistor；ＴＦＴ）等の半導体素子を有する半導体装置およびその製造方法、ならびにそのような半導体装置を備えた表示装置および電子機器に関する。 The present disclosure relates to a semiconductor device having a semiconductor element such as a thin film transistor (TFT), a manufacturing method thereof, and a display device and an electronic apparatus including such a semiconductor device.
　近年、有機ＴＦＴなどの有機半導体を用いた半導体素子の開発が進められている（例えば、特許文献１参照）。この有機半導体を用いた半導体素子は、フレキシブル有機ＥＬ（Electro Luminescence）ディスプレイあるいはフレキシブル電子ペーパーなどの表示装置、またはフレキシブルプリント基板、有機薄膜太陽電池、タッチパネルなどの電子機器への応用が想定されている。 In recent years, development of semiconductor elements using organic semiconductors such as organic TFTs has been promoted (see, for example, Patent Document 1). The semiconductor element using the organic semiconductor is assumed to be applied to a display device such as a flexible organic EL (Electro Luminescence) display or flexible electronic paper, or an electronic device such as a flexible printed circuit board, an organic thin film solar cell, and a touch panel. .
特開２０１１－５４８７７号公報JP 2011-54877 A
　ところで、上記した有機半導体等の半導体を用いた半導体素子（半導体装置）では一般に、例えば、素子の特性劣化を抑えたり、電極間の短絡（ショート）等を防止したりするなどにより、信頼性の向上を図ることが求められる。 By the way, in the semiconductor element (semiconductor device) using a semiconductor such as the above-described organic semiconductor, generally, for example, reliability of the element can be improved by suppressing deterioration of element characteristics or preventing a short circuit between electrodes. Improvement is required.
　したがって、信頼性を向上させることが可能な半導体装置およびその製造方法、ならびに表示装置および電子機器を提供することが望ましい。 Therefore, it is desirable to provide a semiconductor device capable of improving reliability, a manufacturing method thereof, a display device, and an electronic device.
　本開示の一実施の形態の半導体装置は、１または複数の半導体素子を備えたものである。この半導体素子は、半導体層と、半導体層と電気的に接続された複数の電極と、これら複数の電極間に配設された電極分離層とを有している。 A semiconductor device according to an embodiment of the present disclosure includes one or a plurality of semiconductor elements. This semiconductor element has a semiconductor layer, a plurality of electrodes electrically connected to the semiconductor layer, and an electrode separation layer disposed between the plurality of electrodes.
　本開示の一実施の形態の表示装置は、上記本開示の一実施の形態の半導体装置と、表示部とを備えたものである。 A display device according to an embodiment of the present disclosure includes the semiconductor device according to the embodiment of the present disclosure and a display unit.
　本開示の一実施の形態の電子機器は、上記本開示の一実施の形態の表示装置を備えたものである。 An electronic apparatus according to an embodiment of the present disclosure includes the display device according to the embodiment of the present disclosure.
　本開示の一実施の形態の半導体装置、表示装置および電子機器では、半導体素子において、半導体層と電気的に接続された複数の電極間に電極分離層が設けられている。これにより、電極間の距離（例えば、チャネル領域におけるチャネル長）が電極分離層のパターンによって制御（規定）されるようになり、電極形成の際の上記距離（チャネル長）のばらつき（変動）が抑えられる。 In the semiconductor device, the display device, and the electronic device according to an embodiment of the present disclosure, an electrode separation layer is provided between a plurality of electrodes electrically connected to the semiconductor layer in the semiconductor element. As a result, the distance between the electrodes (for example, the channel length in the channel region) is controlled (specified) by the pattern of the electrode separation layer, and the variation (variation) in the distance (channel length) at the time of electrode formation is increased. It can be suppressed.
　本開示の一実施の形態の半導体装置の製造方法は、基板上に１または複数の半導体素子を形成することを含むようにしたものであり、この半導体素子を形成することは、基板上に半導体層およびこの半導体層と電気的に接続された複数の電極を形成することを含んでいる。複数の電極を形成することでは、所定のパターンからなる電極分離層を形成した後に、この電極分離層の非形成領域の少なくとも一部分に対して印刷プロセスを用いることにより、複数の電極を形成する。 A method of manufacturing a semiconductor device according to an embodiment of the present disclosure includes forming one or a plurality of semiconductor elements on a substrate, and forming the semiconductor element includes forming a semiconductor on the substrate. Forming a layer and a plurality of electrodes electrically connected to the semiconductor layer. In forming a plurality of electrodes, after forming an electrode separation layer having a predetermined pattern, a plurality of electrodes are formed by using a printing process on at least a part of the non-formation region of the electrode separation layer.
　本開示の一実施の形態の半導体装置の製造方法では、半導体素子を形成する際に、所定のパターンからなる電極分離層が形成された後にこの電極分離層の非形成領域の少なくとも一部分に対して印刷プロセスを用いることにより、半導体層と電気的に接続された複数の電極が形成される。これにより、電極間の距離（例えば、チャネル領域におけるチャネル長）が電極分離層のパターンによって制御（規定）されるようになり、印刷プロセスを用いた電極形成の際の上記距離（チャネル長）のばらつき（変動）が抑えられる。 In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, when forming a semiconductor element, after an electrode separation layer having a predetermined pattern is formed, at least a part of the non-formation region of the electrode separation layer is formed. By using a printing process, a plurality of electrodes electrically connected to the semiconductor layer are formed. As a result, the distance between the electrodes (for example, the channel length in the channel region) is controlled (defined) by the pattern of the electrode separation layer, and the distance (channel length) in the electrode formation using the printing process is Variation (variation) is suppressed.
　本開示の一実施の形態の半導体装置、表示装置および電子機器によれば、半導体素子において、半導体層と電気的に接続された複数の電極間に電極分離層を設けるようにしたので、電極形成の際の電極間の距離のばらつきを抑えることができる。よって、例えば、素子の特性劣化を抑えたり電極間の短絡等を防止したりすることができ、信頼性を向上させることが可能となる。 According to the semiconductor device, the display device, and the electronic device of the embodiment of the present disclosure, the electrode separation layer is provided between the plurality of electrodes electrically connected to the semiconductor layer in the semiconductor element. In this case, variation in the distance between the electrodes can be suppressed. Therefore, for example, it is possible to suppress deterioration of the characteristics of the element, to prevent a short circuit between electrodes, and to improve reliability.
　本開示の一実施の形態の半導体装置の製造方法によれば、半導体素子を形成する際に、所定のパターンからなる電極分離層を形成した後にこの電極分離層の非形成領域の少なくとも一部分に対して印刷プロセスを用いることによって、半導体層と電気的に接続された複数の電極を形成するようにしたので、印刷プロセスを用いた電極形成の際の電極間の距離のばらつきを抑えることができる。よって、例えば、素子の特性劣化を抑えたり電極間の短絡等を防止したりすることができ、信頼性を向上させることが可能となる。 According to the method for manufacturing a semiconductor device of one embodiment of the present disclosure, when forming a semiconductor element, after forming an electrode separation layer having a predetermined pattern, at least a part of the non-formation region of the electrode separation layer is formed. Since the plurality of electrodes electrically connected to the semiconductor layer are formed by using the printing process, it is possible to suppress variations in the distance between the electrodes when forming the electrodes using the printing process. Therefore, for example, it is possible to suppress deterioration of the characteristics of the element, to prevent a short circuit between electrodes, and to improve reliability.
本開示の第１の実施の形態に係る半導体素子としての薄膜トランジスタの構成例を表す断面図である。It is sectional drawing showing the structural example of the thin-film transistor as a semiconductor element which concerns on 1st Embodiment of this indication. 第１の実施の形態に係る薄膜トランジスタの製造方法を工程順に表す断面図である。It is sectional drawing showing the manufacturing method of the thin-film transistor which concerns on 1st Embodiment in order of a process. 図２Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 2A. 図２Ｂに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 2B. 図２Ｃに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 2C. 図３Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3A. 図３Ｂに続く工程を表す断面図である。FIG. 3B is a cross-sectional diagram illustrating a process following the process in FIG. 3B. 図３Ｃに続く工程を表す断面図である。FIG. 3C is a cross-sectional diagram illustrating a process following the process in FIG. 3C. 図３Ｄに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 3D. 図４Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 4A. 図４Ｂに続く工程を表す断面図である。FIG. 4B is a cross-sectional diagram illustrating a process following the process in FIG. 4B. 図４Ｃに続く工程を表す断面図である。FIG. 4D is a cross-sectional diagram illustrating a process following the process in FIG. 4C. 比較例に係る薄膜トランジスタの構成を表す断面図である。It is sectional drawing showing the structure of the thin-film transistor which concerns on a comparative example. 第２の実施の形態に係る薄膜トランジスタの構成例を表す断面図である。It is sectional drawing showing the structural example of the thin-film transistor which concerns on 2nd Embodiment. 第２の実施の形態に係る薄膜トランジスタの製造方法を工程順に表す断面図である。It is sectional drawing showing the manufacturing method of the thin-film transistor which concerns on 2nd Embodiment in process order. 図７Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 7A. 図７Ｂに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 7B. 図７Ｃに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 7C. 図７Ｄに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 7D. 図８Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8A. 図８Ｂに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8B. 図８Ｃに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8C. 図８Ｄに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 8D. 図９Ａに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 9A. 図９Ｂに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 9B. 図９Ｃに続く工程を表す断面図である。It is sectional drawing showing the process of following FIG. 9C. 第３の実施の形態に係る薄膜トランジスタの構成例を表す断面図である。It is sectional drawing showing the structural example of the thin-film transistor which concerns on 3rd Embodiment. 第３の実施の形態に係る薄膜トランジスタの他の構成例を表す断面図である。It is sectional drawing showing the other structural example of the thin-film transistor which concerns on 3rd Embodiment. 各実施の形態の薄膜トランジスタの表示装置への適用例を表す断面図である。FIG. 10 is a cross-sectional view illustrating an application example of a thin film transistor of each embodiment to a display device. 図１２Ａに示した適用例を表す平面図である。It is a top view showing the application example shown to FIG. 12A. 図１２Ａに示したＴＦＴ層における電極分離層の一配置例を模式的に表す平面図である。FIG. 12B is a plan view schematically illustrating an arrangement example of electrode separation layers in the TFT layer illustrated in FIG. 12A. 図１２Ａに示したＴＦＴ層における電極分離層の他の配置例を模式的に表す平面図である。FIG. 12B is a plan view schematically showing another arrangement example of the electrode separation layer in the TFT layer shown in FIG. 12A. 図１２Ａおよび図１２Ｂに示した表示装置の電子機器への適用例１の外観を表す斜視図である。13A is a perspective view illustrating an appearance of an application example 1 of the display device illustrated in FIGS. 12A and 12B to an electronic device. FIG. 図１２Ａおよび図１２Ｂに示した表示装置の電子機器への適用例１の他の外観を表す斜視図である。12A is a perspective view illustrating another appearance of application example 1 of the display device illustrated in FIGS. 12A and 12B to an electronic device. FIG. 適用例２の外観を表す斜視図である。12 is a perspective view illustrating an appearance of application example 2. FIG. 適用例３の表側から見た外観を表す斜視図である。14 is a perspective view illustrating an appearance of Application Example 3 viewed from the front side. FIG. 適用例３の裏側から見た外観を表す斜視図である。14 is a perspective view illustrating an appearance of Application Example 3 viewed from the back side. FIG. 適用例４の外観を表す斜視図である。14 is a perspective view illustrating an appearance of application example 4. FIG. 適用例５の外観を表す斜視図である。14 is a perspective view illustrating an appearance of application example 5. FIG. （Ａ）は適用例６の開いた状態の正面図、（Ｂ）はその側面図、（Ｃ）は閉じた状態の正面図、（Ｄ）は左側面図、（Ｅ）は右側面図、（Ｆ）は上面図、（Ｇ）は下面図である。(A) is a front view of the application example 6 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view.
　以下、本開示の実施の形態について、図面を参照して詳細に説明する。なお、説明は以下の順序で行う。
 
１．第１の実施の形態（トップコンタクト・ボトムゲート型の有機ＴＦＴの例）
２．第２の実施の形態（トップコンタクト・トップゲート型の有機ＴＦＴの例）
３．第３の実施の形態（ボトムコンタクト型の有機ＴＦＴの例）
４．適用例（表示装置，電子機器への適用例）
５．変形例（無機半導体を用いた半導体素子，ＴＦＴ以外の半導体素子の例等）
  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.

1. First embodiment (example of top contact / bottom gate type organic TFT)
2. Second embodiment (example of top contact / top gate type organic TFT)
3. Third embodiment (example of bottom contact type organic TFT)
4). Application examples (application examples for display devices and electronic devices)
5. Modified examples (semiconductor elements using inorganic semiconductors, examples of semiconductor elements other than TFT)
＜第１の実施の形態＞
［薄膜トランジスタ１の全体構成］
　図１は、本開示の第１の実施の形態に係る半導体素子（薄膜トランジスタ１）の概略構成例を、断面図で模式的に表したものである。この薄膜トランジスタ１は、例えば表示装置のアクティブマトリクス回路などに用いられる、トップコンタクト・ボトムゲート型のものである。薄膜トランジスタ１は、例えば、基板１１上に、ゲート電極１２、ゲート絶縁膜１３、有機半導体層１４（半導体層）、一対のソース・ドレイン電極１５Ａ，１５Ｂ（複数の電極）および電極分離層（チャネル領域制御層）１６、ならびに保護膜１７がこの順に積層された構造を有している。すなわち、この薄膜トランジスタ１は、有機半導体を用いた有機ＴＦＴである。 <First Embodiment>
[Overall Configuration of Thin Film Transistor 1]
FIG. 1 schematically shows a schematic configuration example of the semiconductor element (thin film transistor 1) according to the first embodiment of the present disclosure in a cross-sectional view. The thin film transistor 1 is of a top contact / bottom gate type used in, for example, an active matrix circuit of a display device. The thin film transistor 1 includes, for example, a gate electrode 12, a gate insulating film 13, an organic semiconductor layer 14 (semiconductor layer), a pair of source / drain electrodes 15A and 15B (a plurality of electrodes), and an electrode separation layer (channel region) on a substrate 11. The control layer 16 and the protective film 17 are stacked in this order. That is, the thin film transistor 1 is an organic TFT using an organic semiconductor.
　基板１１は、例えば、ガラス，石英，シリコン，ガリウム砒素等の無機材料、金属材料、あるいはプラスチック材料等からなる。金属材料としては、例えば、アルミニウム（Ａｌ）、ニッケル（Ｎｉ）またはステンレスなどが挙げられる。プラスチック材料としては、ポリイミド，ポリエチレンテレフタレート（ＰＥＴ），ポリエチレンナフタレート（ＰＥＮ），ポリメチルメタクリレート（ＰＭＭＡ），ポリカーボネート（ＰＣ），ポリエーテルスルホン（ＰＥＳ），ポリエチルエーテルケトン（ＰＥＥＫ），芳香族ポリエステル（液晶ポリマー）等が挙げられる。この基板１１は、ウェハなどの剛性の基板であってもよく、薄層ガラスやフィルム、紙（一般紙）などの可撓性基板（フレキシブル基板）であってもよい。なお、基板１１の表面には、例えば、密着性を確保するためのバッファ層またはガス放出を防止するためのガスバリア層などの各種層が設けられていてもよい。 The substrate 11 is made of, for example, an inorganic material such as glass, quartz, silicon, gallium arsenide, a metal material, or a plastic material. Examples of the metal material include aluminum (Al), nickel (Ni), and stainless steel. Plastic materials include polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), polyethyl ether ketone (PEEK), aromatic polyester ( Liquid crystal polymer). The substrate 11 may be a rigid substrate such as a wafer, or may be a flexible substrate (flexible substrate) such as a thin glass layer, a film, or paper (general paper). The surface of the substrate 11 may be provided with various layers such as a buffer layer for ensuring adhesion and a gas barrier layer for preventing gas release.
　ゲート電極１２は、薄膜トランジスタ１のゲート電極として機能するものである。このゲート電極１２は、基板１１の上に設けられており、例えば、金属材料、無機導電性材料、有機導電性材料または炭素材料のいずれか１種類または２種類以上により構成されている。金属材料は、例えば、アルミニウム、銅（Ｃｕ）、モリブデン（Ｍｏ）、チタン（Ｔｉ）、クロム（Ｃｒ）、ニッケル、パラジウム（Ｐｄ）、金（Ａｕ）、銀（Ａｇ）、白金（Ｐｔ）またはそれらを含む合金などである。無機導電性材料は、例えば、酸化インジウム（Ｉｎ２Ｏ３）、酸化インジウムスズ（ＩＴＯ）、酸化インジウム亜鉛（ＩＺＯ）または酸化亜鉛（ＺｎＯ）などである。有機導電性材料は、例えば、ポリエチレンジオキシチオフェン（ＰＥＤＯＴ）またはポリスチレンスルホン酸（ＰＳＳ）などである。炭素材料は、例えば、グラファイトなどである。なお、ゲート電極１２は、上記した各種材料の層が２層以上積層されたものでもよい。 The gate electrode 12 functions as a gate electrode of the thin film transistor 1. The gate electrode 12 is provided on the substrate 11 and is made of, for example, one or more of a metal material, an inorganic conductive material, an organic conductive material, and a carbon material. Examples of the metal material include aluminum, copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel, palladium (Pd), gold (Au), silver (Ag), platinum (Pt), or An alloy containing them. Examples of the inorganic conductive material include indium oxide (In 2 O 3 ), indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). The organic conductive material is, for example, polyethylene dioxythiophene (PEDOT) or polystyrene sulfonic acid (PSS). The carbon material is, for example, graphite. Note that the gate electrode 12 may be formed by stacking two or more layers of the various materials described above.
　ゲート絶縁膜１３は、ゲート電極１２を覆うように形成されており、例えば、無機絶縁性材料または有機絶縁性材料のいずれか１種類または２種類以上により構成されている。無機絶縁性材料は、例えば、酸化ケイ素（ＳｉＯｘ）、窒化ケイ素（ＳｉＮｘ）、酸化アルミニウム（Ａｌ２Ｏ３）、酸化チタン（ＴｉＯ２）、酸化ハフニウム（ＨｆＯｘ）またはチタン酸バリウム（ＢａＴｉＯ３）などである。有機絶縁性材料は、例えば、ポリビニルフェノール（ＰＶＰ）、ポリイミド、ポリメタクリル酸アクリレート、感光性ポリイミド、感光性ノボラック樹脂またはポリパラキシリレンなどである。なお、ゲート絶縁膜１３は、上記した各種材料の層が２層以上積層されたものでもよい。 The gate insulating film 13 is formed so as to cover the gate electrode 12, and is made of, for example, one or more of an inorganic insulating material and an organic insulating material. Examples of the inorganic insulating material include silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), hafnium oxide (HfO x ), and barium titanate (BaTiO 3 ). 3 ). Examples of the organic insulating material include polyvinylphenol (PVP), polyimide, polymethacrylic acid acrylate, photosensitive polyimide, photosensitive novolak resin, and polyparaxylylene. Note that the gate insulating film 13 may be formed by stacking two or more layers of the various materials described above.
　有機半導体層１４は、薄膜トランジスタ１の形成領域において島状に形成されており、例えば、ＰＸＸ（peri-xanthenoxanthene）誘導体により構成されている。また、この有機半導体層１４は、例えば、ペンタセン（Ｃ２２Ｈ１４），Triisopropylsilylethynyl（ＴＩＰＳ）ペンタセン，ポリチオフェンなどの他の有機半導体材料により構成されていてもよい。 The organic semiconductor layer 14 is formed in an island shape in the region where the thin film transistor 1 is formed, and is made of, for example, a PXX (peri-xanthenoxanthene) derivative. The organic semiconductor layer 14 may be made of other organic semiconductor materials such as pentacene (C 22 H 14 ), Triisopropylsilylethynyl (TIPS) pentacene, polythiophene, and the like.
　ソース・ドレイン電極１５Ａ，１５Ｂは、有機半導体層１４上において、この有機半導体層１４と接するように（電気的に接続されるように）配設された電極である。これらのソース・ドレイン電極１５Ａ，１５Ｂはそれぞれ、導電性材料、特に、そのまま有機半導体層１４とオーミック接触を与えうる金属、金属酸化物、導電性高分子または炭素等により構成されていることが好ましい。そのような金属としては、例えば、金（Ａｕ），銅（Ｃｕ），銀（Ａｇ），ニッケル（Ｎｉ）またはチタン（Ｔｉ）が挙げられる。また、例えば、厚み２０ｎｍのチタン（Ｔｉ）層と、厚み２００ｎｍのアルミニウム（Ａｌ）層と、厚み２０ｎｍのチタン（Ｔｉ）層とをこの順に積層した積層構造となっていてもよい。上記した金属酸化物としては、例えば、ＣｕＯｘ，ＮｉＯｘ，ＴｉＯｘ，ＩＴＯ（Indium Tin Oxide；酸化インジウムスズ）またはＭｏＯｘ，ＷＯｘが挙げられる。また、上記した導電性高分子としては、例えば、水溶性ＰＥＤＯＴ－ＰＳＳが挙げられる。 The source / drain electrodes 15 </ b> A and 15 </ b> B are electrodes disposed on the organic semiconductor layer 14 so as to be in contact with (electrically connected to) the organic semiconductor layer 14. These source / drain electrodes 15A and 15B are each preferably made of a conductive material, in particular, a metal, a metal oxide, a conductive polymer, carbon, or the like that can provide ohmic contact with the organic semiconductor layer 14 as it is. . Examples of such a metal include gold (Au), copper (Cu), silver (Ag), nickel (Ni), and titanium (Ti). Further, for example, a stacked structure in which a titanium (Ti) layer having a thickness of 20 nm, an aluminum (Al) layer having a thickness of 200 nm, and a titanium (Ti) layer having a thickness of 20 nm are stacked in this order may be employed. Examples of the metal oxide include CuO x , NiO x , TiO x , ITO (Indium Tin Oxide), MoO x , and WO x . Examples of the conductive polymer include water-soluble PEDOT-PSS.
　電極分離層１６は、ゲート絶縁膜１３および有機半導体層１４の上において、ソース・ドレイン電極１５Ａ，１５Ｂの間を含め、ここではこれらソース・ドレイン電極１５Ａ，１５Ｂの周囲を取り囲むようにして配設されている。この電極分離層１６は、有機半導体層１４におけるチャネル領域、具体的にはチャネル長Ｌ（図１参照）を制御（規定）するためのもの（チャネル領域制御層）である。つまり、電極分離層１６は、少なくとも、有機半導体層１４におけるチャネル領域に対応する領域上に、チャネル長Ｌと略同一（望ましくは同一）の長さで、チャネル幅方向に沿って連続的に形成されている。このような電極分離層１６は絶縁性材料からなり、有機半導体層１４におけるチャネルにダメージを与えない材料（チャネルを保護する材料）、特にダメージを与えない溶剤で構成された組成物を使用することが望ましい。具体的には、フッ素系樹脂などをフッ素系溶剤に溶解してなる組成物、ポリビニルアルコールやエチルセルロースなどを水に溶解してなる組成物などを好ましく例示することができる。ただし、有機半導体層１４にダメージを与えないのであれば、アルコール系、エーテル系などの溶剤を用いた組成物を使用してもよい。また、フッ素系界面活性剤などの材料も適宜添加してもかまわない。 The electrode isolation layer 16 is disposed on the gate insulating film 13 and the organic semiconductor layer 14 so as to surround the source / drain electrodes 15A and 15B, including between the source / drain electrodes 15A and 15B. Has been. The electrode separation layer 16 is for controlling (defining) a channel region in the organic semiconductor layer 14, specifically, a channel length L (see FIG. 1) (channel region control layer). In other words, the electrode separation layer 16 is continuously formed along the channel width direction at least on the region corresponding to the channel region in the organic semiconductor layer 14 with a length substantially the same as the channel length L (preferably the same). Has been. Such an electrode separation layer 16 is made of an insulating material, and a material that does not damage the channel in the organic semiconductor layer 14 (a material that protects the channel), particularly a composition that includes a solvent that does not damage is used. Is desirable. Specifically, a composition formed by dissolving a fluorine-based resin or the like in a fluorine-based solvent, a composition formed by dissolving polyvinyl alcohol, ethyl cellulose or the like in water can be preferably exemplified. However, as long as the organic semiconductor layer 14 is not damaged, a composition using a solvent such as alcohol or ether may be used. Moreover, you may add suitably materials, such as a fluorochemical surfactant.
　保護膜１７は、ソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６の少なくとも一部を覆うように配設されている。この保護膜１７は、上記した電極分離層１６と同じ材料で構成してもよく、あるいは異なる材料で構成してもよい。保護膜１７の形成方法としては、塗布あるいは蒸着等の手法を用いて行うことが可能である。塗布を用いる場合、電極分離層１６と同様に、この保護膜１７は、有機半導体層１４にダメージを与えない溶媒で溶解された樹脂であることが好ましい。例えば、（Ｃ６Ｆ１０）ｎなどのフッ素樹脂により構成されているのが望ましい。なお、そのような樹脂としては、上記したフッ素樹脂の他、ＰＶＡ（ポリビニルアルコール；水溶性）などを例示することができる。また、塗布以外の方法である蒸着を用いて成膜されたパリレン樹脂等を使用してもよい。 The protective film 17 is disposed so as to cover at least a part of the source / drain electrodes 15 </ b> A and 15 </ b> B and the electrode separation layer 16. This protective film 17 may be made of the same material as the electrode separation layer 16 described above, or may be made of a different material. The protective film 17 can be formed using a technique such as coating or vapor deposition. When coating is used, like the electrode separation layer 16, the protective film 17 is preferably a resin dissolved in a solvent that does not damage the organic semiconductor layer 14. For example, it is desirable to be made of a fluororesin such as (C 6 F 10 ) n . In addition, as such resin, PVA (polyvinyl alcohol; water-soluble) etc. other than the above-mentioned fluororesin can be illustrated. Moreover, you may use the parylene resin etc. which were formed into a film using vapor deposition which is methods other than application | coating.
［薄膜トランジスタ１の製造方法］
　この薄膜トランジスタ１は、例えば次のようにして製造することができる。図２Ａ～図４Ｄは、薄膜トランジスタ１の製造方法における主要な工程例を、工程順に断面図で表わしたものである。 [Method of Manufacturing Thin Film Transistor 1]
The thin film transistor 1 can be manufactured, for example, as follows. 2A to 4D are cross-sectional views showing main process examples in the method of manufacturing the thin film transistor 1 in order of processes.
（ゲート電極１２の形成工程）
　最初に、図２Ａ～図２Ｃに示したようにして、基板１１上にゲート電極１２を形成する。 (Formation process of gate electrode 12)
First, the gate electrode 12 is formed on the substrate 11 as shown in FIGS. 2A to 2C.
　具体的には、まず、上述した材料よりなる基板１１を用意し、図２Ａに示したように、この基板１１上に、例えば真空成膜法、塗布法またはめっき法により、上述した金属材料よりなる電極膜１２０を成膜する。真空成膜法は、例えば、真空蒸着法、フラッシュ蒸着法、スパッタリング法、物理的気相成長法（ＰＶＤ）、化学的気相成長法（ＣＶＤ）、パルスレーザ堆積法（ＰＬＤ）またはアーク放電法などである。塗布法は、例えば、スピンコート法、スリットコート法、バーコート法またはスプレーコート法などである。めっき法は、例えば、電解めっき法または無電解めっき法などである。 Specifically, first, a substrate 11 made of the above-described material is prepared. As shown in FIG. 2A, the substrate 11 is made of the above-described metal material by, for example, a vacuum film forming method, a coating method, or a plating method. An electrode film 120 is formed. Examples of the vacuum film forming method include a vacuum deposition method, a flash deposition method, a sputtering method, a physical vapor deposition method (PVD), a chemical vapor deposition method (CVD), a pulse laser deposition method (PLD), or an arc discharge method. Etc. Examples of the coating method include spin coating, slit coating, bar coating, and spray coating. Examples of the plating method include an electrolytic plating method and an electroless plating method.
　次いで、図２Ｂに示したように、この電極膜１２０上に、所定のマスクパターン（レジストパターン）からなるレジスト膜８１（フォトレジスト膜）を形成する。続いて、このレジスト膜８１を用いて電極膜１２０を所定のパターンにエッチングしたのち、アッシング法またはエッチング法などを用いてレジスト膜８１を除去する。これにより図２Ｃに示したように、基板１１上にゲート電極１２が形成される。ここで、上記したレジストパターンを形成する際には、例えば、フォトレジストを塗布してフォトレジスト膜を形成したのち、フォトリソグラフィ法、レーザ描画法、電子線描画法またはＸ線描画法などを用いてフォトレジスト膜をパターニングする。ただし、レジスト転写法などを用いてレジストパターンを形成してもよい。電極膜１２０のエッチング方法は、例えば、ドライエッチング法、またはエッチャント溶液を用いたウェットエッチング法であり、そのドライエッチング法は、例えば、イオンミリングまたは反応性イオンエッチング（ＲＩＥ）などである。マスクを除去するためのエッチング方法も同様である。 Next, as shown in FIG. 2B, a resist film 81 (photoresist film) made of a predetermined mask pattern (resist pattern) is formed on the electrode film 120. Subsequently, after the electrode film 120 is etched into a predetermined pattern using the resist film 81, the resist film 81 is removed using an ashing method or an etching method. As a result, the gate electrode 12 is formed on the substrate 11 as shown in FIG. 2C. Here, when forming the resist pattern, for example, after applying a photoresist to form a photoresist film, a photolithography method, a laser drawing method, an electron beam drawing method, an X-ray drawing method, or the like is used. To pattern the photoresist film. However, the resist pattern may be formed using a resist transfer method or the like. The etching method of the electrode film 120 is, for example, a dry etching method or a wet etching method using an etchant solution, and the dry etching method is, for example, ion milling or reactive ion etching (RIE). The etching method for removing the mask is the same.
　なお、ゲート電極１２の形成方法は、例えば、インクジェット法、スクリーン印刷法、グラビア印刷法またはグラビアオフセット印刷法などの印刷法でもよい。また、レーザアブレーション法、マスク蒸着法またはレーザ転写法などを用いて、マスクとしてレジストパターンの代わりに金属パターンを形成してもよい。もちろん、ゲート電極１２を形成するために、金属材料の代わりに上述した無機導電性材料、有機導電性材料または炭素材料などを用いることも可能である。 In addition, the formation method of the gate electrode 12 may be a printing method such as an inkjet method, a screen printing method, a gravure printing method, or a gravure offset printing method. Alternatively, a metal pattern may be formed instead of the resist pattern as a mask using a laser ablation method, a mask vapor deposition method, a laser transfer method, or the like. Of course, in order to form the gate electrode 12, the above-described inorganic conductive material, organic conductive material, or carbon material can be used instead of the metal material.
（ゲート絶縁膜１３の形成工程）
　続いて、図３Ａに示したように、ゲート電極１２上を覆うようにゲート絶縁膜１３を形成する。このゲート絶縁膜１３の形成手順は、例えば、その形成材料により異なる。無機絶縁性材料を用いる場合の形成手順は、例えば、塗布法がゾル・ゲル法などでもよいことを除き、ゲート電極１２を形成する場合と同様である。有機絶縁性材料を用いる場合の形成手順は、例えば、フォトリソグラフィ法などを用いて感光性材料をパターニングしてもよいことを除き、ゲート電極１２を形成した場合と同様である。なお、このゲート絶縁膜１３の形成方法の一例としては、例えばＰＶＰ（ポリビニルフェノール）と硬化剤（例えばメラミン樹脂）との混合溶液を、例えばスピンコート法などにより塗布・焼成して形成する手法が挙げられる。 (Formation process of gate insulating film 13)
Subsequently, as shown in FIG. 3A, a gate insulating film 13 is formed so as to cover the gate electrode 12. The formation procedure of the gate insulating film 13 differs depending on, for example, the formation material. The formation procedure in the case of using an inorganic insulating material is the same as that for forming the gate electrode 12 except that, for example, the coating method may be a sol-gel method. The formation procedure in the case of using the organic insulating material is the same as that in the case of forming the gate electrode 12 except that the photosensitive material may be patterned using, for example, a photolithography method. An example of a method for forming the gate insulating film 13 is a method in which a mixed solution of, for example, PVP (polyvinylphenol) and a curing agent (for example, melamine resin) is applied and baked by, for example, a spin coating method. Can be mentioned.
（有機半導体層１４の形成工程）
　次いで、例えば図３Ｂ～図３Ｄに示したようにして、ゲート絶縁膜１３上に例えば塗布法や蒸着法を用いて、有機半導体層１４を形成する。 (Formation process of the organic semiconductor layer 14)
Next, for example, as shown in FIGS. 3B to 3D, the organic semiconductor layer 14 is formed on the gate insulating film 13 by using, for example, a coating method or a vapor deposition method.
　具体的には、まず、例えば上述した有機半導体材料、例えばＰＸＸ誘導体を有機溶剤などの溶媒に分散または溶解させた溶液（混合溶液）を調製し、この混合溶液をゲート絶縁膜１３の上面に塗布し、加熱（焼成）する。塗布方法としては、スピンコート法、スリットコート法、キャップコート法、印刷法、インクジェット法などがあげられるが、特に限定されない。これにより図３Ｂに示したように、ゲート絶縁膜１３上に、上述した有機半導体材料、例えばＰＸＸ誘導体よりなる有機半導体層１４が形成される。溶媒としては、例えば、トルエン、キシレン、メシチレンまたはテトラリンなどを用いることが可能である。 Specifically, first, for example, a solution (mixed solution) in which the above-described organic semiconductor material, for example, a PXX derivative is dispersed or dissolved in a solvent such as an organic solvent, is prepared, and this mixed solution is applied to the upper surface of the gate insulating film 13. And heating (firing). Examples of the coating method include spin coating, slit coating, cap coating, printing, and inkjet, but are not particularly limited. As a result, as shown in FIG. 3B, the organic semiconductor layer 14 made of the above-described organic semiconductor material, for example, a PXX derivative, is formed on the gate insulating film 13. As the solvent, for example, toluene, xylene, mesitylene, tetralin, or the like can be used.
　次いで、例えば図３Ｃ，図３Ｄに示したように、このようにして形成した有機半導体層１４に対する素子分離を行い、前述した島形状からなる有機半導体層１４を形成する。ここでは、前述したゲート電極１２の形成工程と同様に、所定のマスクパターン（レジストパターン）からなるレジスト膜８２（フォトレジスト膜）を用いて、例えばＲＩＥ法やウェットエッチング法により、有機半導体層１４のパターニングを行う。ただし、素子分離の方法としてはこれには限られず、例えばレーザアブレーション法を用いて行うようにしてもよい。また、例えば反転オフセット印刷法等の印刷法を用いて、有機半導体層１４を直接的にパターン形成することも可能である。 Next, for example, as shown in FIGS. 3C and 3D, element isolation is performed on the organic semiconductor layer 14 formed in this manner, and the organic semiconductor layer 14 having the island shape described above is formed. Here, in the same manner as the formation process of the gate electrode 12 described above, the organic semiconductor layer 14 is formed by, for example, RIE or wet etching using a resist film 82 (photoresist film) made of a predetermined mask pattern (resist pattern). Patterning is performed. However, the element isolation method is not limited to this, and for example, laser ablation may be used. Also, the organic semiconductor layer 14 can be directly patterned using a printing method such as a reverse offset printing method.
（ソース・ドレイン電極１５Ａ，１５Ｂの形成工程）
　続いて、図４Ａ～図４Ｄに示したようにして、有機半導体層１４上にこの有機半導体層１４と接するように（電気的に接続されるように）、一対のソース・ドレイン電極１５Ａ，１５Ｂを形成する。 (Process for forming source / drain electrodes 15A and 15B)
Subsequently, as shown in FIGS. 4A to 4D, a pair of source / drain electrodes 15A and 15B are formed on the organic semiconductor layer 14 so as to be in contact with the organic semiconductor layer 14 (so as to be electrically connected). Form.
　ここで本実施の形態では、これらのソース・ドレイン電極１５Ａ，１５Ｂを、印刷法（印刷プロセス）を用いて形成する。また、前述した所定のパターンからなる電極分離層１６を形成した後に、この電極分離層１６の非形成領域の少なくとも一部分に対して印刷法を用いて、ソース・ドレイン電極１５Ａ，１５Ｂを形成する。すなわち、ここではこのような電極分離層１６を利用して、ソース・ドレイン電極１５Ａ，１５Ｂを形成するようにする。このとき、この電極分離層１６もまた、印刷法を用いて形成することが可能である。このようにしてソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６を形成する際の印刷法としては、例えば、反転印刷法等の転写印刷法、グラビアオフセット法、インクジェット法などが挙げられるが、特に限定はされない。以下、本実施の形態では、反転印刷法を用いてソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６を形成する場合について説明する。 In this embodiment, the source / drain electrodes 15A and 15B are formed by using a printing method (printing process). Further, after the electrode separation layer 16 having the predetermined pattern is formed, the source / drain electrodes 15A and 15B are formed by using a printing method on at least a part of the non-formation region of the electrode separation layer 16. That is, here, the electrode / separation layer 16 is used to form the source / drain electrodes 15A and 15B. At this time, the electrode separation layer 16 can also be formed using a printing method. Examples of the printing method for forming the source / drain electrodes 15A and 15B and the electrode separation layer 16 in this way include a transfer printing method such as a reverse printing method, a gravure offset method, and an inkjet method. There is no limitation. Hereinafter, in the present embodiment, a case where the source / drain electrodes 15A and 15B and the electrode separation layer 16 are formed by using the reverse printing method will be described.
　具体的には、まず図４Ａに示したように、転写版９１上に、前述した所定のパターンからなる電極分離層１６を形成する。そして、図４Ｂに示したように、この転写版９１上の電極分離層１６を、ゲート絶縁膜１３および有機半導体層１４の上の前述した位置に転写させ、その後、この電極分離層１６の乾燥および焼成を行う。これにより、ゲート絶縁膜１３および有機半導体層１４の上に、所定のパターンからなる電極分離層１６が形成される。 Specifically, first, as shown in FIG. 4A, the electrode separation layer 16 having the predetermined pattern described above is formed on the transfer plate 91. Then, as shown in FIG. 4B, the electrode separation layer 16 on the transfer plate 91 is transferred to the above-mentioned positions on the gate insulating film 13 and the organic semiconductor layer 14, and then the electrode separation layer 16 is dried. And firing. Thereby, an electrode isolation layer 16 having a predetermined pattern is formed on the gate insulating film 13 and the organic semiconductor layer 14.
　次いで、図４Ｃに示したように、転写版９２上に、所定のパターンからなるソース・ドレイン電極１５Ａ，１５Ｂを形成する。そして、図４Ｄに示したように、この転写版９２上のソース・ドレイン電極１５Ａ，１５Ｂを、ゲート絶縁膜１３および有機半導体層１４の上における、電極分離層１６の非形成領域の少なくとも一部分（電極分離層１６の隙間）に転写させる。これにより、ゲート絶縁膜１３および有機半導体層１４の上に、一対のソース・ドレイン電極１５Ａ，１５Ｂが形成される。 Next, as shown in FIG. 4C, source / drain electrodes 15 A and 15 B having a predetermined pattern are formed on the transfer plate 92. Then, as shown in FIG. 4D, the source / drain electrodes 15A and 15B on the transfer plate 92 are formed on at least a part of a region where the electrode isolation layer 16 is not formed on the gate insulating film 13 and the organic semiconductor layer 14 ( It is transferred to the gaps of the electrode separation layer 16. Thereby, a pair of source / drain electrodes 15A and 15B are formed on the gate insulating film 13 and the organic semiconductor layer.
（保護膜１７の形成工程）
　次に、電極分離層１６およびソース・ドレイン電極１５Ａ，１５Ｂの上に、上述した材料からなる保護膜１７を形成する。具体的には、例えば（Ｃ６Ｆ１０）ｎなどのフッ素樹脂を全面塗布した後、その膜上に一般的なレジスト膜（フォトレジスト膜）を塗布し、フォトリソグラフィ技術を用いて所望のパターンを形成することにより、保護膜１７を形成する。このフォトリソグラフィ技術を用いたパターン形成の際には、例えば酸素プラズマを用いて、フッ素樹脂膜をドライエッチング加工する。そして、エッチング加工後は、フォトレジスト膜を除去する。なお、感光性フッ素樹脂を用いた、フォトリソグラフィ技術によるパターン形成も可能である。また、ここでは、フォトリソグラフィ技術を用いたパターン形成を例に挙げて説明したが、これには限られない。以上により、図１に示した薄膜トランジスタ１が完成する。 (Formation process of protective film 17)
Next, the protective film 17 made of the above-described material is formed on the electrode isolation layer 16 and the source / drain electrodes 15A and 15B. Specifically, for example, after applying a fluororesin such as (C 6 F 10 ) n over the entire surface, a general resist film (photoresist film) is applied on the film, and a desired pattern is formed using a photolithography technique. By forming the protective film 17, the protective film 17 is formed. At the time of pattern formation using this photolithography technique, the fluororesin film is dry-etched using, for example, oxygen plasma. Then, after the etching process, the photoresist film is removed. Note that pattern formation by a photolithography technique using a photosensitive fluororesin is also possible. Here, the pattern formation using the photolithography technique has been described as an example, but the present invention is not limited to this. Thus, the thin film transistor 1 shown in FIG. 1 is completed.
［薄膜トランジスタ１の作用・効果］
　この薄膜トランジスタ１では、ゲート電極１２に所定の閾値電圧以上の電圧（ゲート電圧）が印加されると、有機半導体層１４内にチャネル（チャネル領域）が形成される。これにより、ソース・ドレイン電極１５Ａ，１５Ｂ間に電流（ドレイン電流）が流れ、トランジスタ（有機ＴＦＴ）として機能する。 [Operation / Effect of Thin Film Transistor 1]
In the thin film transistor 1, when a voltage (gate voltage) higher than a predetermined threshold voltage is applied to the gate electrode 12, a channel (channel region) is formed in the organic semiconductor layer 14. Thereby, a current (drain current) flows between the source / drain electrodes 15A and 15B, and functions as a transistor (organic TFT).
　ところで、このような有機ＴＦＴでは、有機半導体層上に金属層を直性成膜してエッチング加工することにより、ソース・ドレイン電極を形成する手法が用いられている。ところがこの手法では、有機半導体と電極金属との組合せによっては、有機半導体の表面にダメージが生じ、特性劣化をもたらすおそれがある。 By the way, in such an organic TFT, a method of forming a source / drain electrode by directly forming a metal layer on an organic semiconductor layer and etching it is used. However, with this method, depending on the combination of the organic semiconductor and the electrode metal, the surface of the organic semiconductor may be damaged, leading to characteristic deterioration.
　これに対して、印刷プロセス（印刷法）を用いて、トップコンタクト型のソース・ドレイン電極を直接パターン形成する場合、理想的には、チャネル上の有機半導体層の表面に何も触れることなく、ソース・ドレイン電極を形成することができる。したがって、有機半導体層へのダメージを抑えつつトップコンタクト構造を形成することができ、良好なトランジスタ特性が得られる。つまり、印刷法は、トップコンタクト型の有機ＴＦＴを製造する際に、ソース・ドレイン電極の形成方法として好適な手法であると言える。また、このような印刷法による電極形成技術の中でも、反転オフセット印刷法による配線形成技術は、精細度において優れた成果を収めている。 On the other hand, when directly patterning the top contact type source / drain electrodes using a printing process (printing method), ideally, without touching the surface of the organic semiconductor layer on the channel, Source / drain electrodes can be formed. Therefore, a top contact structure can be formed while suppressing damage to the organic semiconductor layer, and good transistor characteristics can be obtained. That is, it can be said that the printing method is a suitable method as a method of forming the source / drain electrodes when manufacturing the top contact type organic TFT. Among the electrode forming techniques based on the printing method, the wiring forming technique based on the reverse offset printing method has achieved excellent results in definition.
（比較例）
　ところが、図５に示した比較例に係る薄膜トランジスタ（薄膜トランジスタ１０１）では、本実施の形態の薄膜トランジスタ１とは異なり、前述した電極分離層１６を利用したソース・ドレイン電極１５Ａ，１５Ｂの形成がなされていないため、以下の問題が生じ得る。 (Comparative example)
However, in the thin film transistor (thin film transistor 101) according to the comparative example shown in FIG. 5, unlike the thin film transistor 1 of the present embodiment, the source / drain electrodes 15A and 15B using the electrode separation layer 16 are formed. Therefore, the following problems may occur.
　すなわち、まず、印刷法による微細パターンの形成は、寸法再現性の観点からハードルが高く、特にチャネル長Ｌが１０μｍ程度以下となる短チャネルデバイスにおけるソース・ドレイン電極を印刷法により形成するのは、困難を極める。具体的には、ソース・ドレイン電極を印刷により形成する際に、インクがペースト状であることから焼成までの間に液だれを起こして電極形状が変化し易く、チャネル長Ｌが変動してしまう。また、印刷時の押し付け圧により、ソース・ドレイン電極同士が接触（ショート）し易い。 That is, first, the fine pattern formation by the printing method has a high hurdle from the viewpoint of dimensional reproducibility, and in particular, the source / drain electrodes in the short channel device in which the channel length L is about 10 μm or less are formed by the printing method. Extremely difficult. Specifically, when the source / drain electrodes are formed by printing, since the ink is in a paste form, dripping occurs before firing and the electrode shape easily changes, and the channel length L varies. . Further, the source / drain electrodes are likely to contact (short) due to the pressing pressure during printing.
　このように比較例の薄膜トランジスタ１０１では、ソース・ドレイン電極１５Ａ，１５Ｂを印刷法により形成する際に、ソース・ドレイン電極１５Ａ，１５Ｂ間の距離（チャネル長Ｌ）のばらつき（変動）が生じ得る。その結果、薄膜トランジスタ１０１の特性劣化や、ソース・ドレイン電極１５Ａ，１５Ｂ間の短絡（ショート）等を招き、素子の信頼性が低下してしまうことになる。 As described above, in the thin film transistor 101 of the comparative example, when the source / drain electrodes 15A and 15B are formed by the printing method, the distance (channel length L) between the source / drain electrodes 15A and 15B may vary (fluctuate). As a result, the characteristics of the thin film transistor 101 are deteriorated, the source / drain electrodes 15A and 15B are short-circuited, and the reliability of the device is lowered.
（本実施の形態の作用）
　そこで本実施の形態では、以下説明するようにして、上記比較例における問題点を解消している。具体的には、まず、本実施の形態の薄膜トランジスタ１では、一対のソース・ドレイン電極１５Ａ，１５Ｂ間に、有機半導体層１４におけるチャネル領域（チャネル長Ｌ）を制御するための電極分離層１６（チャネル領域制御層）が設けられている。換言すると、この薄膜トランジスタ１を製造する際に、所定のパターンからなる電極分離層１６が形成された後に、この電極分離層１６の非形成領域の少なくとも一部分に対して印刷法を用いることにより、一対のソース・ドレイン電極１５Ａ，１５Ｂが形成される。 (Operation of this embodiment)
Therefore, in this embodiment, as described below, the problem in the comparative example is solved. Specifically, first, in the thin film transistor 1 of the present embodiment, the electrode separation layer 16 (for controlling the channel region (channel length L) in the organic semiconductor layer 14 between the pair of source / drain electrodes 15A and 15B ( A channel region control layer) is provided. In other words, when the thin film transistor 1 is manufactured, after the electrode separation layer 16 having a predetermined pattern is formed, a printing method is used for at least a part of the non-formation region of the electrode separation layer 16 to form a pair. Source / drain electrodes 15A and 15B are formed.
　これにより、ソース・ドレイン電極１５Ａ，１５Ｂ間の距離（チャネル長Ｌ）が、電極分離層１６のパターンによって制御（規定）されるようになる。その結果、薄膜トランジスタ１では、印刷法を用いたソース・ドレイン電極１５Ａ，１５Ｂ形成の際の、チャネル長Ｌのばらつき（変動）が抑えられる。 Thereby, the distance (channel length L) between the source / drain electrodes 15A and 15B is controlled (defined) by the pattern of the electrode separation layer 16. As a result, in the thin film transistor 1, the variation (variation) in the channel length L when the source / drain electrodes 15A and 15B are formed using the printing method is suppressed.
　以上のように本実施の形態では、有機半導体層１４と電気的に接続された一対のソース・ドレイン電極１５Ａ，１５Ｂ間に電極分離層１６を設ける。換言すると、所定のパターンからなる電極分離層１６を形成した後に、この電極分離層１６の非形成領域の少なくとも一部分に対して印刷法を用いることにより、一対のソース・ドレイン電極１５Ａ，１５Ｂを形成する。これにより、印刷法を用いたソース・ドレイン電極１５Ａ，１５Ｂ形成の際のチャネル長Ｌのばらつきを抑えることができる。具体的には、印刷の際の寸法再現性やインクの粘性等によらず、チャネル長Ｌを再現性良く形成することができる。よって、素子の信頼性を向上させることが可能となる。 As described above, in the present embodiment, the electrode separation layer 16 is provided between the pair of source / drain electrodes 15A and 15B electrically connected to the organic semiconductor layer 14. In other words, after forming the electrode separation layer 16 having a predetermined pattern, a pair of source / drain electrodes 15A and 15B are formed by using a printing method on at least a part of the non-formation region of the electrode separation layer 16. To do. Thereby, it is possible to suppress variations in the channel length L when the source / drain electrodes 15A and 15B are formed using the printing method. Specifically, the channel length L can be formed with good reproducibility regardless of the dimensional reproducibility during printing and the viscosity of the ink. Therefore, the reliability of the element can be improved.
　以下、本開示の他の実施の形態（第２，第３の実施の形態）について説明する。なお、第１の実施の形態における構成要素と同一のものには同一の符号を付し、適宜説明を省略する。 Hereinafter, other embodiments of the present disclosure (second and third embodiments) will be described. In addition, the same code | symbol is attached | subjected to the same thing as the component in 1st Embodiment, and description is abbreviate | omitted suitably.
＜第２の実施の形態＞
［薄膜トランジスタ１Ａの構成］
　図６は、第２の実施の形態に係る半導体素子（薄膜トランジスタ１Ａ）の概略構成例を、断面図で模式的に表したものである。本実施の形態の薄膜トランジスタ１Ａは、第１の実施の形態の薄膜トランジスタ１（トップコンタクト・ボトムゲート型）とは異なり、トップコンタクト・トップゲート型の有機ＴＦＴである。 <Second Embodiment>
[Configuration of Thin Film Transistor 1A]
FIG. 6 schematically shows a schematic configuration example of the semiconductor element (thin film transistor 1A) according to the second embodiment in a cross-sectional view. Unlike the thin film transistor 1 (top contact / bottom gate type) of the first embodiment, the thin film transistor 1A of the present embodiment is a top contact / top gate type organic TFT.
　すなわち、この薄膜トランジスタ１Ａは、例えば、基板１１上に、絶縁膜１８、有機半導体層１４、一対のソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６、ゲート絶縁膜１３、ゲート電極１２、ならびに保護膜１７がこの順に積層された構造を有している。つまり、ゲート電極１２およびゲート絶縁膜１３の積層位置（形成順序）が異なっている点、および絶縁膜１８を更に設けるようにした点を除いては、基本的には薄膜トランジスタ１と同様の構成となっている。 That is, the thin film transistor 1A includes, for example, an insulating film 18, an organic semiconductor layer 14, a pair of source / drain electrodes 15A and 15B and an electrode separation layer 16, a gate insulating film 13, a gate electrode 12, and a protective film on a substrate 11. 17 has a structure laminated in this order. That is, the configuration is basically the same as that of the thin film transistor 1 except that the stacked positions (formation order) of the gate electrode 12 and the gate insulating film 13 are different and the insulating film 18 is further provided. It has become.
　絶縁膜１８は、基板１１と、有機半導体層１４、ソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６との間に設けられており、例えば前述したゲート絶縁膜１３と同様の絶縁性材料からなる。 The insulating film 18 is provided between the substrate 11, the organic semiconductor layer 14, the source / drain electrodes 15 </ b> A and 15 </ b> B, and the electrode separation layer 16. For example, the insulating film 18 is made of the same insulating material as the gate insulating film 13 described above. .
［薄膜トランジスタ１Ａの製造方法］
　この薄膜トランジスタ１Ａは、例えば次のようにして製造することができる。図７Ａ～図９Ｄは、薄膜トランジスタ１Ａの製造方法における主要な工程例を、工程順に断面図で表わしたものである。 [Method for Manufacturing Thin Film Transistor 1A]
The thin film transistor 1A can be manufactured, for example, as follows. FIG. 7A to FIG. 9D show main process examples in the manufacturing method of the thin film transistor 1A in cross-sectional views in the order of the processes.
（絶縁膜１８の形成工程）
　本実施の形態では、まず、図７Ａに示したように、基板１１上に絶縁膜１８を形成する。この絶縁膜１８の形成方法（成膜方法）は、前述したゲート絶縁膜１３の場合と基本的には同様である。 (Process for forming insulating film 18)
In the present embodiment, first, an insulating film 18 is formed on the substrate 11 as shown in FIG. 7A. The formation method (film formation method) of the insulating film 18 is basically the same as that of the gate insulating film 13 described above.
（有機半導体層１４の形成工程）
　次いで、例えば図７Ｂ～図７Ｄに示したように、絶縁膜１８上に、第１の実施の形態と同様の手法を用いて、前述した島形状からなる有機半導体層１４を形成する。すなわち、絶縁膜１８上に有機半導体層１４を成膜した後、所定のマスクパターン（レジストパターン）からなるレジスト膜８３（フォトレジスト膜）を用いて、有機半導体層１４のパターニング（素子分離）を行う。 (Formation process of the organic semiconductor layer 14)
Next, as shown in FIGS. 7B to 7D, for example, the organic semiconductor layer 14 having the island shape described above is formed on the insulating film 18 by using the same method as in the first embodiment. That is, after the organic semiconductor layer 14 is formed on the insulating film 18, the organic semiconductor layer 14 is patterned (element isolation) using a resist film 83 (photoresist film) made of a predetermined mask pattern (resist pattern). Do.
（ソース・ドレイン電極１５Ａ，１５Ｂの形成工程）
　続いて、図８Ａ～図８Ｄに示したように、第１の実施の形態と同様の手法を用いて、有機半導体層１４上にこの有機半導体層１４と接するように（電気的に接続されるように）、一対のソース・ドレイン電極１５Ａ，１５Ｂを形成する。 (Process for forming source / drain electrodes 15A and 15B)
Subsequently, as shown in FIGS. 8A to 8D, the organic semiconductor layer 14 is in contact with (electrically connected to) the organic semiconductor layer 14 by using the same technique as in the first embodiment. Thus, a pair of source / drain electrodes 15A and 15B is formed.
　すなわち、本実施の形態においても、所定のパターンからなる電極分離層１６を利用して、ソース・ドレイン電極１５Ａ，１５Ｂを形成する。またこのとき、反転印刷法等の印刷法を用いて、ソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６を形成する。 That is, also in the present embodiment, the source / drain electrodes 15A and 15B are formed using the electrode separation layer 16 having a predetermined pattern. At this time, the source / drain electrodes 15A and 15B and the electrode separation layer 16 are formed using a printing method such as a reverse printing method.
（ゲート絶縁膜１３の形成工程）
　次に、図９Ａに示したように、第１の実施の形態と同様の手法を用いて、ソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６の上を覆うようにゲート絶縁膜１３を形成する。 (Formation process of gate insulating film 13)
Next, as shown in FIG. 9A, the gate insulating film 13 is formed so as to cover the source / drain electrodes 15A and 15B and the electrode isolation layer 16 by using the same method as in the first embodiment. .
（ゲート電極１２の形成工程）
　次いで、図９Ｂ～図９Ｄに示したように、第１の実施の形態と同様の手法を用いて、ゲート絶縁膜１３上にゲート電極１２を形成する。すなわち、ゲート絶縁膜１３上に電極膜１２０を成膜した後、所定のマスクパターン（レジストパターン）からなるレジスト膜８４（フォトレジスト膜）を用いて、電極膜１２０のパターニングを行うことにより、ゲート電極１２を形成する。 (Formation process of gate electrode 12)
Next, as shown in FIGS. 9B to 9D, the gate electrode 12 is formed on the gate insulating film 13 by using the same method as in the first embodiment. That is, after the electrode film 120 is formed on the gate insulating film 13, the electrode film 120 is patterned using a resist film 84 (photoresist film) made of a predetermined mask pattern (resist pattern). The electrode 12 is formed.
（保護膜１７の形成工程）
　続いて、ゲート絶縁膜１３およびゲート電極１２の上に、第１の実施の形態と同様の手法を用いて、保護膜１７を形成する。以上により、図６に示した薄膜トランジスタ１Ａが完成する。 (Formation process of protective film 17)
Subsequently, a protective film 17 is formed on the gate insulating film 13 and the gate electrode 12 by using the same method as in the first embodiment. Thus, the thin film transistor 1A shown in FIG. 6 is completed.
［薄膜トランジスタ１Ａの作用・効果］
　本実施の形態の薄膜トランジスタ１Ａにおいても薄膜トランジスタ１と同様に、一対のソース・ドレイン電極１５Ａ，１５Ｂ間に、有機半導体層１４におけるチャネル領域（チャネル長Ｌ）を制御するための電極分離層１６（チャネル領域制御層）が設けられている。換言すると、この薄膜トランジスタ１Ａを製造する際に、所定のパターンからなる電極分離層１６が形成された後に、この電極分離層１６の非形成領域の少なくとも一部分に対して印刷法を用いることにより、一対のソース・ドレイン電極１５Ａ，１５Ｂが形成される。 [Operation / Effect of Thin Film Transistor 1A]
In the thin film transistor 1A of the present embodiment, similarly to the thin film transistor 1, an electrode isolation layer 16 (channel) for controlling a channel region (channel length L) in the organic semiconductor layer 14 is interposed between the pair of source / drain electrodes 15A and 15B. (Region control layer) is provided. In other words, when the thin film transistor 1A is manufactured, after the electrode separation layer 16 having a predetermined pattern is formed, the printing method is used for at least a part of the non-formation region of the electrode separation layer 16 to form a pair. Source / drain electrodes 15A and 15B are formed.
　したがって、本実施の形態においても、第１の実施の形態と同様の作用により同様の効果を得ることが可能である。すなわち、印刷法を用いたソース・ドレイン電極１５Ａ，１５Ｂ形成の際のチャネル長Ｌのばらつきを抑えることができ、素子の信頼性を向上させることが可能となる。 Therefore, also in this embodiment, it is possible to obtain the same effect by the same operation as that of the first embodiment. That is, variations in the channel length L when forming the source / drain electrodes 15A and 15B using the printing method can be suppressed, and the reliability of the element can be improved.
＜第３の実施の形態＞
［薄膜トランジスタ１Ｂ，１Ｃの構成］
　図１０および図１１はそれぞれ、第３の実施の形態に係る半導体素子（薄膜トランジスタ１Ｂ，１Ｃ）の概略構成例を、断面図で模式的に表したものである。本実施の形態の薄膜トランジスタ１Ｂ，１Ｃはそれぞれ、これまで説明した薄膜トランジスタ１，１Ａ（トップコンタクト型）とは異なり、ボトムコンタクト型の有機ＴＦＴである。つまり、これらの薄膜トランジスタ１Ｂ，１Ｃでは、ソース・ドレイン電極１５Ａ，１５Ｂが、有機半導体層１４の下層においてこの有機半導体層１４と接するように（電気的に接続されるように）なっている。 <Third Embodiment>
[Configuration of Thin Film Transistors 1B and 1C]
FIG. 10 and FIG. 11 schematically show schematic configuration examples of semiconductor elements ( thin film transistors 1B and 1C) according to the third embodiment in cross-sectional views. Unlike the thin film transistors 1 and 1A (top contact type) described so far, the thin film transistors 1B and 1C of the present embodiment are bottom contact type organic TFTs, respectively. In other words, in these thin film transistors 1B and 1C, the source / drain electrodes 15A and 15B are in contact (electrically connected) with the organic semiconductor layer 14 below the organic semiconductor layer 14.
　具体的には、図１０に示した薄膜トランジスタ１Ｂは、ボトムコンタクト・ボトムゲート型の有機ＴＦＴである。すなわち、この薄膜トランジスタ１Ｂは、例えば、基板１１上に、ゲート電極１２、ゲート絶縁膜１３、一対のソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６、有機半導体層１４、ならびに保護膜１７がこの順に積層された構造を有している。 Specifically, the thin film transistor 1B shown in FIG. 10 is a bottom contact / bottom gate type organic TFT. That is, the thin film transistor 1B includes, for example, a gate electrode 12, a gate insulating film 13, a pair of source / drain electrodes 15A and 15B, an electrode separation layer 16, an organic semiconductor layer 14, and a protective film 17 in this order on a substrate 11. It has a laminated structure.
　一方、図１１に示した薄膜トランジスタ１Ｃは、ボトムコンタクト・トップゲート型の有機ＴＦＴである。すなわち、この薄膜トランジスタ１Ｃは、例えば、基板１１上に、絶縁膜１８、一対のソース・ドレイン電極１５Ａ，１５Ｂおよび電極分離層１６、有機半導体層１４、ゲート絶縁膜１３、ゲート電極１２、ならびに保護膜１７がこの順に積層された構造を有している。 On the other hand, the thin film transistor 1C shown in FIG. 11 is a bottom contact / top gate type organic TFT. That is, the thin film transistor 1C includes, for example, an insulating film 18, a pair of source / drain electrodes 15A and 15B and an electrode separation layer 16, an organic semiconductor layer 14, a gate insulating film 13, a gate electrode 12, and a protective film on a substrate 11. 17 has a structure laminated in this order.
［薄膜トランジスタ１Ｂ，１Ｃの作用・効果］
　本実施の形態の薄膜トランジスタ１Ｂ，１Ｃにおいても薄膜トランジスタ１，１Ａと同様に、一対のソース・ドレイン電極１５Ａ，１５Ｂ間に、有機半導体層１４におけるチャネル領域（チャネル長Ｌ）を制御するための電極分離層１６（チャネル領域制御層）が設けられている。換言すると、これらの薄膜トランジスタ１Ｂ，１Ｃを製造する際に、所定のパターンからなる電極分離層１６が形成された後に、この電極分離層１６の非形成領域の少なくとも一部分に対して印刷法を用いることにより、一対のソース・ドレイン電極１５Ａ，１５Ｂが形成される。 [Operations and effects of thin film transistors 1B and 1C]
In the thin film transistors 1B and 1C of the present embodiment, similarly to the thin film transistors 1 and 1A, electrode separation for controlling the channel region (channel length L) in the organic semiconductor layer 14 is performed between the pair of source / drain electrodes 15A and 15B. A layer 16 (channel region control layer) is provided. In other words, when the thin film transistors 1B and 1C are manufactured, after the electrode separation layer 16 having a predetermined pattern is formed, a printing method is used for at least a part of the non-formation region of the electrode separation layer 16. Thus, a pair of source / drain electrodes 15A and 15B is formed.
　したがって、本実施の形態においても、第１，第２の実施の形態と同様の作用により同様の効果を得ることが可能である。すなわち、印刷法を用いたソース・ドレイン電極１５Ａ，１５Ｂ形成の際のチャネル長Ｌのばらつきを抑えることができ、素子の信頼性を向上させることが可能となる。 Therefore, also in this embodiment, it is possible to obtain the same effect by the same operation as in the first and second embodiments. That is, variations in the channel length L when forming the source / drain electrodes 15A and 15B using the printing method can be suppressed, and the reliability of the element can be improved.
＜適用例＞
　続いて、上記各実施の形態で説明した半導体素子（薄膜トランジスタ１，１Ａ～１Ｃ）の適用例（このような半導体素子を１または複数備えてなる半導体装置の、表示装置および電子機器への適用例）について説明する。 <Application example>
Subsequently, application examples of the semiconductor elements ( thin film transistors 1, 1A to 1C) described in the above embodiments (application examples of a semiconductor device including one or a plurality of such semiconductor elements to display devices and electronic devices) ).
［表示装置］
　図１２Ａおよび図１２Ｂは、上記各実施の形態の半導体素子（薄膜トランジスタ１，１Ａ～１Ｃ）を備えた表示装置（表示装置２）の概略構成を模式的に表したものである。具体的には、図１２Ｂは平面構成（Ｘ－Ｙ平面構成）を、図１２Ａは、図１２ＢにおけるＩＩ－ＩＩ線に沿った矢視断面構成（Ｚ－Ｘ断面構成）を、それぞれ示している。 [Display device]
12A and 12B schematically show a schematic configuration of a display device (display device 2) including the semiconductor elements ( thin film transistors 1, 1A to 1C) of the above-described embodiments. Specifically, FIG. 12B shows a planar configuration (XY planar configuration), and FIG. 12A shows an arrow sectional configuration (ZX sectional configuration) along the line II-II in FIG. 12B. .
　この表示装置２は、基板１１、ＴＦＴ層２２（半導体装置）、表示層２３（表示部）および透明基板２４をこの順に積層したものである。具体的には、基板１１における表示領域２０Ａ上には、ＴＦＴ層２２、表示層２３および透明基板２４が積層される一方、基板１１における額縁領域（非表示領域）２０Ｂ上には、これらのＴＦＴ層２２、表示層２３および透明基板２４は積層されていない。 This display device 2 is obtained by laminating a substrate 11, a TFT layer 22 (semiconductor device), a display layer 23 (display portion), and a transparent substrate 24 in this order. Specifically, the TFT layer 22, the display layer 23, and the transparent substrate 24 are stacked on the display region 20 </ b> A in the substrate 11, while these TFTs are formed on the frame region (non-display region) 20 </ b> B in the substrate 11. The layer 22, the display layer 23, and the transparent substrate 24 are not laminated.
　ＴＦＴ層２２は、薄膜（金属膜等の導電膜や、絶縁膜など）を含む複数のデバイスを含む層である。このデバイスしては、画素を選択するためのスイッチング素子としてのＴＦＴの他、容量素子（保持容量素子など）、配線（走査線，信号線など）および電極（画素電極など）等が挙げられる。ここで、上記したＴＦＴが、上記各実施の形態の薄膜トランジスタ（有機ＴＦＴ）により構成されている。すなわち、このＴＦＴ層２２は、１または複数の半導体素子（上記各実施の形態の薄膜トランジスタ）を備えた、本開示の「半導体装置」の一具体例に対応している。 The TFT layer 22 is a layer including a plurality of devices including a thin film (a conductive film such as a metal film or an insulating film). Examples of this device include a TFT as a switching element for selecting a pixel, a capacitor element (such as a storage capacitor element), a wiring (such as a scanning line or a signal line), and an electrode (such as a pixel electrode). Here, the above-described TFT is constituted by the thin film transistor (organic TFT) of each of the above embodiments. That is, the TFT layer 22 corresponds to a specific example of “semiconductor device” of the present disclosure including one or a plurality of semiconductor elements (the thin film transistors of the above embodiments).
　表示層２３は、例えば画素電極と共通電極との間に、電気泳動粒子や液晶層、有機ＥＬ（Electro Luminescence）層あるいは無機ＥＬ層などを含んで構成されている。すなわち、表示層２３は、電気泳動素子や液晶素子、有機ＥＬ素子あるいは無機ＥＬ素子等を用いて構成されている。なお、画素電極はＴＦＴ層２２に画素ごとに設けられ、共通電極は透明基板２４の一面に亘り設けられている。 The display layer 23 includes, for example, an electrophoretic particle, a liquid crystal layer, an organic EL (Electro-Luminescence) layer, or an inorganic EL layer between the pixel electrode and the common electrode. That is, the display layer 23 is configured using an electrophoretic element, a liquid crystal element, an organic EL element, an inorganic EL element, or the like. Note that the pixel electrode is provided for each pixel in the TFT layer 22, and the common electrode is provided over one surface of the transparent substrate 24.
　透明基板２４は、例えば、基板１１と同様の材料を用いて構成されている。なお、この透明基板２４上に、更に表示層２３への水分の浸入を防止する防湿膜および外光の表示面への映り込みを防止するための光学機能膜を設けるようにしてもよい。 The transparent substrate 24 is configured using, for example, the same material as the substrate 11. A moisture-proof film for preventing moisture from entering the display layer 23 and an optical function film for preventing external light from being reflected on the display surface may be provided on the transparent substrate 24.
　ここで、このような表示装置２におけるＴＦＴ層２２（半導体装置）では、これまで説明した薄膜トランジスタ１（１Ａ～１Ｃ）が、例えば以下のように形成されている。具体的には、例えば図１３Ａおよび図１３Ｂに示したように、複数の薄膜トランジスタ１（１Ａ～１Ｃ）が、Ｙ軸方向に沿って配置されている。また、各薄膜トランジスタ１（１Ａ～１Ｃ）における一方のソース・ドレイン電極１５Ｂ（ドレイン電極）に対し、Ｙ軸方向に沿って延在する信号線２２Ｓ（配線）が共通接続されている。そして、少なくとも、この信号線２２Ｓと各薄膜トランジスタ１（１Ａ～１Ｃ）における他方のソース・ドレイン電極１５Ａ（ソース電極）との間の領域に、電極分離層１６が形成されている。 Here, in the TFT layer 22 (semiconductor device) in such a display device 2, the thin film transistor 1 (1A to 1C) described so far is formed as follows, for example. Specifically, for example, as shown in FIGS. 13A and 13B, a plurality of thin film transistors 1 (1A to 1C) are arranged along the Y-axis direction. A signal line 22S (wiring) extending along the Y-axis direction is commonly connected to one source / drain electrode 15B (drain electrode) in each thin film transistor 1 (1A to 1C). An electrode separation layer 16 is formed at least in a region between the signal line 22S and the other source / drain electrode 15A (source electrode) in each thin film transistor 1 (1A to 1C).
　詳細には、図１３Ａに示した例では、信号線２２Ｓと各薄膜トランジスタ１（１Ａ～１Ｃ）における他方のソース・ドレイン電極１５Ａとの間の領域に加え、各薄膜トランジスタ１（１Ａ～１Ｃ）における他方のソース・ドレイン電極１５Ａ同士の間の領域にも、電極分離層１６が形成されている。これにより、図１３Ａの例では、電極分離層１６が、各薄膜トランジスタ１（１Ａ～１Ｃ）における他方のソース・ドレイン電極１５Ａの周囲を囲むように形成されている。このように構成した場合、ソース・ドレイン電極１５Ａを印刷形成する際に、各薄膜トランジスタ１（１Ａ～１Ｃ）におけるソース・ドレイン電極１５Ａ同士が接触しない（短絡しない）ようにすることができ、素子の信頼性を更に向上させることが可能となる。なお、これに対して図１３Ｂに示した例では、各薄膜トランジスタ１（１Ａ～１Ｃ）における他方のソース・ドレイン電極１５Ａ同士の間の領域には、電極分離層１６が形成されていない。 Specifically, in the example shown in FIG. 13A, in addition to the region between the signal line 22S and the other source / drain electrode 15A in each thin film transistor 1 (1A to 1C), the other in each thin film transistor 1 (1A to 1C). An electrode isolation layer 16 is also formed in a region between the source / drain electrodes 15A. Accordingly, in the example of FIG. 13A, the electrode separation layer 16 is formed so as to surround the other source / drain electrode 15A of each thin film transistor 1 (1A to 1C). When configured in this way, when the source / drain electrodes 15A are printed and formed, the source / drain electrodes 15A in the thin film transistors 1 (1A to 1C) can be prevented from contacting each other (not short-circuited). The reliability can be further improved. On the other hand, in the example shown in FIG. 13B, the electrode separation layer 16 is not formed in the region between the other source / drain electrodes 15A in each thin film transistor 1 (1A to 1C).
［電子機器］
　次に、図１４Ａ～図１９を参照して、上記表示装置２の適用例について説明する。この表示装置２は、テレビジョン装置，デジタルカメラ，ノート型パーソナルコンピュータ、携帯電話等の携帯端末装置あるいはビデオカメラなどのあらゆる分野の電子機器に適用することが可能である。言い換えると、表示装置２は、外部から入力された映像信号あるいは内部で生成した映像信号を、画像あるいは映像として表示するあらゆる分野の電子機器に適用することが可能である。 [Electronics]
Next, application examples of the display device 2 will be described with reference to FIGS. 14A to 19. The display device 2 can be applied to electronic devices in various fields such as television devices, digital cameras, notebook personal computers, portable terminal devices such as mobile phones, and video cameras. In other words, the display device 2 can be applied to electronic devices in various fields that display a video signal input from the outside or a video signal generated inside as an image or video.
（適用例１）
　図１４Ａおよび図１４Ｂはそれぞれ、表示装置２が適用される電子ブックの外観を表したものである。この電子ブックは、例えば、表示部２１０および非表示部２２０を有しており、この表示部２１０が表示装置２により構成されている。 (Application example 1)
14A and 14B each show the appearance of an electronic book to which the display device 2 is applied. The electronic book has, for example, a display unit 210 and a non-display unit 220, and the display unit 210 is configured by the display device 2.
（適用例２）
　図１５は、表示装置２が適用されるテレビジョン装置の外観を表したものである。このテレビジョン装置は、例えば、フロントパネル３１０およびフィルターガラス３２０を含む映像表示画面部３００を有しており、この映像表示画面部３００が表示装置２により構成されている。 (Application example 2)
FIG. 15 illustrates an appearance of a television device to which the display device 2 is applied. This television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is configured by the display device 2.
（適用例３）
　図１６Ａおよび図１６Ｂは、表示装置２が適用されるデジタルカメラの外観を表したものである。このデジタルカメラは、例えば、フラッシュ用の発光部４１０、表示部４２０、メニュースイッチ４３０およびシャッターボタン４４０を有しており、この表示部４２０が表示装置２により構成されている。 (Application example 3)
16A and 16B show the appearance of a digital camera to which the display device 2 is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440, and the display unit 420 includes the display device 2.
（適用例４）
　図１７は、表示装置２が適用されるノート型パーソナルコンピュータの外観を表したものである。このノート型パーソナルコンピュータは、例えば、本体５１０，文字等の入力操作のためのキーボード５２０および画像を表示する表示部５３０を有しており、この表示部５３０が表示装置２により構成されている。 (Application example 4)
FIG. 17 shows the appearance of a notebook personal computer to which the display device 2 is applied. The notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. The display unit 530 is configured by the display device 2.
（適用例５）
　図１８は、表示装置２が適用されるビデオカメラの外観を表したものである。このビデオカメラは、例えば、本体部６１０，この本体部６１０の前方側面に設けられた被写体撮影用のレンズ６２０，撮影時のスタート／ストップスイッチ６３０および表示部６４０を有している。そして、この表示部６４０が表示装置２により構成されている。 (Application example 5)
FIG. 18 shows the appearance of a video camera to which the display device 2 is applied. This video camera includes, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. The display unit 640 includes the display device 2.
（適用例６）
　図１９は、表示装置２が適用される携帯電話機の外観を表したものである。この携帯電話機は、例えば、上側筐体７１０と下側筐体７２０とを連結部（ヒンジ部）７３０で連結したものであり、ディスプレイ７４０，サブディスプレイ７５０，ピクチャーライト７６０およびカメラ７７０を有している。そして、これらのうちのディスプレイ７４０またはサブディスプレイ７５０が、表示装置２により構成されている。 (Application example 6)
FIG. 19 shows an appearance of a mobile phone to which the display device 2 is applied. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. Of these, the display 740 or the sub-display 750 is constituted by the display device 2.
＜変形例＞
　以上、いくつかの実施の形態および適用例を挙げて本開示の技術を説明したが、本技術はこれらの実施の形態等に限定されず、種々の変形が可能である。 <Modification>
The technology of the present disclosure has been described above with some embodiments and application examples, but the technology is not limited to these embodiments and the like, and various modifications are possible.
　例えば、上記実施の形態等において説明した各層の材料および厚み、または成膜方法および成膜条件等は限定されるものではなく、他の材料および厚みとしてもよく、または他の成膜方法および成膜条件としてもよい。具体的には、例えば、半導体素子（薄膜トランジスタ）を形成する工程において、複数の電極（一対のソース・ドレイン電極）を形成した後に、電極分離層（チャネル領域制御層）を除去するようにしてもよい。すなわち、この電極分離層を、複数の電極を形成する際の犠牲層として用い、最終的に製造された半導体素子内に残っていないようにしてもよい。また、上記実施の形態等では、表示装置の構成を具体的に挙げて説明したが、全ての層を備える必要はなく、また、他の層を更に備えていてもよい。 For example, the material and thickness of each layer described in the above embodiment and the like, or the film formation method and film formation conditions are not limited, and other materials and thicknesses may be used. It is good also as film | membrane conditions. Specifically, for example, in the step of forming a semiconductor element (thin film transistor), after forming a plurality of electrodes (a pair of source / drain electrodes), the electrode separation layer (channel region control layer) may be removed. Good. In other words, this electrode separation layer may be used as a sacrificial layer when forming a plurality of electrodes so that it does not remain in the finally manufactured semiconductor device. In the above-described embodiments and the like, the configuration of the display device has been specifically described, but it is not necessary to include all layers, and other layers may be further included.
　また、上記実施の形態等では、半導体素子（薄膜トランジスタ）における半導体層が有機半導体層である場合（有機ＴＦＴである場合）を例に挙げて説明したが、これには限られない。すなわち、半導体層が無機半導体（例えば、シリコン（Ｓｉ），化合物半導体，酸化物半導体等）であってもよい（無機ＴＦＴであってもよい）。 In the above-described embodiment and the like, the case where the semiconductor layer in the semiconductor element (thin film transistor) is an organic semiconductor layer (in the case of an organic TFT) has been described as an example, but the present invention is not limited thereto. That is, the semiconductor layer may be an inorganic semiconductor (for example, silicon (Si), a compound semiconductor, an oxide semiconductor, etc.) (may be an inorganic TFT).
　更に、上記実施の形態等では、本開示の半導体素子の一例として、有機半導体層、ゲート電極、一対のソース・ドレイン電極および配線層を備えた薄膜トランジスタ（有機ＴＦＴ）を挙げて説明したが、これには限られない。すなわち、例えば、有機半導体層、一対の電極（アノード電極およびカソード電極）ならびに配線層を備えたダイオード（整流素子）等の他の半導体素子に対しても、本技術を適当することが可能である。 Furthermore, in the above-described embodiment and the like, as an example of the semiconductor element of the present disclosure, a thin film transistor (organic TFT) including an organic semiconductor layer, a gate electrode, a pair of source / drain electrodes, and a wiring layer has been described. It is not limited to. That is, for example, the present technology can also be applied to other semiconductor elements such as an organic semiconductor layer, a pair of electrodes (anode electrode and cathode electrode), and a diode (rectifier element) including a wiring layer. .
　加えて、本開示の半導体素子（半導体装置）は、上記実施の形態等で説明した表示装置には限られず、例えば、受光素子（センサ）や太陽電池等の他のデバイス、およびそれらのデバイスを備えた電子機器などにも適用することが可能である。 In addition, the semiconductor element (semiconductor device) of the present disclosure is not limited to the display device described in the above embodiment and the like, for example, other devices such as a light receiving element (sensor) and a solar battery, and those devices. The present invention can also be applied to electronic devices provided.
　なお、本技術は以下のような構成を取ることも可能である。
（１）
　１または複数の半導体素子を備え、
　前記半導体素子は、
　半導体層と、
　前記半導体層と電気的に接続された複数の電極と、
　前記複数の電極間に配設された電極分離層と
　を有する半導体装置。
（２）
　前記半導体素子が、前記半導体層と、ゲート電極と、前記複数の電極としての一対のソース・ドレイン電極と、前記電極分離層とを有する薄膜トランジスタである
　上記（１）に記載の半導体装置。
（３）
　前記電極分離層は、前記半導体層におけるチャネル領域を制御するものである
　上記（２）に記載の半導体装置。
（４）
　前記電極分離層は、前記チャネル領域におけるチャネル長を制御するものである
　上記（３）に記載の半導体装置。
（５）
　前記半導体素子が複数設けられると共に、各半導体素子における前記一対のソース・ドレイン電極のうちの一方の電極に対して共通接続された配線が設けられ、
　少なくとも前記配線と各半導体素子における他方の電極との間の領域に、前記電極分離層が形成されている
　上記（２）ないし（４）のいずれかに記載の半導体装置。
（６）
　各半導体素子における前記他方の電極同士の間の領域にも、前記電極分離層が形成されている
　上記（５）に記載の半導体装置。
（７）
　前記電極分離層が、各半導体素子における前記他方の電極の周囲を囲むように形成されている
　上記（６）に記載の半導体装置。
（８）
　前記複数の電極は、前記半導体層上でこの半導体層と電気的に接続されている
　上記（２）ないし（７）のいずれかに記載の半導体装置。
（９）
　前記薄膜トランジスタは、ゲート絶縁膜および保護膜を備え、
　基板上に、前記ゲート電極、前記ゲート絶縁膜、前記半導体層、前記一対のソース・ドレイン電極および前記保護膜の順に積層されている
　上記（８）に記載の半導体装置。
（１０）
　前記半導体層が有機半導体層である
　上記（１）ないし（９）のいずれかに記載の半導体装置。
（１１）
　１または複数の半導体素子を有する半導体装置と表示部とを備え、
　前記半導体素子は、
　半導体層と、
　前記半導体層と電気的に接続された複数の電極と、
　前記複数の電極間に配設された電極分離層と
　を有する表示装置。
（１２）
　表示装置を備え、
　前記表示装置は、１または複数の半導体素子を有する半導体装置と表示部とを備え、
　前記半導体素子は、
　半導体層と、
　前記半導体層と電気的に接続された複数の電極と、
　前記複数の電極間に配設された電極分離層と
　を有する電子機器。
（１３）
　基板上に１または複数の半導体素子を形成する工程を含み、
　前記半導体素子を形成する工程は、前記基板上に、半導体層およびこの半導体層と電気的に接続された複数の電極を形成する工程を含み、
　前記複数の電極を形成する工程では、所定のパターンからなる電極分離層を形成した後に、この電極分離層の非形成領域の少なくとも一部分に対して印刷プロセスを用いることにより、前記複数の電極を形成する
　半導体装置の製造方法。
（１４）
　前記電極分離層を、印刷プロセスを用いて形成する
　上記（１３）に記載の半導体装置の製造方法。
（１５）
　前記印刷プロセスとして、転写印刷法を用いる
　上記（１３）または（１４）に記載の半導体装置の製造方法。
（１６）
　前記半導体素子を形成する工程は、前記複数の電極を形成した後に前記電極分離層を除去する工程を含む
　上記（１３）ないし（１５）のいずれかに記載の半導体装置の製造方法。 In addition, this technique can also take the following structures.
(1)
Comprising one or more semiconductor elements,
The semiconductor element is
A semiconductor layer;
A plurality of electrodes electrically connected to the semiconductor layer;
A semiconductor device comprising: an electrode separation layer disposed between the plurality of electrodes.
(2)
The semiconductor device according to (1), wherein the semiconductor element is a thin film transistor including the semiconductor layer, a gate electrode, a pair of source / drain electrodes as the plurality of electrodes, and the electrode separation layer.
(3)
The semiconductor device according to (2), wherein the electrode separation layer controls a channel region in the semiconductor layer.
(4)
The semiconductor device according to (3), wherein the electrode separation layer controls a channel length in the channel region.
(5)
A plurality of the semiconductor elements are provided, and a wiring commonly connected to one of the pair of source / drain electrodes in each semiconductor element is provided,
The semiconductor device according to any one of (2) to (4), wherein the electrode isolation layer is formed at least in a region between the wiring and the other electrode of each semiconductor element.
(6)
The semiconductor device according to (5), wherein the electrode separation layer is also formed in a region between the other electrodes in each semiconductor element.
(7)
The semiconductor device according to (6), wherein the electrode separation layer is formed so as to surround a periphery of the other electrode in each semiconductor element.
(8)
The semiconductor device according to any one of (2) to (7), wherein the plurality of electrodes are electrically connected to the semiconductor layer on the semiconductor layer.
(9)
The thin film transistor includes a gate insulating film and a protective film,
The semiconductor device according to (8), wherein the gate electrode, the gate insulating film, the semiconductor layer, the pair of source / drain electrodes, and the protective film are stacked in this order on a substrate.
(10)
The semiconductor device according to any one of (1) to (9), wherein the semiconductor layer is an organic semiconductor layer.
(11)
A semiconductor device having one or more semiconductor elements and a display unit;
The semiconductor element is
A semiconductor layer;
A plurality of electrodes electrically connected to the semiconductor layer;
A display device comprising: an electrode separation layer disposed between the plurality of electrodes.
(12)
A display device,
The display device includes a semiconductor device having one or a plurality of semiconductor elements and a display unit,
The semiconductor element is
A semiconductor layer;
A plurality of electrodes electrically connected to the semiconductor layer;
And an electrode separation layer disposed between the plurality of electrodes.
(13)
Forming one or more semiconductor elements on a substrate;
The step of forming the semiconductor element includes a step of forming a semiconductor layer and a plurality of electrodes electrically connected to the semiconductor layer on the substrate,
In the step of forming the plurality of electrodes, after forming an electrode separation layer having a predetermined pattern, the plurality of electrodes are formed by using a printing process on at least a part of the non-formation region of the electrode separation layer. A method for manufacturing a semiconductor device.
(14)
The method for manufacturing a semiconductor device according to (13), wherein the electrode separation layer is formed using a printing process.
(15)
The method for manufacturing a semiconductor device according to (13) or (14), wherein a transfer printing method is used as the printing process.
(16)
The step of forming the semiconductor element includes a step of removing the electrode separation layer after forming the plurality of electrodes. The method for manufacturing a semiconductor device according to any one of (13) to (15).
　本出願は、日本国特許庁において２０１２年３月２６日に出願された日本特許出願番号２０１２－６８８４４号を基礎として優先権を主張するものであり、この出願のすべての内容を参照によって本出願に援用する。 This application claims priority on the basis of Japanese Patent Application No. 2012-68844 filed on March 26, 2012 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.
　当業者であれば、設計上の要件や他の要因に応じて、種々の修正、コンビネーション、サブコンビネーション、および変更を想到し得るが、それらは添付の請求の範囲やその均等物の範囲に含まれるものであることが理解される。 Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (16)

  1. 　１または複数の半導体素子を備え、
    　前記半導体素子は、
    　半導体層と、
    　前記半導体層と電気的に接続された複数の電極と、
    　前記複数の電極間に配設された電極分離層と
    　を有する半導体装置。     Comprising one or more semiconductor elements,
    The semiconductor element is
    A semiconductor layer;
    A plurality of electrodes electrically connected to the semiconductor layer;
    A semiconductor device comprising: an electrode separation layer disposed between the plurality of electrodes.
  2. 　前記半導体素子が、前記半導体層と、ゲート電極と、前記複数の電極としての一対のソース・ドレイン電極と、前記電極分離層とを有する薄膜トランジスタである
    　請求項１に記載の半導体装置。     The semiconductor device according to claim 1, wherein the semiconductor element is a thin film transistor including the semiconductor layer, a gate electrode, a pair of source / drain electrodes as the plurality of electrodes, and the electrode separation layer.
  3. 　前記電極分離層は、前記半導体層におけるチャネル領域を制御するものである
    　請求項２に記載の半導体装置。     The semiconductor device according to claim 2, wherein the electrode separation layer controls a channel region in the semiconductor layer.
  4. 　前記電極分離層は、前記チャネル領域におけるチャネル長を制御するものである
    　請求項３に記載の半導体装置。     The semiconductor device according to claim 3, wherein the electrode isolation layer controls a channel length in the channel region.
  5. 　前記半導体素子が複数設けられると共に、各半導体素子における前記一対のソース・ドレイン電極のうちの一方の電極に対して共通接続された配線が設けられ、
    　少なくとも前記配線と各半導体素子における他方の電極との間の領域に、前記電極分離層が形成されている
    　請求項２に記載の半導体装置。     A plurality of the semiconductor elements are provided, and a wiring commonly connected to one of the pair of source / drain electrodes in each semiconductor element is provided,
    The semiconductor device according to claim 2, wherein the electrode isolation layer is formed at least in a region between the wiring and the other electrode of each semiconductor element.
  6. 　各半導体素子における前記他方の電極同士の間の領域にも、前記電極分離層が形成されている
    　請求項５に記載の半導体装置。     The semiconductor device according to claim 5, wherein the electrode separation layer is also formed in a region between the other electrodes in each semiconductor element.
  7. 　前記電極分離層が、各半導体素子における前記他方の電極の周囲を囲むように形成されている
    　請求項６に記載の半導体装置。     The semiconductor device according to claim 6, wherein the electrode separation layer is formed so as to surround a periphery of the other electrode in each semiconductor element.
  8. 　前記複数の電極は、前記半導体層上でこの半導体層と電気的に接続されている
    　請求項２に記載の半導体装置。     The semiconductor device according to claim 2, wherein the plurality of electrodes are electrically connected to the semiconductor layer on the semiconductor layer.
  9. 　前記薄膜トランジスタは、ゲート絶縁膜および保護膜を備え、
    　基板上に、前記ゲート電極、前記ゲート絶縁膜、前記半導体層、前記一対のソース・ドレイン電極および前記保護膜の順に積層されている
    　請求項８に記載の半導体装置。     The thin film transistor includes a gate insulating film and a protective film,
    The semiconductor device according to claim 8, wherein the gate electrode, the gate insulating film, the semiconductor layer, the pair of source / drain electrodes, and the protective film are stacked in this order on a substrate.
  10. 　前記半導体層が有機半導体層である
    　請求項１に記載の半導体装置。     The semiconductor device according to claim 1, wherein the semiconductor layer is an organic semiconductor layer.
  11. 　１または複数の半導体素子を有する半導体装置と表示部とを備え、
    　前記半導体素子は、
    　半導体層と、
    　前記半導体層と電気的に接続された複数の電極と、
    　前記複数の電極間に配設された電極分離層と
    　を有する表示装置。     A semiconductor device having one or more semiconductor elements and a display unit;
    The semiconductor element is
    A semiconductor layer;
    A plurality of electrodes electrically connected to the semiconductor layer;
    A display device comprising: an electrode separation layer disposed between the plurality of electrodes.
  12. 　表示装置を備え、
    　前記表示装置は、１または複数の半導体素子を有する半導体装置と表示部とを備え、
    　前記半導体素子は、
    　半導体層と、
    　前記半導体層と電気的に接続された複数の電極と、
    　前記複数の電極間に配設された電極分離層と
    　を有する電子機器。     A display device,
    The display device includes a semiconductor device having one or a plurality of semiconductor elements and a display unit,
    The semiconductor element is
    A semiconductor layer;
    A plurality of electrodes electrically connected to the semiconductor layer;
    And an electrode separation layer disposed between the plurality of electrodes.
  13. 　基板上に１または複数の半導体素子を形成することを含み、
    　前記半導体素子を形成することは、前記基板上に、半導体層およびこの半導体層と電気的に接続された複数の電極を形成することを含み、
    　前記複数の電極を形成することでは、所定のパターンからなる電極分離層を形成した後に、この電極分離層の非形成領域の少なくとも一部分に対して印刷プロセスを用いることにより、前記複数の電極を形成する
    　半導体装置の製造方法。     Forming one or more semiconductor elements on a substrate;
    Forming the semiconductor element includes forming a semiconductor layer and a plurality of electrodes electrically connected to the semiconductor layer on the substrate,
    In forming the plurality of electrodes, after forming an electrode separation layer having a predetermined pattern, the plurality of electrodes are formed by using a printing process on at least a part of the non-formation region of the electrode separation layer. A method for manufacturing a semiconductor device.
  14. 　前記電極分離層を、印刷プロセスを用いて形成する
    　請求項１３に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 13, wherein the electrode separation layer is formed using a printing process.
  15. 　前記印刷プロセスとして、転写印刷法を用いる
    　請求項１３に記載の半導体装置の製造方法。     The method for manufacturing a semiconductor device according to claim 13, wherein a transfer printing method is used as the printing process.
  16. 　前記半導体素子を形成することは、前記複数の電極を形成した後に前記電極分離層を除去することを含む
    　請求項１３に記載の半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 13, wherein forming the semiconductor element includes removing the electrode separation layer after forming the plurality of electrodes.
PCT/JP2013/055090 2012-03-26 2013-02-27 Semiconductor device and method for manufacturing same, display device, and electronic equipment WO2013146035A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-068844 2012-03-26
JP2012068844 2012-03-26

Publications (1)

Publication Number Publication Date
WO2013146035A1 true WO2013146035A1 (en) 2013-10-03

Family

ID=49259311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/055090 WO2013146035A1 (en) 2012-03-26 2013-02-27 Semiconductor device and method for manufacturing same, display device, and electronic equipment

Country Status (1)

Country Link
WO (1) WO2013146035A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003098548A (en) * 2001-09-26 2003-04-03 Hitachi Ltd Liquid crystal display device and manufacturing method therefor
JP2004288880A (en) * 2003-03-24 2004-10-14 Konica Minolta Holdings Inc Thin film transistor and its fabricating process
JP2007329446A (en) * 2006-05-12 2007-12-20 Seiko Epson Corp Method for forming metal wiring, manufacturing method of active matrix substrate, device, electro-optic device, and electronic equipment
JP2011054877A (en) * 2009-09-04 2011-03-17 Konica Minolta Holdings Inc Method of manufacturing thin-film transistor
JP2011187626A (en) * 2010-03-08 2011-09-22 Sony Corp Thin film transistor and electronic apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003098548A (en) * 2001-09-26 2003-04-03 Hitachi Ltd Liquid crystal display device and manufacturing method therefor
JP2004288880A (en) * 2003-03-24 2004-10-14 Konica Minolta Holdings Inc Thin film transistor and its fabricating process
JP2007329446A (en) * 2006-05-12 2007-12-20 Seiko Epson Corp Method for forming metal wiring, manufacturing method of active matrix substrate, device, electro-optic device, and electronic equipment
JP2011054877A (en) * 2009-09-04 2011-03-17 Konica Minolta Holdings Inc Method of manufacturing thin-film transistor
JP2011187626A (en) * 2010-03-08 2011-09-22 Sony Corp Thin film transistor and electronic apparatus

Similar Documents

Publication Publication Date Title
JP6035734B2 (en) Semiconductor element, display device and electronic apparatus
JP5286826B2 (en) Thin film transistor array, method for manufacturing thin film transistor array, and active matrix display
JP2014145857A (en) Display device and method of manufacturing the same, and electronic equipment
KR20190053164A (en) Semiconductor element and electronic apparatus
TWI556452B (en) Semiconductor device, display unit, and electronic apparatus
JP2013105950A (en) Semiconductor device and electronic equipment
TW201316581A (en) Organic thin-film transistor, method of manufacturing organic thin-film transistor, and display
JP5655421B2 (en) Semiconductor device, display device, and electronic device
US9401486B2 (en) Driving circuit board, method of manufacturing the same, display unit, and electronic apparatus
JP2010135584A (en) Thin film transistor, method of manufacturing thin film transistor, display device, and electronic apparatus
JP2012038924A (en) Semiconductor device, display device, and electronic equipment
WO2013146035A1 (en) Semiconductor device and method for manufacturing same, display device, and electronic equipment
CN102916130A (en) Circuit board, method of manufacturing circuit board, display, and electronic unit
TWI655678B (en) Thin film transistor array and image display device
JP2013201201A (en) Thin film transistor array, thin film transistor array manufacturing method and image display device
WO2016052127A1 (en) Thin-film transistor, method for producing thin-film transistor, and display device
JPWO2018038107A1 (en) Organic thin film transistor, method of manufacturing the same and image display device
WO2014155998A1 (en) Thin-film transistor array and image display device
KR20120129771A (en) Semiconductor element and electronic apparatus
US20140070193A1 (en) Transistor, method of manufacturing transistor, method of manufacturing semiconductor unit, and method of manufacturing display unit
JPWO2019078267A1 (en) Organic thin film transistor, its manufacturing method, active matrix array and image display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13767913

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13767913

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP