WO2013132332A1 - Procédés permettant de former des structures semi-conductrices incluant du matériau semi-conducteur iii-v au moyen de substrats comprenant du molybdène, et structures formées par de tels procédés - Google Patents

Procédés permettant de former des structures semi-conductrices incluant du matériau semi-conducteur iii-v au moyen de substrats comprenant du molybdène, et structures formées par de tels procédés Download PDF

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Publication number
WO2013132332A1
WO2013132332A1 PCT/IB2013/000564 IB2013000564W WO2013132332A1 WO 2013132332 A1 WO2013132332 A1 WO 2013132332A1 IB 2013000564 W IB2013000564 W IB 2013000564W WO 2013132332 A1 WO2013132332 A1 WO 2013132332A1
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substrate
molybdenum nitride
substantially planar
molybdenum
layer
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PCT/IB2013/000564
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English (en)
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Christian J. Werkhoven
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Soitec
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Priority claimed from US13/416,697 external-priority patent/US8916483B2/en
Priority claimed from FR1252408A external-priority patent/FR2988219B1/fr
Application filed by Soitec filed Critical Soitec
Publication of WO2013132332A1 publication Critical patent/WO2013132332A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present disclosure relates to methods of forming semiconductor structures that include a ⁇ -V semiconductor material, and to semiconductor structures formed by such methods.
  • Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuit (IC) devices (e.g., logic processors and memory devices) and discrete devices such as, radiation emitting devices (e.g. , light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity surface emitting lasers (VCSELs)), and radiation sensing devices (e.g., optical sensors).
  • IC integrated circuit
  • LEDs light emitting diodes
  • RCLEDs resonant cavity light emitting diodes
  • VCSELs vertical cavity surface emitting lasers
  • Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on and/or in a surface of a semiconductor substrate.
  • wafers Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or "wafers" of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in) or more).
  • silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is generally used to form active devices on the silicon wafer.
  • a very thin layer e.g., less than about three hundred nanometers (300 nm)
  • the majority of the silicon wafer thickness may be included in the electrical path-way of one or more device structures formed from the silicon wafer, such device structures being commonly referred to as "vertical" device structures.
  • So-called "engineered substrates” have been developed that include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred nanometers (300 nm)) disposed on a layer of dielectric material (e.g., silicon dioxide (Si0 2 ), silicon nitride (Si 3 N 4 ), or aluminum oxide (A1 2 0 3 )).
  • the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the semiconductor material and the layer of dielectric material may be disposed on a relatively thicker host or base substrate to facilitate handling of the overall engineered substrate by manufacturing equipment.
  • the base substrate is often referred to in the art as a "handle” or "handling” substrate.
  • the base substrate may also comprise a semiconductor material other than silicon.
  • a wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), III-V semiconductor materials, and 1I-VI semiconductor materials.
  • an engineered substrate may include an epitaxial layer of III-V semiconductor material formed on a surface of a base substrate, such as, for example, aluminum oxide (A1 2 0 3 ) (which may be referred to as "sapphire").
  • the epitaxial layer may be formed on the surface of the base substrate by a transfer process from a donor strudure, for example a donor substrate or donor ingot. The transfer from a donor structure may be desirable when the donor material is highly valuable or in scarce supply.
  • additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V semiconductor material to form one or more devices on the engineered substrate.
  • the Coefficient of Thermal Expansion (CTE) mismatch (or difference) between the epitaxial layer and the base substrate comprising the engineered substrate may influence the formation and processing of the additional layers of material.
  • CTE mismatch between the epitaxial layer and the base substrate is substantial, then the engineered substrate may be negatively impacted during the formation of additional layers of materials.
  • the present disclosure includes methods of fabricating semiconductor structures.
  • molybdenum nitride is formed at one or more surfaces of a substrate comprising molybdenum, and a layer of III- V semiconductor material is provided over the substrate.
  • the present disclosure includes semiconductor structures that include a substrate comprising molybdenum, molybdenum nitride at an at least substantially planar surface of the substrate, and a layer of GaN bonded to the molybdenum nitride.
  • FIG. 1 is a simplified and schematically illustrated cross-sectional view of a substrate comprising molybdenum
  • FIG. 2 illustrates molybdenum nitride at outer surfaces of the substrate shown in
  • FIG. 1 is a diagrammatic representation of FIG. 1 ;
  • FIG. 3 illustrates ions being implanted into a donor structure comprising a III-V semiconductor material
  • FIG. 4 illustrates the donor structure of FIG. 3 bonded to the substrate having molybdenum nitride thereon as shown in FIG. 2;
  • FIG. 5 illustrates a layer of III-V semiconductor material transferred from the donor structure of FIG. 3 to the substrate having molybdenum nitride thereon;
  • FIG. 6 illustrates the structure of FIG. 5 after polishing an exposed major surface thereof
  • FIG. 7 illustrates an additional epitaxial layer of III-V semiconductor material formed over the transferred layer of III-V semiconductor material.
  • IIIVV semiconductor material means and includes any semiconductor material that is at least predominantly comprised of one or more elements from group IIIA of the periodic table (B, Al, Ga, In, and Tl) and one or more elements from group VA of the periodic table (N, P, As, Sb, and Bi).
  • III-V semiconductor materials include, but are not limited to, GaN, GaP, GaAs, InN, InP, InAs, A1N, A1P, AlAs, InGaN, InGaP, GalnN, InGaNP, GalnNAs, etc.
  • the present disclosure includes methods of fabricating semiconductor structures that include a layer of III-V semiconductor material on a substrate comprising molybdenum.
  • molybdenum nitride may be formed or otherwise provided at a surface of a substrate. The surface may be at least substantially planar.
  • a layer of III-V semiconductor material, such as GaN, may be provided on the surface of the substrate. Examples of such methods are disclosed below with reference to the figures.
  • FIG. 1 illustrates a substrate 100 comprising molybdenum.
  • the substrate 100 may comprise a generally planar wafer, for example, and may be at least substantially comprised of molybdenum.
  • the substrate 100 may consist essentially of molybdenum.
  • the molybdenum may have a polycrystalline microstructure.
  • the substrate 100 may be at least substantially comprised of polycrystalline molybdenum.
  • the substrate 100 may have an exposed major surface 102 on which a III-V semiconductor material, such as GaN, may be provided, as discussed subsequently herein.
  • the exposed major surface 102 may be at least substantially planar.
  • molybdenum nitride 104 may be formed or otherwise provided at the exposed major surface 102 of the substrate 100.
  • the molybdenum nitride 104 may comprise a MoN phase, a Mo 2 N phase, or both MoN and Mo 2 N phases.
  • the substrate 100 may be at least substantially encapsulated with molybdenum nitride 104.
  • the molybdenum nitride 104 may be present in the form of a layer of
  • molybdenum nitride 104 and the layer of molybdenum nitride 104 may have an average layer thickness of between about one nanometer ( 1 nm) and about five hundred nanometers (500 nm), and, more particularly, between about ten nanometers (10 nm) and about one hundred nanometers (100 nm).
  • the molybdenum nitride 104 may be formed by introducing nitrogen atoms into the surfaces of the substrate 100, such as the exposed major surface 102, and nitriding a volume of the molybdenum within the substrate 100. In other embodiments, the molybdenum nitride 104 may be formed by growing, depositing or otherwise forming a layer of molybdenum nitride 104 on the surfaces of the substrate 100.
  • the molybdenum nitride 104 may be formed by exposing the substrate 100 to a microwave plasma comprising nitrogen radicals.
  • a microwave plasma comprising nitrogen radicals.
  • an expanding plasma activated by microwave discharge may be directed onto surfaces of the substrate 100 comprising molybdenum that are to be nitrided.
  • the plasma may be generated in an environment comprising a gas or gaseous mixture that includes nitrogen ( 2 ).
  • one or more of hydrogen gas (H 2 ) and inert gas e.g., argon
  • H 2 hydrogen gas
  • inert gas e.g., argon
  • the molybdenum nitride 104 may be formed by utilizing a reactive sputtering process to deposit a molybdenum nitride film onto surfaces of the substrate 100 that are to include the molybdenum nitride 104.
  • the substrate 100 may be provided within a sputter deposition system.
  • An at least substantially pure molybdenum target may be used to sputter molybdenum during the sputter deposition process.
  • a gas or gaseous mixture that includes nitrogen (N 2 ) may be provided within the deposition system during the deposition process.
  • one or more of hydrogen gas (H 2 ) and inert gas ⁇ e.g., argon) may also be present.
  • H 2 hydrogen gas
  • inert gas ⁇ e.g., argon inert gas
  • the sputtered molybdenum may react with the nitrogen within the deposition system to deposit the molybdenum nitride 104 on the substrate 100.
  • Such processes are discussed in further detail in, for example, Y. Wang and R. Lin, Amorphous molybdenum nitride thin films prepared by reactive sputter deposition, Materials Science & Engineering B, vol. 1 12, pp. 42-49 (Elsevier 2004).
  • the molybdenum nitride 104 may be formed by atomic layer deposition (ALD) processes.
  • ALD atomic layer deposition
  • a molybdenum precursor such as molybdenum pentachloride or bis(tert-butylimido)-bis(dimethylamido)molybdenum maybe utilized in an ALD process with a nitrogen precursor, such as ammonia.
  • the molybdenum precursor and nitrogen precursor may be alternatively pulsed into a reaction chamber to form the molybdenum nitride 104.
  • Such processes are discussed in further detail in, for example, V.
  • the molybdenum nitride 104 may be formed by annealing the substrate 100 in an environment comprising nitrogen gas (N 2 ) and hydrogen gas (H 2 ) at a temperature greater than about 400°C, and, more particularly, at temperatures from about 400°C to about 1 ,000°C ⁇ e.g., about 650°C).
  • the volumetric ratio of hydrogen gas to nitrogen gas within the annealing chamber may be between about 0.05 and about 10.00.
  • the annealing time may be from one ( 1) minute to one hundred (100) minutes or more.
  • Such processes are discussed in further detail in, for example, T. Amazawa and H. Oikawa, Nitridation of vacuum evaporated molybdenum films in H 2 /N2 mixtures, J. Vac. Sci. Technol. A, vol. 16(4), Jul/Aug, pp. 2510-16 (1998).
  • the crystallinity of an exposed major surface 106 of the molybdenum nitride 104 may be less than a crystallinity of the exposed major surface 102 of the substrate 100 prior to formation of the molybdenum nitride 104.
  • the exposed major surface 102 of the substrate 100 may have a polycrystalline microstructure.
  • the molybdenum nitride 104 may be formed to have an amorphous microstructure in some embodiments. In other embodiments, the molybdenum nitride 104 may be formed to have a polycrystalline microstructure. In such embodiments, the
  • molybdenum nitride 104 may be formed to comprise material grains that exhibit an average grain size that is less than an average grain size of material grains at the exposed major surface 102 of the substrate 100 prior to formation of the molybdenum nitride 104.
  • the molybdenum nitride 104 may be formed to comprise material grains that exhibit an average grain size of about ten nanometers (10 nm) or less, and, more particularly, about two and one half nanometers (2.5 nm) or less.
  • the molybdenum nitride 104 By providing the molybdenum nitride 104 with an amorphous microstructure, or with a polycrystalline microstructure having a relatively fine grain structure, unwanted diffusion of molybdenum or other elements out from the substrate 100 and into subsequently formed overlying materials during subsequent processing may be hindered. Further, by encapsulating the substrate 100 in molybdenum nitride 104, the encapsulated substrate 100 may be subjected to environments that might otherwise consume or degrade the substrate 100, such as environments comprising chlorine gas and/or hydrochloric acid vapor at elevated temperatures.
  • Molybdenum nitride may exhibit a hardness that is greater than a hardness exhibited by elemental molybdenum.
  • the molybdenum nitride 104 may be formed such that an exposed major surface 106 of the molybdenum nitride 104 exhibits a hardness that is higher than a hardness exhibited by the exposed major surface 102 of the substrate 100 prior to forming the molybdenum nitride 104.
  • the exposed major surface 106 of the molybdenum nitride 104 may exhibit a Vickers hardness HV of at least about 175, and, more particularly, a Vickers hardness HV of about 200 or more.
  • the exposed major surface 106 of the molybdenum nitride 104 may be subjected to one or more of an a grinding process, a polishing process, and an etching process (e.g., a chemical-mechanical polishing (CMP) process) to reduce a surface roughness of the exposed major surface 106 of the molybdenum nitride 104.
  • CMP chemical-mechanical polishing
  • molybdenum nitride 104 exhibits a surface roughness Ra that is less than a surface roughness Ra of the exposed major surface 102 of the substrate 100 prior to forming the molybdenum nitride 104.
  • the surface roughness Ra of the exposed major surface 106 of the molybdenum nitride 104 may be about five nanometers (5 nm) or less, about three nanometers (3 nm) or less, or even about two nanometers (2 nm) or less.
  • the molybdenum nitride 104 may exhibit such levels of surface roughness upon formation of the molybdenum nitride 104 without the need for subsequent polishing or etching, as there may be no roughness resulting from the presence of grain boundaries.
  • a III-V semiconductor material may be provided over the at least substantially planar exposed major surface 102 of the substrate 100.
  • a layer of GaN may be provided over the at least substantially planar exposed major surface 102 of the substrate 100 as subsequently described, although other III-V semiconductor materials may be provided in additional embodiments.
  • a layer of GaN may be provided over the at least substantially planar exposed major surface 102 of the substrate 100 by bonding a separately formed layer of GaN to the exposed major surface 106 of the molybdenum nitride 104, or by growing or otherwise depositing GaN on the exposed major surface 106 of the molybdenum nitride 104.
  • a layer of GaN may be provided over the at least substantially planar exposed major surface 102 of the substrate 100 by transferring a layer of GaN from a donor structure onto the exposed major surface 106 of the molybdenum nitride 104.
  • the process known in the art as the SMART-CUT® process may be used to transfer a layer of GaN from a donor structure onto the exposed major surface 106 of the molybdenum nitride 104.
  • a plurality of ions may be implanted into a donor structure 200 along an ion implant plane 202.
  • the donor structure 200 may comprise a bulk crystalline semiconductor material, such as monocrystalline GaN.
  • the implantation of ions is represented in FIG. 3 by directional arrows 204.
  • the implanted ions along the ion implant plane 202 define a weakened ion implant plane within the donor structure 200, along which the donor structure 200 subsequently may be cleaved or otherwise fractured.
  • the depth at which the ions are implanted into the donor structure 200 is at least partially a function of the energy with which the ions are implanted into the donor structure 200. Generally, ions implanted with less energy will be implanted at relatively shallower depths, while ions implanted with higher energy will be implanted at relatively deeper depths.
  • the donor structure 200 is bonded to the major surface 106 of the molybdenum nitride 104 on the substrate 100, after which the donor structure 200 is cleaved or otherwise fractured along the ion implant plane 202.
  • the bonding surfaces of the donor structure 200 and the molybdenum nitride 104 may be brought into direct physical contact and direct molecular bonds may be established between the molybdenum nitride 104 and the donor structure 200 to form the structure shown in FIG. 4.
  • the bonded donor structure 200 may be cleaved or otherwise fractured along the ion implant plane 202.
  • the donor structure 200 (with the substrate 100 bonded thereto) may be heated to cause the donor structure 200 to fracture along the ion implant plane 202.
  • mechanical forces may be applied to the donor structure 200 to assist in the cleaving of the donor structure 200 along the ion implant plane 202.
  • a portion of the donor structure 200 remains bonded to the molybdenum nitride 104 over the exposed major surface 102 of the substrate 100, which portion defines a layer of GaN 108.
  • a remainder of the donor structure 200 may be reused in further SMART-CUT® processes to transfer additional portions of the donor structure 200 to additional substrates.
  • the exposed major surface 1 10 of the layer of GaN 108 comprises a fractured surface of the donor structure 200, and may include ion impurities and imperfections in the crystal lattice of the layer of GaN 108.
  • the GaN 108 in some applications, may comprise a single crystal of GaN (i.e., monocrystalline GaN).
  • the layer of GaN 108 may be treated in an effort to reduce impurity levels and improve the quality of the crystal lattice (i.e., reduce the number of defects in the crystal lattice proximate the exposed major surface 1 10) in the layer of GaN 108. Such treatments may involve one or more of grinding, polishing, etching, and thermal annealing.
  • the layer of GaN 108 may be provided on the molybdenum nitride 104 over the exposed major surface 102 of the substrate 100 by epitaxially growing or otherwise depositing the layer of GaN 108 on the molybdenum nitride 104, or by bonding bulk crystalline GaN to the molybdenum nitride 104 and subsequently thinning the bulk crystalline GaN using one or more of a grinding process, a polishing process, and an etching process (e.g., a chemical-mechanical polishing process).
  • a grinding process e.g., a chemical-mechanical polishing process
  • one or more additional layers of III-V semiconductor material may be provided over the layer of GaN 108.
  • an additional layer 1 12 comprising GaN or InGaN may be epitaxially grown on the layer of GaN 108.
  • active device structures such as active regions, transistors, conductive lines and vias, etc.
  • an active semiconductor device such as a radiation emitting device (e.g., a light emitting diode (LED), a laser diode, etc.) or a radiation receiving device (e.g., an optical sensor, a solar cell, etc.).
  • a radiation emitting device e.g., a light emitting diode (LED), a laser diode, etc.
  • a radiation receiving device e.g., an optical sensor, a solar cell, etc.
  • Molybdenum exhibits of coefficient of thermal expansion (CTE) of about 5.5 x 10 "6 "1
  • GaN exhibits a closely matching CTE of about 5.6 x 10 "6 " ' .
  • molybdenum nitride 104 on the substrate 100 as described herein, improved bonding between the layer of GaN 108 and the substrate 100 may be attained. Further, problems associated with processing exposed elemental molybdenum may be avoided by encapsulating the substrate 100 comprising molybdenum with molybdenum nitride 104, as previously described herein.
  • Methods similar to those described herein may be applied to other substrates comprising metals or metal alloys and overlying layers of other types of semiconductor material, wherein the substrates and the semiconductor materials have closely matching coefficients of thermal expansion (e.g., coefficients of thermal expansion within about two and one-half percent (2.5%) of one another), by providing a metal nitride at outer surfaces of the substrate prior to bonding.
  • coefficients of thermal expansion e.g., coefficients of thermal expansion within about two and one-half percent (2.5%) of one another
  • Embodiment 1 A method of fabricating a semiconductor structure, comprising: forming molybdenum nitride at an at least substantially planar surface of a substrate comprising molybdenum; and providing a layer of GaN over the at least substantially planar surface of the substrate.
  • Embodiment 2 The method of Embodiment 1 , further comprising selecting the substrate to be at least substantially comprised of molybdenum.
  • Embodiment 3 The method of Embodiment 2, further comprising selecting the substrate to be at least substantially comprised of polycrystalline molybdenum.
  • Embodiment 4 The method of any one of Embodiments 1 through 3, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises at least substantially encapsulating the substrate with molybdenum nitride.
  • Embodiment 5 The method of any one of Embodiments 1 through 4, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises introducing nitrogen into the at least substantially planar surface of the substrate and forming the molybdenum nitride in the at least substantially planar surface of a substrate.
  • Embodiment 6 The method of any one of Embodiments 1 through 4, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises depositing molybdenum nitride on the at least substantially planar surface of the substrate.
  • Embodiment 7 The method of Embodiment 6, wherein depositing molybdenum nitride on the at least substantially planar surface of the substrate comprises depositing the molybdenum nitride using at least one of a chemical vapor deposition process, a sputtering process, and an atomic layer deposition process.
  • Embodiment 8 The method of any one of Embodiments 1 through 4, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises growing molybdenum nitride on the at least substantially planar surface of the substrate.
  • Embodiment 9 The method of any one of Embodiments 1 through 8, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises providing an exposed major surface of the molybdenum nitride with a surface roughness less than a surface roughness of the at least substantially planar surface of the substrate.
  • Embodiment 10 The method of any one of Embodiments 1 through 9, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises providing an exposed major surface of the molybdenum nitride with a crystallinity less than a crystallinity of the at least substantially planar surface of the substrate.
  • Embodiment 1 1 The method of Embodiment 10, wherein providing the exposed major surface of the molybdenum nitride with a crystallinity less than a crystallinity of the at least substantially planar surface of the substrate prior to forming the molybdenum nitride comprises forming the molybdenum nitride to comprise amorphous molybdenum nitride.
  • Embodiment 12 The method of Embodiment 10, wherein providing the exposed major surface of the molybdenum nitride with a crystallinity less than a crystallinity of the at least substantially planar surface of the substrate prior to forming the molybdenum nitride comprises forming the molybdenum nitride to comprise material grains having an average grain size less than an average grain size of material grains of the substrate at the exposed major surface of the substrate.
  • Embodiment 13 The method of any one of Embodiments 1 through 12, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises exposing the substrate to a microwave plasma comprising nitrogen radicals.
  • Embodiment 14 The method of any one of Embodiments 1 through 12, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises utilizing a reactive sputtering process to deposit a molybdenum nitride film on the at least substantially planar surface of the substrate.
  • Embodiment 15 The method of any one of Embodiments 1 through 12, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises annealing the substrate in an environment comprising nitrogen and hydrogen at a temperature greater than about 400°C.
  • Embodiment 16 The method of any one of Embodiments 1 through 15, wherein forming molybdenum nitride at the at least substantially planar surface of the substrate comprises forming an exposed major surface of the molybdenum nitride to exhibit a hardness greater than a hardness exhibited by the exposed major surface of the substrate.
  • Embodiment 17 The method of Embodiment 16, further comprising forming the exposed major surface of the molybdenum nitride to exhibit a Vickers hardness HV of about 175 or more.
  • Embodiment 18 The method of any one of Embodiments 1 through 17, further comprising subjecting an exposed major surface of the molybdenum nitride to at least one of a grinding process, a polishing process, and an etching process.
  • Embodiment 19 The method of any one of Embodiments 1 through 18, wherein providing a layer of GaN over the at least substantially planar surface of the substrate comprises bonding the layer of GaN to an exposed major surface of the molybdenum nitride.
  • Embodiment 20 The method of Embodiment 19, wherein providing a layer of GaN over the at least substantially planar surface of the substrate comprises: implanting ions into a GaN donor structure and forming a weakened ion implant plane within the GaN donor structure, the layer of GaN defined on a side of the weakened ion implant plane; bonding the GaN donor structure to the exposed major surface of the molybdenum nitride; and fracturing the GaN donor structure along the weakened ion implant plane leaving the layer of GaN bonded to the exposed major surface of the molybdenum nitride.
  • Embodiment 21 The method of any one of Embodiments 1 through 20, further comprising epitaxially growing at least one layer of IIl-V semiconductor material on the layer of GaN.
  • Embodiment 22 A semiconductor structure, comprising: a substrate comprising molybdenum; molybdenum nitride at an at least substantially planar surface of the substrate; and a layer of GaN bonded to the molybdenum nitride.
  • Embodiment 23 The semiconductor structure of Embodiment 22, wherein the substrate is at least substantially comprised of molybdenum.
  • Embodiment 24 The semiconductor structure of Embodiment 23, wherein the substrate is at least substantially comprised of polycrystalline molybdenum.
  • Embodiment 25 The semiconductor structure of any one of Embodiments 22 through 22, wherein the molybdenum nitride comprises a layer of molybdenum nitride disposed between the substrate and the layer of GaN.
  • Embodiment 26 The semiconductor structure of Embodiment 25, wherein the layer of molybdenum nitride has an average layer thickness of between about one nanometer (1 nm) and about five hundred nanometers (500 nm).
  • Embodiment 27 The semiconductor structure of any one of Embodiments 22 through 26, wherein the molybdenum nitride comprises at least one of MoN and Mo 2 N.
  • Embodiment 28 The semiconductor structure of any one of Embodiments 22 through 27, wherein the substrate is at least substantially encapsulated with molybdenum nitride.
  • Embodiment 29 The semiconductor structure of any one of Embodiments 22 through 28, wherein the molybdenum nitride comprises amorphous molybdenum nitride.
  • Embodiment 30 The semiconductor structure of any one of Embodiments 22 through 28, wherein the molybdenum nitride comprises polycrystalline molybdenum nitride having an average grain size of about ten nanometers ( 10 nm) or less.
  • Embodiment 31 The semiconductor structure of any one of Embodiments 22 through 30, wherein the layer of GaN is bonded to the molybdenum nitride with direct molecular bonds.
  • Embodiment 32 The semiconductor structure of any one of Embodiments 22 through 3 1 , further comprising at least one epitaxial layer of 1II-V semiconductor material on the layer of GaN.

Abstract

Les procédés de fabrication de structures semi-conductrices selon l'invention consistent à former du nitrure de molybdène sur une ou plusieurs surfaces d'un substrat comprenant du molybdène, et à disposer une couche d'un matériau semi-conducteur III-V, par exemple du GaN, sur le substrat. Des structures semi-conductrices formées par les procédés ci-décrits peuvent inclure un substrat comprenant du molybdène, du nitrure de molybdène sur une ou plusieurs surfaces du substrat, et une couche de GaN liée au nitrure de molybdène.
PCT/IB2013/000564 2012-03-09 2013-03-05 Procédés permettant de former des structures semi-conductrices incluant du matériau semi-conducteur iii-v au moyen de substrats comprenant du molybdène, et structures formées par de tels procédés WO2013132332A1 (fr)

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US13/416,697 2012-03-09
US13/416,697 US8916483B2 (en) 2012-03-09 2012-03-09 Methods of forming semiconductor structures including III-V semiconductor material using substrates comprising molybdenum
FR1252408A FR2988219B1 (fr) 2012-03-16 2012-03-16 Procedes de formation de structures semi-conductrices comprenant un materiau semi-conducteur des groupes iii-v en utilisant des substrats comprenant du molybdene, et structures formees par ces procedes
FR1252408 2012-03-16

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