WO2013131185A1 - Procédés de test de mémoire otp non programmée - Google Patents

Procédés de test de mémoire otp non programmée Download PDF

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Publication number
WO2013131185A1
WO2013131185A1 PCT/CA2013/050154 CA2013050154W WO2013131185A1 WO 2013131185 A1 WO2013131185 A1 WO 2013131185A1 CA 2013050154 W CA2013050154 W CA 2013050154W WO 2013131185 A1 WO2013131185 A1 WO 2013131185A1
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WIPO (PCT)
Prior art keywords
bitline
voltage
fuse
memory cell
transistor
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PCT/CA2013/050154
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English (en)
Inventor
Wlodek Kurjanowicz
Steven Smith
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Sidense Corp.
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Filing date
Publication date
Priority claimed from US13/412,500 external-priority patent/US8767433B2/en
Application filed by Sidense Corp. filed Critical Sidense Corp.
Publication of WO2013131185A1 publication Critical patent/WO2013131185A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

Definitions

  • the BVDSS for the nmos transistor is not only in the order of 6.5V, but once the S-D punch through occurs it creates permanent damage resulting in few kilo ohms leakage between the source and the drain.
  • U.S. Patent No. 6,515,344 proposed a range of P+/N+ anti-fuse configurations, implemented using a minimum size gate between two opposite type diffusion regions.
  • N MOS anti-fuses have been built in an isolated P-well using a standard Deep N- VVell process.
  • An example of Deep N-vVell based anti-fuses is disclosed in U.S. Patent No. 6,61 1 ,040 (Geisomini et al. ).
  • U.S. Patent Nos. 6,960,819 (Chen et al. ) and 6,700, 176 (Ito et al. ) disclose other Deep N-vVell anti-fuses. These anti-fuses consisted of a capacitor featuring direct tunnelling current rather then Fowler Nordheim current. These applications confirm that anti-fuse performance is generally improved for thinner gate oxide capacitors (approx 20A, which is typical for transistors in 0.13um process).
  • U.S. Patent No. 6,580, 145 (Wu et al. ) disclosed a new version of a traditional anti- fuse structure utilizing dual gate oxides, with the thicker gate oxide being used for nmos (or pmos) access transistors and the thinner gate oxide for the capacitor.
  • the N-vVell (or P-vVell) is used as a bottom plate of the anti-fuse capacitor.
  • Peng attempts to improve a classic planar DRAM-like anti-fuse array by introducing "row program lines" which connect to the capacitors and run parallel to the word lines. If decoded, the row program lines can minimize exposure of access transistors to a high programming voltage, which would otherwise occur through already programmed cells. Peng and Fong further improve their array in U.S. Patent No. 6,671 ,040 (Fong et al. ) by adding a variable voltage controlling programming current, which allegedly controls the degree of gate oxide breakdown, allowing for multilevel or analog storage applications.
  • U.S. Patent No. 6,777,757 shows a memory array using a single transistor structure.
  • Peng eliminates the LDD diffusion from a regular NMOS transistor.
  • a cross-point array structure is formed of horizontal active area (S/D) stripes crossing vertical poly gate stripes. Drain contacts are shared between neighbouring cells and connected to horizontal wordlines. Source regions are also shared and left floating.
  • Peng assumes that if the LDD diffusion is omitted, the gate oxide breakdown location will be far enough from the drain area and a local N+ region will be created rather than D-G (drain-gate) short. If such a region was created, the programmed cells could be detected by positively biasing the gate and sensing the gate to drain current.
  • Peng achieves a cross-point memory architecture
  • his array requires CMOS process modifications (LDD elimination, thicker gate oxide at the edge) and has the following disadvantages: (a) All row decoders, column decoders and sense amplifiers must switch a wide range of voltages: 8V/3.3V/0V or 8V/1.8V/0V. (b) During a program operation, the 3.3V column drivers are effectively shorted to 8V row drivers or 0V drivers through programmed cells. This puts many limits on the array size, affects driver size and impacts reliability and effectiveness of programming, (c) Every program operation requires that all the array active areas (except for the programmed row) are biased at 8V.
  • the first voltage is VSS and the second voltage is a positive voltage greater than VSS.
  • coupling includes driving the first bitline and the second bitline with a sense amplifier circuit.
  • comparing includes sensing a voltage level of the first bitline relative to the second bitline with the sense amplifier circuit, and coupling includes coupling a reference capacitance to the second bitline, where the reference capacitance is less than the capacitance of the normal memory cell.
  • determining includes determining that the normal memory cell is defective when the first bitline voltage is sensed to be greater than the second bitline voltage.
  • activating further includes activating a test memory cell connected to the second bitline, where the test memory cell being identical to the normal memory cell and omitting an anti-fuse device.
  • the normal memory cell and the test memory cell are activated at the same time, and determining includes determining that the normal memory cell is defective when the first bitline voltage is sensed to be greater than the second bitline voltage. This determination can be made because the normal memory cell adds a smaller capacitive load to the first bitline than the test memory cell adds to the second bitline when they are defective.
  • determining includes determining that the normal memory cell is defective when the second bitline voltage is sensed to be greater than the first bitline voltage. This determination can be made because the test memory cell has higher capacitive coupling of the second voltage to the second bitline than the normal memory cell capacitive coupling of the second voltage to the first bitline, when the normal memory cell is defective.
  • Fig. 1 is a circuit diagram of a DRAM-type anti-fuse cell
  • Fig. 3 is a cross-sectional view of the DRAM-type anti-fuse cell of Figure 2 along line x-x;
  • Fig. 6a and 6b are planar layouts of an alternate anti-fuse transistor according to an embodiment of the present invention.
  • Fig. 7a and 7b are planar layouts of an alternate anti-fuse transistor according to an embodiment of the present invention.
  • Fig. 8 is a planar layout of an alternate anti-fuse transistor according to an embodiment of the present invention.
  • Fig. 9 is a flow chart of a method for forming a variable thickness gate oxide for the anti-fuse transistor of the present invention.
  • Fig. 10a-10c illustrate the formation of the variable thickness gate oxide in accordance with steps of the flow chart of Figure 9;
  • Fig. 1 1 a is a cross-point configured anti-fuse transistor memory array configured for single-ended sensing according to an embodiment of the present invention
  • Fig. 1 1 b is a cross-point configured anti-fuse transistor memory array configured for differential sensing according to an embodiment of the present invention
  • Fig. 12 is a layout of the anti-fuse transistors of the memory array shown in Figure 1 1 ;
  • Fig. 13 is a folded bitline configured anti-fuse transistor memory array according to an embodiment of the present invention.
  • Fig. 14 is a layout of anti-fuse transistors employing wordline segments according to an embodiment of the present invention.
  • Fig. 17a is a flow chart showing a method for sensing data using the folded bitline anti-fuse memory array of Figure 16, according to an embodiment of the present invention
  • Fig. 18 is a circuit schematic of a folded bitline anti-fuse memory array having an alternate reference charge circuit, according to embodiment of the present invention.
  • Fig. 19a is a flow chart showing an alternate method for sensing data using the folded bitline anti-fuse memory array of Figure 16 or 18, according to an embodiment of the present invention
  • Fig. 19b is a timing diagram showing signal transitions in accordance with the method described in Figure 19a;
  • Fig. 20 is a circuit schematic of a folded bitline anti-fuse memory array having a selectable reference charge circuit, according to embodiment of the present invention.
  • Fig. 21 is a circuit schematic of a folded bitline anti-fuse memory array having a capacitive loading reference charge circuit, according to embodiment of the present invention.
  • Fig. 22a is a flow chart showing an alternate method for sensing data using the folded bitline anti-fuse memory array of Figure 21 , according to an embodiment of the present invention
  • Fig. 22b is a timing diagram showing signal transitions in accordance with the method described in Figure 22a;
  • Fig. 23 is a timing diagram showing signal transitions in accordance with an alternate sensing method, according to an embodiment of the present invention.
  • Fig. 24 is a timing diagram showing signal transitions in accordance with an alternate sensing method, according to an embodiment of the present invention.
  • Fig. 25 is a circuit illustration of four metal bitlines connected to respective memory cells;
  • Fig. 26 is a circuit schematic of a folded bitline anti-fuse memory array having a column precharge circuit, according to an embodiment of the present invention;
  • Fig. 27 is a flow chart showing a method of precharging the bitlines of the folded bitline anti-fuse memory array of Figure 26, according to an embodiment of the present invention
  • Fig. 30 is a circuit schematic of a folded bitline single-transistor anti-fuse memory array having test cells and dummy cells, according to an alternate embodiment of the present invention
  • Fig. 33 is a flow chart of a capacitive coupling testing method for unprogrammed OTP memory cells, according to a present embodiment.
  • Fig. 34 is a flow chart of a general unprogrammed OTP testing method, according to a present embodiment.
  • the present invention provides an array of non-volatile memory cells arranged in a complementary bitline configuration following a folded or an open bitline architecture.
  • the following description specifically refers to the preferred folded bitline arrangement, but it equally applies to the alternative open bitline arrangement or to combinations of the two.
  • the memory array further includes precharge circuits for precharging the bitline pairs to a voltage reference, a reference circuit for injecting a reference charge on one bitline of each bitline pair, and bitline sense amplifiers for sensing a voltage differential between said bitline pairs.
  • the voltage differential will depend on the programming state of the non-volatile memory cells coupled to the bitlines through an activated wordline.
  • FIG. 1 is a circuit diagram of such a memory cell, while Figures 2 and 3 show the planar and cross-sectional views respectively, of the known anti-fuse memory cell of Figure 1.
  • the memory cell of Figure 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12.
  • a wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
  • FIG. 2 and 3 It can be seen from Figures 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple.
  • the gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18.
  • a thin gate oxide 20 also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath.
  • diffusion regions 22 and 24 are formed on either side of gate 14 CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied.
  • LDD lightly doped diffusions
  • Figure 4 shows a cross- sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process.
  • the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output MOS transistor with one floating diffusion terminal.
  • the disclosed anti-fuse transistor also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device.
  • the cross-section view of Figure 4 is taken along the channel length of the device, which in the presently described embodiment is a p-channel device.
  • the present invention can be implemented as an n-channel device.
  • a simplified plan view of the anti-fuse transistor 100 is shown in Figure 5.
  • Bitline contact 116 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of Figure 4.
  • the active area 118 is the region of the device where the channel region 104 and diffusion regions 110 and 112 are formed, which is defined by an OD mask during the manufacturing process.
  • the dashed outline 120 defines the areas in which the thick gate oxide is to be grown via an OD2 mask during the manufacturing process.
  • OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first. Details of the CMOS process steps for fabricating anti-fuse transistor 100 will be discussed later.
  • floating diffusion region 112 is an optional structure for anti-fuse transistor 100 that can be used to enhance the probability of thin gate oxide breakdown, as will be discussed later.
  • the anti-fuse transistor embodiments of the present invention take advantage of a typically prohibited CMOS manufacturing design rule for gate oxide design layout and formation to enhance gate oxide breakdown performance. All gate oxide processing steps in today's CMOS processes assume and are optimized for uniform gate oxide thickness within the active gate area. By introducing the variable thickness gate oxide devices into the standard CMOS flow, additional defects and electrical field disturbances are created at the boundary between the thick and thin gate oxides. Those defects may include, but are not limited to: oxide thinning, plasma etching of silicon at the boundary, residues from cleaning process and silicon recess due to different thermal oxidation rates between unmasked and partially masked regions. All these effects increase trap and defect density at the thin oxide boundary, leading to increased leakage and locally lowered breakdown voltage. Therefore, a low voltage, compact anti-fuse structure can be created without any process modification.
  • anti-fuse transistor 100 While the anti-fuse transistor described above is suitable for OTP memory array applications due to its compact size, additional modifications can be made to anti-fuse transistor 100 to further increase thin oxide breakdown probability.
  • gate area, gate/diffusion perimeter is a factor that can increase the probability of thin gate oxide breakdown.
  • the previously shown floating diffusion region 112 can be added to the anti-fuse transistor structure, and the floating diffusion/gate perimeter is preferably increased by incorporating multiple line segments and angles to the diffusion/gate boundary. Further breakdown enhancement can be achieved by heavily doping floating diffusion region 112 to a concentration similar to diffusion regions of the high voltage transistors.
  • the diffusion regions, LDD and channel implantation are different for thin gate oxide transistors and thick gate oxide transistors.
  • the diffusion regions, LDD and the thin gate oxide channel implantation of the anti-fuse transistors can be either type; the low voltage type corresponding to the thin gate oxide, or the high voltage type corresponding to the thick gate oxide ( I/O oxide), or both, provided that the resulting thin gate oxide threshold voltage is not greater in magnitude than the thick gate oxide threshold voltage.
  • Figures 6a and 6b illustrate examples where the polysilicon gate can be shaped to increase the floating diffusion region perimeter.
  • Figures 7a and 7b illustrate examples where the diffusion region and/or the polysilicon gate can be shaped to increase the floating diffusion region perimeter.
  • anti-fuse transistor 300 has a straight gate/diffusion perimeter at the floating diffusion end of the device.
  • a shaped active region 302 has a diffusion region with bitline contact 304, and a polysilicon gate 306 formed in a "U" shape over the shaped active region 302.
  • the OD2 mask 308 defines where the thick gate oxide is formed underneath polysilicon gate 306. Due to the narrowed active region 302, a portion of polysilicon gate 306 will form an access edge 310 that is substantially smaller in perimeter than fusible edge 312 defined by another portion of polysilicon gate 306.
  • the polysilicon gate is effectively divided into two portions that are coupled to each other. The first portion forms a channel in the active area between the diffusion region with bitline contact 304, while the second portion is positioned adjacent to the floating diffusion region. The first portion is formed over thick gate oxide and the second portion is formed over thin gate oxide.
  • Figure 8 shows a pair of anti-fuse transistors, of which only one will be described as both are substantially symmetrical to each other.
  • Anti-fuse transistor 400 has an active region 402 with a diffusion region with bitline contact 404.
  • a polysilicon gate 406 formed over a variable thickness gate oxide layer (not shown).
  • the OD2 mask 408 defines where the thick gate oxide is formed underneath polysilicon gate 406.
  • the floating diffusion region, channel region, and polysilicon gate share a common straight "U" shaped edge.
  • a polysilicon contact 410 is used to make electrical contact with a metal wordline.
  • the diffusion region containing the bitline contacts 404 are oriented as shown to allow for sufficient spacing of RPO 412 from the respective contacts 404. The applicability of the paired anti-fuse transistors shown in Figure 8 will be described later with regards to folded bitline sensing architectures.
  • an RPO can be used to ensure that the diffusion regions with the bitline contact and a portion of the polysilicon gate is free from salicidation.
  • the OD2 mask is considered a non-critical masking step, a low resolution mask is used and the design rules require a large margin of the OD2 mask over active gate areas and particularly, do not have provisions for the OD2 mask ending within the active gate area.
  • the OD2 mask ends within the active gate area creating a split-channel anti-fuse structure that features thicker gate oxide on the drain (i.e. diffusion contact) side and thinner gate oxide on the opposite side (either channel or non-connected source side).
  • this technology requires that the gate length (polysilicon line width) should be larger then the process minimum and depends on actual OD2 mask tolerances, but otherwise does not require any process or mask grade change.
  • the minimum gate length for the split channel anti-fuse structure can be approximated as a sum of minimum gate length for the thick and thin gate oxide. Those skilled in the art will appreciate that accurate calculations can be made based on mask tolerances, and the gate length can be minimized by tightening OD2 mask tolerances.
  • step 506 additional standard CMOS processing steps can be employed at step 506 to complete the anti-fuse transistor structure as shown in Figure 4.
  • This can include formation of the polysilicon gate, LDD regions, sidewall spacers, RPO, and diffusion regions, and salicidation, for example.
  • a salicidiation step is included to salicide the polysilicon gate and the floating diffusion region of the anti- fuse transistor.
  • An RPO is formed over the diffusion region before hand to protect it from the salicidation process.
  • the salicided floating diffusion region will enhance oxide breakdown in the region.
  • FIG. 1 a illustrates a plurality of anti-fuse transistor memory cells arranged in a basic cross-point array, according to an embodiment of the present invention. Sensing is single ended in the present embodiment.
  • the anti-fuse transistor memory array 700 includes anti-fuse transistors 702 coupled to wordlines VVL0-WL3 and bitlines BL0, BL1 , BL2 and BL3.
  • Anti-fuse transistors 702 can be implemented with any of the previously described anti-fuse transistors.
  • Each bitline is connected to a p-channel isolation transistor 704, which in turn is connected to p-channel pass gates 706, 708, 710 and 712.
  • isolation transistors 704 are thick gate oxide transistors, where this thick gate oxide can be the same combination of the intermediate oxide and the thin gate oxide used for the anti-fuse transistor embodiments of the present invention.
  • the gate terminal of all isolation transistors 704 receive isolation voltage VB, while the gate terminals of pass gates 706, 708, 710 and 712 receive column select signals Y0, Y1 , Y2 and Y3 respectively.
  • the column select signals perform a one of four bitline selection to couple one of the bitlines to cross-point sense amplifier 714.
  • Cross-point sense amplifier 714 can be a current sense amplifier that compares the current of the bitline to a reference current IREF, and generally denotes single-ended sensing schemes in the present description, where a bitline voltage or current is compared to a reference signal carried on another line.
  • Figure 12 illustrates a layout configuration of four anti-fuse transistors 702 shown in Figure 1 1 a.
  • Each anti-fuse transistor of Figure 12 have a layout similar to anti-fuse transistor 100 shown in Figure 5, except that there is no floating source diffusion region to reduce the overall area of each cell. Accordingly, the same reference numerals are used to denote the same elements in Figure 12.
  • each bitline contact 116 and active area 118 is shared by two anti-fuse transistors, and the OD2 mask 120 is extended along the wordline direction for all the anti-fuse transistors aligned along the same row.
  • the cell coupled to VVLO and BL0 is programmed by applying a negative voltage -VPP to VVLO and a positive voltage VPOS (or VDD) to BL0, while keeping the other wordlines at VDD and the other bitlines at 0V or another voltage significantly smaller then VPOS.
  • VPOS positive voltage
  • VPOS + VPP positive programming voltage
  • VPOS has to be applied to the cell to be programmed, but once programmed this cell would read as a low state. Either individual cell or multiple cells sharing the same word line can be programmed simultaneously.
  • programming circuitry is not shown, those of skill in the art will understand that such circuits can be coupled to the bitlines, and incorporated into the wordline driver circuits.
  • the thick gate oxide isolation transistors 704 are used to isolate the bit lines from the rest of the chip, including the sense amplifiers. These devices can be un-decoded or Y-decoded. Keeping the isolation devices at ground or at the VB level allows the bit lines to float towards a negative voltage, thus having no effect on the programming operation.
  • the voltages used for program (PGM) and read operations are summarized in Table 1 below.
  • the un-programmed cells behave like switched capacitors, featuring very low leakage current.
  • all the word lines WL are kept at VDD, at the same level as the back-bias for the array.
  • All the bit lines BL are also precharged to VDD and therefore, there is no leakage and no current flowing anywhere in the array even if some of the cells were programmed.
  • one of the word lines is activated, by driving WLO to 0V for example, or to another appropriate voltage sufficient for inducing a channel underneath the polysilicon gate. If the cell was not programmed, the bit line will see an increased capacitance and minimally increased leakage.
  • FIG. 1 1 b illustrates another configuration of anti-fuse transistors 702 shown in Figure 1 1 b arranged in the twin cell configuration.
  • the elements of Figure 1 1 b are essentially the same as those in Figure 1 1 a, with the exception of differential sense amplifier 716 which replaces cross-point sense amplifier 714, and the connection of pass gates 706, 708, 710 and 712.
  • Pass gates 706 and 708 now have their gate terminals connected to Y0, while pass gates 710 and 712 have their gate terminals connected to Y1. Therefore, activation of Y0 will turn on both pass gates 706 and 708.
  • the bitlines are now labeled as complementary pairs, BL0/BL0* and BL1/BL1 *, where one pair of complementary bitlines is coupled to the differential sense amplifier 716 during a read operation.
  • a sense amplifier is a type of dual-ended sensing scheme, since either one of the bitlines connected to the differential sense amplifier 716 will typically carry a reference voltage while the other will carry data of the accessed memory cell. In the present example, the reference voltage will be the complement of the data of the memory cell being accessed.
  • bitlines Prior to a read operation, all the bitlines are precharged to VDD. Since the bitlines are all precharged to VDD, one of the bitlines will be pulled toward ground through a programmed cell during a read operation when one wordline is activated. Sensing data from a pair of bitlines carrying VDD and ground becomes straightforward.
  • bitlines are isolated from the sense amplifier since only Y0 would be driven to ground to activate pass transistors 706 and 708 and couple BL0/BL0* to folded bitline sense amplifier 716.
  • the column select signals Y0 and Y1 can be activated at a predetermined time after the wordlines are driven, to give the bitlines time to discharge to a sufficiently low voltage level, preferably to ground to provide the largest sensing margin.
  • Figure 14 illustrates an alternate differential cell arrangement according to another embodiment of the present invention.
  • the anti-fuse transistor cells shown are identical to those shown in Figure 12, but are now arranged such that the polysilicon wordlines are broken into segments 820, where each segment 820 is coupled to two different anti-fuse transistor cells.
  • the anti-fuse transistor pair shown in Figure 8 can be used here as well.
  • the segments can be connected to metal wordlines through wordline contact 822 via intermediate metal lines as required. It is well known in the art that the combination of metal wordlines connected to polysilicon wordline segments improves overall performance of the memory array.
  • the particular arrangement shown in Figure 14 enables single-ended sensing or dual-ended sensing of the bitlines by configuring the wordline decoders.
  • the wordline drivers can be controlled dynamically to drive only one wordline or two wordlines simultaneously in similar fashion to the DRAM decoder shown in issued U.S. Patent No. 6,549,483.
  • the single ended mode is used for a non-volatile memory cell test, and program and verify operations, whereas the dual ended mode is used for normal read operations only.
  • Such a combination allows for independent sensing optimization for read, test and verify, resulting in greatly improved read margins. The details of the single ended sensing mode will be described later.
  • Sense/program circuit 900 includes a high voltage cross-coupled p-type latch circuit 902 and a low voltage sense circuit 904 separated by thick gate oxide isolation transistors 906 controlled by Viso. Viso is preferably a variable voltage signal, such that Viso can be less than VDD for data verification after programming to limit current draw.
  • bitline sense amplifier 716 for sensing a voltage differential on the complementary bitlines BL0/BL0* or BL1/BL1 *.
  • bitline sense amplifier 716 can be implemented with a standard DRAM CMOS cross-coupled inverter circuit, which is well known in the DRAM field. With the appropriate timing control and associated bitline sensing circuits, high speed sensing of the described anti-fuse memory cells arranged in a complementary bitline scheme, such as the folded bitline architecture, can be achieved.
  • the precharge circuit 1010 includes two n-channel precharge transistors 1016 and 1018 connected in series between BL and BL* and having their gate terminals connected to precharge signal BLPCH.
  • the shared source/drain terminal of precharge transistors 1016 and 1018 receives a precharge voltage VPCH.
  • both precharge transistors 1016 and 1018 will turn on to precharge bitlines BL and BL* to VPCH in response to an active high logic level of BLPCH, in preparation for a read operation.
  • the reference charge circuit 1012 includes n-channel steering transistors 1020 and 1022 connected in series between BL and BL*, a capacitance circuit implemented as an n-channel transistor 1024, and a p-channel precharge transistor 1026.
  • Steering transistor 1020 has its gate terminal connected to even selection signal E_REF
  • steering transistor 1022 has its gate terminal connected to odd selection signal 0_REF.
  • Capacitance circuit 1024 has its gate terminal connected to voltage supply VCC, and is connected in series with precharge transistor 1026 between the shared source/drain terminal of steering transistors 1020 and 1022 and voltage supply VCC.
  • Precharge transistor 1026 has its gate terminal connected to precharge signal PCH*.
  • capacitance circuit 1024 will be precharged when a low logic level PCH* pulse is received.
  • the duration of the PCH* pulse can be predetermined based on the size of transistor 1024 and the desired reference charge to be provided.
  • either steering transistor 1020 or 1022 is turned on to couple the reference charge of capacitance circuit 1024 to the corresponding bitline.
  • the charge being added to a bitline can be approximately 50 millivolts.
  • signals E_REF and 0_REF can be controlled by the same even/odd addressing bit used for selecting VVLO or WL1. In one embodiment, activation of VVLO will cause E_REF to be activated, thereby coupling the reference charge to the complementary bitline.
  • bitline sense amplifier 1014 When enable signals H_EN and L_EN are activated, either at the same time or at different times, bitline sense amplifier 1014 will sense a small voltage differential between BL and BL*, and quickly drive both BL and BL* to the full logic level states of H_EN and L_EN.
  • the memory array of Figure 16 is inverted relative to the embodiment shown in Figure 13. More specifically, the memory array of Figure 13 uses p-channel anti-fuse memory cells while the memory array of Figure 16 uses n-channel anti-fuse memory cells. Accordingly, the values shown in Table 1 for operating the memory array of Figure 13 should be inverted for the memory of Figure 16.
  • the memory array shown in Figure 16 can be operated in one of two different modes.
  • the first mode is a standard single cell/bit mode
  • a second mode is a two cell/bit mode.
  • the two cell/bit mode one memory cell connected to one bitline of the folded bitline pair and a second memory cell connected to the other bitline of the folded bitline pair are both accessed at the same time by driving their respective wordlines at the same time.
  • a redundancy mode can be used.
  • two wordlines corresponding to two memory cells connected to the same bitline are activated during a read operation.
  • the general high speed sensing scheme for a single cell/bit mode of operation is as follows. It is assumed that ISO is at the high logic level to turn on isolation transistors 1006 and 1008, and that capacitance circuit 1024 has been precharged. First, both BL/BL* are precharged to a first voltage supply level provided by VPCH, such as VSS, by activating BLPCH and turning on transistors 1016 and 1018. Then one wordline, such as VVLO, is driven to a second supply voltage level preferably opposite to the first voltage supply level, such as VCC for example. VVLO is connected to anti-fuse memory cell 1004, which has its drain terminal connected to BL*.
  • E_REF is driven to the high logic level to turn on steering transistor 1020 and couple the capacitance circuit 1024 to bitline BL.
  • a reference charge will be present on bitline BL, which will raise the voltage of BL by about 50 millivolts for example.
  • Enable signals H_EN and L_EN can then be driven to high and low voltage levels respectively for enabling bitline sense amplifier 1014.
  • wordline VVLO will raise the voltage level of BL* from the precharge voltage of VSS towards VCC through the conduction path of the memory cell.
  • the voltage of BL* will be 100 millivolts, which is higher than the reference voltage of BL, when the bitline sense amplifier 1014 is activated. This voltage differential is quickly detected, amplified and latched by bitline sense amplifier 1014.
  • BL* will remain at the precharge voltage of VSS, which is less than the reference voltage of BL. In this case, the bitline sense amplifier 1014 will latch the opposite state.
  • the high speed sensing scheme for a two cell/bit mode of operation is as follows. It is assumed that ISO is at the high logic level to turn on isolation transistors 1006 and 1008. Reference charge circuit 1012 can be disabled for the two cell/bit mode of operation as a reference charge is not required. First, both BL/BL* are precharged to a first voltage supply level provided by VPCH, such as VSS, by activating BLPCH and turning on transistors 1016 and 1018. Then a pair of wordlines, such as VVLO and WL1 , are driven to a second supply voltage level preferably opposite to the first voltage supply level, such as VCC for example.
  • VPCH such as VSS
  • Figure 17b shows signal traces for the control signals used in the bitline sensing circuitry of Figure 16, and of the wordline and bitline voltages.
  • the presently described method is directed to a single cell/bit bit mode of operation.
  • step 1100 where the capacitance circuit 1024 is precharged when PCH* is pulsed for a predetermined duration of time.
  • the bitlines are precharged to the first voltage supply level, such as VSS in the present example, by pulsing BLPCH to the high logic level for a predetermined duration of time.
  • the BLPCH and PCH* pulses are concurrent, but can occur at any time relative to each other but before a wordline is activated.
  • the desired wordline is driven to the second voltage supply level at step 1104.
  • VVLO will be driven to VCC in the present example. Occurring at substantially the same time, but noted as step 1106, E_REF is driven to VCC to turn on steering transistor 1020. Although not shown in Figure 17b, 0_REF remains at VSS.
  • the VCC biased wordline will charge up BL* through its conductive channel.
  • E_REF turns on steering transistor 1020 to add the reference charge to BL.
  • Steering transistor 1020 is kept on for a predetermined period of time, and then shut off by driving E_REF to VSS at step 1108.
  • H_EN is driven to the high logic level
  • L_EN is driven to the low logic level to activate bitline sense amplifier 1014.
  • the differential between BL and BL* is sensed and fully latched by the bitline sense amplifier 1014.
  • the ISO signal is driven to the low logic state to turn off isolation transistors 1006 and 1008 during sensing, to decrease the load on the bitline sense amplifier 1014. This also allows the wordline to be turned off in order to accelerate bitline precharge for the next read cycle.
  • a memory cell is connected to one bitline while either steering transistor 1020 or 1022 is connected to the other bitline, acting as a reference bitline.
  • the bitline from which data is to be sensed from a connected memory cell can be called a data bitline.
  • dummy memory cells can be used instead of the steering transistors 1020 and 1022, according to an embodiment of the present invention. More specifically, dummy memory cells are identical to "normal" memory cells in the memory array. By using dummy memory cells for delivering the reference voltage, the bitline to wordline coupling becomes virtually identical on both the reference bitline and the data bitline.
  • Figure 18 is a schematic of an alternate folded bitline anti-fuse memory array according to another embodiment of the present invention.
  • the alternate folded bitline anti-fuse memory array shown in Figure 18 is similar to that shown in Figure 16, but employs an alternate reference charge circuit that uses dummy memory cells.
  • Folded bitline anti-fuse memory array 1200 includes the same numbered elements as previously shown and described in Figure 16, and hence no further description of these elements is required.
  • Reference charge circuit 1202 includes dummy memory cells 1204 and 1206, each having a gate terminal connected to dummy wordline DvVLO and DVVL1 respectively.
  • dummy memory cells 1204 and 1206 have an additional drain diffusion region for receiving the reference voltage. Dummy memory cells 1204 and 1206 are not programmed, but a dummy cell will form a conductive channel between its source and drain terminals when a positive gate voltage is applied.
  • the common terminal of dummy memory cells 1204 and 1206 is connected to a capacitance means 1208 and a precharge transistor 1210.
  • N-channel precharge transistor 1210 has a gate terminal connected to precharge signal PCH.
  • capacitance means 1208 and n-channel precharge transistor 1210 functions equivalent ⁇ to capacitance circuit 1024 and p-channel precharge transistor 1026, except that capacitance means 1208 is precharged when PCH pulses to the high logic level to turn on precharge transistor 1210.
  • reference charge circuit 1202 is connected to the upper bitlines, whereas the reference charge circuit 1012 of Figure 16 was connected to the lower bitlines.
  • the reference charge circuit 1012 of Figure 16 can be modified to replace the n-channel steering transistors 1020 and 1022 with dummy memory cells.
  • the n-channel isolation transistors 1006 and 1008 effectively divide the bitlines into an upper portion and a lower portion, where the upper portion is a high voltage domain and the lower portion is a low voltage domain. Because signal ISO is limited to a predetermined low supply voltage, any high voltages appearing on the upper portion of the bitlines during programming operations will be blocked from the more sensitive low voltage bitline sense amplifier circuitry connected to the lower portion. Accordingly, those skilled in the art will understand that the transistors of the high voltage domain can have gate oxide thicknesses that are greater than those transistors in the low voltage domain.
  • the sensing method shown in Figure 19a is similar to the sensing method shown in Figure 17a, except that PCH* remains active to keep precharge transistor 1026 turned on while steering transistor 1020 is turned on.
  • Figure 19 is one example of the timing control over E_REF and PCH* for adjusting the reference charge to be provided.
  • the PCH* pulse duration and the E_REF signal deactivation time can be tailored to achieve the desired reference charge on the un-accessed bitline.
  • the timing can be controlled externally in a test mode, or internally with well known logic circuitry. This adjustability allows for several advantageous applications.
  • bitline sense amplifier will flip its state, which reveals the voltage applied to the bitline by the programmed memory cell.
  • the embodiment of the invention shown in Figures 16 and 18 can sense the difference in voltage between a pair of folded bitlines, in order to sense the programmed or unprogrammed state of an anti-fuse memory cell. Furthermore, timing of the reference charge circuit 1012 can be adjusted to change the reference charge being added to the reference bitline. This can be done for testing operations, as previously described, or to ensure that the optimal reference voltage level is provided to improve sensing margins of programmed anti-fuse memory cells. Those skilled in the art will understand that process variations can change the current conducting level of programmed anti-fuse memory cells, therefore, having the ability to adjust the reference voltage after the memory array is programmed will ensure reliable operation.
  • FIG 20 is a schematic of an alternate folded bitline anti-fuse memory array according to another embodiment of the present invention.
  • the alternate folded bitline anti-fuse memory array shown in Figure 20 is similar to that shown in Figure 16, but employs an alternate reference charge circuit that can increase the amount of charge to be added to an reference bitline.
  • Folded bitline anti-fuse memory array 1400 includes the same numbered elements as previously shown and described in Figure 16, and hence no further description of these elements is required.
  • Reference charge circuit 1402 includes supplemental capacitance circuits 1404 and 1406, each having a gate terminal connected to a selection signal C1 and C2, respectively.
  • the supplemental capacitance circuits are shown in the present embodiments as n-channel transistors connected in parallel to primary capacitance circuit 1024, but p-channel transistors can be used with equal effectiveness.
  • one or both of capacitance circuits 1404 and 1406 can be activated by driving C1 and C2 to the high logic level.
  • Transistors 1404 and 1406 can be identically sized as transistor 1024, or each can be sized differently. Furthermore, any number of additional capacitance circuits can be included, and any combination of supplemental capacitance circuits can be activated, to provide more flexibility and finer control over the reference charge to be added to the reference bitline. The sensing operation can be the same as previously described for Figure 17a.
  • an additional capacitance can be added to the data bitline of the complementary bitline pair from which data of a connected memory cell is to be sensed.
  • the additional capacitance is not added to the reference bitline.
  • the additional capacitance added to the bitline changes the rate at which its voltage rises relative to the other bitline (such as the reference bitline) that does not have the additional capacitance added to it.
  • Figure 21 is a schematic of the alternate folded bitline anti-fuse memory array according to the present embodiment of the invention.
  • Folded bitline anti-fuse memory array 1500 includes the same numbered elements as previously shown and described in Figure 16, and hence no further description of these elements is required.
  • Reference charge circuit 1502 includes previously described steering transistors 1020 and 1022, and a capacitance means 1504 connected to the shared source/drain terminal of transistors 1020 and 1022. The sensing operation of folded bitline anti-fuse memory array 1500 will now be described with reference to the flow chart of Figure 22a and the timing diagram of Figure 22b.
  • transistor 1004 is to be accessed (Case 1 shown in Figure 22b), and is an unprogrammed anti-fuse memory cell which does not have a gate to drain conduction channel.
  • the sense operation starts at step 1600 where the bitlines are precharged to the first voltage supply, such as VSS for example. This corresponds to BLPCH pulsing high in Figure 22b.
  • a selected wordline is driven to a second voltage supply, such as VCC for example. Occurring concurrently with the selected wordline activation, but noted as step 1604, signal 0_REF is raised to VCC to turn on steering transistor 1022.
  • the capacitance means 1504 is coupled to the same bitline that memory cell 1004 is connected to.
  • the sense amplifiers are turned on by driving H_EN and L_EN to the high and low logic levels respectively.
  • the p-channel transistors 1028 and 1030 of bitline sense amplifier will turn on and pull both BL and BL* towards H_EN. Since memory cell 1004 is non-conductive, both bitlines BL and BL* should rise at approximately the same rate.
  • bitline sense amplifier 1014 will fully latch and drive BL to the H_EN logic level and BL* to the L_EN logic level.
  • the advantage of this present scheme is that no timing control over reference charge circuit 1502 is required.
  • the bitline sense amplifier 1014 is activated either at the same time, or shortly after the selected wordline VVLO and the proper steering signal are activated.
  • bitline sense amplifier 1014 latches to a state opposite to the one in Case 1.
  • bitline sense amplifiers will latch to unpredictable logic states. Since both BL and BL* start at a precharged VSS value, minor voltage variations or manufacturing variations can affect the bitline voltages, and hence sensing by the bitline sense amplifiers. Hence, the present scheme of adding capacitance to the data bitline will ensure that properly fabricated memory cells operating in a two cell/bit mode will be consistently sensed.
  • the precharge-to-VCC sensing method can be executed with the folded bitline anti-fuse memory array of Figure 16, and is similar to the sensing method outlined in Figure 17a.
  • the timing diagram of Figure 23 shows traces for the control signals of Figure 16 and of the bitlines BL and BL* for two different cases. In Case 1 , the accessed memory cell connected to BL* is programmed. In Case 2, the accessed memory cell connected to BL* is unprogrammed.
  • Case 1 after both bitlines are precharged to a first voltage supply, such as VCC for example, a wordline such as VVLO is driven to a second voltage supply V1 , such as VCC + 1.5 volts for example. If the anti-fuse memory cell 1004 is programmed, then the wordline will pull bitline BL* up to a voltage of about VCC + 100 millivolts. Then a negative reference charge is added to the data bitline BL* by activating 0_REF, reducing it by 50 millivolts for example. The reference bitline BL remains at VCC. Therefore, when the bitline sense amplifier is activated, the differential between the data bitline and the reference bitline is sensed and fully latched.
  • VCC first voltage supply
  • V1 such as VCC + 1.5 volts for example.
  • sensing/testing scheme embodiments have been described with respect to memory arrays consisting of single transistor anti-fuse memory cells. Those skilled in the art will understand that the sensing/testing embodiments can be applied to memory arrays consisting of memory cells having two transistors, such as those illustrated in Figures 2 and 3, with the appropriate control over the cell plate voltage Vcp.
  • All the previously described embodiments are directed to circuits and methods for sensing data on bitlines of a memory array, and in particular folded bitlines of a memory array. Advances in semiconductor manufacturing and scaling allows for tight packing of bitlines in the memory array, thereby reducing the spacing between adjacent bitlines. This leads directly to an increase in capacitive coupling between the tightly packed bitlines, which can potentially cause read errors.
  • An example of the bitline capacitive coupling effect is described with reference to Figure 25.
  • anti-fuse memory cells 1750 there are four anti-fuse memory cells 1750, of only one which is labeled, each having a drain diffusion terminal connected to a respective bitline, and gates connected to a wordline VVL
  • the memory cells connected to BLO, BL1 and BL3 have been programmed, while the memory cell 1750 connected to BL2 is not programmed.
  • a programmed anti-fuse memory cell 1750 has a resistor element 1752 connected between VVL and its respective source terminal, to functionally illustrate the conductive link formed during programming of the anti-fuse cell.
  • the memory cell connected to BL2 is not programmed, therefore BL2 should remain at the precharge voltage of VSS.
  • Figure 26 is a circuit schematic of an OTP memory array 1800 having a novel bitline precharge circuit for mitigating the above described bitline coupling effects, according to an embodiment of the present invention.
  • bitlines adjacent to a data bitline for sensing by a bitline sense amplifier are precharged to a voltage level corresponding to the opposite logic state of the precharge voltage of the data bitline.
  • the reference bitlines and the data bitlines can be called selected bitlines, while the remaining bitlines can be called unselected bitlines.
  • the data bitline is precharged to VSS, which corresponds to a logic "0"
  • its adjacent unselected bitlines are precharged to a high voltage level which corresponds to a logic " 1 ".
  • OTP memory array 1800 includes n-channel single transistor anti-fuse memory cells 1802 as previously described in the embodiments of the present invention, preferably arranged in the folded bitline scheme. It is noted that OTP memory array 1800 is illustrated differently than in the previous figures, but is still functionally representative of a folded bitline configuration. It will be apparent to those skilled in the art that the proposed precharge scheme is applicable to any type of memory cell and bitline architecture. Complementary bitlines BL0/BL0*, BL1/BL1 *, BL2/BL2* and BL3/BL3* are selectively coupled to a bitline sense amplifier 1804 through column select circuit 1806.
  • Column select circuit 1806 is configured with n-channel column select devices 1808, 1810, 1812, 1814, 1816, 1818, 1820 and 1822. It is noted that the column select devices are paired due to the folded bitline configuration. For example, column select devices 1808 and 1822 are controlled by the same column select signal Y-SEL[0]. The remaining column select device pairs are controlled by column select signals Y-SEL[1 ], Y-SEL[2] and Y-SEL[3]. The operation of column select circuit 1806 and its n-channel column select devices is well known in the art. Based on a column address, a pair of column select devices are activated to couple one complementary bitline pair to bitline sense amplifier 1804 for sensing.
  • Selective precharge circuit 1824 is similar in configuration to column select circuit 1806, and includes n-channel column precharge devices 1826, 1828, 1830, 1832,
  • the signals controlling each pair of column precharge devices and each pair of column select devices connected to the same bitlines are based on complementary column address signals (not shown). More specifically, PC_S[0] to PC_S[3] and Y-SEL[0] to Y-SEL[3] are generated with different decoding circuits, which use complementary column address signals and with different timing.
  • the precharge voltage circuit 1842 can provide a predetermined precharge voltage level prior to a read operation. In another embodiment, the precharge voltage circuit 1842 can simply be the VCC voltage supply. In either embodiment, a primary precharge circuit similar to precharge circuit 1010 of Figure 16 can integrated with the bitline sense amplifier circuit 1804 for precharging only the selected bitlines to VSS prior to the read operation.
  • the column precharge devices of selective precharge circuit 1824 and the column select devices are activated simultaneously in a precharge phase such that the selected bitlines are precharged to VSS while the bitlines adjacent to the selected bitlines are precharged to the high voltage level.
  • the control over the specific bitlines to precharge to the high voltage level during the precharge phase can be achieved by controlling signals PC_S[0] to PC_S[3].
  • a read phase where the selected wordline is activated, the appropriate reference charge is added to the reference bitlines, and both the data bitlines and the reference bitlines are coupled to the bitline sense amplifier 1804 for data sensing.
  • step 1900 all the column precharge devices of selective precharge circuit 1824, except devices 1828 and 1838 are activated to precharge all bitlines except BL1 and BL1 * to the high voltage level.
  • step 1902 Occurring concurrently at step 1902, only column select devices 1810 and 1820 will be turned on by driving Y-SEL[1 ] to a high logic level while the precharge to VSS circuit in BLSA 1804 is activated. Due to the column decoding scheme based on complementary column addresses, devices 1828 and 1838 are turned off while devices 1826, 1830, 1832, 1834, 1836 and 1838 are turned on. Therefore, the unselected bitlines adjacent to selected bitlines BL1/BL1 * are driven to the high voltage level while the selected bitlines are driven to VSS. Now VVL1 can be driven to the high voltage level at step 1904. BL1 can be the reference bitline in a single ended sensing scheme, but can be the complementary bitline in a two cell per bit sensing scheme. Then at step 1906, the bitline sense amplifier 1804 can be activated to sense the voltage differential on
  • the selected bitlines would be precharged to VSS while the remaining unselected bitlines are precharged to the high voltage level. Conversely, if the column address is changing between read cycles, all the bitlines can be precharged to the high voltage level at the end of one read cycle. Then the selected bitlines are precharged from the high voltage level to VSS when the new column address signal (Y-SEL[0] to Y-SEL[3]) has been activated.
  • bitline precharge embodiment can be used in combination with any of the previously described bitline sensing schemes.
  • precharging all bitlines except the data bitline and the reference bitline to the high voltage level will minimize the bitline capacitance coupling effect, since the unselected bitlines will remain at the precharged high voltage level regardless of the programmed/unprogrammed states of the memory cells connected thereto.
  • three bitlines will be precharged to the high voltage level. This can be a source of power consumption since many of the bitlines are precharged from VSS to VDD in preparation for the next read operation.

Abstract

L'invention porte sur des procédés de test de cellules de mémoire à anti-fusible à un seul transistor et à deux transistors non programmées qui consistent à tester des connexions des cellules à une ligne de bit par comparaison d'une caractéristique de tension d'une ligne de bit connectée à la cellule sous test à celle d'une ligne de bit de référence ayant une caractéristique de tension prédéterminée. Certains procédés peuvent utiliser des cellules d'essai comprenant un transistor d'accès configuré d'une manière identique au transistor d'accès d'une cellule de mémoire normale, mais omettant le dispositif anti-fusible présent dans la cellule de mémoire normale, pour tester la présence d'une connexion de la cellule de mémoire normale à la ligne de bit. Une telle cellule d'essai peut être utilisée dans un test supplémentaire pour déterminer le niveau de couplage capacitif de la tension de ligne de mot aux lignes de bit par rapport à celui d'une cellule de mémoire normale sous test.
PCT/CA2013/050154 2012-03-05 2013-03-01 Procédés de test de mémoire otp non programmée WO2013131185A1 (fr)

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US13/412,500 US8767433B2 (en) 2004-05-06 2012-03-05 Methods for testing unprogrammed OTP memory

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WO2017136106A1 (fr) * 2016-02-02 2017-08-10 Qualcomm Incorporated Contrainte de bruit aléatoire d'un amplificateur de détection
CN109427376A (zh) * 2017-08-24 2019-03-05 三星电子株式会社 配置为防止由于泄漏电流进入位线的读取失败的存储设备
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CA2578837A1 (fr) * 2006-12-29 2007-05-15 Sidense Corp. Detection du procede de chiffrement vernam a haute vitesse
CA2646220A1 (fr) * 2008-04-03 2009-03-10 Sidense Corp. Circuit de controle pour reseau de memoire otp non programme

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WO2017058111A1 (fr) * 2015-09-28 2017-04-06 Agency For Science, Technology And Research Procédé de détection d'erreur dans un dispositif de mémoire vive magnétique à champ électrique oscillant (tef-ram), et dispositif tef-ram
WO2017136106A1 (fr) * 2016-02-02 2017-08-10 Qualcomm Incorporated Contrainte de bruit aléatoire d'un amplificateur de détection
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CN109427376B (zh) * 2017-08-24 2023-06-13 三星电子株式会社 配置为防止由于泄漏电流进入位线的读取失败的存储设备
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