WO2013111451A1

WO2013111451A1 - System simulation device

Info

Publication number: WO2013111451A1
Application number: PCT/JP2012/081018
Authority: WO
Inventors: 祐市桜井; 健一新保; 鳥羽　忠信; 大坂　英樹
Original assignee: 株式会社日立製作所
Priority date: 2012-01-26
Filing date: 2012-11-30
Publication date: 2013-08-01
Also published as: JP2013152653A

Abstract

The present invention provides a system simulation device with which processing load of a processor unit calculation unit is lightened, and high-speed processing is made possible. The system simulation device extracts selected information from a network packet with a network packet information extraction unit using information selected with a packet extraction site selection unit, and carries out a simulation calculation with the processor unit calculation unit using the extracted information.

Description

System simulation device

The present invention relates to a system simulation apparatus.

There is Japanese Patent No. 3090388 (Patent Document 1) as background art in this technical field. This publication describes "a method for simulating data traffic transferred over a network between a plurality of nodes interconnected by a network, wherein the data traffic causes a plurality of interactions between the plurality of nodes. 1 or more of the plurality of nodes are client nodes, and one or more of the plurality of nodes is described as a server node.

There is also Japanese Patent No. 3746371 (Patent Document 2). In this publication, “by simulating a process executed on a multiprocessor system in which a plurality of processors are connected to a system control device by an independent bus for each processor and a main memory is connected to the system control device, "Performance simulation method for measuring execution performance of the multiprocessor system".

Japanese Patent No. 3090388 Japanese Patent No. 3746371

Patent Document 1 describes a network simulation mechanism. There is also a description of system simulation evaluation. For example, an example of modeling transaction traffic of a distributed processing system is described.

However, the system simulation apparatus used in the conventional embedded system design is composed of a network simulator and a processor unit calculation unit, and it is necessary to simulate a network packet including a network destination address and data in accordance with a processor cycle having many state change points. is there. Therefore, the simulation of a large-scale processor system has a problem that the calculation time is long and cannot be used in practical time.

Therefore, the present invention provides a system simulation apparatus that reduces the processing load on the processor unit calculation unit and enables high-speed processing.

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems. To give an example, a system simulation apparatus, which is a system configuration model definition unit that defines the configuration of a system that performs simulation, and the system configuration model definition A network simulation unit that constructs a system defined by the unit, a processor unit calculation unit that performs a simulation calculation of the system constructed by the network simulation unit, a performance display unit that displays a system simulation calculation result, and the defined The system configuration model is converted into the configuration information of the network simulation unit, and the configuration information is input to the network simulation unit, and the configuration information of the processor unit calculation unit is converted into the configuration information. A simulation parameter input unit to be input to the processor unit calculation unit, specific information is extracted from the network packet, and a network packet information extraction unit to be input to the processor unit calculation unit is extracted from the network packet by the network packet information extraction unit A packet extraction part selection unit for selecting a part; a packet extraction setting input part for inputting information selected by the packet extraction part selection unit to the network packet information extraction unit and the processor unit calculation unit; Using the information selected by the packet extraction part selection unit, the network packet information extraction unit extracts information selected from the network packet, and performs simulation calculation using the information extracted by the processor unit calculation unit And features.

According to the present invention, it is possible to provide a system simulation apparatus that reduces the processing load on the processor unit calculation unit and enables high-speed processing.

Issues, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

Example of configuration diagram of system simulation apparatus according to embodiment 1 Example of user interface of system configuration model definition part Example of GUI dialog of packet extraction part selection part Example of flowchart explaining processing of system simulation apparatus according to embodiment 1 Example of configuration diagram of conventional system simulation device Example of flowchart explaining processing in conventional system simulation apparatus Example of a graph on the time axis explaining the comparison of evaluation calculation cycles on a real computer when using a conventional system simulation device Example of a diagram illustrating network packet information extraction unit 106 Example diagram illustrating network packets Example of graph on time axis explaining evaluation calculation cycle in real computer when system simulation apparatus according to embodiment 1 is used Example processor model diagram that illustrates the processing in the processor module Example of a diagram explaining the calculation contents of the processor unit calculation unit (processor shared bus probability calculation model) The figure which shows the calculation contents of the performance calculation of the real-time property calculation model of the processor module Example of GUI dialog for system evaluation content selection section Example of configuration diagram showing system simulation apparatus 1500 in the fifth embodiment Example of GUI dialog 1501 in the processor unit calculation unit / operation content selection unit Example of configuration diagram showing system simulation apparatus 1600 in Embodiment 6 Example of configuration diagram showing system simulation apparatus 1700 in Embodiment 7 Example of configuration diagram showing system simulation apparatus 1900 in the eighth embodiment Example of a diagram for explaining packet extraction data input time to processor unit calculation hardware according to embodiment 8 Example of a diagram illustrating packet input time to a processor unit calculation unit according to a conventional example

Hereinafter, examples will be described with reference to the drawings.

Here, an embodiment of a system simulation apparatus according to the present invention will be described.
FIG. 1 is an example of a configuration diagram of a system simulation apparatus according to the present embodiment.

The system simulation apparatus 100 includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, a network packet information extraction unit 106, and a processor unit calculation unit 107. , A device comprising the performance display unit 108.

The system configuration model definition unit 101 is a part that defines the configuration of the system that performs the simulation. In this definition unit 101, the system configuration of the evaluation target is defined by inputting the contents of the target system that the user wants to evaluate.

The simulation parameter input unit 102 converts the system configuration model defined by the system configuration model definition unit 101 into the configuration information of the network simulation unit 105 and the configuration information of the processor unit calculation unit 107, and sends them to the respective simulation units. Enter it.

The packet extraction part selection unit 103 is a selection part that selects a part to be extracted from a network packet, and takes the form of a GUI dialog as an example.

The packet extraction setting input unit 104 inputs a part extracted from the network packet selected by the packet extraction part selection unit 103 to the network packet information extraction unit 106 and the processor unit calculation unit 107.

The network simulation unit 105 performs network simulation of the system using the system configuration model parameters defined by the system configuration model definition unit 101 and converted by the simulation parameter input unit 102.

The network packet information extraction unit 106 receives the network packet output from the network simulation unit 105, extracts information from the network packet according to the selection of the network packet extraction information selection unit 103, and calculates only the extracted packet information by processor unit calculation. Processing to output to the unit 107 is performed.

The processor unit calculation unit 107 is defined by the system configuration model definition unit 101, converted by the simulation parameter input unit 102, selected by the packet extraction part selection unit 103, and converted by the packet extraction setting input unit 104. The processor unit calculation is performed using the obtained packet extraction site parameters, and the system is simulated.

The performance display unit 108 is a part for displaying a system simulation result, and visualizes the result and outputs it as GUI or text information.

FIG. 2 is an example of a user interface of the system configuration model definition unit 101.
As an example, the system configuration model definition unit 101 includes a GUI (graphical user interface) 200, and a data generator module 201, a transmission path module 202, a switch module 203, and a processor module 205 as modules.

The system configuration model definition unit GUI (graphical user interface) 200 is an example of a user interface of the system configuration model definition unit, and displays a system to be simulated on a computer screen. Functional blocks called modules (components) related to system simulation are arranged according to user settings, and inputs for connecting each of them to each other via a network are received.

The data generator module 201 generates a network packet according to the set generation pattern.
The transmission path module 202 inputs a network packet, analyzes the payload size, calculates the time taken for the network packet to pass through the transmission path module 202, that is, the transmission latency time, and calculates the latency parameter of the network packet Add and set the transmission latency time.

In the system simulation apparatus, the time required for the simulation target object to complete a certain operation is called service time. In the transmission path module 202, “transmission path module 202 inputs a network packet, The payload size is analyzed, and the transmission latency time is set as the service time for the network packet ”.

The switch module 203 is a module that inputs a network packet, switches the output port destination according to the switch setting table, and outputs the destination.

The processor module 205 is a module that performs a desired calculation using a network packet and outputs a calculation result.

In the system configuration model definition unit 101, for example, a system as a simulation target can be configured using a combination of the above modules, and a large-scale processor system in which, for example, about 1000 processor modules 205 are arranged can be constructed.

The simulation parameter input unit 102 converts the defined system configuration model into the configuration information of the network simulation unit 105 and the configuration information of the processor unit calculation unit 107, and inputs them to the respective simulation units.

As an example, in the network simulation unit 105, the configuration and number of each module of the data generator 201, the transmission path 202, and the switch 203, parameters determined individually for each module, and the connection relationship between the modules are shown. The connection relationship shown is set as a parameter.

As an example, in the processor unit calculation unit 107, the configuration and number of the processor modules 205, parameters determined for each module, and the connection relationship with the network simulation unit 105 are set as parameters.

FIG. 3 shows an example of the GUI dialog 300 of the packet extraction part selection unit 103.
The packet extraction part selection unit 103 is exemplified as a dialog 300, and accepts information selection input of a network packet to be used for simulation when the user inputs selection of an extraction part.

The selected information is input to the packet extraction setting input unit 104 by the packet extraction site selection unit 103, and the packet extraction setting input unit 104 inputs the packet extraction site parameters to the network packet information extraction unit 106 and the processor unit calculation unit 107. .

For example, in the network packet information extraction unit 106 and the processor unit calculation unit 107, information indicating a part extracted from the network packet is input as a parameter.

The network simulation unit 105, the network packet information extraction unit 106, and the processor unit calculation unit 107 cooperate with each other according to the set parameters to perform system simulation calculation.

FIG. 4 is an example of a flowchart for explaining processing of the system simulation apparatus according to the present embodiment.

The simulation is started (401), and the system configuration model is defined by the user setting and input in the user interface 200 of the system configuration model definition unit (402), and the simulation is performed by the simulation parameter input unit 102 using the defined model. A parameter is generated (403), and the generated simulation parameter is input to the network simulation unit 105 and the processor unit calculation unit 107 by the simulation parameter input unit 102 (404).

Next, a part to be extracted from the network packet is selected by setting input on the packet extraction part selection screen 300 (405), and information on the part to be extracted is connected to the network packet information extraction part 106 by the packet extraction setting input part 104. It inputs into the processor unit calculation part 107 (406).

Next, the state of all modules in the state of discrete time 0 is calculated and updated (407).

Next, in response to the occurrence of a network event (410) in the network simulation unit 105, event processing is performed in an event routine (411).
A network event refers to a state change point that triggers to calculate and update the state in the network simulation unit.

The network event is different for each module. For example, in the data generator module 201, an event “generates a network packet” occurs, and processing associated therewith is performed.

Further, for example, in the switch module 203, an event “extracts a network packet from the input buffer” occurs, and accordingly, the event routine performs a process of moving the network packet to a predetermined output port.

Next, in the network packet information extraction unit 106, the information selected by the user's setting input in the extraction information selection unit 103 is extracted from the packet (420).

In each processor module 205 in the processor unit calculation unit 107, a processor event is generated by the transmitted network packet information (421), and the processor unit calculation is performed (430).

It is determined whether the performance calculation of all modules is completed (440).
When the calculation of all the modules is completed, the state update of all modules in the discrete time state is completed, and the discrete time is advanced by 1 (441).

The expiration of the simulation time is determined (442). When the simulation time expires, the performance calculation result is visualized in the state display unit using the calculation result so far and output as GUI or text information (443).
Then, the simulation is terminated (444).

FIG. 5 is an example of a configuration diagram of a conventional system simulation apparatus.
Here, for comparison, a conventional system simulation apparatus will be described with reference to FIG.

A conventional system simulation apparatus 500 is an apparatus including a system configuration model definition unit 501, a simulation parameter input unit 502, a network simulation unit 505, a processor unit calculation unit 507, and a performance display unit 508.

The system configuration model definition unit 501 is a part that defines the configuration of a system that performs simulation, and the definition unit 501 receives a target system to be evaluated.

The simulation parameter input unit 502 converts the system configuration model defined by the system configuration model definition unit 501 into the configuration information of the network simulation unit 505 and the configuration information of the processor unit calculation unit 507, and sends them to the respective simulation units. Enter it.

The network simulation unit 505 performs network simulation of the system using the system configuration model parameters defined by the system configuration model definition unit 501 and converted by the simulation parameter input unit 502.

The processor unit calculation unit 507 performs a simulation of the processor unit of the system using the system configuration model parameters defined by the system configuration model definition unit 501 and converted by the simulation parameter input unit 502.

The performance display unit 508 is a part for displaying a system simulation result, and visualizes the result and outputs it as GUI or text information.

FIG. 6 is an example of a flowchart for explaining processing in a conventional system simulation apparatus.
A system simulation processing flow in which the respective parts of the conventional system simulation apparatus 500 cooperate will be described with reference to FIG.

Simulation starts (601), a configuration model is defined (602), simulation parameters are generated using the defined model (603), and are input to the network simulation unit 505 and the processor unit calculation unit 507 (604).

Next, the state of all modules in the discrete time 0 state is calculated and updated (607).

In response to the occurrence of a network event (610) in the network simulation unit 505, event processing is performed in an event routine (611).

Next, in each processor module in the processor unit calculator 507, a processor event is generated by the transmitted network packet (621).

Multi-rate processing is performed (630), using the network packet data sent and calculating the performance in the processor cycle.

It is judged whether the performance calculation of all modules is completed (640).

When the calculation of all modules is completed, the state update of all modules in the discrete time state is completed, and the discrete time is advanced by 1 (641).

The simulation time is judged to be expired (642). When the simulation time is expired, the performance calculation result is visualized in the state display unit using the calculation result so far and output as GUI or text information (643).
Then, the simulation is terminated (644).

As described above, the conventional system simulation apparatus 500 needs to perform simulation by combining a network packet including a network destination address, data, and the like, and a processor cycle having many state change points.

In the system simulation apparatus, the state change of each module accompanying the network packet transmission simulation occurs when the transmission of the network packet is completed.

For example, if a network packet size is 300 bytes of data and a simulation is performed that passes through a transmission path with a speed of 1.25 Gbps, the state change of each module associated with the network packet transmission simulation is It occurs every 240 ns when expressed in terms of time interval (rate).

Further, in the system simulation apparatus, the state change of the processor event in each processor module in the processor unit calculation unit 507 occurs every processor cycle. The processor cycle refers to the reciprocal of the clock that drives each processor module.

For example, assume that each processor module is driven by a 1 GHz clock. In this case, the state change of the processor event occurs every 1 ns in terms of time interval (rate).

As described above, the interval of the state change due to the network packet transmission simulation and the interval of the processor event state change in each processor module are different as described above. Performing a plurality of simulations with different state change intervals in a single system simulation apparatus is called multirate calculation.

The above-described conventional system simulation apparatus 500 performs simulation by combining a network packet including a network destination, data, and the like and a processor cycle having many state change points, and performs multirate calculation. To tell.

The conventional system simulation apparatus 500 has a first goal of obtaining an accurate simulation result. For this reason, when modules with different state change intervals (rates) are combined, the multi-rate calculation to keep the state change intervals (rates) of each module faithfully and calculate individually is essential to obtain accurate simulation results. It was a function.

However, multirate calculation has a problem that the calculation time is long.
In the above example, the state change of each module accompanying the network packet transmission simulation occurs every 240 ns, and the state change of the processor event in each processor module in the processor unit calculator 507 occurs every 1 ns. .
That is, the state change of the processor event occurs 240 times as much as the transmission simulation of one network packet.

For example, when one network packet is transmitted as processing data to the processor module in the processor unit calculation unit 507, the simulation time is 240 times longer than when only a network packet is transmitted.

Further, a change in the state of the processor event occurs in each processor module in the processor unit calculation unit 507. For this reason, the simulation of a large-scale processor system cannot be used in practical time because of a long calculation time.

FIG. 7 is an example of a graph on the time axis for explaining a comparison of evaluation calculation cycles in an actual computer when a conventional system simulation apparatus is used.

As an example, in the processor unit calculation unit 507 shown in FIG. 5, an evaluation calculation cycle in an actual computer when performing a simulation evaluation of a large-scale system having 1000 processor models in the processor unit calculation unit 507 is shown in FIG. Will be described below.

In FIG. 7, 99 calculation cycles of the processor unit calculation unit 507 are necessary (702) with respect to one simulation cycle (701) of the network simulation unit 505.

Since multi-rate processing is required for each 1000 processors, multi-rate processing calculation cycles are accumulated for 1000 processors.

For example, when the network packet is a 300-byte packet, the processor unit calculation unit 507 needs about 100 times the multi-rate calculation cycle of the actual computer as compared to the network event processing cycle.

In addition, this multi-rate calculation is generated independently for each processor module 205, and multi-rate calculation cycles are added by the number of processor modules to update one discrete time state as a whole system.

In a large-scale system having 1000 processor models as illustrated, multi-rate calculation cycles several hundred times as many as network events occur in each of 1000 processor modules 205.

Furthermore, the simulation evaluation of an actual system uses about 1 million packets for evaluation. Therefore, the number of computations accumulated for the number of processor models of the above-mentioned multi-rate computation is further accumulated more than 1 million times, and the amount of computation of an actual computer diverges, and there is a problem that does not fit within a practical computation time.

On the other hand, the system simulation apparatus 100 according to the present embodiment includes a network simulator, a processor unit calculation unit, a selection unit that selects a part to be extracted from the network packet, and an extraction unit that extracts information from the network packet according to the setting. By using the data, the processing load on the processor unit calculation unit is reduced, and high-speed processing is possible.

Hereinafter, a configuration that reduces the processing load of the processor unit calculation unit and enables high-speed processing in the present invention will be described.

FIG. 8 is an example of a diagram illustrating the network packet information extraction unit 106.
The network packet input interface 801 is a part to which a network packet is input.

The packet field selection unit 802 extracts information from the network packet according to the packet extraction part selection unit 103 and the packet extraction setting input unit 104.

The processor unit calculation unit information generation unit 803 generates input data for the processor unit calculation unit 107.

FIG. 9 is an example of a diagram illustrating a network packet.
The packet size input to the network packet input interface 801 is 300 bytes as shown in FIG. 9 as an example (901).

The flow of network packet information extraction will be described with reference to FIGS.
As an example, the packet field selection unit 802 extracts “Format Type” and “Transaction” fields.

“Format Type” is 4 bits, and the type of network packet is defined. For example, “Format Type” defines “packet that performs cache operation on remote processor”, “packet related to remote bus I / O”, “network inspection packet”, and “other packet”.

Further, “Transaction” is 4 bits, and indicates the operation contents to be performed by the type of packet defined by “Format Type”.
For example, the operation of “clearing data at a certain address to zero” for “packet that caches a remote processor” or “writing data to a certain address” for “packet related to remote bus I / O” is “Transaction ".

When the processor unit calculation unit information generation unit 803 extracts the fields of “Format Type” and “Transaction”, the output data is, for example, 8 bits.

Here, the packet field selection unit 802 has a table for judging by combining field definitions such as “Format Type” and “Transaction”, so that “data write operation to bus I / O” can be performed from the input network packet. It is also possible to extract information such as “

The presence / absence of “data write operation to bus I / O” can be expressed by 1-bit information at a minimum. By using the packet extraction part selection unit 103, the packet extraction setting input unit 104, and the network packet information extraction unit 106, The size of information extracted from network packets can be reduced to a minimum of 1 bit.

This reduces the amount of information input to the processor unit calculation unit 107, reduces the calculation load, and enables high-speed processing.

In the present embodiment, the setting is made to extract “Format Type” and “Transaction” information from the network packet. However, the present invention is not limited to this, and other extraction information selected by the packet extraction part selection unit 103 is used. However, the calculation load in the processor unit calculation unit 107 is reduced according to the combination, and high-speed processing is possible.

FIG. 10 is an example of a graph on the time axis for explaining an evaluation calculation cycle in an actual computer when the system simulation apparatus according to the present embodiment is used.

FIG. 10 shows an evaluation calculation cycle in an actual computer when the system simulation apparatus 100 according to the present embodiment is used when performing a simulation evaluation of a large-scale system having more than 1000 processor models in the processor unit calculation unit 107. Use and explain.

In an example in which four calculation cycles of the processor unit calculation unit 107 are required (1002) for one simulation cycle (1001) of the network simulation unit 105, performance calculation is performed for each of 1000 processors, and as a result, the multirate processing of the conventional example is performed. Compared with the example 700 in which is accumulated, high-speed processing is realized.

This is because the processor unit calculation unit 107 uses information extracted from the network packet in the network packet information extraction unit 106 for calculation.
The calculation in the processor unit calculation unit 107 does not require multi-rate calculation, and can be realized in a calculation cycle of an actual computer several times as much as event processing of network events.

Further, the processing of the processor unit calculation unit 107 according to the present embodiment occurs independently for each processor model 205, and the update of one discrete time state as the entire system requires a calculation cycle for the number of processor models. Accumulate.

For example, in a large-scale processor system having 1000 processor models, calculation cycles several times as many as network events occur in each of 1000 processor models.

Furthermore, the simulation evaluation of an actual system uses about 1 million packets for evaluation.

In the conventional example, multi-rate calculation of several hundred times is reduced to several times in the system simulation apparatus 100 according to the present embodiment, and the number of calculations of the above-mentioned calculation corresponding to the number of processor models is further accumulated about 1 million times. It will be a thing.

From the above, the effect of reducing the amount of calculation of the actual computer obtained with respect to the conventional example can be obtained, and the amount of calculation of the actual computer does not diverge and falls within a practical calculation time.

In the present embodiment, the system configuration definition unit 101 and the packet extraction part selection unit 103 are configured to be set by user input. However, the present invention is not limited to this, and preset conditions are stored in a memory or the like. A configuration may be employed in which values and conditions stored in a memory or the like are read out and set and input.

In this embodiment, an example of a system simulation apparatus that performs network performance evaluation will be described as system simulation evaluation.

The system simulation apparatus according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, a network packet information extraction unit 106, and a processor unit. It is a device comprising a calculation unit (processor shared bus probability calculation model) 1200 and a performance display unit 108.

In the system simulation apparatus 100 of FIG. 1, the processor unit calculation unit 107 is changed to a processor unit calculation unit (processor shared bus probability calculation model) 1200. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

The processor shared bus probability calculation model is a calculation method that calculates the time from the arrival of data to the processor unit to the completion of data processing based on the probability of the shared bus, which is the service time in the processor unit. It is.

A detailed description of the processor shared bus probability calculation model is given below.
When evaluating the network performance of the system, for example, the transmission capacity of the network, the total latency from when the network packet is generated by the data generator module 201 to when the service is received by the processor module 205 is used.

In other words, when calculating the network performance of the system, the service time of the processor unit calculation unit can be simplified to a method of calculating the latency time from when the network packet arrives at the processor unit calculation unit until the service is given. .

FIG. 11 is an example of a processor model diagram for explaining processing in the processor module.
The network interface 1101 is a part having a function of mutually converting packet data transmitted over the network and data exchanged over the processor shared bus.

The memory 1102 is an area for storing and storing a series of data and instructions necessary for the processing of the processor 1100.

The processor shared bus 1103 is a bus-type data transmission path that allows the network interface 1101, the memory 1102, and the CPU core 1104 in the processor 1100 to be mutually accessible.

The CPU core 1104 is a part that reads instructions and data from the memory 1102 in the processor 1100 via the processor shared bus 1103, performs calculation processing, and returns the results to the memory and the network interface 1101 via the processor shared bus 1103.

For example, in the processor model 1100, if a network packet arrives at the network interface 1101, in this case, the packet data cannot be directly used for performance calculation in the processor model 1100. Therefore, the packet is sent to the buffer of the network interface 1101. Store.

Next, the contents of the packet are analyzed to determine what kind of processing the processor 1100 performs.

For example, in the case of a network packet for writing data to the memory 1102 of the processor 1100, a write access request is issued from the network interface 1101 to the processor shared bus 1103.

In addition, the CPU Core 1104 performs some processing on the network packet data.
These processes are performed in a processor cycle.

The contents of service processing for network packets will be described with reference to FIG.
The main access that the network packet generated by the data generator 201 described in FIG. 2 performs to the processor module 205 is read and write processing to the memory 1102.

That is, the packet latency of the processor module may be given as a service the time from the arrival of the network packet to the storage in the memory 1102.

However, here, there are fluctuation factors in latency. This is the occurrence of a congestion state (conflict) with the network interface 1101 when the CPU core 1104 accesses the processor shared bus 1103.

When the processor shared bus 1103 is occupied, such as when a large amount of data is exchanged with the memory 1102 for a long time when the CPU core 1104 is in a high load state, the right to use the processor shared bus 1103 is acquired from the network interface 1101 The packet cannot wait in the buffer inside the network interface 1101.

The waiting state of the packet due to the occupation of the processor shared bus 1103 is also counted as a latency, which causes a deterioration in network performance.

In this embodiment, the occupied state of the processor shared bus 1103 by the processing of the CPU core 1104 is defined as a decrease in the availability rate of the processor shared bus 1103 as viewed from the network interface 1101.

That is, the state of the processor shared bus 1103 by the processing of the CPU core 1104 can be grasped stochastically when considered for a long period of time.

This is modeled as the availability rate of the shared bus 1103 as seen from the network interface 1101.

The bus availability rate is set to be low for processor modules with a high load on the CPU core 1104 and high for processor modules with a low load.

From the above, after the arrival of the network packet, the processor module 205 determines whether or not to provide the service based on the bus availability rate, and calculates the service time.
The above is the detailed description of the processor shared bus probability calculation model.

FIG. 12 is an example of a diagram illustrating the calculation contents of the processor unit calculation unit (processor shared bus probability calculation model) 1200.
A processor unit calculation unit (processor shared bus probability calculation model) 1200 according to this embodiment includes processor unit calculation data 1201, a bus busy state 1202, a bus valid / invalid switching unit 1203, a service time calculation unit (processor shared bus probability calculation model) 1204. , The bus availability rate 1205.

An example of a system simulation flow for evaluating the transmission capacity of the network using the processor unit calculation unit (processor shared bus probability calculation model) 1200 will be described with reference to FIG.

The processor unit calculation data 1201 is packet data containing data of a certain size, and is generated from the generator 201.

In the processor unit calculation unit (processor shared bus probability calculation model) 1200, the bus valid / invalid switching unit 1203 determines whether or not to pass the processor unit calculation data 1201 to the service calculation unit 1204 that provides a service to the packet. .

The bus availability ratio 1205 outputs a value for switching whether or not to allow the processor unit calculation data 1201 to pass to the service calculation unit 1204 in the bus valid / invalid switching unit 1203. '= No pass.

It is probabilistic that the bus availability rate 1205 outputs “1” and “0”, and is set to “output 40% of“ 1 ””, for example.

The bus busy state 1202 becomes “1” when the bus valid / invalid switching unit 1203 determines that the processor unit calculation data 1201 does not pass.

When the bus valid / invalid switching unit 1203 determines that the processor unit calculation data 1201 does not pass, the packet data is held in the buffer in the network interface and given latency time is given.

When the bus valid / invalid switching unit 1203 determines that the processor unit calculation data 1201 has passed, the service calculation unit 1204 calculates a service time and sets the service time as a parameter of the processor unit calculation data.

An example of a system simulation apparatus that performs network performance evaluation as system simulation evaluation using the processor unit calculation unit (processor shared bus probability calculation model) 1200 shown above will be described. The packet extraction part selection unit 103 shown in FIG. Then, selection of a part to be extracted from a network packet necessary for network performance evaluation is accepted, and “Transaction Type” and “Transaction” are selected in the dialog 300 as an example.

The selected information is input to the packet extraction unit setting input unit 104, converted into necessary parameters for each of the network packet information extraction unit 106 and the processor unit calculation unit (processor shared bus probability calculation model), and input to each part. To do.

For example, the network packet information extraction unit 104 and the processor unit calculation unit (processor shared bus probability calculation model) input information indicating that the parts “Transaction Type” and “Transaction” to be extracted from the network packet are selected as parameters. To do.

Thereby, the network packet information extraction unit 106 enters a mode for extracting “抽出 Transaction Type” and “Transaction” from the network packet.

The processor unit calculator (processor shared bus probability calculation model) calculates the performance of only the bus I / O of the processor from the information indicating that the parts “Transaction Type” and “Transaction” to be extracted from the network packet are selected. It becomes a mode.

When evaluating the network performance of the system, for example, the transmission capacity of the network, the total latency from when the network packet is generated by the data generator module 201 to when the processor module 205 receives a service is used.
That is, the transmission capacity is calculated by packet size (unit: Bytes) / total latency (unit: time).

From the above, when calculating the performance of the network, the processor unit calculation unit only needs to be able to calculate the latency time from when the network packet arrives at the processor unit calculation unit until the service is provided.

Next, the contents of the packet are analyzed to determine what processing the processor 1100 should perform.
For example, in the case of a network packet for writing data to the memory 1102 of the processor 1100, a write access request is issued from the network interface 1101 to the processor shared bus 1103.
In addition, the CPU Core 1104 performs some processing on the network packet data. These processes are performed in a processor cycle.

The contents of service processing for network packets will be described with reference to FIG.
The main access that the network packet generated by the data generator 201 described in FIG. 2 performs to the processor module 205 is read and write processing to the memory 1102.
That is, the packet latency of the processor module may be given as a service the time from the arrival of the network packet to the storage in the memory 1102.

In this embodiment, the occupied state of the processor shared bus 1103 by the processing of the CPU core 1104 is defined as a decrease in the availability rate of the processor shared bus 1103 as viewed from the network interface 1101.
In other words, it is assumed that the state of the processor shared bus 1103 by the processing of the CPU core 1104 can be grasped stochastically in the long term.

From the above, the processor module 205 determines whether or not to provide a service based on the bus availability after the arrival of the network packet.

FIG. 12 shows an example of a diagram for explaining the calculation contents of the processor unit calculation unit (processor shared bus probability calculation model) 1200.

An example of a system simulation flow for evaluating the transmission capacity of the network using the processor unit calculation unit (processor shared bus probability calculation model) 1200 having the above functions will be described with reference to FIG.

The transmission capacity of the network packet is determined by measuring the time taken to generate a network packet from the data generator module 201 and receiving the service in the processor module 205, and dividing the size of the packet data by the time to obtain the per-unit time. It measures the data transmission capacity of the network.

Packet data containing data of a certain size is generated from the generator 201.

In the serial transmission path 202, depending on the transmission speed (capacity), it takes a certain time when the packet data passes through the transmission path. This time is called latency. For example, when a packet having a size of 100 Bytes passes through a 1 Gbps transmission path 202, a latency of 800 ns occurs.

The switch module 203 accepts the packet next. The switch module 203 has buffers for input and output, and generates packet latency for switch processing. For example, let the latency through the switch 203 be 300 ns.

Next, the processor module 205 determines whether to provide a service to the packet based on the shared bus availability rate.

Suppose, for example, that the service time in the processor module is 1us.

As described above, the latency generated from the generation of the 100 Bytes packet in the data generator 201 to the provision of the packet service in the processor model 205 becomes 2.1 us at 800 ns + 300 ns + 1 us, and the data transmission capacity in the system is 100 Bytes / 2.1 us = 752.4. It is evaluated as a system with a transmission capacity of MB / s.

In the processor module of the above-described embodiment, the calculation being performed receives I / O information related to network packet read and write, and determines whether to provide a service to the packet according to a predetermined shared bus availability rate. It is.

The processor unit calculation unit (processor shared bus probability calculation model) 1200 calculates that the service is provided when the service is provided, and the packet data is held in a buffer in the network interface when the service is not provided, and a predetermined latency time is given. Do.

These processes do not cause multi-rate calculation in the processor cycle that occurs when the processor model shown in FIG. 11 is processed, and high-speed processing is possible.

For example, for a single network event, the calculation of the processor module in this embodiment can be calculated with about 4 cycles at most.

This is capable of processing about two orders of magnitude faster than the conventional multi-rate calculation cycle. From the above, the network transmission capacity can be evaluated as the network performance of the system within the actual available calculation time and within the actually available calculation time.

Also, as a system network performance, it is important in a system that requires real-time performance, for example, evaluation of buffer usage in each module of the network is incorporated.

The buffer usage of each

module

201, 203, 205 is determined by how the input transmission capacity and output transmission capacity of the module change. The network packet is stored in the buffer when it is input to each module. At this point, the buffer usage increases by one.

Also, when the packet can be output, the buffer usage is reduced by 1 because the packet is taken out from the buffer and transferred to the subsequent stage.

In order to prevent the system from breaking down, it is necessary to evaluate and obtain the upper limit value of the buffer usage in advance, and to construct a system having a buffer exceeding this upper limit value.

The buffer usage is affected by the network topology and the processing load status of the CPU module core of the processor module. In other words, if the network topology is such that network packets from multiple generators are processed by a single processor module via the switch, packet data from multiple generators is congested at the output port of the switch. Cause transmission capacity to decrease.

∙ This may reduce the buffer consumption speed of the switch input port and increase the buffer usage. In addition, if the CPU core of the processor module is heavy and the availability rate of the processor shared bus is low, the transmission capacity of the network interface of the processor will decrease, and the port buffer that supplies data to this processor will be used. The amount may increase.

In extreme cases, the buffer becomes full due to the relationship between the input and output of the port, and a situation in which no more new packet data can be loaded occurs.
That is, as system simulation, it is only necessary to model the transmission capacity and to model the movement of the buffer in the port.

In this embodiment, the transmission capacity can be calculated by system simulation evaluation.
Regarding the buffer usage, a recording unit for recording the maximum usage is provided in the buffer of each module.
After the system simulation is completed, the maximum usage of all modules is output as a performance evaluation value as GUI or text information.

From the above, the buffer usage can be evaluated as the network performance of the system within the calculation time that can be actually used.

In this embodiment, an example in which real-time performance is evaluated as a system simulation apparatus that performs network performance evaluation will be described as system simulation evaluation.

The system simulation apparatus according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, a network packet information extraction unit 106, and a processor unit. This is a device comprising a calculation unit (real-time evaluation model) 1300 and a performance display unit 108.

In the system simulation apparatus 100 of FIG. 1, the processor unit calculation unit 107 is changed to a processor unit calculation unit (real-time evaluation model) 1300. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

The real-time evaluation model of the processor unit calculation unit is the service time in the processor unit, which is the time from the arrival of data to the processor unit until the data processing is completed. It is a calculation method that is calculated based on the original.

A detailed explanation of the real-time evaluation model is shown below.
In order to evaluate the real-time property of the system, the time from when a packet is generated by the data generator until the service is received by the specified time (deadline) by the processor module is calculated and evaluated. As the processor unit calculation unit, the time until the data processing is completed after the data arrives at the processor unit, which is the service time in the processor unit, is calculated using the priority, processing content and size of the packet, The method for calculating the service time can be simplified.

For this processing, it is only necessary to have “priority”, “Transaction”, and “Size” information of the network packet.
The processor model for calculating real-time performance has a standard service time for each transaction (processing) content prepared for each priority as a value.

In addition, the processor processing speed is multiplied by the packet size information and added to the previous service time to obtain the service time for the final network packet.
Further, there is a certain fluctuation called jitter in the real-time service time. Having a parameter (time) for obtaining this, the fluctuation in this range is randomly obtained and added to the service time.

In the processor module of the above-described embodiment, the calculation being performed receives “priority”, “Transaction”, and “Size” information of the network packet, and services the packet according to the predetermined real-time performance information of the processor module. It only calculates how much to give.

The above is the detailed description of the real-time evaluation model.
FIG. 13 is an example of a diagram for explaining the calculation contents of the processor unit calculation unit (real-time evaluation model) 1300.

A processor unit calculation unit (real-time evaluation model) 1300 according to this embodiment includes a processor unit calculation data 1301, a bus busy state 1302, a standard service time grant unit 1303, a standard service time storage unit 1304, a packet size service time calculation unit 1305, a service. It comprises a jitter storage unit 1306 and a service time calculation unit (real-time evaluation model) 1307.

An example of a flow for evaluating real-time performance as a system simulation apparatus that performs network performance evaluation using the processor unit calculation unit (real-time evaluation model) 1300 will be described with reference to FIG.

The processor unit calculation data 1301 is packet data containing data of a certain size and is generated from the generator 201.

The standard service time grant unit 1303 obtains a standard service time for each priority and process, and sets the service time in the parameter of the processor unit calculation data.

The service time granted by the standard service time grant unit 1303 is stored in advance in the standard service time storage unit 1304 as a standard service time for each transaction (processing) content prepared for each priority (priority). Have as.

The packet size service time calculation unit 1305 multiplies the processing speed of the processor by the size information of the packet, adds the previous service time, obtains the service time for the final network packet, and sets the parameter of the processor unit calculation data 1301 as the parameter. Set the service time.

Also, there is a certain fluctuation called jitter in the real-time service time. The parameter (time) for obtaining this is stored in the service jitter storage unit 1306, and the fluctuation in this range is obtained at random, and is added to the service time by the packet size service time calculation unit 1305.

The service time calculation unit (real-time evaluation model) 1307 calculates the service time of the data transmission latency for the processor unit calculation data 1301, and sets the service time in the transmission latency parameter of the processor unit calculation data 1301.

In the packet extraction part selection unit 103 for explaining an example of a system simulation apparatus that evaluates real-time performance as a system simulation apparatus that performs network performance evaluation using the processor unit calculation unit (real-time evaluation model) 1300 shown above, The part extracted from the network packet required for real-time evaluation of network performance is selected. For example, in the dialog, select “priority”, “Transaction”, and “Size”.

The selected information is input to the packet extraction unit setting input unit 104, and the network packet information extraction unit 106 and the processor unit calculation unit (real-time property evaluation model) 1300 convert it into necessary parameters and input the respective parameters.

For example, in the network packet information extraction unit 106 and the processor unit calculation unit (real-time evaluation model) 1300, information indicating that the parts “priority”, “Transaction”, and “Size” to be extracted from the network packet are selected as parameters. Enter as.

Thereby, the network packet information extraction unit 106 enters a mode for extracting “priority”, “Transaction”, and “Size” from the network packet.

The processor module in the processor unit calculation unit (real-time evaluation model) 1300 determines the real-time performance of the processor from information indicating that the parts “priority”, “Transaction”, and “Size” extracted from the network packet are selected. It becomes the mode which performs only calculation.

FIG. 13 shows the calculation contents of the performance calculation of the real-time property calculation model of the processor module.

When evaluating the real-time performance of the system, calculate the time from when the packet is generated by the data generator until the service is received by the processor module by the specified time (deadline).

That is, the processor unit calculation unit may perform a process of providing a service up to a predetermined deadline for a packet having a certain priority, processing content, and size.

For this processing, it is only necessary to have “priority”, “Transaction”, and “Size” information of the network packet.

The processor model that calculates real-time performance has a standard service time for each transaction (processing) content prepared for each priority as a value.

Also, the processor processing speed is multiplied by the packet size information and added to the previous service time to obtain the service time for the final network packet.

Also, there is a certain fluctuation called jitter in the real-time service time. Having a parameter (time) for obtaining this, the fluctuation in this range is randomly obtained and added to the service time.

This enables processing that is about two orders of magnitude faster than the conventional multi-rate calculation cycle.
Based on the above, the real-time performance of the system can be evaluated within the practical calculation time.

An example of a system simulation apparatus for selecting contents to be evaluated by system simulation will be described with respect to an embodiment of the system simulation apparatus according to the present invention.

This embodiment describes an example of a system simulation apparatus that selects contents to be evaluated by system simulation instead of selecting information to be extracted from a packet.

A system simulation apparatus according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a system evaluation content selection unit, a system evaluation content setting input unit, a network simulation unit 105, a network packet information extraction unit 106, and a processor unit calculation. This is a device comprising a unit 107 and a performance display unit 108.

In the system simulation apparatus 100 of FIG. 1, the packet extraction part selection unit 103 and the packet extraction setting input unit 104 are changed to a system evaluation content selection unit and a system evaluation content setting input unit. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

FIG. 14 is an example of a GUI dialog of the system evaluation content selection unit.

In the system evaluation content selection unit 1400, the evaluation content to be performed by the system simulation apparatus is selected.

As an example, in FIG. 14, “network performance, buffer usage evaluation”, “network performance, buffer usage evaluation (bidirectional packet processing)”, “real-time performance evaluation”, or a combination thereof is selected.

The selected information is input to the system evaluation content setting input unit, and the network packet information extraction unit 106 and the processor unit calculation unit 107 automatically convert them into necessary parameters and input them to the respective parts.

For example, when “network performance and buffer usage evaluation” is selected in the system evaluation content selection unit 1400, the network packet information extraction unit 106 selects the parts “Transaction Type” and “Transaction” to be extracted from the network packet. Is input as a parameter.

Further, information indicating that the processor shared bus probability calculation model is used is input to the processor unit calculation unit 107 as a parameter.

As a result, the network packet information extraction unit 106 enters a mode for extracting “Transaction Type” and “Transaction” from the network packet. In addition, the processor module in the processor unit calculation unit 107 uses a processor shared bus probability calculation model. In this mode, the performance calculation is performed only for the bus I / O of the processor.

As described above, by selecting an arbitrary system evaluation content by the system simulation apparatus according to the present embodiment, the system simulation apparatus automatically completes information extraction selection of the network packet and parameter setting of the processor unit calculation unit, thereby enabling high-speed system simulation evaluation. Realizes processing and enables system simulation evaluation within practical calculation time.

An embodiment of a system simulation apparatus according to the present invention will be described with reference to an example of a system simulation apparatus that selects contents to be calculated by a processor unit calculation unit.
FIG. 15 is an example of a configuration diagram of the system simulation apparatus of the present embodiment.

In the present embodiment, an example of a system simulation apparatus that does not select information to be extracted from a packet but selects contents to be calculated by a processor unit calculation unit will be described.

A system simulation apparatus 1500 according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a processor unit calculation unit operation content selection unit 1501, a processor unit calculation unit operation content setting input unit 1502, a network simulation unit 105, a network It is an apparatus comprising a packet information extraction unit 106, a processor unit calculation unit 107, and a performance display unit 108.

In the system simulation apparatus 100 of FIG. 1, the packet extraction part selection unit 103 and the packet extraction setting input unit 104 are changed to a processor unit calculation unit calculation content selection unit 1501 and a processor unit calculation unit calculation content setting input unit 1502. is there. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

FIG. 16 shows an example of a GUI dialog of the processor unit calculation unit / calculation content selection unit 1501.

In the processor unit calculation unit operation content selection unit 1501, the operation content to be performed by the processor unit calculation unit 107 is selected.

As an example, in FIG. 16, “shared bus load calculation”, “bidirectional network processing”, “real time processing evaluation”, or a combination thereof is selected.

The selected information is input to the processor unit calculation unit / calculation content setting input unit 1502, and the network packet information extraction unit 106 and the processor unit calculation unit 107 are automatically converted into necessary parameters and input to the respective parts.

For example, when “shared bus load calculation” is selected in the processor unit calculation unit operation content setting selection unit 1501, the network packet information extraction unit 106 selects the parts “Transaction type” and “Transaction” to be extracted from the network packet. The information that indicates the event is input as a parameter.

As a result, the network packet information extraction unit 106 uses the network packet “
It becomes a mode to extract “Transaction Type” and “Transaction”.

In the processor module in the processor unit calculation unit 107, a mode using the processor shared bus probability calculation model is set, and a mode for calculating the performance of only the processor bus I / O is set.

By selecting the operation contents in an arbitrary processor unit calculation unit by the system simulation apparatus of the present embodiment shown above, the system simulation apparatus automatically realizes information extraction selection of the network packet and high-speed processing of the processor unit, Enables system simulation evaluation within practical calculation time.

Regarding the embodiment of the system simulation apparatus according to the present invention, the network packet input to the processor unit calculation unit in the system simulation apparatus is not unidirectional, but bidirectional processing is supported between the network simulator unit and the processor unit calculation unit. An example of a system simulation apparatus configured as described above will be described.
FIG. 17 is an example of a configuration diagram showing a system simulation apparatus 1600 in the present embodiment.

A system simulation apparatus 1600 according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, a network packet information extraction unit 106, and a processor. The unit includes a unit calculation unit 107, a performance display unit 108, a packet data storage unit 1609, a buffer 1610, and a packet data response unit 1611.

A packet data storage unit 1609, a buffer 1610, and a packet data response unit 1611 are added to the system simulation apparatus 100 of FIG. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

This example is an example when the processing result by the processor unit calculation unit 107 is reused by the network simulation unit 105.

The network packet including the destination ID and payload is transmitted from the network simulation unit 105 to the processor unit calculation unit 107 and the buffer 1610 through the packet data storage unit 1609.

The calculation result of the processor unit calculation unit 107 is added to the network packet taken out from the buffer 1610 and transmitted to the network simulation unit 105 as a response packet.

The system simulation apparatus 1600 according to the present embodiment is used, for example, to simulate a distributed computing system.

In a distributed computing system in which a plurality of processor units are distributed and connected to each other via a network, processing data is sent to the processor unit calculation unit, calculation processing is performed, and then the processing result is sent to the network simulation unit. Perform reusable bidirectional processing.

In the conventional example that does not depend on this example, multi-rate calculation of several hundred times is required, and the amount of calculation of the actual computer is divergent, and there are cases where it does not fit within the practical calculation time. In the system simulation apparatus 1600 according to the example, an effect of reducing the calculation amount of the real computer is obtained, and the calculation amount of the real computer does not diverge and falls within a practical calculation time.

The packet data storage unit 1609, the buffer 1610, and the packet data response unit 1611 are essential for the purpose of holding and reusing network packet information lost in the network packet information extraction unit 106.

In this embodiment, the processor unit calculation unit 107 uses information extracted from the network packet in the network packet information extraction unit 106 for calculation.

The calculation in the processor unit calculation unit 107 does not require multi-rate calculation, and can be realized in a calculation cycle of an actual computer several times as much as event processing of network events.

The calculation in the processor unit calculation unit 107 uses information extracted from the network packet in the network packet information extraction unit 106 and information other than the information extracted in the network packet information extraction unit 106 is lost. Bidirectional processing in which the calculation result in the unit 107 is reused in the network simulation unit 105 is impossible.

For this reason, the packet data storage unit 1609 transmits a network packet including the destination ID and payload from the network simulation unit 105 to the processor unit calculation unit 107 and the buffer 1610.

The buffer 1610 accumulates and holds the network packet data processed by the processor unit calculation unit 107.

The packet data response unit 1611 adds the calculation result of the processor unit calculation unit 107 to the network packet extracted from the buffer 1610, and transmits it to the network simulation unit 105 as a response packet.

As described above, the bidirectional processing in which the processing result by the processor unit calculation unit 107 is reused by the network simulation unit 105 is enabled.

As an embodiment of the system simulation apparatus according to the present invention, an example of a system simulation apparatus having a configuration in which a plurality of processor unit calculation units are used instead of a single one will be described.
FIG. 18 is an example of a configuration diagram showing a system simulation apparatus 1700 in the present embodiment.

A system simulation apparatus 1700 according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, and a first network packet information extraction unit 1706. , A second network packet information extraction unit 1707, an nth network packet information extraction unit 1708, a first processor unit calculation unit 1709, a second processor unit calculation unit 1710, an nth processor unit calculation unit 1711, and a performance display unit 108 It is.

In the system simulation apparatus 100 of FIG. 1, the network packet information extraction unit 106 is replaced with a first network packet information extraction unit 1706, a second network packet information extraction unit 1707, an n-th network packet information extraction unit 1708, and a processor unit calculation unit. 107 is changed to a first processor unit calculator 1709, a second processor unit calculator 1710, and an n-th processor unit calculator 1711. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

The configuration including a large-scale processor unit in the processor unit calculation unit may not be configured with a single processor unit due to various restrictions.

On the other hand, a first network packet information extraction unit 1706, a second network packet information extraction unit 1707, an nth network packet information extraction unit 1708, a first processor unit calculation unit 1709, a second processor unit calculation unit 1710, an nth processor The unit calculator 1711 is configured to solve these restrictions.

In the present embodiment, an example of a system simulation apparatus that performs hardware division of a processor unit calculation unit will be described as a system simulation apparatus.
FIG. 19 is an example of a configuration diagram of the system simulation apparatus of this embodiment. A system simulation apparatus 1900 according to this embodiment includes a system configuration model definition unit 101, a simulation parameter input unit 102, a packet extraction part selection unit 103, a packet extraction setting input unit 104, a network simulation unit 105, a network packet information extraction unit 106, and a processor. It is a device comprising a unit calculation hardware unit 1907 and a performance display unit 108.

In the system simulation apparatus 100 of FIG. 1, the processor unit calculation unit 107 is changed to a processor unit calculation hardware unit 1907. The other configurations have the same functions as the configurations denoted by the same reference numerals shown in FIG. 1 and have not been described.

This embodiment includes a selection unit 103 that selects a part to be extracted from a network packet and an extraction unit 106 that extracts information from the network packet according to the setting in the system simulation apparatus. It was decided to consist of.

FIG. 20 is an example of a diagram for explaining the packet extraction data input time to the processor unit calculation hardware according to this embodiment.
As an example, the input time of bus I / O information for 1000 processor modules is shown.

FIG. 21 is an example of a diagram for explaining the packet input time to the processor unit calculation unit according to the conventional example.

In this embodiment, the time taken to input one network packet by the packet extraction part selection unit 103, the packet extraction setting input unit 104, and the network packet information extraction unit 106 is reduced to 1/5.

That is, the network information transmission time, which took about 10000 cycles in the conventional example, is reduced to about 1/5 of 2000 cycles in the system simulation apparatus according to this embodiment.

Furthermore, the system simulation evaluation uses about 1 million packets for evaluation.
That is, since the above transmission time is further accumulated over 1 million times, the effect of reducing the amount of communication to the processor unit calculation hardware obtained with respect to the conventional example can be obtained.

As described above, the interface speed between the network simulation unit 105 and the processor unit calculation unit is improved, and the hardware acceleration division of the processor unit calculation unit is realized, thereby improving the speed of the system simulation device.

As described above, this embodiment enables the hardware division of the processor unit calculation unit by improving the interface speed between the network simulation unit 105 and the processor unit calculation unit hardware.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

Also, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

DESCRIPTION OF SYMBOLS 100 System simulation apparatus 101,501 System configuration model definition part 102,502 Simulation parameter input part 103 Packet extraction part selection part 104 Packet extraction setting input part 105,505 Network simulation part 106 Network packet information extraction part 107,507 Processor

unit calculation part

108, 508 Performance display unit 200 GUI (graphical user interface) of system configuration model definition unit
201 Data generator module 202 Transmission path module 203 Switch module 205 Processor module 300

GUI dialog

401, 402, 403, 404, 405, 406, 410, 411, 420, 421, 430, 440, 441 of the packet extraction

part selection unit

103, 442, 443, 444 Individual flow explaining processing of system simulation apparatus 500 Conventional

system simulation apparatus

601, 602, 603, 604, 610, 611, 621, 630, 640, 641, 642, 643, 644 Conventional system simulation Individual flow 801 explaining the processing of the device Network packet input interface 802 Packet field selection unit 803 Processor unit calculation unit information generation unit 901 Network packet 1100 Processor Model 1101 network interface 1102 memory 1103 processors share bus 1104 CPU core
1200 processor unit calculator (processor shared bus probability calculation model)
1201 Processor unit calculation data 1202 Bus busy state 1203 Bus valid / invalid switching unit 1204 Service time calculation unit (processor shared bus probability calculation model)
1205 Bus availability 1300 Processor unit calculator (real-time calculation model)
1301 Processor unit calculation data 1302 Bus busy state 1303 Standard service time grant unit 1304 Standard service time storage unit 1305 Packet size service time calculation unit 1306 Service jitter storage unit 1307 Service time calculation unit (real-time evaluation model)
1400 Example of GUI Dialog of System Evaluation Content Selection Unit 1500 System Simulation Device 1501 according to Embodiment 5 Processor Unit Calculation Unit Operation Content Selection Unit 1502 Processor Unit Calculation Unit Operation Content Setting Input Unit 1501 Processor Unit Calculation Unit GUI of Operation Content Selection Unit Dialog Example 1600 System Simulation Device 1609 According to Embodiment 6 Packet Data Storage Unit 1610 Buffer 1611 Packet Data Response Unit 1700 System Simulation Device 1706 According to Embodiment 7 First Network Packet Information Extraction Unit 1707 Second Network Packet Information Extraction Unit 1708 Nth network packet information extraction unit 1709 first processor unit calculation unit 1710 second processor unit calculation unit 1711 nth processor unit Calculation unit 1900 System simulation apparatus 1907 according to the eighth embodiment Processor unit calculation hardware unit

Claims

A system configuration model definition section that defines the configuration of the system for simulation;
A network simulation unit for constructing a system defined by the system configuration model definition unit;
A processor unit calculation unit for performing simulation calculation of a system constructed by the network simulation unit;
A performance display for displaying system simulation calculation results;
A system simulation apparatus comprising:
The defined system configuration model is converted into configuration information of the network simulation unit, and the configuration information is input to the network simulation unit and converted into configuration information of the processor unit calculation unit. A simulation parameter input unit that inputs the processor unit calculation unit,
Extracting specific information from the network packet, and inputting to the processor unit calculation unit network packet information extraction unit,
A packet extraction part selection unit for selecting a part to be extracted from a network packet in the network packet information extraction unit;
A packet extraction setting input unit that inputs information selected by the packet extraction part selection unit to the network packet information extraction unit and the processor unit calculation unit;
Using the information selected by the packet extraction part selection unit, the network packet information extraction unit extracts information selected from the network packet, and performs simulation calculation using the information extracted by the processor unit calculation unit A system simulation apparatus characterized by that.
The system simulation apparatus according to claim 1,
As the processor unit calculation unit, a processor unit calculation unit (processor shared bus) including processor unit calculation data, a bus busy state, a bus valid / invalid switching unit, a service time calculation unit (processor shared bus probability calculation model), and a bus availability rate A system simulation apparatus having a probability calculation model).
The system simulation apparatus according to claim 1,
As the processor unit calculation unit, processor unit calculation data, bus busy state, standard service time grant unit, standard service time storage unit, packet size service time calculation unit, service jitter storage unit, service time calculation unit (real-time evaluation model), A system simulation apparatus comprising a processor unit calculation unit (real-time evaluation model).
The system simulation apparatus according to claim 1,
A system evaluation content selection unit as the packet extraction part selection unit,
A system evaluation content setting input unit as the packet extraction setting input unit,
A system simulation apparatus in which a system simulation apparatus automatically completes information extraction selection of a network packet and parameter setting of a processor unit calculation unit by selecting an arbitrary system evaluation content.
The system simulation apparatus according to claim 1,
As the packet extraction part selection unit, a processor unit calculation unit for selecting calculation content to be performed by the processor unit calculation unit, a calculation content selection unit,
As the packet extraction setting input unit, a network packet information extraction unit and a processor unit calculation unit automatically convert into necessary parameters, and a processor unit calculation unit that inputs to each part has a calculation content setting input unit,
By selecting the calculation contents in any processor unit calculation unit,
A system simulation apparatus, wherein the system simulation apparatus automatically completes information extraction selection of a network packet and parameter setting of a processor unit calculation unit.
The system simulation apparatus according to claim 1,
The system simulation apparatus has a packet data storage unit, a buffer, and a packet data response unit,
A system simulation apparatus that performs bidirectional processing in which a processing result by a processor unit calculation unit is reused in a network simulation unit.
The system simulation apparatus according to claim 1,
A system simulation apparatus comprising a first processor unit calculator, a second processor unit calculator, and an nth processor unit calculator as the processor unit calculator.
The system simulation apparatus according to claim 1,
A system simulation apparatus comprising processor unit calculation hardware as the processor unit calculation unit.
The system simulation apparatus according to claim 1,
A system simulation apparatus having a user setting input screen, wherein a system configuration model definition setting and a packet extraction part selection setting can be input on the user setting input screen.