WO2013107058A1

WO2013107058A1 - Method and apparatus for providing uplink control signaling

Info

Publication number: WO2013107058A1
Application number: PCT/CN2012/070705
Authority: WO
Inventors: Shuang TAN; Erlin Zeng; Chunyan Gao; Jari Mattila
Original assignee: Renesas Mobile Corporation
Priority date: 2012-01-21
Filing date: 2012-01-21
Publication date: 2013-07-25

Abstract

A method, apparatus and computer program product are provided to provide improved uplink control signaling so as to reduce downlink throughput loss. In the context of a method, the acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits may be encoded utilizing two or more encoders. The number of encoders that are utilized is dependent on a number of bits to be encoded. The method may also rate match the encoded A/N bits and encoded CSI bits. At least one of the encoding and the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits. The method may also interleave the encoded A/N bits and the encoded CSI bits following the rate matching.

Description

METHOD AND APPARATUS FOR PROVIDING UPLINK CONTROL SIGNALING

TECHNOLOGICAL FIELD

[0001] An example embodiment of the present invention relates generally to uplink control signaling and, more particularly, to uplink control signaling that provides

acknowledgement/negative acknowledgement (A/N) and channel state information (CSI) bits.

BACKGROUND

[0002] In order to establish and maintain a downlink between an access point, such as a node B, an evolved node B (eNB), a base station or the like, uplink control signaling from the mobile terminal, such as user equipment, to the access point is provided. In at least some instances, such as in conjunction with the uplink control signaling for carrier aggregation, the uplink control signaling may include A N bits and CSI bits. However, in systems compliant with Release 10 of the Long Term Evolution (LTE) standard, at least some of the CSI bits may be dropped from the uplink transmission, thereby causing downlink throughput loss.

[0003] In order to determine the probability of CSI dropping in a time division duplexing (TDD) configuration, the scheme proposed by LTE Release 11 for frequency division duplexing (FDD) that utilizes hybrid automatic repeat request - acknowledgement (HARQ-ACK) and periodic CSI multiplexing in the physical uplink control channel (PUCCH) format 3 is utilized for up to ten A N bits in combination with the dual RM encoder design of LTE Release 10 that drops periodic CSI bits for more than 10 A/N bits. In this regard, in a scenario in which one component carrier needs to have one periodic CSI per twenty milliseconds to insure the relevance of the component carrier, one example implementation that utilizes TDD configuration 4 has three configured component carriers, has twelve A/N bits with spatial bundling and will have periodic CSI bits in three of the four uplink subframes, such that the A N bits will collide with the CSI bits and therefore cause the CSI bits to be dropped with a 75% probability. By way of comparison, a second example implementation that utilizes TDD configuration 4 has four configured component carriers, has sixteen A/N bits with spatial bundling and will have periodic CSI bits in every uplink subframe, such that the A N bits will collide with the CSI bits and therefore cause the CSI bits to be dropped with a 100% probability, that is, the A N bits always, collide with the CSI bits. By way of further comparison, a third example implementation that utilizes TDD configuration 5 has two configured component carriers, has eighteen A/N bits with spatial bundling and will have periodic CSI bits in three of the four uplink subframes, such that the A/N bits will collide with the CSI bits and therefore cause the CSI bits to be dropped with a 100% probability. As the above examples illustrate, the periodic CSI bits may be dropped relatively frequently for TDD, thereby leaving to downlink throughput loss.

[0004] The uplink control signaling that includes A/N bits and CSI bits may multiplex multiple A/N bits with periodic CSI bits in the PUCCH format 3. Two coding methods have been proposed for multiplexing the A N bits and the periodic CSI bits based on the LTE Release 10 dual RM encoder structure. One of these coding methods relies upon joint coding in which the HARQ-ACK bits, the CSI bits and the source routing (SR) bits are combined together as the input of a conventional PUCCH format 3. This joint coding is limited to 21 total bits and results in the A/N bits and the CSI bits having the same effective code rate.

[0005] The other coding method relies upon separate coding with the A/N bits and the CSI bits being fed to different RM encoders. More particularly, the A/N bits and the CSI bits may be separately encoded and rate matched. For example, a first Reed-Muller (RM) encoder may be utilized to encode the A/N bits and a second RM encoder may be utilized to encode the CSI bits. Following rate matching, the coded A/N bits and the coded CSI bits may be interleaved. The resulting combination of the coded A/N bits and the coded CSI bits may then be modulated, such as in accordance with quadrature phase shift keying (QPSK) and then mapped into two slots of a subframe in accordance with PUCCH format 3. While different code rates may be utilized in conjunction with the A/N bits and the CSI bits, neither the A/N bits nor the CSI bits may have more than 11 bits in accordance with this coding method.

[0006] Although each approach has some advantages, each approach also has certain disadvantages. In this regard, the joint coding of the A/N bits and the CSI bits provides more flexibility regarding the number of A/N bits and the number of CSI bits with the total number of bits being limited to 21 bits in comparison to the separate coding technique which limits each of the A/N bits and the CSI bits to 11 bits. However, the separate coding technique can more readily take into account the different bit error rates (BER) and block error rates (BLER) of the A/N bits, e.g., 10^"3, and CSI bits, e.g., 10^"2, while the joint coding technique would result in the A/N bits and the CSI bits having the same BER/BLER. Thus, while the joint coding and separate coding techniques have advantages, both joint coding and separate coding have disadvantages in regard to resource efficiency and flexibility that, in combination with the limited capacity of PUCCH format 3, may lead to CSI dropping, A/N bit dropping or bundling which may, in turn, lead to downlink throughput loss. BRIEF SUMMARY

[0007] A method, apparatus and computer program product are therefore provided according to an example embodiment that may provide improved uplink control signaling so as to reduce downlink throughput loss. In this regard, a method, apparatus and computer program product may be provided in accordance with an example embodiment in order to apply separate coding rates to the A/N bits and the CSI bits to take into account the different performance requirements, while also loosening the respective payload size limitations imposed by the overall payload capacity of PUCCH format 3. Additionally, the method, apparatus and computer program product may dynamically determine the number of encoders to be utilized based upon the number of bits to be encoded, thereby permitting adaptation as the number of A N bits and CSI bits change from subframe to subframe. As such, the method, apparatus and computer program product of an example embodiment may provide both resource efficiency and flexibility so as to provide improved uplink control signaling.

[0008] In one embodiment, a method is provided that includes encoding

acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders. The number of encoders that are utilized is dependent on a number of bits to be encoded. The method of this embodiment also rate matches encoded A/N bits and encoded CSI bits. At least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits. The method of this embodiment also interleaves the encoded A N bits and the encoded CSI bits following the rate matching.

[0009] In another embodiment, an apparatus is provided that includes at least one processor and at least one memory including computer program code with the at least one memory and the computer program code being configured to, with the processor, cause the apparatus to at least encode acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders. The number of encoders that are utilized is dependent on a number of bits to be encoded. The at least one memory and the computer program code of this embodiment are also configured to, with the processor, cause the apparatus to rate match encoded A/N bits and encoded CSI bits and to interleave the encoded A/N bits and the encoded CSI bits following the rate matching. At least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A N bits and a coding rate of the CSI bits.

[0010] In a further embodiment, an apparatus is provided that includes means for encoding acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders. The number of encoders that are utilized is dependent on a number of bits to be encoded. The apparatus of this embodiment also includes means for rate matching encoded A/N bits and encoded CSI bits. At least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits. The apparatus of this embodiment also includes means for interleaving the encoded A/N bits and the encoded CSI bits following the rate matching.

[0011] In yet another embodiment, a computer program product is provided that includes at least one non-transitory computer-readable storage medium having computer-readable program instructions stored therein with the computer-readable program instructions including program instructions configured to encode acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders. The number of encoders that are utilized is dependent on a number of bits to be encoded. The computer-readable program instructions of this embodiment also include program instructions configured to rate match encoded A/N bits and encoded CSI bits and program instructions configured to interleave the encoded A N bits and the encoded CSI bits following the rate matching. At least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

[0012] In one embodiment, a method is provided that includes de-interleaving encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits. The method of this embodiment also includes rate matching the encoded A/N bits and the encoded CSI bits and decoding A/N bits and CSI bits utilizing two or more decoders. The number of decoders that are utilized is dependent on a number of bits to be decoded. At least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

[0013] In another embodiment, an apparatus is provided that includes at least one processor and at least one memory including computer program code with the at least one memory and the computer program code being configured to, with the processor, cause the apparatus to at least de-interleave encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits. The at least one memory and the computer program code of this embodiment are also configured to, with the processor, cause the apparatus to rate match the encoded A/N bits and the encoded CSI bits and to decode A/N bits and CSI bits utilizing two or more decoders. The number of decoders that are utilized is dependent on a number of bits to be decoded. At least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

[0014] In a further embodiment, an apparatus is provided that includes means for de- interleaving encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits. The apparatus of this embodiment also includes means for rate matching the encoded A N bits and the encoded CSI bits and means for decoding A N bits and CSI bits utilizing two or more decoders. The number of decoders that are utilized is dependent on a number of bits to be decoded. At least one of the decoding and the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A N bits or a coding rate of the CSI bits.

[0015] In yet another embodiment, a computer program product is provided that includes at least one non-transitory computer-readable storage medium having computer-readable program instructions stored therein with the computer-readable program instructions including program instructions configured to de-interleave encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits. The computer-readable program instructions of this embodiment also include program instructions configured to rate match the encoded A N bits and the encoded CSI bits and program instructions configured to decode A/N bits and CSI bits utilizing two or more decoders. The number of decoders that are utilized is dependent on a number of bits to be decoded. At least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Having thus described certain embodiments of the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0017] Figure 1 is a schematic representation of a system in which an uplink may be established between mobile terminal and a network entity, such as an access point, in accordance with an example embodiment of the present invention;

[0018] Figure 2 is a block diagram of an apparatus that may be specifically configured to perform the operations of an example embodiment of the present invention;

[0019] Figure 3 is a flow chart illustrating the operations performed from the perspective of an encoding apparatus, such as mobile terminal, in accordance with one embodiment of the present invention;

[0020] Figure 4 is a block diagram illustrating the coding and interleaving of A/N bits and CSI bits in accordance with one example of the operations of Figure 2;

[0021] Figure 5 is a block diagram illustrating the coding and interleaving of A N bits and CSI bits in accordance with another example of the operations of Figure 2;

[0022] Figure 6 is a flow chart illustrating the operations performed from the perspective of a decoding apparatus, such as a network entity, e.g., an access point, in accordance with one embodiment of the present invention;

[0023] Figure 7 is a block diagram illustrating the decoding and de-interleaving of A/N bits and CSI bits in accordance with one example of the operations of Figure 6; and

[0024] Figure 8 is a block diagram illustrating the decoding and de-interleaving of A N bits and CSI bits in accordance with another example of the operations of Figure 6.

DETAILED DESCRIPTION

[0025] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the inventions are shown. Indeed, these inventions may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.

[0026] As used in this application, the term "circuitry" refers to all of the following:

(a)hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry) and (b) to combinations of circuits and software (and/or firmware), such as (as applicable): (i) to a combination of processor(s) or (ii) to portions of processor(s)/software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and

(c) to circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that

require software or firmware for operation, even if the software or firmware is not

physically present.

[0027] This definition of "circuitry" applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term "circuitry" would also cover an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. The term "circuitry" would also cover, for example and if applicable to the particular claim element, a baseband integrated circuit or application specific integrated circuit for a mobile phone or a similar integrated circuit in server, a cellular network device, or other network device.

[0028] In accordance with example embodiments of the present invention, a technique for providing uplink control signaling, such as to provide acknowledgement/negative

acknowledgement (A/N) and channel state information (CSI) bits as well as source routing (SR) bits for carrier aggregation or other purposes is provided. Referring now to Figure 1 , a system that supports communications between a mobile terminal 10 and a network 14, such as an LTE network, an LTE-Advanced (LTE-A) network, a Global Systems for Mobile communications (GSM) network, a Code Division Multiple Access (CDMA) network, e.g., a Wideband CDMA (WCDMA) network, a CDMA2000 network or the like, a General Packet Radio Service (GPRS) network or other type of network, via an access point 12 is shown. Various types of mobile terminals may be employed including, for example, a mobile communication device such as, for example, a mobile telephone, portable digital assistant (PDA), pager, laptop computer, or any of numerous other hand held or portable communication devices, computation devices, content generation devices, content consumption devices, or combinations thereof. Regardless of the type of mobile terminal, the mobile terminal may communicate with the network via an access point, such as a Node B, an eNB, a base station, a relay node or other type of access point.

[0029] The communications between the mobile terminal 10 and the access point 12 may include transmissions via an uplink and a downlink that are established between the mobile terminal and the access point. Uplink control signaling including A/N bits and CSI bits may be provided via the uplink which, among other functions, may assist in the configuration of the downlink. By providing for improved uplink control signaling in accordance with an example embodiment of the present invention, the extent to which the CSI bits are dropped may be reduced which may, in turn, reduce the downlink throughput loss.

[0030] The mobile terminal 10 and the access point 12 may implement example

embodiments of the method, apparatus and computer program product in order to provide for improved uplink control signaling. In this regard, the mobile terminal 10 and a network entity, such as the access point, may each embody or otherwise be associated with an apparatus 20 that is generally depicted in Figure 2 and that may be configured in accordance with an example embodiment of the present invention as described below, such as in conjunction with Figure 3 from the perspective of the mobile terminal and Figure 8 from the perspective of the access point. However, it should be noted that the components, devices or elements described below may not be mandatory and thus some may be omitted in certain embodiments. Additionally, some embodiments may include further or different components, devices or elements beyond those shown and described herein.

[0031] As shown in Figure 2, the apparatus 20 may include or otherwise be in

communication with a processing system including, for example, processing circuitry that is configurable to perform actions in accordance with example embodiments described herein. The processing circuitry may be configured to perform data processing, application execution and/or other processing and management services according to an example embodiment of the present invention. In some embodiments, the apparatus or the processing circuitry may be embodied as a chip or chip set. In other words, the apparatus or the processing circuitry may comprise one or more physical packages (e.g., chips) including materials, components and/or wires on a structural assembly (e.g., a baseboard). The structural assembly may provide physical strength,

conservation of size, and/or limitation of electrical interaction for component circuitry included thereon. The apparatus or the processing circuitry may therefore, in some cases, be configured to implement an embodiment of the present invention on a single chip or as a single "system on a chip." As such, in some cases, a chip or chipset may constitute means for performing one or more o erations for providing the functionalities described herein.

[0032] In an example embodiment, the processing circuitry may include a processor 22 and memory 24 that may be in communication with or otherwise control a communication interface 26 and, in some cases in which the apparatus is embodied by the mobile terminal 10, a user interface 28. As such, the processing circuitry may be embodied as a circuit chip (e.g., an integrated circuit chip) configured (e.g., with hardware, software or a combination of hardware and software) to perform operations described herein. However, in some embodiments taken in the context of the mobile terminal or the access point 12, the processing circuitry may be embodied as a portion of mobile terminal or the access point.

[0033] The user interface 28 (if implemented in embodiments of the apparatus 20 embodied by the mobile terminal 10) may be in communication with the processing circuitry to receive an indication of a user input at the user interface and/or to provide an audible, visual, mechanical or other output to the user. As such, the user interface may include, for example, a keyboard, a mouse, a joystick, a display, a touch screen, a microphone, a speaker, and/or other input/output mechanisms. In one embodiment, the user interface includes user interface circuitry configured to facilitate at least some functions of the user equipment by receiving user input and providing output.

[0034] The communication interface 26 may include one or more interface mechanisms for enabling communication with other devices and/or networks. In some cases, the communication interface may be any means such as a device or circuitry embodied in either hardware, or a combination of hardware and software that is configured to receive and/or transmit data from/to a network 14 and/or any other device or module in communication with the processing circuitry, such as between the mobile terminal 10 and the access point 12. In this regard, the

communication interface may include, for example, an antenna (or multiple antennas) and supporting hardware and/or software for enabling communications with a wireless

communication network and/or a communication modem or other hardware/software for supporting communication via cable, digital subscriber line (DSL), universal serial bus (USB), Ethernet or other methods. [0035] In an example embodiment, the memory 24 may include one or more non-transitory memory devices such as, for example, volatile and/or non-volatile memory that may be either fixed or removable. The memory may be configured to store information, data, applications, instructions or the like for enabling the apparatus 20 to carry out various functions in accordance with example embodiments of the present invention. For example, the memory could be configured to buffer input data for processing by the processor 22. Additionally or alternatively, the memory could be configured to store instructions for execution by the processor. As yet another alternative, the memory may include one of a plurality of databases that may store a variety of files, contents or data sets. Among the contents of the memory, applications may be stored for execution by the processor in order to carry out the functionality associated with each respective application. In some cases, the memory may be in communication with the processor via a bus for passing information among components of the apparatus.

[0036] The processor 22 may be embodied in a number of different ways. For example, the processor may be embodied as various processing means such as one or more of a

microprocessor or other processing element, a coprocessor, a controller or various other computing or processing devices including integrated circuits such as, for example, an ASIC (application specific integrated circuit), an FPGA (field programmable gate array), or the like. In an example embodiment, the processor may be configured to execute instructions stored in the memory 24 or otherwise accessible to the processor. As such, whether configured by hardware or by a combination of hardware and software, the processor may represent an entity (e.g., physically embodied in circuitry - in the form of processing circuitry) capable of performing operations according to embodiments of the present invention while configured accordingly. Thus, for example, when the processor is embodied as an ASIC, FPGA or the like, the processor may be specifically configured hardware for conducting the operations described herein.

Alternatively, as another example, when the processor is embodied as an executor of software instructions, the instructions may specifically configure the processor to perform the operations described herein.

[0037] Figures 3 and 6 are flowcharts illustrating the operations performed by a method, apparatus and computer program product, such as apparatus 20 of Figure 2, from the perspective of the mobile terminal 10 and a network entity, such as an access point 12, respectively, in accordance with one embodiment of the present invention. It will be understood that each block of the flowchart, and combinations of blocks in the flowchart, may be implemented by various means, such as hardware, firmware, processor, circuitry and/or other device associated with execution of software including one or more computer program instructions. For example, one or more of the procedures described above may be embodied by computer program instructions. In this regard, the computer program instructions which embody the procedures described above may be stored by a non-transitory memory 24 of an apparatus employing an embodiment of the present invention and executed by a processor 22 in the apparatus. As will be appreciated, any such computer program instructions may be loaded onto a computer or other programmable apparatus (e.g., hardware) to produce a machine, such that the resulting computer or other programmable apparatus provides for implementation of the functions specified in the flowchart blocks. These computer program instructions may also be stored in a non-transitory computer- readable storage memory that may direct a computer or other programmable apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage memory produce an article of manufacture, the execution of which implements the function specified in the flowchart blocks. The computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart blocks. As such, the operations of Figures 3 and 6, when executed, convert a computer or processing circuitry into a particular machine configured to perform an example embodiment of the present invention. Accordingly, the operations of Figures 3 and 6 define an algorithm for configuring a computer or processing circuitry, e.g., processor, to perform an example embodiment. In some cases, a general purpose computer may be provided with an instance of the processor which performs the algorithm of Figures 3 and 6 to transform the general purpose computer into a particular machine configured to perform an example embodiment,

[0038] Accordingly, blocks of the flowcharts support combinations of means for performing the specified functions and combinations of operations for performing the specified functions. It will also be understood that one or more blocks of the flowchart, and combinations of blocks in the flowchart, can be implemented by special purpose hardware-based computer systems which perform the specified functions, or combinations of special purpose hardware and computer instructions.

[0039] In some embodiments, certain ones of the operations above may be modified or further amplified as described below. It should be appreciated that each of the modifications, optional additions or amplifications below may be included with the operations above either alone or in combination with any others among the features described herein. Referring now to Figure 3, the operations performed by a method, apparatus and computer program product of an example embodiment are illustrated from the perspective of an apparatus 20 that may be embodied by or otherwise associated with the mobile terminal 10. In order to provide for improved uplink control signaling, the apparatus 20 embodied by the mobile terminal 10 may include means, such as the processor 22 or the like, for determining the number of encoders to be utilized in order to encode the A/N bits and the CSI bits based upon the number of bits to be encoded. See operation 30 of Figure 3. The apparatus 20 embodied by the mobile terminal 10 may also include means, such as the processor 22, a plurality of encoders or the like, for encoding A N bits and CSI bits utilizing two or more encoders, such as two or more Reed-Muller (RM) encoders. See operation 32 of Figure 3. The apparatus embodied by the mobile terminal may also include means, such as the processor, a plurality of encoders or the like, for rate matching the encoded A/N bits and the encoded CSI bits. See operation 34. As described below, at least one of the encoding of the A/N bits and the CSI bits or the rate matching of the encoded A N bits and the encoded CSI bits may be performed in accordance with a coding rate defined by a ratio γ of the coding rate of the A/N bits to the coding rate of the CSI bits. In other words, the coding rate ratio γ may be defined as: y = g * ^t cs_i^ ^^ne coding rate ratio γ may be a predefined ratio or may be configured by higher layer signaling between the access point 12 and the mobile terminal 10. As shown in operation 36 of Figure 3, the apparatus embodied by the mobile terminal may also include means, such as the processor, an interleaver or the like, for interleaving the encoded A/N bits and the encoded CSI bits following the rate matching.

[0040] In one embodiment, the apparatus 20 embodied by the mobile terminal 10 may also include means, such as the processor 22, a modulator or the like, for modulating, such as by quadrature phase shift key (QPSK) modulation, the encoded combination of the encoded A/N bits and the CSI bits following the interleaving. See operation 38 of Figure 3. Further, the apparatus embodied by the mobile terminal may include means, such as the processor or the like, for mapping the QPSK modulated bits into a plurality of slots of a subframe. See operation 39. As a result, a greater number of A/N bits and CSI bits may be transmitted via the uplink in the same subframe, thereby reducing instances of CSI dropping and correspondingly reducing the downlink throughput loss.

[0041] In one example, the A N bits and the CSI bits may be separately encoded as shown, for example, by the apparatus of Figure 4. Although the apparatus of Figure 4 may be embodied in various manners, the apparatus of Figure 4 including, for example, the converter 40, the plurality of encoders 42, the interleaver 44 and the modulator 46, may be embodied by the processor 22. Alternatively, the converter, the plurality of encoders, the interleaver and the modulator 46 may be discrete components configured to operate as described herein. Regardless of the configuration, the SR bits may be encoded with either the A/N bits or the CSI bits depending upon the number of A/N bits and CSI bits. In one example, in an instance in which the number of A/N bits equals a predefined number, such as 11, and the number of CSI bits is less than the predefined number, the SR bits may be encoded with the CSI bits. Otherwise, such as in an instance in which the number of A/N bits is less than the predefined number or in which the number of CSI bits equals 11, the SR bits may be encoded with the A/N bits. For purposes of illustration, but not of limitation, the SR bits are encoded with the A/N bits in the embodiment of Figure 4. In the following explanation of Figure 4, however, reference to the A/N bits includes both the A/N bits and the SR bits.

[0042] Prior to encoding the A/N and CSI bits, the number of A/N bits that may be transmitted and, therefore, the number of A/N bits that are to be encoded may be determined. In this regard, based upon the coding rate ratio γ, the apparatus 20, such as the processor 22, may define the number of virtual A/N bits represented by the A/N bits, the CSI bits and the SR bits in order to determine the maximum number of actual A/N bits that may be transmitted via the uplink. In this regard, each A/N bit may equal one virtual A/N bit, each CSI bit may equal γ virtual A/N bits and each SR bit may equal γ virtual A/N bits when the SR bit is encoded with the CSI bits but may equal one virtual A/N bit otherwise, such as in instances in which the SR bit is encoded with the A/N bits. The processor may then determine the total number of virtual A/N bits to be transmitted. In an instance in which the total number of virtual A/N bits exceeds a predefined number, such as 21 , A/N dropping or bundling may be applied until the number of virtual A/N bits is less than or equal the predefined number. [0043] Following any such A/N dropping or bundling and in an instance in which the number of A N bits exceeds a predefined number, such as 11, the A/N bits are divided by a converter 40 into a plurality, such as 2, information blocks. In an instance in which the number of A/N bits is m₀ and the number of SR bits is k, the A N and SR bits may be divided into two information blocks in an instance in which mo + k > 11 with the information blocks being provided as input to two RM encoders 42. In this embodiment, the number of bits provided as input to the two RM encoders is mi and m₂, wherein m_i = and m_s = ^\. Otherwise, if m₀

+ k < 11, only one RM encoder is required for the A N information blocks with m₁ = _Q + k and m₂ = 0. Upon receipt by the encoders, each of the information blocks is encoded and rate matched. Although two RM encoders are utilized to encode the A/N and SR bits in this embodiment, different numbers of RM encoders may be utilized in other embodiments with the number of RM encoders that are utilized being based upon the number of bits to be encoded. For example, the threshold for the number of virtual A/N bits above which there is A/N dropping or bundling may be raised such that additional A/N and SR bits are to be encoded, thereby requiring additional encoders.

[0044] As shown in Figure 4, the n CSI bits may be provided to a different encoder 42 for encoding and rate matching the CSI bits. Each of the encoders provides for separate rate matching in order to satisfy the coding rate ratio γ and to also satisfy the number of total coded bits in the predetermined format, such as the 48 total coded bits in the PUCCH format 3. In the embodiment of Figure 4, for example, the number of coded bits at the output of the three RM encoders and rate matchers are iV = [^J^ x 4s] for RM encoder 1, M_± = j^ ¹^ x (48 - A^f)] for

RM encoder 2 and , = 48 - Λ^Γ - M_t for RM encoder 3. By way of example in which the coding rate ratio of γ equals 0.5, the following table is provided to illustrate the number of the coded bits for the A/N bits and the SR bits and the number of coded bits for the CSI bits as well as the resulting coding rates for different numbers of A N, SR and CSI source bits.

3 2 0 36 12 0.083 0.167

3 6 0 24 24 0.125 0.25

3 1 1 0 17 31 0.176 0.355

7 2 0 42 6 0.167 0.333

7 6 0 34 14 0.206 0.429

7 11 0 27 21 0.259 0.524

1 1 2 0 44 4 0.25 0.5

1 1 6 0 38 10 0.289 0.6

11 11 0 32 16 0.344 0.688

16 2 0 23/22 3 0.348/0.364 0.667

16 6 0 20/20 8 0.4/0.4 0.75

16 1 1 0 18/18 12 0.444/0.444 0.917

21 2 1 23/23 2 0.435/0.435 1

21 6 3 21/20 7 0.429/0.45 0.857

21 1 1 5 18/18 12 0.444/0.444 0.917

[0045] As shown in the foregoing table, 16 A N bits and 11 CSI bits can be simultaneously transmitted in the same subframe in the worst case, thereby providing an improvement in uplink control signaling even in the worst case so as to reduce CSI dropping and the resulting downlink throughput loss.

[0046] Following the encoding and rate matching, the encoded CSI bits and the encoded A/N bits may be jointly interleaved by interleaver 44. Following the interleaving, the encoded combination of the encoded A/N bits and the encoded CSI bits may be modulated by a modulator 46, such as by being QPSK modulated, and the modulated bits may then be mapped into a plurality of slots 48 of a subframe, as also shown in the example embodiment of Figure 4.

[0047] Referring now to Figure 5, another example of a technique for encoding A/N bits and CSI bits using two or more encoders, e.g. two or more RM encoders, is provided. Although the apparatus of Figure 5 may be embodied in various manners, the apparatus of Figure 5 including, for example, the encoders 50, 54, the converter 52, the interleaver 56 and the modulator 58, may be embodied by the processor 22. Alternatively, the plurality of encoders, the converter, the interleaver and the modulator may be discrete components configured to operate as described herein. As described above, prior to the encoding of the A/N bits, the number of virtual A N bits may be determined with A/N dropping or bundling being applied if the number of virtual A/N bits exceeds a predetermined number of bits. Following any A N dropping or bundling, the A N bits are initially encoded by encoder 50, such as an RM encoder, in accordance with this embodiment using a coding rate of γ. As described above, the SR bits may be encoded either with the A/N bits or the CSI bits depending upon the number of A/N bits and CSI bits, but for purposes of the example depicted in Figure 5, the S bits will be encoded with the A N bits such that subsequent reference to the A N bits also includes the SR bits. The encoded A/N bits and the CSI bits may then be combined by a converter 52 which outputs a plurality of information blocks, each of which is provided to a respective encoder 54.

[0048J The number of encoders 54 may depend upon the number of bits output by the converter 52 and input to the encoders for encoding. For example, in instances in which each encoder may receive 1 1 bits, the number L of encoders may be defined as L = [^^0** *"]. The number of input bits may be ?ti_[ = ^: j? ^r÷*] for RM encoder 1 and _l = for the 1-

th RM encoder. In this embodiment, the number of output bits may be M_L = [^^y^ 4s] for

RM encoder and rate matcher 1 and M, = for the 1-th RM encoder

and rate matcher. The number of bits to be encoded may change frequently, such as on a subframe by subframe basis, such that the number of encoders may be determined on a correspondingly frequent basis. For example, in a TDD system with multiple component carriers, the number of A/N bits in one subframe depends on the subframe index (ranging from 0 to 9) and the number of component carriers that are scheduled. As such, the number of A/N bits may change subframe by subframe. Additionally, the number of CSI bits depends on the CSI feedback type with the payload size of different feedback types varying from 1 bit to 1 1 bits. As in the embodiment described in conjunction with Figure 4, the coded and rate matched bits from the plurality of encoders and rate matchers may then be interleaved by interleaver 56, modulated by a modulator 58, such as in accordance with QPSK modulation, and mapped into two slots 59 of a subframe, such as in accordance with PUCCH format 3.

[0049] Once mapped into the slots of a subframe, such as in accordance with the example embodiments of Figures 4 and 5, the encoded and rate matched A/N, CSI and S bits may be transmitted via the uplink from a mobile terminal 10 to an access point 12 in order to provide uplink control signaling. Upon receipt, the access point or other network entity may decode the control signals in order to determine the A/N bits, the CSI bits and the SR bits. By way of further explanation and with reference to operation 60 of Figure 6, for example, an apparatus 20 embodied by a network entity, such as the access point or the like, may include means, such as a processor 22, a demodulator or the like, for demodulating, such as in accordance with QPSK demodulation, the modulated representation of the encoded and rate matched A/N, CSI and SR bits upon receipt by the access point or other network entity and extraction from slots of the subframe. The apparatus embodied by the network entity may also include means, such as the processor, a de-interleaver or the like, for de-interleaving the encoded A/N bits and the encoded CSI bits following the demodulation. See operation 62. The apparatus embodied by the network entity may also include means, such as the processor or the like, for determining the number of decoders to be utilized in order to decode the encoded A N bits and the encoded CSI bits based upon the number of bits to be decoded. See operation 64. The apparatus embodied by the network entity, such as the access point or the like, of this embodiment may also include means, such as the processor, a decoder, a rate matcher or the like, for rate matching the encoded A/N bits and the encoded CSI bits. See operation 66. Further, the apparatus embodied by the network entity, such as the access point or the like, may include means, such as a processor, a decoder or the like, for decoding the A N bits and the CSI bits utilizing two or more decoders. See operation 68 of Figure 6. In this regard, the decoding and/or the rate matching may be performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits. Following the decoding, the apparatus embodied by the network entity, such as the access point or the like, may utilize the A/N bits, the CSI bits or the SR bits for appropriately configuring the downlink, thereby reducing downlink throughput loss.

[0050] By way of example, an apparatus 20 embodied by a network entity, such as an access point 12 or the like, may receive a control signaling that has been encoded in the manner described above in conjunction with the embodiment of Figure 4. In this regard, the modulated bits representative of the encoded combination of the A/N bits and the CSI bits may be extracted from the corresponding slots 69 of the subframe and may be demodulated by a demodulator 70, such as by QPSK demodulation. The resulting encoded combination of the A N bits and the CSI bits may be provided to a de-interleaver 72 embodied, for example, by the processor 22 in one embodiment. The de-interleaver may separate the encoded CSI bits from the encoded A/N bits and, in an instance in which the number of encoded A/N bits exceeds a predefined number, such as 11, may divide the encoded A/N bits into a plurality of information blocks, such as the two information blocks shown in Figure 7. The CSI bits may, in turn, be provided to a decoder 74, such as an RM decoder, for decoding the encoded CSI bits and for rate matching the decoded CSI bits. Correspondingly, each information block of encoded A/N bits may be provided to a respective decoder, such as an RM decoder, for decoding the A/N bits and for rate matching the A/N bits. The decoders may be embodied, for example, by the processor. Although the A/N bits are provided to two decoders in this embodiment, the number of decoders is dependent upon the number of bits to be decoded such that other embodiments may utilize additional decoders in an instance in which more A/N bits are to be decoded. The decoded A/N bits may then be combined, such as by a converter 76 embodied, for example, by the processor in order to produce the A/N bits as well as any SR bits encoded with the A/N bits. Although the demodulator, the de-interleaver, the decoders and the converter may be embodied by the processor, the demodulator, the de-interleaver, the decoders and the converter may be differently embodied, such as by being embodied as discrete components.

[0051] Another example of decoding in which the A N bits and the CSI bits have been encoded in accordance with the example embodiment of Figure 5 is shown in Figure 8. In this regard, the modulated bits representative of the encoded combination of the A/N bits and the CSI bits may be extracted from the corresponding slots 78 of the subframe and may be demodulated by a demodulatore 80, such as by QPSK demodulation, prior to be provided to a de-interleaver 82. The de-interleaver 82 may separate the encoded combination of the A/N bits and the CSI bits into a plurality of information blocks, each of which includes encoded A/N bits and encoded CSI bits. The information blocks are provided to a plurality of decoders 84, such as to each of a plurality of RM decoders. As described above, the number L of decoders is dependent upon the number of bits to be decoded such that other embodiments may utilize different numbers of decoders in an instance in which different numbers of bits are to be decoded. The encoded bits provided to a respective decoder are decoded and rate matched and the resulting output is provided to a converter 86 for separating the A N bits from a CSI bits. The A/N bits output by the converter are still encoded with a coding rate of γ. Thus, these bits are provided to another decoder 88, such as an RM decoder, for decoding the A/N bits as well as any SR bits that were encoded therewith. As described above, a processor 22 may embody the demodulator, the de- interleaver, the decoders and the converter, or the demodulator, de-interleaver, the decoders and the converter may be differently configured, such as by being embodied as discrete components. [0052] By providing additional A/N bits and CSI bits and by dynamically determining the number of encoders to be utilized based upon the number of bits to be encoded, the method, apparatus and computer program product of an example embodiment may provide improved control uplink signaling with reduced CSI dropping. As a result of the improved uplink control signaling, the downlink throughput loss may be correspondingly reduced.

[0053] Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

WHAT IS CLAIMED IS:

1. A method comprising:

encoding acknowledgement negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing at least two or more encoders, wherein a number of encoders that are utilized is dependent on a number of bits to be encoded;

rate matching encoded A/N bits and encoded CSI bits, wherein at least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A N bits and a coding rate of the CSI bits; and

interleaving the encoded A/N bits and the encoded CSI bits following the rate matching.

2. A method according to Claim 1 further comprising determining the number of encoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be encoded.

3. A method according to any one of Claims 1 or 2 wherein encoding the A/N bits and the CSI bits comprises separately encoding the A/N bits and the CSI bits, wherein rate matching comprises separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and wherein interleaving comprises jointly interleaving the encoded A N bits and the encoded CSI bits following the rate matching.

4. A method according to any one of Claims 1-3 further comprising dividing the A/N bits into a plurality of information blocks in an instance in which there are at least a predefined number of A N bits and providing each information block of A/N bits to a different respective encoder.

5. A method according to Claim 4 wherein dividing the A N bits comprises dividing the A/N bits into first and second information blocks and wherein providing each information block to a different respective encoder comprises providing the first and second information blocks of A/N bits to first and second encoders, respectively.

6. A method according to any one of Claims 1-5 further comprising: encoding one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

encoding one or more SR bits with the A N bits in an instance in which there are less than the predefined number of A N bits or at least the predefined number of CSI bits.

7. A method according to any one of Claims 1 or 2 wherein encoding the A/N bits and the CSI bits comprises:

encoding the A/N bits in accordance with the coding rate defined by the ratio γ; combining the encoded A/N bits and the CSI bits; and

encoding a combination of the encoded A/N bits and the CSI bits.

8. A method according to Claim 7 further comprising dividing the combination of the encoded A/N bits and the CSI bits into a plurality of information blocks and providing each information block of A/N bits to a different respective encoder.

9. A method according to any one of Claims 7 or 8 wherein encoding the A/N bits comprises encoding one or more source routing (SR) bits with the A/N bits.

10. A method according to any one of Claims 1-9 further comprising:

quadrature phase shift keying (QPSK) modulating the encoded combination of the encoded A/N bits and the CSI bits following interleaving; and

mapping QPSK bits into a plurality of slots of a subframe.

11. A method according to any one of Claims 1-10 further comprising:

determining a number of virtual A/N bits wherein each A/N bit equals one virtual

A/N bit, each CSI bit equals γ virtual A/N bits, each source routing (SR) bit that is encoded with the A/N bits equals one virtual A/N bit; and in an instance in which a total number of virtual A/N bits exceeds a predetermined threshold, applying A/N dropping or bundling prior to encoding the A/N bits.

12. An apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the processor, cause the apparatus to at least:

encode acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders, wherein a number of encoders that are utilized is dependent on a number of bits to be encoded;

rate match encoded A/N bits and encoded CSI bits, wherein at least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits; and

interleave the encoded A/N bits and the encoded CSI bits following the rate matching.

13. An apparatus according to Claim 12 wherein the at least one memory and the computer program code are further configured to, with the processor, cause the apparatus to determine the number of encoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be encoded.

14. An apparatus according to any one of Claims 12 or 13 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to encode the A/N bits and the CSI bits by separately encoding the A/N bits and the CSI bits, to rate match by separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and to interleave by jointly interleaving the encoded A/N bits and the encoded CSI bits following the rate matching.

15. An apparatus according to any one of Claims 12-14 wherein the at least one memory and the computer program code are also configured to, with the processor, cause the apparatus to divide the A/N bits into a plurality of information blocks in an instance in which there are at least a predefined number of A N bits and to provide each information block of A/N bits to a different respective encoder.

16. An apparatus according to Claim 15 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to divide the A N bits by dividing the A/N bits into first and second information blocks and to provide each information block to a different respective encoder by providing the first and second information blocks of A/N bits to first and second encoders, respectively.

17. An apparatus according to any one of Claims 12-16 wherein the at least one memory and the computer program code are also configured to, with the processor, cause the apparatus to:

encode one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

encode one or more SR bits with the A N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

18. An apparatus according to any one of Claims 12 or 13 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to encode the A N bits and the CSI bits by:

encoding the A/N bits in accordance with the coding rate defined by the ratio γ;

combining the encoded A/N bits and the CSI bits; and

encoding a combination of the encoded A/N bits and the CSI bits.

1 . An apparatus according to Claim 18 wherein the at least one memory and the computer program code are also configured to, with the processor, cause the apparatus to divide the combination of the encoded A N bits and the CSI bits into a plurality of information blocks and to provide each information block of A/N bits to a different respective encoder.

20. An apparatus according to any one of Claims 18 or 19 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to encode the A/N bits by encoding one or more source routing (SR) bits with the A/N bits.

21. An apparatus according to any one of Claims 12-20 wherein the at least one memory and the computer program code are also configured to, with the processor, cause the apparatus to:

quadrature phase shift keying (QPSK) modulate the encoded combination of the encoded A/N bits and the CSI bits following interleaving; and

map QPSK bits into a plurality of slots of a subframe.

22. An apparatus according to any one of Claims 12-21 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to:

determine a number of virtual A N bits wherein each A/N bit equals one virtual A/N bit, each CSI bit equals γ virtual A/N bits, each source routing (SR) bit that is encoded with the A N bits equals one virtual A/N bit; and

in an instance in which a total number of virtual A N bits exceeds a predetermined threshold, apply A N dropping or bundling prior to encoding the A/N bits.

23. An apparatus according to any one of Claims 12-22 wherein the apparatus is embodied by a mobile telephone.

24. An apparatus according to any one of Claims 12-23 further comprising user interface circuitry configured to facilitate user control of at least some functions of the mobile telephone through use of a display.

25. An apparatus comprising:

means for encoding acknowledgement/negative acknowledgement (A/N) bits and channel state information (CSI) bits utilizing two or more encoders, wherein a number of encoders that are utilized is dependent on a number of bits to be encoded; means for rate matching encoded A/N bits and encoded CSI bits, wherein at least one of the encoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits; and

means for interleaving the encoded A/N bits and the encoded CSI bits following the rate matching.

26. An apparatus according to Claim 25 further comprising means for determining the number of encoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be encoded.

27. An apparatus according to any one of Claims 25 or 26 wherein the means for encoding the A N bits and the CSI bits comprises means for separately encoding the A/N bits and the CSI bits, wherein the means for rate matching comprises means for separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio y, and wherein the means for interleaving comprises means for jointly interleaving the encoded A N bits and the encoded CSI bits following the rate matching.

28. An apparatus according to any one of Claims 25-27 further comprising means for dividing the A/N bits into a plurality of information blocks in an instance in which there are at least a predefined number of A/N bits and means for providing each information block of A N bits to a different respective encoder.

29. An apparatus according to Claim 28 wherein the means for dividing the A N bits comprises means for dividing the A/N bits into first and second information blocks and wherein the means for providing each information block to a different respective encoder comprises means for providing the first and second information blocks of A/N bits to first and second encoders, respectively.

30. An apparatus according to any one of Claims 25-29 further comprising: means for encoding one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

means for encoding one or more SR bits with the A N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

31. An apparatus according to any one of Claims 25 or 26 wherein the means for encoding the A/N bits and the CSI bits comprises:

means for encoding the A N bits in accordance with the coding rate defined by the ratio γ; means for combining the encoded A/N bits and the CSI bits; and

means for encoding a combination of the encoded A/N bits and the CSI bits.

32. An apparatus according to Claim 31 further comprising means for dividing the combination of the encoded A/N bits and the CSI bits into a plurality of information blocks and means for providing each information block of A/N bits to a different respective encoder.

33. An apparatus according to any one of Claims 31 or 32 wherein the means for encoding the A/N bits comprises means for encoding one or more source routing (SR) bits with the A/N bits.

34. An apparatus according to any one of Claims 25-33 further comprising:

means for quadrature phase shift keying (QPS ) modulating the encoded combination of the encoded A/N bits and the CSI bits following interleaving; and

means for mapping QPSK bits into a plurality of slots of a subframe.

35. An apparatus according to any one of Claims 25-34 further comprising:

means for determining a number of virtual A N bits wherein each A/N bit equals one virtual A/N bit, each CSI bit equals γ virtual A/N bits, each source routing (SR) bit that is encoded with the A N bits equals one virtual A/N bit; and

in an instance in which a total number of virtual A/N bits exceeds a predetermined threshold, means for applying A/N dropping or bundling prior to encoding the A/N bits.

36. A computer program product comprising at least one non-transitory computer- readable storage medium having computer-readable program instructions stored therein with the computer-readable program instructions comprising program instructions configured to:

37. A computer program product according to Claim 36 wherein the computer- readable program instructions further comprise program instructions configured to determine the number of encoders to be utilized based upon the number of bits, including A N bits and CSI bits, to be encoded.

38. A computer program product according to any one of Claims 36 or 37 wherein the program instructions configured to encode the A/N bits and the CSI bits comprise program instructions configured to separately encode the A/N bits and the CSI bits, wherein the program instructions configured to rate match comprise program instructions configured to separately rate match the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and wherein the program instructions configured to interleave comprise program instructions configured to jointly interleave the encoded A/N bits and the encoded CSI bits following the rate matching.

39. A computer program product according to any one of Claims 36-38 wherein the computer-readable program instructions further comprise program instructions configured to divide the A/N bits into a plurality of information blocks in an instance in which there are at least a predefined number of A/N bits and program instructions configured to provide each

information block of A/N bits to a different respective encoder.

40. A computer program product according to Claim 39 wherein the program instructions configured to divide the A/N bits comprise program instructions configured to divide the A/N bits into first and second information blocks and wherein the program instructions configured to provide each information block to a different respective encoder comprise program instructions configured to provide the first and second information blocks of A/N bits to first and second encoders, respectively.

41. A computer program product according to any one of Claims 36-40 wherein the computer-readable program instructions further comprise program instructions configured to: encode one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

42. A computer program product according to any one of Claims 36 or 37 wherein the program instructions configured to encode the A/N bits and the CSI bits comprise program instructions configured to:

encode the A/N bits in accordance with the coding rate defined by the ratio γ;

combine the encoded A/N bits and the CSI bits; and

encode a combination of the encoded A/N bits and the CSI bits.

43. A computer program product according to Claim 42 wherein the computer- readable program instructions further comprise program instructions configured to divide the combination of the encoded A/N bits and the CSI bits into a plurality of information blocks and program instructions configured to provide each information block of A N bits to a different respective encoder.

44. A computer program product according to any one of Claims 42 or 43 wherein the program instructions configured to encode the A/N bits comprise program instructions configured to encode one or more source routing (SR) bits with the A/N bits.

45. A computer program product according to any one of Claims 36-44 wherein the computer-readable program instructions further comprise program instructions configured to: quadrature phase shift keying (QPSK) modulate the encoded combination of the encoded A/N bits and the CSI bits following interleaving; and

map QPSK bits into a plurality of slots of a subframe.

46. A computer program product according to any one of Claims 36-45 wherein the computer-readable program instructions further comprise program instructions configured to: determine a number of virtual A/N bits wherein each A N bit equals one virtual A/N bit, each CSI bit equals γ virtual A/N bits, each source routing (SR) bit that is encoded with the A N bits equals one virtual A/N bit; and

in an instance in which a total number of virtual A/N bits exceeds a predetermined threshold, apply A/N dropping or bundling prior to encoding the A/N bits.

47. A method comprising:

de-interleaving encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits;

rate matching the encoded A/N bits and the encoded CSI bits; and

decoding A N bits and CSI bits utilizing two or more decoders, wherein a number of decoders that are utilized is dependent on a number of bits to be decoded, and wherein at least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

48. A method according to Claim 47 further comprising determining the number of decoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be decoded.

49. A method according to any one of Claims 47 or 48 wherein rate matching comprises separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and wherein decoding the A/N bits and the CSI bits comprises separately decoding the A/N bits and the CSI bits.

50. A method according to any one of Claims 47-49 wherein, in an instance in which the A/N bits are decoded by a plurality of decoders, the method further comprises combining the A/N bits output by the different respective decoders.

51. A method according to any one of Claims 47-50 further comprising:

decoding one or more source routing (S ) bits with the CSI bits in an instance in which there are at least a predefined number of A N bits and less than the predefined number of CSI bits; and

decoding one or more SR bits with the A/N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

52. A method according to any one of Claims 47 or 48 wherein decoding the A/N bits and the CSI bits comprises:

decoding a combination of the encoded A N bits and the CSI bits;

separating the encoded A/N bits and the CSI bits; and

decoding the A/N bits in accordance with the coding rate defined by the ratio γ.

53. A method according to Claim 52 wherein decoding the A/N bits comprises decoding one or more source routing (SR) bits with the A/N bits.

54. An apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the processor, cause the apparatus to at least:

de-interleave encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits;

rate match the encoded A/N bits and the encoded CSI bits; and decode A/N bits and CSI bits utilizing two or more decoders, wherein a number of decoders that are utilized is dependent on a number of bits to be decoded, and wherein at least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

55. An apparatus according to Claim 54 wherein the at least one memory and the computer program code are further configured to, with the processor, cause the apparatus to determine the number of decoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be decoded.

56. An apparatus according to any one of Claims 54 or 55 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to rate match by separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and to decode the A/N bits and the CSI bits by separately decoding the A/N bits and the CSI bits.

57. An apparatus according to any one of Claims 54-56 wherein, in an instance in which the A/N bits are decoded by a plurality of decoders, the at least one memory and the computer program code are also configured to, with the processor, cause the apparatus to combine the A/N bits output by the different respective decoders.

58. An apparatus according to any one of Claims 54-57 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to:

decode one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

decode one or more SR bits with the A/N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

59. An apparatus according to any one of Claims 54 or 55 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to decode the A/N bits and the CSI bits by:

decoding a combination of the encoded A/N bits and the CSI bits;

separating the encoded A/N bits and the CSI bits; and

60. An apparatus according to Claim 59 wherein the at least one memory and the computer program code are configured to, with the processor, cause the apparatus to decode the A/N bits by decoding one or more source routing (SR.) bits with the A/N bits.

61. An apparatus according to any one of Claims 54-60 wherein the apparatus is embodied by an evolved Node B.

62. An apparatus comprising:

means for de-interleaving encoded acknowledgement/negative acknowledgement (A/N) bits and encoded channel state information (CSI) bits;

means for rate matching the encoded A N bits and the encoded CSI bits; and

means for decoding A/N bits and CSI bits utilizing two or more decoders, wherein a number of decoders that are utilized is dependent on a number of bits to be decoded, and wherein at least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

63. An apparatus according to Claim 62 further comprising means for determining the number of decoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be decoded.

64. An apparatus according to any one of Claims 62 or 63 wherein the means for rate matching comprises means for separately rate matching the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and wherein the means for decoding the A/N bits and the CSI bits comprises means for separately decoding the A/N bits and the CSI bits.

65. An apparatus according to any one of Claims 62-64 wherein, in an instance in which the A/N bits are decoded by a plurality of decoders, the apparatus further comprises means for combining the A/N bits output by the different respective decoders.

66. An apparatus according to any one of Claims 62-65 further comprising:

means for decoding one or more source routing (SR.) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

means for decoding one or more SR bits with the A/N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

67. An apparatus according to any one of Claims 62 or 63 wherein the means for decoding the A N bits and the CSI bits comprises:

means for decoding a combination of the encoded A N bits and the CSI bits;

means for separating the encoded A/N bits and the CSI bits; and

means for decoding the A N bits in accordance with the coding rate defined by the ratio γ.

68. An apparatus according to Claim 67 wherein the means for decoding the A N bits comprises means for decoding one or more source routing (SR) bits with the A/N bits.

69. A computer program product comprising at least one non-transitory computer- readable storage medium having computer-readable program instructions stored therein with the computer-readable program instructions comprising program instructions configured to:

rate match the encoded A/N bits and the encoded CSI bits; and

decode A/N bits and CSI bits utilizing two or more decoders, wherein a number of decoders that are utilized is dependent on a number of bits to be decoded, and wherein at least one of the decoding or the rate matching is performed in accordance with a coding rate defined by a ratio γ of a coding rate of the A/N bits and a coding rate of the CSI bits.

70. A computer program product according to Claim 69 wherein the computer- readable program instructions further comprise program instructions configured to determine the number of decoders to be utilized based upon the number of bits, including A/N bits and CSI bits, to be decoded.

71. A computer program product according to any one of Claims 69 or 70 wherein the program instructions configured to rate match comprise program instructions configured to separately rate match the encoded A/N bits and the encoded CSI bits to satisfy the coding rate defined by the ratio γ, and wherein the program instructions configured to decode the A/N bits and the CSI bits comprise program instructions configured to separately decode the A N bits and the CSI bits.

72. A computer program product according to any one of Claims 69-71 wherein, in an instance in which the A N bits are decoded by a plurality of decoders, the computer-readable program instructions further comprise program instructions configured to combine the A/N bits output by the different respective decoders.

73. A computer program product according to any one of Claims 69-72 wherein the computer-readable program instructions further comprise program instructions configured to: decode one or more source routing (SR) bits with the CSI bits in an instance in which there are at least a predefined number of A/N bits and less than the predefined number of CSI bits; and

decode one or more SR bits with the A N bits in an instance in which there are less than the predefined number of A/N bits or at least the predefined number of CSI bits.

74. A computer program product according to any one of Claims 69 or 70 wherein program instructions configured to decode the A/N bits and the CSI bits comprise program instructions configured to:

decode a combination of the encoded A/N bits and the CSI bits;

separate the encoded A/N bits and the CSI bits; and decode the A/N bits in accordance with the coding rate defined by the ratio γ.

75. A computer program product according to Claim 74 wherein the program instructions configured to decode the A/N bits comprise program instructions configured to decode one or more source routing (SR) bits with the A N bits.