WO2013098580A1

WO2013098580A1 - Method and device for determining a delay profile of a code division multiple access transmission

Info

Publication number: WO2013098580A1
Application number: PCT/IB2011/003317
Authority: WO
Inventors: Pierre Didier; Arnaud RIGOLLE; Mickaël BOUYAUD
Original assignee: Renesas Mobile Corporation
Priority date: 2011-12-27
Filing date: 2011-12-27
Publication date: 2013-07-04

Abstract

For determining a delay profile of a code division multiple access transmission for which a signal is received by a device, the device is caused to provide the received signal in plural copies, and for each copy: applying a distinct delay to obtain a delayed signal; despreading the delayed signal to obtain despread symbols; applying a first coherent integration on the despread symbols to obtain integrated symbols; applying an inter-correlation computation on the integrated symbols to obtain complex symbols; and applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

Description

Method and device for determining a delay profile of a code division multiple access transmission

The present invention generally relates to determining a delay profile when receiving signals in a wireless telecommunications system.

In wireless telecommunications systems, a signal received by a receiver device is generally composed of several delayed echoes, or replicas, of a signal transmitted by a transmitter device due to reflections on physical obstacles. This phenomenon is referred to as multipath transmission. An estimation of the multipath delays shall then be performed by the receiver device in order to correctly demodulate the received signal.

Correlation between a pilot pattern known code sequence and the received signal allows defining a delay profile, in which peaks of energy correspond to the delays of the multipath transmission. The delay profile gives the intensity of a signal received via a multipath channel as a function of time delay. The time delay is the difference in travel time between multipath arrivals. The delay profile is generally represented by a graph, in which the abscissa is in units of time and the ordinate usually represents power in decibels. The delay profile allows extracting channel's characteristics such as the delay spread, which provides an indication of the multipath richness of the channel.

To determine the delay profile, the receiver device generates plural copies of the received signal. Each copy of the signal is then delayed by the receiver device by a distinct delay. A despreading operation consisting in a complex correlation is then applied by the receiver device to each delayed copy in case of CDMA {Code Division Multiple Access) transmissions.

The power of the despread signal is then typically computed as the sum of its squared real part and of its squared imaginary part. Power of the despread signal is finally integrated over time to mitigate the variations due to fast fading channel.

Integrating the power of the despread signal, referred to as non-coherent integration, does not improve the SNR {Signal-to-Noise Ratio) since integrated power contains both useful signal power but also noise power. Therefore, for a given delay, the resulting energy in the delay profile may be significantly increased due to the presence of noise, and such a situation may lead to an erroneous result of the multipath search. Therefore, the performance of the receiver device would be reduced.

It is desirable to improve the SNR {Signal-to-Noise Ratio) of the signals resulting from the correlation. In other words, it is desirable to improve the quality of the delay profile.

It is furthermore desirable to improve the quality of the delay profile in fast fading transmission conditions.

It is furthermore desirable to provide a delay profile determination approach allowing determining a frequency offset in the received signal.

It is desirable to reach at least one of the aforementioned objectives in the scope of CDMA communications systems, and more particularly in WCDMA {Wideband CDMA) communications systems.

To that end, the present invention concerns a method for determining a delay profile of a code division multiple access transmission for which a signal is received by a device, said method causing the device to perform providing the received signal in plural copies, and for each copy: applying a distinct delay to obtain a delayed signal; despreading the delayed signal to obtain despread symbols; applying a first coherent integration on the despread symbols to obtain integrated symbols. The method is further such that it causes the device to perform, for each copy: applying an inter-correlation computation on the integrated symbols to obtain complex symbols; and applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

Thus, using a delay profile based on complex signals allows to improve the SNR of the delay profile by applying the second coherent integration. Integration is said to be coherent since it is performed using the received signal itself, composed of useful signal plus noise signal that can be separated by integration, and not using the power of the received signal, the power operator used typically for non-coherent integration inducing an inextricable mixture of useful signal and noise. The quality of the delay profile is therefore improved.

The present invention also concerns a device for determining a delay profile of a code division multiple access transmission signal aiming at being received by the device, the device comprising circuitry causing the device to implement means for providing the received signal in plural copies, and for each copy: means for applying a distinct delay to obtain a delayed signal; means for despreading the delayed signal to obtain despread symbols; means for applying a first coherent integration on the despread symbols to obtain integrated symbols. The circuitry further causes, for each copy, the device to implement: means for applying an inter-correlation computation on the integrated symbols to obtain complex symbols; and means for applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

The present invention also concerns a device for determining a delay profile of a code division multiple access transmission signal aiming at being received by the device, wherein the device comprises circuitry causing the device to perform providing the received signal in plural copies and for each copy: applying a distinct delay to obtain a delayed signal; despreading the delayed signal to obtain despread symbols; applying a first coherent integration on the despread symbols to obtain integrated symbols; applying an inter-correlation computation on the integrated symbols to obtain complex symbols; and applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

The present invention also concerns a computer program that can be downloaded from a communication network and/or stored on a medium that can be read by a computer or processing device. This computer program comprises instructions for causing implementation of the aforementioned method, when said program is run by a processor.

The present invention also concerns information storage means, storing a computer program comprising a set of instructions causing implementation of the aforementioned method, when the stored information is read from said information storage means and run by a processor.

Since the features and advantages related to the device and to the computer program are identical to those already mentioned with regard to the corresponding aforementioned method, they are not repeated here.

The characteristics of the invention will emerge more clearly from a reading of the following description of an example of embodiment, said description being produced with reference to the accompanying drawings, among which:

Fig. 1 schematically represents a delay profile determination unit in a receiver device;

Fig. 2 schematically represents a frequency offset determination unit in a receiver device;

Fig. 3 schematically represents an architecture of a receiver device in which the present invention may be implemented;

Fig. 4 schematically represents an algorithm for determining a delay profile performed by the receiver device;

Fig. 5 schematically represents an algorithm for determining a frequency offset performed by the receiver device.

The present invention aims at being implemented in a CDMA communications system at least comprising a transmitter and a receiver.

Whereas the invention is more particularly described hereafter in the context of a WCDMA communication system, the same principles apply more generally in CDMA communications system.

Preferably, the receiver device is a mobile terminal, also referred to as user equipment (UE), and the transmitter device is a base station, a base transceiver station (BTS) or a Node B of a Universal Mobile Telecommunications System (UMTS). Alternatively, the receiver device may also be a modem device, which may be installed as part of a MS or UE, but may be also a separate module, which can be attached to various devices. It should be noted, that although the invention is described as a receiver device, due to the fact that the invention is needed in reception of signal, the device may, and likely will, include also transmitter functionalities. Thus, the device implementing the receiver functionality may be a receiver or a transceiver, having at least one receiving chain, and may generally be referred to as a device or a communication device.

Fig. 1 schematically represents a delay profile determination unit of the receiver device. The delay profile determination unit comprises:

- a signal receiver 110;

- a set of delay lines 120, 121, 122;

- a set of despreading units 130, 131, 132;

- a set of first coherent integration units 140, 141, 142;

- a set of delaying buffers 150, 151, 152;

- a set of combiners 160, 161, 162; and

- a set of second coherent integration units 170, 171, 172.

For illustrative purpose, only three elements are shown in the set of delay lines, in the set of despreading units, in the set of first coherent integration units, in the set of delaying buffers, in the set of combiners and in the set of second coherent integration units. The delay profile determination unit may comprise a different plurality of elements in these sets, keeping in mind that the sets however comprise a same number of elements.

The signal receiver 110 receives a WCDMA signal and provides this WCDMA signal to each delay lines 120, 121, 122. Plural copies of the WCDMA signal are therefore provided and such copies of the WCDMA signal are input to respective delay lines 120, 121, 122. The delay lines 120, 121, 122 apply a distinct delay τ to the WCDMA signal. The delays τ applied by the respective delay lines are comprised between a minimum delay value Tmi_n and a maximum delay value x_max.

Each delay line 120, 121, 122 is connected to a despreading unit 130, 131, 132 and provides to the concerned despreading unit a delayed WCDMA signal.

Each despreading unit 130, 131, 132 is connected to a first coherent integration unit 140, 141, 142 and provides to the concerned first coherent integration unit despread symbols D_n( ), which are defined as follows:

wherein: - R represents the received WCDMA signal;

- A represents the pilot pattern as used by the transmitter, which is known by the receiver device and more particularly by the delay profile determination unit;

- PN represents a pseudo-noise scrambling sequence;

- k represents a chip counter as used during the despreading operation;

- c represents the equivalent duration in chips of a despread symbol D_n( ), commonly referred to as spreading factor;

- n represents a despread symbol counter, each symbol having a unitary length equal to the symbol duration and referred to as Ts;

and wherein X^* represents the complex conjugate of X.

A chip is a pulse of a Direct-Sequence Spread Spectrum (DSSS) code, such as a pseudo-noise code sequence used in direct-sequence CDMA channel access techniques.

In a particular embodiment, the number c of chips equals 512, which allows compatibility with open- loop space time transmit diversity CPICH (Common Pilot Indicator CHannel) pilot pattern as defined by the specification 3GPP TS 25.211 "Physical channels and mapping of transport channels onto physical channels (FDD) ". In WCDMA FDD (Frequency Division Duplex) cellular systems, CPICH is a downlink channel broadcast by Node Bs with slowly varying power and of a known bit sequence.

Each first coherent integration unit 140, 141, 142 is connected to an inter- correlation computation unit composed by a delaying buffer 150, 151, 152 and a combiner 160, 161, 162. Each first coherent integration unit 140, 141, 142 provides to the concerned inter-correlation computation unit integrated symbols D'_m T), which are defined as follows:

D'_m( ) =— D_{M m+n}(r)

n=0

wherein:

- m represents a counter of integrated symbols, each one having a unitary length equal to M times the symbol duration (M. Ts);

- M represents a number of despread symbols on which the first coherent integration operation is applied, and M > 2; and

- n represents a symbol counter as used during the first coherent integration operation. In a particular embodiment, the number M of despread symbols equals 2, which allows accuracy in determining the delay profile even in fast varying channel conditions. In addition, the processing time period for determining the delay profile is shortened.

Each inter-correlation computation unit is connected to a second coherent integration unit 170, 171 , 172 and provides to the concerned second coherent integration unit complex symbols IQ_p ( ), which are defined according to two possible variants.

A first variant is expressed as follows:

/ρ^ (τ) = D'^* _m_₁ (_T) x D'_m (r)

wherein p represents a counter of integrated symbols, each one having a unitary length equal to 2.M times the symbol duration (2.M. Ts).

In a second variant, the complex symbols IQ_p ( ) are defined as follows:

^²⁾ (τ) = /QW ^* (T) = D'^ d) x D'^* _M (T)

Each delaying buffer 150, 151 , 152 is therefore used to store the symbol D'_m ( ) during one operation cycle, so as to allow the multiplication with the next symbol in sequence by the combiner 160, 161 , 162, one of them being conjugated.

Each second coherent integration unit 170, 171 , 172 provides complex symbols IQi' ( ), which are defined as follows:

^Ncoh ¹

p=0

wherein:

- the complex symbols lQ_p ( ) correspond equivalently either to IQ_p (τ) or /<¾²⁾ (τ);

- N_coh represents a number of complex symbols on which the second coherent integration operation is applied;

- p represents a counter as used during the second coherent integration; and

- / represents a counter of integrated symbols, each one having a unitary length equal to N_coh multiplied by 2.M times the symbol duration (2.M. N_coh. Ts).

The set of signals 180, 181 , 182 provided by the second coherent integration unit 170, 171 , 172 forms the delay profile. In other words, each signal 180, 181 , 182 represents a part of the delay profile, said part of the delay profile corresponding to the delay applied by the delay line 120, 121 , 122. The complex symbols IQ_p (τ) being computed as the complex multiplication of two successive integrated despread symbols D'^^ Cr) and D'_m ( ), one of them being conjugated, it can be noticed that:

- their magnitude, or complex modulus, is homogeneous to the power of integrated despread symbols; and

- their noise level is reduced and has a zero expectancy value as the result of the product of two uncorrected noise sequences.

It results in an increase of the SNR during the coherent integration performed by the second coherent integration unit 170, 171 , 172. It should be noted that such an increase of the SNR wouldn't have been achievable if the accumulation would have been performed on the basis of a power signal defined by \D'_m ( ) |², since the second integration would be no more coherent in this the signal power and also the noise power would then be integrated.

Fig. 2 schematically represents a frequency offset determination unit in the receiver device.

A frequency offset appears when the quartz driving the processing clock of the receiver device is misaligned with the quartz driving the processing clock of the transmitter device. It is desirable to detect and determine such a frequency offset, if any, in order to allow the receiver device to perform corrective actions to compensate such a misalignment.

The frequency offset determination unit comprises a peak detection unit 201 and a frequency offset computation unit 200.

The peak detection unit 201 receives the complex symbols IQ[ ( ) from the second coherent integration units 170, 171 , 172. The frequency offset computation unit 200 receives the complex symbols IQ_p ( ) from the combiners 160, 161 , 162.

The peak detection unit 201 detects at least one peak value in terms of magnitude in the complex symbols IQ[ ( ) forming the delay profile.

In a first embodiment, the peak detection unit 201 detects the maximum value in terms of magnitude among the complex symbols IQ[ ( ) forming the delay profile, and provides to the frequency offset computation unit 200 information representative of the delay τ corresponding to this detected maximum value. Then, the frequency offset computation unit 200 determines the frequency offset F₀ff as follows, with two variants according to whether IQ_p ( ) is computed based on

definition: F_s angle [ IQ_p (τ) ]

2π

and:

^Foff = + Foff if IQ_p ( ) = IQ ⁾ (T)

wherein:

- F_s represents the sampling frequency of the communications system;

- angle [z] function returns the phase angle - expressed in radians - of a complex value z; and

-

represents the frequency offset value with indeterminate sign.

Correct sign to deduce actual frequency offset value F₀ff depends on whether IQp^1*1 (τ) or IQ_p ²^ (τ) are used to define the complex symbols IQ_p (τ).

Therefore, the frequency offset is determined on the basis of the angle of the complex symbols IQ_p (τ) corresponding to the complex symbol lQ[ { ) having the maximum value in terms of magnitude among the complex symbols IQ[ ( ) forming the delay profile.

In a second embodiment, the peak detection unit 201 detects plural peak values among the complex symbols IQ[ ( ) forming the delay profile, and provides to the frequency offset computation unit 200 information representative of a set of selected delays { τ_£ } respectively corresponding to these peak values. Then, the frequency offset computation unit 200 determines the frequency offset F₀ff as follows, on the basis of the set of selected delay values { τ_£ } provided by the peak detection unit 201 :

_ F_S angle [∑i IQ_p (Ti ]

^F°ff - 7 ^x 2^

and:

^Foff = + Poⁱf^sf if iQ_P ( ) = iQi¹⁾ ( )

Therefore, the frequency offset is determined on the basis of the angle of the sum of the complex symbols IQ_p ( ) corresponding to the complex symbols lQ[ { ) having the detected peak values among the complex symbols IQ[ ( ) forming the delay profile. Thus, by determining the delay profile using the aforementioned inter- correlation computation, the frequency offset can be easily determined.

Fig. 3 schematically represents an architecture of a receiver device in which the present invention may be implemented.

According to the shown architecture, the receiver device comprises the following components interconnected by a communications bus 310: a processor, microprocessor, microcontroller or CPU {Central Processing Unit) 300; a RAM (Random-Access Memory) 301 ; a ROM (Read-Only Memory) 302; an SD (Secure Digital) card reader 303, or any other device adapted to read information stored on storage means; a communication interface 304.

The communication interface 304 allows the receiver device to wirelessly communicate with the transmitter device.

CPU 300 is capable of executing instructions loaded into RAM 301 from ROM 302 or from an external memory, such as an SD card. After the receiver device has been powered on, CPU 300 is capable of reading instructions from RAM 301 and executing these instructions. The instructions form one computer program that causes CPU 300 to perform some or all of the steps of the algorithms described hereafter with regard to Figs. 4 and 5.

Any and all steps of the algorithms described hereafter with regard to Figs. 4 and 5 may be implemented in software by execution of a set of instructions or program by a programmable computing machine, such as a PC (Personal Computer), a DSP (Digital Signal Processor) or a microcontroller; or else implemented in hardware by a machine or a dedicated component, such as an FPGA (Field- Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit).

In other words, the receiver device includes circuitry, or a device including circuitry, causing the receiver device to perform the steps of the algorithms described hereafter with regard to Figs. 4 and 5. Such a device including circuitry causing the receiver device to perform the steps of the algorithms described hereafter with regard to Figs. 4 and 5 may be an external device connectable to the receiver device Such receiver device may also be installed as part of another device. In example, this kind of installation would be useful when the receiver device is in form of a chip, a chipset, or a module. Alternatively, instead of being installed in or connected to a dedicated communication device, the receiver device according to the invention may provide communication capability to any suitable device, such as a computer device, a machine, in example, a vending machine, or a vehicle like a car or truck, where the device may be installed in or connected to for this purpose. The term circuitry refers either to hardware implementation, consisting in analogue and/or digital processing, or to a combination of hardware and software implementation, including instructions of computer program associated with memories and processor causing the processor to perform any and all steps of the algorithms described hereafter with regard to Figs. 4 and 5.

Fig. 4 schematically represents an algorithm for determining a delay profile performed by the receiver device. The steps of the algorithm shown in Fig. 4 are preferably reiterated for each symbol n received from the transmitter device during a transmission time period defined by N_coh.

In a step 400, the receiver device applies delays τ to a received WCDMA signal. The delays τ applied by the receiver device are comprised between a minimum delay value Tmin and a maximum delay value x_max. A set of delayed signals is therefore obtained by execution of the step 400.

In a following step 401 , the receiver device despreads the delayed signals obtained in the step 400. For each delayed signal, despread symbols D_n ( ) are then obtained, wherein the despread symbols D_n (τ) are defined as already mentioned with regard to Fig. 1.

In a following step 402, the receiver device performs a first coherent integration on each sequence of despread symbols D_n ( ). For each sequence of despread symbols D_n ( ), integrated symbols D'_m ( ) are then obtained, wherein the integrated symbols D'_m ( ) are defined as already mentioned with regard to Fig. 1.

In a following step 403 , the receiver device performs an inter-correlation computation on each sequence of integrated symbols D'_m ( ) . For each sequence of integrated symbols D'_m ( ), complex symbols IQ_p ( ) are then obtained, wherein the complex symbols IQ_p (τ) are defined as already mentioned with regard to Fig. 1.

In a following step 404, the receiver device performs a second coherent integration on each sequence of complex symbols IQ_p ( ). For each sequence of complex symbols IQ_p ( ), complex symbols IQi' ( ) are obtained, wherein the complex symbols IQ[ ( ) are defined as already mentioned with regard to Fig. 1.

The set of symbols IQ[ ( ) resulting from execution of the second coherent integration forms the delay profile. The steps 400 to 404 are preferably performed in parallel for the different values of the delay τ. The received WCDMA signal is then provided by the receiver device in plural copies in order to allow applying in parallel the various delays τ, and the subsequent despreading, integrations and inter-correlation operations, to each copy of the received WCDMA signal.

When the steps 400 to 404 are sequentially performed for the different values of the delay τ, the received WCDMA signal is stored in a storage unit and the receiver device provides copies of the received WCDMA signal when executing the steps 400 to 404 for each value of the delay τ. In other words, the received WCDMA signal is retrieved from the storage unit, and a copy is therefore provided, for applying another delay τ.

Fig. 5 schematically represents an algorithm for determining a frequency offset performed by the receiver device. The steps of the algorithm shown in Fig. 5 are performed for at least one symbol / for each signal forming the delay profile. The steps of the algorithm shown in Fig. 5 are preferably reiterated for each symbol /.

In a step 501 , the receiver device selects at least one peak value in the complex symbols lQ[ { ) obtained in the step 404. In other words, the receiver device selects at least one peak value in terms of magnitude in the delay profile.

In a first embodiment, the receiver device detects the maximum value among the magnitude of the complex symbols IQ[ (τ) forming the delay profile.

In a second embodiment, the receiver device detects plural peak value among the magnitude of the complex symbols IQ[ ( ) forming the delay profile.

In a following step 502, the receiver device determines a frequency offset on the basis of the detected peak value(s).

According to the first embodiment, the receiver device determines the frequency offset on the basis of the angle of the complex symbols IQ_p (τ) corresponding to the complex symbol IQ[ ( ) having the maximum value among the complex symbols IQi' (τ) forming the delay profile, as already mentioned with regard to Fig. 2.

According to the second embodiment, the receiver device determines the frequency offset on the basis of the angle of the sum of the complex symbols IQ_p ( ) corresponding to the complex symbols lQ[ { ) having the detected peak values among the complex symbols IQ[ ( ) forming the delay profile, as already mentioned with regard to Fig. 2.

Claims

1. A method for determining a delay profile of a code division multiple access transmission for which a signal is received by a device, said method causing the device to perform:

- providing the received signal in plural copies;

and for each copy:

- applying a distinct delay to obtain a delayed signal;

- despreading the delayed signal to obtain despread symbols;

- applying a first coherent integration on the despread symbols to obtain integrated symbols;

characterized in that the method further causes the device to perform, for each copy:

- applying an inter-correlation computation on the integrated symbols to obtain comp lex symbo Is ; and

- applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

2. The method according to claim 1, characterized in that the first coherent integration is performed on two successive despread symbols.

3. The method according to any one of claims 1 and 2, characterized in that the inter-correlation computation is performed by multiplying a first integrated symbol and the complex conjugate of a second integrated symbol immediately following the first integrated symbol.

4. The method according to any one of claims 1 and 2, characterized in that the inter-correlation computation is performed by multiplying the complex conjugate of a first integrated symbol and a second integrated symbol immediately following the first integrated symbol.

5. The method according to any one of claims 1 to 4, characterized in that the device further performs: - detecting at least one peak value in terms of magnitude in the delay profile; and

- determining a frequency offset on the basis of the detected at least one peak value.

6. The method according to claim 5, characterized in that the frequency offset is determined on the basis of the angle of the complex symbols obtained by performing the inter-correlation computation and corresponding to the symbol having the maximum value in terms of magnitude among the symbols forming the delay profile.

7. The method according to claim 5, characterized in that the frequency offset is determined on the basis of the angle of the sum of complex symbols obtained by performing the inter-correlation computation and corresponding to symbols having peak values in terms of magnitude among the symbols forming the determined delay profile.

8. The method according to any one of claims 1 to 7, characterized in that the device is a user equipment of a wideband code division multiple access communications system.

9. A computer program characterized in that it comprises program code instructions which can be loaded in a programmable device for implementing the method according to any one of claims 1 to 8, when the program code instructions are run by the programmable device.

10. Information storage means, characterized in that they store a computer program comprising program code instructions which can be loaded in a programmable device for implementing the method according to any one of claims 1 to 8, when the program code instructions are run by the programmable device.

11. A device for determining a delay profile of a code division multiple access transmission signal aiming at being received by the device, the device comprising circuitry causing the device to implement:

- means for providing the received signal in plural copies; and for each copy:

- means for applying a distinct delay to obtain a delayed signal;

- means for despreading the delayed signal to obtain despread symbols;

- means for applying a first coherent integration on the despread symbols to obtain integrated symbols;

characterized in that the circuitry further causes, for each copy, the device to implement:

- means for applying an inter-correlation computation on the integrated symbols to obtain complex symbols; and

- means for applying a second coherent integration on the complex symbols to obtain a part of the delay profile, said part corresponding to the delay applied.

12. The device according to claim 11, characterized in that it comprises circuitry causing the device to implement means for applying the first coherent integration on two successive despread symbols.

13. The device according to any one of claims 11 and 12, characterized in that said means for applying the inter-correlation computation comprise means for multiplying a first integrated symbol and the complex conjugate of a second integrated symbol immediately following the first integrated symbol.

14. The device according to any one of claims 11 and 12, characterized in that said means for applying the inter-correlation computation comprise means for multiplying the complex conjugate of a first integrated symbol and a second integrated symbol immediately following the first integrated symbol.

15. The device according to any one of claims 11 to 14, characterized in that it comprises circuitry causing the device to implement:

- means for detecting at least one peak value in terms of magnitude in the delay profile; and

- means for determining a frequency offset on the basis of the detected at least one peak value.

16. The device according to claim 15, characterized in that it comprises circuitry causing the device to implement means for determining the frequency offset on the basis of the angle of the complex symbols obtained by implementing the means for applying the inter-correlation computation and corresponding to the symbol having the maximum value among the symbols forming the delay profile.

17. The device according to claim 15, characterized in that it comprises circuitry causing the device to implement means for determining the frequency offset on the basis of the angle of the sum of complex symbols obtained by implementing the means for applying the inter-correlation computation and corresponding to symbols having peak values among the symbols forming the delay profile.

18. The device according to any one of claims 1 to 17, characterized in that the device is a user equipment of a wideband code division multiple access communications system.