WO2013085290A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2013085290A1
WO2013085290A1 PCT/KR2012/010508 KR2012010508W WO2013085290A1 WO 2013085290 A1 WO2013085290 A1 WO 2013085290A1 KR 2012010508 W KR2012010508 W KR 2012010508W WO 2013085290 A1 WO2013085290 A1 WO 2013085290A1
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Prior art keywords
film
silicon
gas
substrate
etching
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PCT/KR2012/010508
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French (fr)
Korean (ko)
Inventor
권성수
한정민
권봉수
Original Assignee
주식회사 테스
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Priority claimed from KR1020110129975A external-priority patent/KR101305904B1/en
Priority claimed from KR1020120006844A external-priority patent/KR101256797B1/en
Application filed by 주식회사 테스 filed Critical 주식회사 테스
Publication of WO2013085290A1 publication Critical patent/WO2013085290A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method having a fine pattern and a semiconductor device manufacturing method that can achieve a high etching selectivity.
  • Semiconductor devices are used in almost all electronic devices. In particular, as electronic devices become more mobile and high performance, fine pattern formation is increasingly required.
  • semiconductor devices are manufactured by forming a pattern on a wafer by photolithography.
  • the photoresist pattern is exposed and developed to form a photoresist pattern, and the silicon film formed on the wafer is etched using the photoresist pattern to manufacture semiconductor devices by the silicon film.
  • the pattern formation by this photolithography process has a limit in the size. This is because it relates to the wavelength of the light source and the photoresist for reacting the photoresist film.
  • patterns have a minimum size of 10-20 nm or less. In the case of such a size, the formation of a pattern by a photographic process is a very technical situation.
  • TiN titanium nitride
  • the silicon (Si) etching method is a method of anisotropically etching gases such as hydrogen chloride (HCl), hydrogen bromide (HBr) in the RF plasma chamber, sulfur fluoride (SF 6 )
  • anisotropically etching gases such as hydrogen chloride (HCl), hydrogen bromide (HBr) in the RF plasma chamber, sulfur fluoride (SF 6 )
  • An isotropic etching method using a remote plasma source (RPS), an isotropic time using a mixture of nitric acid, hydrofluoric acid and acetic acid, and an anisotropic etching method using a KOH solution have been used.
  • the etching selectivity of each oxide layer is different. This is because the concentration of hydrogen and carbon of each oxide film type affect the liquid phase etch rate. Generally, the higher the concentration of hydrogen, the faster the etch rate in the liquid phase.
  • these methods may have a poor etching selectivity between amorphous silicon or polysilicon and a silicon oxide film or a titanium nitride (TiN) pattern at the time of etching the silicon film, thereby causing a defect in the titanium nitride pattern.
  • TiN titanium nitride
  • an object of the present invention is to provide a method of manufacturing a semiconductor device having a finer pattern than the minimum pattern that can be formed by photolithography.
  • the problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device that can achieve a high etching selectivity.
  • a semiconductor device manufacturing method for achieving the above object, forming a silicon layer on a substrate, forming a photoresist film on the silicon layer, and exposing the photoresist film Developing the exposed photoresist film, forming a pattern on the silicon layer using the developed photoresist film as a mask, removing the photoresist film, forming an insulating film, And trimming the pattern formed on the silicon substrate.
  • the semiconductor device manufacturing method may further include removing a portion of the insulating film after the insulating film is formed to expose the pattern.
  • a silicon oxide film may be used as the insulating film.
  • the insulating film in the removing of a part of the insulating film, the insulating film may be removed by supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the insulating film.
  • HF hydrogen fluoride
  • NH 3 ammonia
  • the hydrogen fluoride (HF) gas and the ammonia (NH 3 ) gas may be removed.
  • the by-product may be removed by a heating method using a lamp.
  • the method may further include the step of removing the by-products by the heating method, the substrate is transferred to the cooling chamber to cool.
  • the pattern may be trimmed by supplying chlorine trifluoride (ClF 3 ) gas to the silicon substrate from which the insulating film is partially removed.
  • ClF 3 chlorine trifluoride
  • the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted.
  • chlorine trifluoride (ClF 3 ) gas may be trimmed by supplying 1 to 30 sccm, the nitrogen (N 2 ) gas at 100 to 1000 sccm.
  • the trimming may be performed under a pressure of 300 mtorr to 8 torr.
  • the trimming process may be continuously performed without breaking the vacuum state.
  • a method of fabricating a semiconductor device comprising: forming a titanium nitride (TiN) film on a substrate, patterning a titanium nitride (TiN) film, Forming a silicon film on a substrate on which patterned titanium nitride (TiN) is formed, and etching the silicon film using chlorine trifluoride (ClF 3 ) gas, and in the etching of the silicon film, the titanium nitride When (TiN) is exposed, the substrate is kept in the range of -76 to 70.
  • the substrate when the titanium nitride is not exposed, the substrate may be maintained within a range of 70 to 80.
  • the substrate may be transferred to a cooling chamber to lower the temperature of the substrate in the cooling chamber.
  • the method may further include removing a silicon oxide film naturally formed on the silicon film.
  • the removing of the silicon oxide film may include supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the silicon oxide film.
  • HF hydrogen fluoride
  • NH 3 ammonia
  • the removing of the silicon oxide film may include removing by-products generated by the reaction between the silicon oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas by a heating method using a lamp. It may further comprise a step.
  • HF hydrogen fluoride
  • NH 3 ammonia
  • the semiconductor device manufacturing method it is possible to manufacture a semiconductor device having a pattern finer than the minimum pattern that can be formed by photolithography.
  • the trimming step is a gas phase reaction, the selectivity between silicon and oxide film can be increased.
  • the trimming process can be continuously performed without breaking the vacuum state, thereby minimizing the variation of the process due to the naturally occurring oxide film.
  • an amorphous silicon film or a polysilicon film can be etched without being damaged by etching a titanium nitride (TiN) pattern.
  • the silicon film after removing the silicon oxide film formed naturally after forming the silicon film, the silicon film can be more easily etched.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing a result of performing a step of forming a silicon layer on the substrate shown in FIG. 1.
  • FIG. 3 is a schematic cross-sectional view showing a result of performing a step of forming the photoresist film shown in FIG.
  • FIG. 4 is a schematic cross-sectional view illustrating the step of exposing the photoresist film shown in FIG. 1.
  • FIG. 5 is a schematic cross-sectional view illustrating a result of performing the developing of the photoresist film shown in FIG. 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a result of performing a step of forming a pattern on the silicon layer illustrated in FIG. 1.
  • FIG. 7 is a schematic cross-sectional view illustrating a result of performing a step of removing the photoresist film shown in FIG. 1.
  • FIG. 8 is a schematic cross-sectional view showing the result of performing the step of forming the insulating film shown in FIG.
  • FIG. 9 is a schematic cross-sectional view illustrating a result of performing a step of partially removing the insulating film illustrated in FIG. 1.
  • FIG. 10 is a schematic cross-sectional view illustrating trimming the pattern illustrated in FIG. 1.
  • FIG. 11 is a graph illustrating an etching selectivity of polysilicon (poly-Si), silicon nitride (SiN), and oxide (oxide).
  • FIG. 12 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • FIG. 13 is a cross-sectional view illustrating an example of a substrate before forming the titanium nitride film illustrated in FIG. 12.
  • FIG. 14 is a cross-sectional view after the step of forming the titanium nitride film shown in FIG. 12 on the substrate shown in FIG.
  • FIG. 15 is a cross-sectional view after the step of patterning the titanium nitride film shown in FIG. 12.
  • FIG. 16 is a cross-sectional view after the step of forming the silicon film shown in FIG.
  • FIG. 17 is a cross-sectional view illustrating a process after removing the silicon oxide film illustrated in FIG. 12.
  • FIG. 18 is a cross-sectional view illustrating a step after etching the silicon film illustrated in FIG. 12.
  • FIG. 19 is a cross-sectional view of a contact plug formed on the barrier film illustrated in FIG. 18.
  • FIG. 20 is an SEM image illustrating etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 40.
  • FIG. 20 is an SEM image illustrating etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 40.
  • FIG. 21 is a photograph showing etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 60;
  • FIG. 22 is a photograph illustrating etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 80;
  • FIG. 23 is a cross-sectional view illustrating a form in which a titanium nitride pattern formed by patterning a titanium nitride film is formed only on a lower portion of an inside of a hole, and a silicon layer is formed thereon.
  • FIG. 24 is a cross-sectional view illustrating a silicon layer etched in FIG. 23.
  • FIG. 25 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed on a lower side of a hole and a side surface of a hole, and a silicon layer formed on the upper portion thereof.
  • FIG. 26 is a cross-sectional view illustrating a silicon layer etched in FIG. 25.
  • FIG. 27 is a cross-sectional view illustrating a titanium nitride pattern formed by patterning a titanium nitride film, a silicon nitride film formed on a lower side of a hole, and a silicon layer formed on a side of a hole.
  • FIG. 28 is a cross-sectional view illustrating a silicon layer etched in FIG. 27.
  • FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention
  • FIGS. 2 to 8 are schematic cross-sectional views showing results of performing each step in FIG. 1.
  • a silicon layer is formed on a substrate S on which an insulating film 101 is naturally formed in an oxygen or nitrogen atmosphere.
  • 102 is formed (step S110).
  • the silicon layer 102 may be formed of various silicon layers according to the required semiconductor device, such as crystalline silicon, microcrystalline silicon, amorphous silicon, and the like.
  • the silicon layer 102 may be formed to a thickness of about 1 micrometer, and may be formed by conventional chemical vapor deposition (CVD). In addition, the silicon layer 102 may be doped with an impurity to form a conductive layer.
  • CVD chemical vapor deposition
  • the photoresist film 103 may be formed to a thickness of, for example, 6500, and a spray type spin coater device for applying a photoresist through a nozzle while rotating the substrate S may be used. .
  • the photoresist film 103 formed on the silicon substrate is exposed using the mask M on which the pattern is formed (step S130). Thereby, light L is divided into the part 103a exposed by the pattern of the said mask M, and the part 103b covered by the mask M. As shown to FIG. The exposed portion 103a is chemically changed by light so that the two portions 103a and 103b have different chemical properties.
  • the exposed photoresist film is developed (step S140), and as shown in FIG. 6, a pattern is formed on the substrate using the same (step S150).
  • a mixture of carbon tetrachloride (CCl 4 ) and argon, a mixture of carbon tetrafluoride (CF 4 ) and oxygen, CF 3 Cl gas, a fluorocarbon compound, and a chlorine gas mixture may be used.
  • the remaining photoresist film 130a is removed through the strip process (step S160).
  • a mixture of monoethanolamine and dimethyl sulfoxide maintained at a temperature of about 10 to 40 degrees Celsius was used for about 300 seconds or less. The process can be carried out. Thereafter, washing may proceed.
  • an insulating film 104 is formed to insulate each electronic device included in the pattern formed on the silicon layer from each other (step S170).
  • a silicon oxide layer SiO 2
  • the insulating film (silicon oxide film) 104 covering the pattern constituted by the silicon pattern forming portion 102b then interferes with the trimming process to be performed. Therefore, it is necessary to remove the insulating film 104 covering the pattern composed of such a silicon pattern forming portion 102b.
  • a fine pattern is formed by trimming the thus formed pattern (step S190).
  • a source gas G1 such as hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the insulating film 104. can do.
  • the reaction mechanism at this time is as follows.
  • an oxide film and ammonium fluoride (NH 4 F) react on the substrate to form an ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ) as a condensation film, which can be removed by a post heat treatment. That is, in step S180 of removing the insulating film, a by-product generated by the reaction of the oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas [(NH 4 ) 2 SiF 6 (s) ] Can be removed.
  • the by-product [hexafluorosilicate (NH 4 ) 2 SiF 6 (s)] can be removed by a heating method using a lamp.
  • the reaction mechanism at this time is as follows.
  • the temperature of the wafer during heating by the lamp is 150C or more, so cooling of the substrate before subsequent trimming is necessary. To this end, it may be cooled for a long time (1-5 minutes) in the subsequent trimming process chamber, but this reduces the throughput. To this end, the proposed scheme can cool the substrate in the cooling chamber and proceed with subsequent trimming before the trimming process in the trimming chamber.
  • FIG. 10 is a schematic cross-sectional view illustrating trimming the pattern illustrated in FIG. 1 (S190).
  • a trimming process of removing the outer portion of the pattern is performed to microstructure the pattern formed of the silicon pattern forming part 102b.
  • Silicon (Si) can be etched by anisotropically etching gases such as hydrogen chloride (HCl) and hydrogen bromide (HBr) in an RF plasma chamber, and by using a remote plasma source such as silicon fluoride (SF 6 ).
  • anisotropically etching gases such as hydrogen chloride (HCl) and hydrogen bromide (HBr) in an RF plasma chamber
  • a remote plasma source such as silicon fluoride (SF 6 ).
  • the isotropic etching method through (RPS) the liquid phase etching method, isotropic time using a mixture of nitric acid, hydrofluoric acid and acetic acid, and anisotropic etching method using KOH solution can be considered.
  • the etching selectivity of each oxide layer is different. This is because the concentration of hydrogen and carbon of each oxide film type affect the liquid phase etch rate. Generally, the higher the concentration of hydrogen, the faster the etch rate in the liquid phase.
  • the method of adjusting the concentration of the solution in the silicon (Si) isotropic etching to minimize the amount of silicon etching during trimming can be examined. This is because when the silicon etching is large, a problem may occur in that the pattern itself is etched.
  • the pattern 102 is trimmed by supplying chlorine trifluoride (ClF 3 ) gas G 2 to the silicon substrate from which the oxide film is removed.
  • ClF 3 chlorine trifluoride
  • the etching rate may have a high etching ratio regardless of the type of oxide film.
  • the reaction mechanism at this time is as follows.
  • the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted.
  • the chlorine trifluoride (ClF 3 ) gas may be trimmed by supplying 1 to 30 sccm, the nitrogen (N 2 ) gas at 100 to 1000 sccm. In addition, the trimming may be performed under a pressure of 300 m torr to 8 torr.
  • the amount etched under these conditions is approximately 10-30.
  • the present invention can also be utilized in the process of etching polysilicon 1000 ⁇ 10,000 or more (high etch amount process).
  • the silicon nitride layer (SiN) and the oxide layer (oxide) are not etched during polysilicon etching.
  • Polysilicon is deposited to form a specific pattern structure during a semiconductor device process. After that, it is used when it is necessary to etch only polysilicon as needed.
  • chlorine trifluoride (ClF 3 ) is 300 ⁇ 1000sccm
  • nitrogen (N 2 ) is 100 ⁇ 1000sccm
  • pressure is about 1 ⁇ 20 torr
  • temperature can be used at room temperature (25) ⁇ 150C range Do.
  • the selectivity between silicon and oxide film can be increased.
  • the trimming process can be continuously performed without breaking the vacuum state, thereby minimizing the variation of the process due to the naturally occurring oxide film.
  • FIG. 12 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
  • a titanium nitride (TiN) film is formed on a substrate (step S210).
  • a titanium nitride (TiN) film is patterned (step S220).
  • the patterned titanium nitride film may be applied to, for example, forming a contact hole or a capacitor of a semiconductor device for connecting the upper conductive layer and the lower conductive layer.
  • a silicon film is formed on the substrate on which the patterned titanium nitride (TiN) is formed (step S230).
  • the silicon film may include, for example, amorphous silicon or polysilicon.
  • Such a silicon film can be formed, for example, for forming an active layer or a diode of a switching element.
  • the silicon oxide film naturally formed on the silicon film may be removed (step S240).
  • the silicon substrate is exposed to oxygen, an unintended silicon oxide film may be formed on the silicon film, and it is necessary to remove this silicon oxide film.
  • hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas are supplied to the silicon oxide film.
  • a by-product [(NH 4 ) 2 SiF 6 (s)] generated by reacting the silicon oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas may be generated. Therefore, these by-products ((NH 4 ) 2 SiF 6 (s)) can be removed by heating. Lamps can be used, for example, to heat these byproducts ((NH 4 ) 2 SiF 6 (s)).
  • the silicon film is etched using chlorine trifluoride (ClF 3 ) gas (step S250).
  • the etched silicon film may be formed of an active layer or a diode of a switching device.
  • the substrate is maintained in the range of -76 to 70.
  • chlorine trifluoride (ClF 3 ) gas may be liquefied in a vacuum in the chamber, and when higher than 70, the titanium nitride pattern may be etched. Therefore, it is preferable to keep the substrate within the range of -76 to 70 in the process of etching the silicon film.
  • a substrate support such as a susceptor for supporting the substrate may be used.
  • the substrate may be transferred to a cooling chamber before the silicon film is formed to transfer the substrate to the temperature. Can be lowered to a range.
  • the cooling chamber maintains the temperature of the substrate at a temperature lower than the temperature in consideration of the temperature rise in the etching process of the silicon film.
  • the titanium nitride (TiN) pattern may be etched to etch the amorphous silicon film or the polysilicon film without causing any damage.
  • FIG. 13 is a cross-sectional view illustrating an example of a substrate before forming the titanium nitride film illustrated in FIG. 12.
  • a contact pad CP may be formed on a surface of the substrate S, and an insulating film 201 may be formed thereon.
  • the insulating film 201 may constitute an interlayer insulating film for isolation between unit elements or for interlayer separation in a multilayer wiring structure.
  • the insulating layer 201 may form a contact hole to expose the contact pad CP.
  • the substrate S is not limited to the illustrated shape. That is, a plurality of films may be formed between the substrate S and the insulating film 201, and many films may be formed under the contact pad CP.
  • FIG. 14 is a cross-sectional view after the step of forming the titanium nitride film shown in FIG. 12 on the substrate shown in FIG.
  • a titanium nitride film 202 is formed on the substrate S shown in FIG. 13.
  • the substrate S may be a substrate including a plurality of films.
  • the titanium nitride film 202 may be formed by a thermal chemical vapor deposition (CVD) process using titanium chloride (TiCl 4 ) and ammonia (NH 3 ).
  • the substrate S is preheated, and then purged using nitrogen (N 2 ) gas or the like.
  • N 2 nitrogen
  • a titanium nitride film 202 is formed on the substrate S at a predetermined thickness.
  • purged with nitrogen (N 2 ) gas or the like to release the unreacted gas, and then unreacted Ti-Cl bond remaining in the titanium nitride film 202 formed by additional injection of ammonia (NH 3 ) gas.
  • NH 3 ammonia
  • the titanium nitride film 202 may be formed of a titanium nitride base film (not shown) and one or more conductive capping films (not shown) formed thereon in order to increase specific resistance.
  • the titanium nitride base film (not shown) may be formed by the method described above, and the conductive capping film (not shown) may be formed by atomic layer deposition (ALD).
  • FIG. 15 is a cross-sectional view after the step of patterning the titanium nitride film shown in FIG. 12.
  • such a titanium nitride film is patterned to form, for example, a barrier film 202a.
  • This barrier film 202a prevents the diffusion of the metal, such as aluminum (Al), that constitutes the contact plug (205 in FIG. 19) to be formed later into the insulating film.
  • an electrode film (not shown) for forming the electrode of the capacitor may be formed.
  • FIG. 16 is a cross-sectional view after the step of forming the silicon film shown in FIG.
  • a silicon film 203 is formed on the substrate S on which the barrier film 202a is formed.
  • the silicon film 203 may be formed of amorphous silicon or polysilicon.
  • the silicon film 203 may be formed using a conventional chemical vapor deposition (CVD) method.
  • the silicon film 203 may be easily oxidized to generate a silicon oxide film (not shown) on the surface. If the silicon oxide film is thus produced, it must be removed. This is because the silicon oxide film and the silicon film have a high etching ratio in the process of etching the silicon film used in the semiconductor manufacturing method according to the present invention. That is, since the silicon film is easily etched, while the silicon oxide film is not easily etched, when the silicon oxide film is formed on the silicon film when etching to pattern the silicon film, it is not easily etched.
  • FIG. 17 is a cross-sectional view illustrating a process after removing the silicon oxide film illustrated in FIG. 12.
  • the silicon oxide film 204 is supplied by supplying hydrogen fluoride (HF) gas (G1) and ammonia (NH 3 ) gas (G1) to the silicon oxide film 204. ) Can be removed. Since this process is substantially the same as the description corresponding to FIG. 9, the detailed description is omitted.
  • HF hydrogen fluoride
  • NH 3 ammonia
  • FIG. 18 is a cross-sectional view illustrating a step after etching the silicon film illustrated in FIG. 12.
  • the silicon film is etched except for a portion that requires the presence of the silicon film to form an active layer or a diode of the switching device.
  • the chlorine trifluoride (ClF 3 ) gas G2 is supplied to the silicon film (203 in FIG. 17) from which the silicon oxide film (204 in FIG. 17) has been removed, thereby providing the silicon film ( 203).
  • gaseous etching such as etching using chlorine trifluoride (ClF 3 ) gas
  • the reaction mechanism at this time is as follows.
  • the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted.
  • the chlorine trifluoride (ClF 3 ) gas may be 1 to 3000 sccm
  • the nitrogen (N 2 ) gas may be supplied at 100 to 3000 sccm to perform etching.
  • the process of etching the silicon film 203 of FIG. 17 may be performed under a pressure of 300 m torr to 20 torr.
  • the substrate (S) is maintained in the range of -76 to 70. If lower than -76, for example, chlorine trifluoride (ClF 3 ) gas may be liquefied in a vacuum in the chamber, and if higher than 70, the titanium nitride pattern may be etched. Therefore, it is preferable to keep the substrate within the range of -76 to 70 in the process of etching the silicon film.
  • ClF 3 chlorine trifluoride
  • the figure on the left shows a situation in which the silicon etching process is immediately performed
  • the figure on the right shows an oxide removal process and the silicon etching process.
  • the upper figure is the figure before the process progression
  • the lower figure is the figure after the process progression.
  • the sheet resistance was 28.28 / sq for the first sample before the etching process, 28.49 / sq for the first measurement after etching, 29.28 / sq for the second measurement, and 28.90 / for the third measurement.
  • the second sample was 25.96 / sq before the etching process, 26.54 / sq for the first measurement after the etching, 26.57 / sq for the second measurement, and 29.05 / sq for the third measurement. You can see almost nothing.
  • the sheet resistance was 29.02 / sq in the first sample before the etching process, 30.64 / sq in the first measurement after etching, 29.35 / sq in the second measurement, 31.88 / sq at the 3rd measurement, the second sample was 26.07 / sq before the etching process, 27.60 / sq at the 1st measurement after etching, 27.95 / sq at the 2nd measurement, 27.40 at the 3rd measurement Measured as / sq, we see little change.
  • the figure on the left shows a situation in which the silicon etching process is immediately performed
  • the figure on the right shows an oxide removal process and the silicon etching process.
  • the upper figure is the figure before the process progression
  • the lower figure is the figure after the process progression.
  • the sheet resistance was 28.97 / sq in the first sample before the etching process, and it was impossible to measure in the first measurement after etching, 36.05 / sq in the second measurement, and 37.55 in the third measurement.
  • / sq was measured
  • the second sample was 42.70 / sq before the etching process
  • the measurement was impossible at the first measurement after etching, the 53.83 / sq at the second measurement, and the measurement was impossible at the third measurement. You can see a very big one.
  • the sheet resistance was 31.16 / sq before the first sample, and the measurement was impossible at the first measurement after etching, and 27.09k / at the second measurement. sq, measured at 8.544 k / sq in the third measurement, the second sample was 26.44 / sq before the etching process, and measurement was not possible.
  • a substrate support such as a susceptor for supporting the substrate may be used, or alternatively, before the silicon film is formed, it is transferred to a cooling chamber.
  • the substrate S can be lowered to the temperature range.
  • the cooling chamber maintains the temperature of the substrate S at a temperature lower than the temperature in consideration of the temperature rise in the etching process of the silicon film.
  • the titanium nitride (TiN) pattern may be etched to etch the amorphous silicon film or the polysilicon film without applying a daisy.
  • FIG. 19 is a cross-sectional view of a contact plug formed on the barrier film illustrated in FIG. 18.
  • a highly conductive metal film (not shown) is formed on the substrate S on which the barrier film 202a is formed and patterned to form a contact plug 205.
  • the contact plug 205 may be formed of aluminum (Al).
  • FIG. 23 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed only on a lower portion of an inside of a hole, and a silicon layer formed on an upper portion thereof, and FIG. 24 illustrates a silicon layer being etched in FIG. 23. It is a cross section.
  • FIG. 25 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed on a lower side of a hole and a side surface of an inside of a hole, and a silicon layer formed on an upper portion thereof.
  • FIG. It is a cross-sectional view showing the appearance.
  • FIG. 23 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed only on a lower portion of an inside of a hole, and a silicon layer formed on an upper portion thereof
  • FIG. 24 illustrates a silicon layer being etched in FIG. 23
  • FIG. 27 is a cross-sectional view illustrating a titanium nitride pattern formed by patterning a titanium nitride film, a silicon nitride film formed on a lower side of a hole, and a silicon layer formed on a side of the hole, and FIG. 28. 27 is a cross-sectional view showing the silicon layer is etched.
  • the silicon oxide film (not shown) naturally formed on the silicon film 301 formed inside the hole of the insulating film 302 is removed.
  • This process can proceed by supplying hydrogen fluoride gas and ammonia gas as described above.
  • chlorine trifluoride (ClF 3 ) is supplied to etch the silicon film 301, as shown in FIGS. 24, 26, and 28, respectively.
  • the titanium nitride pattern 301 is formed only on the lower inner side of the hole of the insulating film 302, or as shown in FIG. 27, the titanium nitride pattern 301 is formed of the insulating film 302. If the silicon nitride film 304 is formed on the inner side of the hole, the silicon nitride film 304 is formed in the lower side of the hole, and maintained within the range of 70 to 80 until the titanium nitride pattern 301 is exposed in the etching process of the formed silicon film 301. After that, when the titanium nitride pattern 301 is exposed, as described above, the titanium nitride pattern 301 is maintained in the range of -76 to 70.
  • the titanium nitride pattern 301 when the titanium nitride pattern 301 is exposed from the initial etching of the silicon film 303, the titanium nitride pattern 301 is etched only when the titanium nitride pattern 301 is exposed within the range of -76 to 70 from the beginning. Can be prevented.

Abstract

Disclosed is a method for manufacturing a semiconductor device having a minute pattern smaller than the smallest pattern that is formable by means of a photolithography process. The method for manufacturing the semiconductor device includes: forming a silicon layer on a substrate; forming a photoresist layer on top of the silicon layer; exposing the photoresist layer; developing the exposed photoresist layer; forming a pattern on the silicon layer by using the photoresist layer as a mask; removing the photoresist layer; forming an insulation layer; and trimming the pattern formed on the silicon substrate.

Description

반도체소자 제조방법Semiconductor device manufacturing method
본 발명은 반도체소자 제조방법에 관한 것으로, 보다 상세히 미세 패턴을 갖는 반도체소자 제조방법 및 높은 식각 선택비를 달성할 수 있는 반도체소자 제조방법에 관한 것이다.The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method having a fine pattern and a semiconductor device manufacturing method that can achieve a high etching selectivity.
반도체소자는 거의 대부분의 전자기기에 사용되어지고 있다. 특히, 전자기기들이 모바일화, 고성능화가 진행됨에 따라서, 점차로 미세한 패턴형성이 요구되어지고 있다.Semiconductor devices are used in almost all electronic devices. In particular, as electronic devices become more mobile and high performance, fine pattern formation is increasingly required.
특히, 반도체소자는 포토리소그래피에 의해서 웨이퍼에 패턴을 형성함으로써 제조된다. 보다 상세히 웨이퍼에 포토레지스터막을 형성한 후, 이를 노광 및 현상하여 포토레지스터 패턴을 형성하고, 이러한 포토레지스터 패턴을 이용하여 웨이퍼에 형성된 실리콘막을 식각함으로써 실리콘막에 의한 반도체 소자들을 제조하게 되는 것이다.In particular, semiconductor devices are manufactured by forming a pattern on a wafer by photolithography. In more detail, after forming a photoresist film on the wafer, the photoresist pattern is exposed and developed to form a photoresist pattern, and the silicon film formed on the wafer is etched using the photoresist pattern to manufacture semiconductor devices by the silicon film.
그런데, 이러한 포토리소그래피 공정에 의한 패턴형성은 그 사이즈에 한계가 있다. 포토레지스터막을 반응시키기 위한 광원의 파장 및 포토레지스트에 관계되기 때문이다.By the way, the pattern formation by this photolithography process has a limit in the size. This is because it relates to the wavelength of the light source and the photoresist for reacting the photoresist film.
반도체 소자의 고직접화에 따라 패턴의 사이즈가 10~20nm 이하의 최소 사이즈를 가지게 되었다. 이러한 사이즈의 경우 사진 공정에 의한 패턴의 형성이 기술적으로 매우 어려운 상황이 된다.As the semiconductor devices become more directly integrated, patterns have a minimum size of 10-20 nm or less. In the case of such a size, the formation of a pattern by a photographic process is a very technical situation.
한편, 실리콘 막을 식각할 때, 배리어막 또는 전극층 형성을 위한 질화티타늄(TiN) 패턴, 또는 절연막을 구성하는 산화막이 식각되어 불량이 생기는 경우가 발생된다.On the other hand, when etching a silicon film, a titanium nitride (TiN) pattern for forming a barrier film or an electrode layer, or an oxide film constituting an insulating film is etched to cause defects.
보다 상세히, 실리콘(Si) 식각이 가능한 방법은 염화수소(HCl), 브로민화수소(HBr) 등의 가스를 RF 플라즈마 챔버(plasma chamber)에서 이방성 식각하는 방식, 플루오르화황(SF6)등의 가스를 리모트 플라즈마 소스(RPS)를 통해 등방성 식각하는 방식, 그리고 액상 식각 방법으로 질산, 불산, 초산의 혼합액을 이용하는 등방성 시각, 그리고 KOH 용액을 이용하는 이방성 식각 방법 등이 사용되어 왔다.More specifically, the silicon (Si) etching method is a method of anisotropically etching gases such as hydrogen chloride (HCl), hydrogen bromide (HBr) in the RF plasma chamber, sulfur fluoride (SF 6 ) An isotropic etching method using a remote plasma source (RPS), an isotropic time using a mixture of nitric acid, hydrofluoric acid and acetic acid, and an anisotropic etching method using a KOH solution have been used.
액상 식각의 경우 산화막별 식각 선택비가 다르게 나타난다. 이는 산화막 종류별 수소의 농도 및 탄소(carbon)의 농도가 액상 식각률에 영향을 주기 때문이다. 일반적으로 수소 농도가 높을수록 액상에서 식각률이 빠른 것으로 알려져 있다. In the case of liquid etching, the etching selectivity of each oxide layer is different. This is because the concentration of hydrogen and carbon of each oxide film type affect the liquid phase etch rate. Generally, the higher the concentration of hydrogen, the faster the etch rate in the liquid phase.
그러나, 이러한 방법들은 실리콘 막의 식각시에 아몰퍼스 실리콘 또는 폴리 실리콘과 실리콘 산화막 또는 질화티타늄(TiN) 패턴과의 식각 선택비가 좋지 않아 질화티타늄 패턴이 식각되어 불량을 야기시킬 수 있다.However, these methods may have a poor etching selectivity between amorphous silicon or polysilicon and a silicon oxide film or a titanium nitride (TiN) pattern at the time of etching the silicon film, thereby causing a defect in the titanium nitride pattern.
따라서, 실리콘 막의 식각시에 아몰퍼스 실리콘 또는 폴리 실리콘과 실리콘 산화막 또는 질화티타늄(TiN) 패턴과의 높은 선택비를 갖는 공정에 대한 연구가 진행되고 있다.Therefore, studies on a process having a high selectivity of amorphous silicon or polysilicon and a silicon oxide film or a titanium nitride (TiN) pattern at the time of etching the silicon film are being conducted.
따라서, 본 발명이 해결하고자 하는 과제는 포토리소그래피에 의해 형성가능한 최소패턴보다 미세한 패턴을 갖는 반도체소자 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a finer pattern than the minimum pattern that can be formed by photolithography.
또한, 본 발명이 해결하고자 하는 과제는 높은 식각 선택비를 달성할 수 있는 반도체소자 제조방법을 제공하는 것이다.In addition, the problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device that can achieve a high etching selectivity.
이러한 과제를 달성하기 위한 본 발명의 예시적인 일 실시예에 의한 반도체소자 제조방법은, 기판에 실리콘층을 형성하는 단계와, 실리콘층 상부에 포토레지스트막을 형성하는 단계와, 상기 포토레지스트막을 노광하는 단계와, 노광된 상기 포토레지스트막을 현상하는 단계와, 현상된 상기 포토레지스트막을 마스크로 이용하여 상기 실리콘층에 패턴을 형성하는 단계와, 상기 포토레지스트막을 제거하는 단계와, 절연막을 형성하는 단계, 및 상기 실리콘 기판에 형성된 패턴을 트리밍하는 단계를 포함한다.A semiconductor device manufacturing method according to an exemplary embodiment of the present invention for achieving the above object, forming a silicon layer on a substrate, forming a photoresist film on the silicon layer, and exposing the photoresist film Developing the exposed photoresist film, forming a pattern on the silicon layer using the developed photoresist film as a mask, removing the photoresist film, forming an insulating film, And trimming the pattern formed on the silicon substrate.
한편, 상기 반도체소자 제조방법은, 상기 절연막을 형성한 후, 상기 패턴을 노출시키기 위해서, 상기 절연막의 일부를 제거하는 단계를 더 포함할 수 있다.Meanwhile, the semiconductor device manufacturing method may further include removing a portion of the insulating film after the insulating film is formed to expose the pattern.
이때, 상기 절연막은 실리콘 산화막이 사용될 수 있다. 이때, 상기 절연막의 일부를 제거하는 단계에서, 상기 절연막에 불화수소(HF) 가스 및 암모니아(NH3)가스를 공급함으로써 상기 절연막을 제거할 수 있다.In this case, a silicon oxide film may be used as the insulating film. In this case, in the removing of a part of the insulating film, the insulating film may be removed by supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the insulating film.
또한, 상기 절연막의 일부를 제거하는 단계에서, 추가적으로 상기 절연막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물을 제거할 수 있다.In addition, in the step of removing a portion of the insulating film, by-products generated by the reaction between the insulating film, the hydrogen fluoride (HF) gas and the ammonia (NH 3 ) gas may be removed.
이때, 상기 부산물은, 램프를 이용한 히팅(heating) 방법에 의해 제거될 수 있다.In this case, the by-product may be removed by a heating method using a lamp.
또한, 상기 방법은 상기 히팅 방법에 의해 부산물을 제거한 후, 상기 기판을 냉각 챔버로 이송하여 냉각하는 단계를 더 포함할 수 있다.In addition, the method may further include the step of removing the by-products by the heating method, the substrate is transferred to the cooling chamber to cool.
한편, 상기 트리밍하는 단계에서는, 절연막이 일부 제거된 상기 실리콘 기판에 삼불화염소(ClF3)가스를 공급하여 상기 패턴을 트리밍(trimming)할 수 있다.In the trimming, the pattern may be trimmed by supplying chlorine trifluoride (ClF 3 ) gas to the silicon substrate from which the insulating film is partially removed.
또한, 상기 삼불화염소(ClF3)가스를 공급하기 전에, 상기 삼불화염소(ClF3)가스를 희석할 수 있으며, 이때, 상기 삼불화염소(ClF3)가스는 질소(N2)가스에 의해 희석될 수 있다.In addition, before supplying the chlorine trifluoride (ClF 3 ) gas, the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted.
또한, 상기 삼불화염소(ClF3)가스는 1 내지 30 sccm, 상기 질소(N2)가스는 100 내지 1000 sccm으로 공급하여 트리밍을 진행할 수 있다.In addition, the chlorine trifluoride (ClF 3 ) gas may be trimmed by supplying 1 to 30 sccm, the nitrogen (N 2 ) gas at 100 to 1000 sccm.
또한, 상기 트리밍하는 단계는, 300 mtorr 내지 8 torr의 압력하에서 진행될 수 있다.In addition, the trimming may be performed under a pressure of 300 mtorr to 8 torr.
또한, 상기 절연막을 제거한 후, 진공 상태를 깨지 않고 상기 트리밍 공정을 연속적으로 진행할 수 있다.In addition, after the insulating film is removed, the trimming process may be continuously performed without breaking the vacuum state.
본 발명의 또 다른 과제를 달성하기 위한 본 발명의 예시적인 일 실시예에 의한 반도체소자 제조방법은, 기판에 질화티타늄(TiN) 막을 형성하는 단계와, 질화티타늄(TiN) 막을 패터닝하는 단계와, 패터닝된 질화티타늄(TiN)이 형성된 기판에 실리콘 막을 형성하는 단계, 및 삼불화염소(ClF3)가스를 이용하여 상기 실리콘 막을 식각하는 단계를 포함하고, 상기 실리콘 막을 식각하는 단계에서는, 상기 질화티타늄(TiN)이 노출되는 경우, 상기 기판은 -76 내지 70의 범위 내로 유지시킨다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming a titanium nitride (TiN) film on a substrate, patterning a titanium nitride (TiN) film, Forming a silicon film on a substrate on which patterned titanium nitride (TiN) is formed, and etching the silicon film using chlorine trifluoride (ClF 3 ) gas, and in the etching of the silicon film, the titanium nitride When (TiN) is exposed, the substrate is kept in the range of -76 to 70.
이때, 상기 실리콘 막을 식각하는 단계에서, 상기 질화티타늄이 노출되지 않는 경우, 상기 기판은 70 내지 80의 범위 내로 유지시킬 수 있다.In this case, in the etching of the silicon film, when the titanium nitride is not exposed, the substrate may be maintained within a range of 70 to 80.
이와 다르게, 상기 실리콘 막을 식각하는 단계 이전에, 상기 기판을 쿨링 챔버로 이송하여, 상기 쿨링 챔버에서 상기 기판의 온도를 낮출 수도 있다.Alternatively, before the etching of the silicon film, the substrate may be transferred to a cooling chamber to lower the temperature of the substrate in the cooling chamber.
한편, 상기 실리콘 막을 형성하는 단계 이후, 상기 실리콘 막에 자연적으로 형성되는 실리콘 산화막을 제거하는 단계를 더 포함할 수 있다.Meanwhile, after the forming of the silicon film, the method may further include removing a silicon oxide film naturally formed on the silicon film.
이때, 상기 실리콘 산화막을 제거하는 단계는, 상기 실리콘 산화막에 불화수소(HF) 가스 및 암모니아(NH3)가스를 공급하는 단계를 포함할 수 있다.In this case, the removing of the silicon oxide film may include supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the silicon oxide film.
또한, 상기 실리콘 산화막을 제거하는 단계는, 상기 실리콘 산화막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물을, 램프를 이용한 히팅(heating) 방법에 의해 제거하는 단계를 더 포함할 수 있다.The removing of the silicon oxide film may include removing by-products generated by the reaction between the silicon oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas by a heating method using a lamp. It may further comprise a step.
본 발명에 의한 반도체소자 제조방법에 의하면, 포토리소그래피에 의해 형성가능한 최소패턴보다 미세한 패턴을 갖는 반도체소자를 제조할 수 있다.According to the semiconductor device manufacturing method according to the present invention, it is possible to manufacture a semiconductor device having a pattern finer than the minimum pattern that can be formed by photolithography.
또한, 트리밍하는 공정이 기상반응이므로, 실리콘과 산화막의 선택비를 높일 수 있다.In addition, since the trimming step is a gas phase reaction, the selectivity between silicon and oxide film can be increased.
또한, 위의 공정들은 각각의 챔버에서 매엽식으로 진행될 수 있으므로, 웨이퍼들 사이의 균일도(wafer-to-wafer uniformity)를 개선할 수 있다.In addition, the above processes can be carried out in each chamber on a single sheet, thereby improving wafer-to-wafer uniformity.
또한, 절연막(실리콘 산화막)을 제거한 후, 진공 상태를 깨지 않고 트리밍 공정을 연속적으로 진행하여 자연적으로 생성되는 산화막에 기인하는 공정의 변동을 최소화할 수 있다.Further, after removing the insulating film (silicon oxide film), the trimming process can be continuously performed without breaking the vacuum state, thereby minimizing the variation of the process due to the naturally occurring oxide film.
본 발명에 의한 반도체소자 제조방법에 의하면, 질화티타늄(TiN) 패턴이 식각되어 데미지가 가해짐이 없이 아몰퍼스 실리콘 막 또는 폴리 실리콘 막을 식각할 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, an amorphous silicon film or a polysilicon film can be etched without being damaged by etching a titanium nitride (TiN) pattern.
또한, 실리콘 막을 형성한 후, 자연적으로 형성되는 실리콘 산화막을 제거하는 경우, 보다 용이하게 실리콘 막을 식각할 수 있다.In addition, after removing the silicon oxide film formed naturally after forming the silicon film, the silicon film can be more easily etched.
도 1은 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법을 도시하는 순서도이다.1 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
도 2는 도 1에서 도시된 기판에 실리콘층을 형성하는 단계의 수행결과를 도시한 개략적인 단면도이다.FIG. 2 is a schematic cross-sectional view showing a result of performing a step of forming a silicon layer on the substrate shown in FIG. 1.
도 3은 도 1에서 도시된 포토레지스트막을 형성하는 단계의 수행결과를 도시한 개략적인 단면도이다.3 is a schematic cross-sectional view showing a result of performing a step of forming the photoresist film shown in FIG.
도 4는 도 1에서 도시된 포토레지스트막을 노광하는 단계를 도시한 개략적인 단면도이다.4 is a schematic cross-sectional view illustrating the step of exposing the photoresist film shown in FIG. 1.
도 5는 도 1에서 도시된 포토레지스트막을 현상하는 단계를 수행한 결과를 도시한 개략적인 단면도이다.FIG. 5 is a schematic cross-sectional view illustrating a result of performing the developing of the photoresist film shown in FIG. 1.
도 6은 도 1에서 도시된 실리콘층에 패턴을 형성하는 단계를 수행한 결과를 도시한 개략적인 단면도이다.FIG. 6 is a schematic cross-sectional view illustrating a result of performing a step of forming a pattern on the silicon layer illustrated in FIG. 1.
도 7은 도 1에서 도시된 포토레지스트막을 제거하는 단계를 수행한 결과를 도시한 개략적인 단면도이다.FIG. 7 is a schematic cross-sectional view illustrating a result of performing a step of removing the photoresist film shown in FIG. 1.
도 8은 도 1에서 도시된 절연막을 형성하는 단계를 수행한 결과를 도시한 개략적인 단면도이다.FIG. 8 is a schematic cross-sectional view showing the result of performing the step of forming the insulating film shown in FIG.
도 9는 도 1에서 도시된 절연막을 일부 제거하는 단계를 수행한 결과를 도시한 개략적인 단면도이다.FIG. 9 is a schematic cross-sectional view illustrating a result of performing a step of partially removing the insulating film illustrated in FIG. 1.
도 10은 도 1에서 도시된 패턴을 트리밍하는 단계를 도시한 개략적인 단면도이다.FIG. 10 is a schematic cross-sectional view illustrating trimming the pattern illustrated in FIG. 1.
도 11은 폴리실리콘(poly-Si) 및 실리콘질화막(SiN) 과 산화막(oxide) 과의 식각 선택비를 도시한 그래프이다.FIG. 11 is a graph illustrating an etching selectivity of polysilicon (poly-Si), silicon nitride (SiN), and oxide (oxide).
도 12는 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법을 도시하는 순서도이다.12 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
도 13은 도 12에서 도시된 질화티타늄 막을 형성하기 이전, 기판의 일 예를 도시한 단면도이다.FIG. 13 is a cross-sectional view illustrating an example of a substrate before forming the titanium nitride film illustrated in FIG. 12.
도 14는 도 13에서 도시된 기판에, 도 12에서 도시된 질화티타늄 막을 형성하는 단계 이후를 도시한 단면도이다.FIG. 14 is a cross-sectional view after the step of forming the titanium nitride film shown in FIG. 12 on the substrate shown in FIG.
도 15는 도 12에서 도시된 질화티타늄 막을 패터닝하는 단계 이후를 도시한 단면도이다.FIG. 15 is a cross-sectional view after the step of patterning the titanium nitride film shown in FIG. 12.
도 16은 도 12에서 도시된 실리콘 막을 형성하는 단계 이후를 도시한 단면도이다.16 is a cross-sectional view after the step of forming the silicon film shown in FIG.
도 17은 도 12에서 도시된 실리콘 산화막을 제거하는 단계 이후를 도시한 단면도이다.FIG. 17 is a cross-sectional view illustrating a process after removing the silicon oxide film illustrated in FIG. 12.
도 18은 도 12에서 도시된 실리콘 막을 식각하는 단계 이후를 도시한 단면도이다.18 is a cross-sectional view illustrating a step after etching the silicon film illustrated in FIG. 12.
도 19는 도 18에서 도시된 배리어 막에 콘택 플러그를 형성한 것을 도시한 단면도이다.FIG. 19 is a cross-sectional view of a contact plug formed on the barrier film illustrated in FIG. 18.
도 20은 기판의 온도를 40로 유지한 조건에서 실리콘 막을 식각하였을 때, 아몰퍼스 실리콘, 폴리 실리콘 및 질화티타늄의 식각 특성을 도시한 SEM사진이다.FIG. 20 is an SEM image illustrating etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 40. FIG.
도 21은 기판의 온도를 60로 유지한 조건에서 실리콘 막을 식각하였을 때, 아몰퍼스 실리콘, 폴리 실리콘 및 질화티타늄의 식각 특성을 도시한 사진이다.FIG. 21 is a photograph showing etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 60;
도 22는 기판의 온도를 80로 유지한 조건에서 실리콘 막을 식각하였을 때, 아몰퍼스 실리콘, 폴리 실리콘 및 질화티타늄의 식각 특성을 도시한 사진이다.FIG. 22 is a photograph illustrating etching characteristics of amorphous silicon, polysilicon, and titanium nitride when the silicon film is etched under the condition that the temperature of the substrate is maintained at 80;
도 23은 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부에만 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이다.FIG. 23 is a cross-sectional view illustrating a form in which a titanium nitride pattern formed by patterning a titanium nitride film is formed only on a lower portion of an inside of a hole, and a silicon layer is formed thereon.
도 24는 도 23에서 실리콘층이 식각된 모습을 도시한 단면도이다.FIG. 24 is a cross-sectional view illustrating a silicon layer etched in FIG. 23.
도 25는 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부 및 홀 내측의 측면에 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이다.FIG. 25 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed on a lower side of a hole and a side surface of a hole, and a silicon layer formed on the upper portion thereof.
도 26은 도 25에서 실리콘층이 식각된 모습을 도시한 단면도이다.FIG. 26 is a cross-sectional view illustrating a silicon layer etched in FIG. 25.
도 27은 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부에 형성되고 및 홀 내측의 측면에는 실리콘 질화막이 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이다.FIG. 27 is a cross-sectional view illustrating a titanium nitride pattern formed by patterning a titanium nitride film, a silicon nitride film formed on a lower side of a hole, and a silicon layer formed on a side of a hole.
도 28은 도 27에서 실리콘층이 식각된 모습을 도시한 단면도이다.FIG. 28 is a cross-sectional view illustrating a silicon layer etched in FIG. 27.
상술한 본 발명의 특징 및 효과는 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이며, 그에 따라 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 것이다. 본 발명은 하기의 실시예들에 한정되지 않고 다른 형태로 구현될 수도 있다. 여기서 소개되는 실시예들은 개시된 내용이 보다 완전해질 수 있도록 그리고 당업자에게 본 발명의 기술적 사상과 특징이 충분히 전달될 수 있도록 하기 위해 제공된다. 도면들에 있어서, 각 장치 또는 막(층) 및 영역들의 두께는 본 발명의 명확성을 기하기 위하여 과장되게 도시되었으며, 또한 각 장치는 본 명세서에서 설명되지 아니한 다양한 부가 장치들을 구비할 수 있다.The above-described features and effects of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, and thus, those skilled in the art to which the present invention pertains may easily implement the technical idea of the present invention. Could be. The present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the present invention to those skilled in the art. In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have various additional devices not described herein.
이하, 첨부한 도면들을 참조하여, 본 발명의 바람직한 실시예들을 보다 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
미세 패턴을 갖는 반도체소자 제조방법Method of manufacturing a semiconductor device having a fine pattern
도 1은 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법을 도시하는 순서도이고, 도 2 내지 도 8은 도 1에서 각 단계의 수행결과를 도시한 개략적인 단면도이다.1 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention, and FIGS. 2 to 8 are schematic cross-sectional views showing results of performing each step in FIG. 1.
도 1 및 도 2를 참조하면, 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법에 의하면, 먼저 산소 또는 질소 분위기에서 자연적으로 형성되는 절연막(101)이 형성되어 있는 기판(S)에 실리콘층(102)을 형성한다(단계 S110). 이러한 실리콘층(102)은 예컨대, 결정질 실리콘, 미세결정질실리콘, 아몰퍼스 실리콘 등, 요구되는 반도체 소자에 따라 다양한 실리콘층이 형성되어질 수 있다.1 and 2, according to the method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention, a silicon layer is formed on a substrate S on which an insulating film 101 is naturally formed in an oxygen or nitrogen atmosphere. 102 is formed (step S110). The silicon layer 102 may be formed of various silicon layers according to the required semiconductor device, such as crystalline silicon, microcrystalline silicon, amorphous silicon, and the like.
상기 실리콘층(102)은 대략 1 마이크로미터의 두께로 형성될 수 있으며, 통상의 화학기상증착(CVD: Chemical Vapor Deposition)으로 형성될 수 있다. 또한, 상기 실리콘층(102)은 도전층으로 형성되기 위하여 불순물이 도핑될 수 있다.The silicon layer 102 may be formed to a thickness of about 1 micrometer, and may be formed by conventional chemical vapor deposition (CVD). In addition, the silicon layer 102 may be doped with an impurity to form a conductive layer.
도 1 및 도 3을 참조하면, 실리콘층(102) 상부에 포지티브 타입이나, 네거티브 타입 등 원하는 타입의 포토레지스트막(103)을 형성한다(단계 S120). 이러한 포토레지스트막(103)은 예컨대 6500 의 두께로 형성될 수 있으며, 기판(S)을 회전시키면서 노즐을 통해 포토레지스트를 도포시키는 스프레이(spray) 타입의 스핀코터(spin coater) 장치를 이용할 수 있다. 1 and 3, a photoresist film 103 of a desired type, such as a positive type or a negative type, is formed on the silicon layer 102 (step S120). The photoresist film 103 may be formed to a thickness of, for example, 6500, and a spray type spin coater device for applying a photoresist through a nozzle while rotating the substrate S may be used. .
도 1 및 도 4를 참조하면, 패턴이 형성된 마스크(M)를 이용하여 상기 실리콘 기판에 형성된 포토레지스트막(103)을 노광한다(단계 S130). 이에 의해, 광(L)이 상기 마스크(M)의 패턴에 의해 노광된 부분(103a)과 마스크(M)에 의해 가리워진 부분(103b)으로 나뉘어진다. 상기 노광된 부분(103a)은 광에 의해 화학적 변화가 발생되어 상기 두 부분(103a, 103b)는 그 화학적 성질을 달리하게 된다. 1 and 4, the photoresist film 103 formed on the silicon substrate is exposed using the mask M on which the pattern is formed (step S130). Thereby, light L is divided into the part 103a exposed by the pattern of the said mask M, and the part 103b covered by the mask M. As shown to FIG. The exposed portion 103a is chemically changed by light so that the two portions 103a and 103b have different chemical properties.
도 1 및 도 5를 참조하면, 노광된 포토레지스트막을 현상하고(단계 S140), 도 6에 도시된 것과 같이, 이를 이용하여 기판에 패턴을 형성한다(단계 S150). 이를 위하여 사염화탄소(CCl4)와 아르곤을 혼합한 혼합물, 사불화탄소(CF4)와 산소의 혼합가스, CF3Cl가스, 불화탄소계 화합물과 염소가스 혼합물등이 사용될 수 있다.1 and 5, the exposed photoresist film is developed (step S140), and as shown in FIG. 6, a pattern is formed on the substrate using the same (step S150). To this end, a mixture of carbon tetrachloride (CCl 4 ) and argon, a mixture of carbon tetrafluoride (CF 4 ) and oxygen, CF 3 Cl gas, a fluorocarbon compound, and a chlorine gas mixture may be used.
도 1, 도 6 및 도 7을 참조하면, 스트립공정을 통해서 남아 있는 포토레지스트막(130a)을 제거한다(단계 S160). 도 6에서의 포토레지스트막의 남겨진 부분(103a)를 제거하기 위해서 섭씨 약 10도 내지 40도 정도의 온도를 유지하는 모노에탄올아민 및 디메틸술폭시드를 혼합한 혼합액을 이용하여 약 300초 이하의 시간으로 공정을 수행할 수 있다. 이후, 세정을 진행할 수 있다.1, 6, and 7, the remaining photoresist film 130a is removed through the strip process (step S160). In order to remove the remaining portion 103a of the photoresist film in FIG. 6, a mixture of monoethanolamine and dimethyl sulfoxide maintained at a temperature of about 10 to 40 degrees Celsius was used for about 300 seconds or less. The process can be carried out. Thereafter, washing may proceed.
이후, 도 1 및 도 8을 참조하면, 실리콘층에 형성된 패턴이 구성하는 각 전자소자들을 상호간에 절연시키기 위한 절연막(104)을 형성한다(단계 S170). 이때, 상기 절연막으로서 실리콘 산화막(SiO2)이 형성될 수 있다. 실리콘패턴 형성부분(102b)으로 구성된 패턴을 덮고 있는 절연막(실리콘 산화막, 104)은 이후, 진행될 트리밍 공정을 방해하게 된다. 따라서, 이러한 실리콘패턴 형성부분(102b)으로 구성된 패턴을 덮고 있는 절연막(104)을 제거할 필요가 있다.1 and 8, an insulating film 104 is formed to insulate each electronic device included in the pattern formed on the silicon layer from each other (step S170). In this case, a silicon oxide layer (SiO 2 ) may be formed as the insulating layer. The insulating film (silicon oxide film) 104 covering the pattern constituted by the silicon pattern forming portion 102b then interferes with the trimming process to be performed. Therefore, it is necessary to remove the insulating film 104 covering the pattern composed of such a silicon pattern forming portion 102b.
이후, 도 1 및 도 9를 참조하면, 이렇게 형성된 패턴을 트리밍함으로써 미세패턴을 형성한다(단계 S190). 도 8의 절연막(104)을 제거하기 위해서, 상기 절연막(104)에 불화수소(HF) 가스 및 암모니아(NH3)가스와 같은 소스가스(G1)를 공급함으로써 상기 절연막(104)의 일부를 제거할 수 있다.1 and 9, a fine pattern is formed by trimming the thus formed pattern (step S190). In order to remove the insulating film 104 of FIG. 8, a part of the insulating film 104 is removed by supplying a source gas G1 such as hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the insulating film 104. can do.
이때의 반응 메커니즘은 다음과 같다.The reaction mechanism at this time is as follows.
HF + NH3-->NH4FHF + NH 3- > NH 4 F
NH4F+SiO2-->(NH4)2SiF6(s)+2H2O(g) + 4NH3(g)NH 4 F + SiO 2- > (NH 4 ) 2 SiF 6 (s) + 2H 2 O (g) + 4NH 3 (g)
한편, 기판상에 산화막과 불화암모늄(NH4F)이 반응하여 암모늄 헥사플루오르실리케이트((NH4)2SiF6)가 응축막으로 형성되는데, 이러한 응축막은 후열처리에 의해 제거될 수 있다. 즉, 상기 절연막을 일부 제거하는 단계(S180)에서, 추가적으로 상기 산화막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물[(NH4)2SiF6(s)]을 제거할 수 있다. 예컨대, 상기 부산물[헥사플루오르실리케이트 (NH4)2SiF6(s)]은, 램프를 이용한 히팅(heating) 방법에 의해 제거될 수 있다.Meanwhile, an oxide film and ammonium fluoride (NH 4 F) react on the substrate to form an ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ) as a condensation film, which can be removed by a post heat treatment. That is, in step S180 of removing the insulating film, a by-product generated by the reaction of the oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas [(NH 4 ) 2 SiF 6 (s) ] Can be removed. For example, the by-product [hexafluorosilicate (NH 4 ) 2 SiF 6 (s)] can be removed by a heating method using a lamp.
이때의 반응 메커니즘은 다음과 같다.The reaction mechanism at this time is as follows.
(NH4)2SiF6(s)-->2NH3(g) + SiF4(g) + 2HF(g)(NH 4 ) 2 SiF 6 (s)-> 2NH 3 (g) + SiF 4 (g) + 2HF (g)
한편, 램프에 의한 히팅시 기판(wafer)의 온도는 150C 이상으로 후속의 트리밍 전 기판의 냉각이 필요하다. 이를 위하여, 이후 진행될 트리밍 공정 챔버에서 장시간(1~5분) 정도 냉각 할 수도 있지만 이런 방식은 쓰루풋(through-put)을 감소시킨다. 이를 위하여, 제안되는 방식은 트리밍 챔버에서 트리밍 공정 전에 냉각 챔버에서 상기 기판을 냉각시킨 후 후속의 트리밍을 진행할 수 있다.On the other hand, the temperature of the wafer during heating by the lamp is 150C or more, so cooling of the substrate before subsequent trimming is necessary. To this end, it may be cooled for a long time (1-5 minutes) in the subsequent trimming process chamber, but this reduces the throughput. To this end, the proposed scheme can cool the substrate in the cooling chamber and proceed with subsequent trimming before the trimming process in the trimming chamber.
도 10은 도 1에서 도시된 패턴을 트리밍하는 단계(S190)를 도시한 개략적인 단면도이다.FIG. 10 is a schematic cross-sectional view illustrating trimming the pattern illustrated in FIG. 1 (S190).
도 10을 참조하면, 실리콘패턴 형성부분(102b)으로 구성된 패턴을 미세구조화하기 위해서 상기 패턴의 외곽부를 제거하는 트리밍 공정을 진행한다.Referring to FIG. 10, a trimming process of removing the outer portion of the pattern is performed to microstructure the pattern formed of the silicon pattern forming part 102b.
실리콘(Si) 식각이 가능한 방법은 염화수소(HCl), 브로민화수소(HBr) 등의 가스를 RF 플라즈마 챔버(plasma chamber)에서 이방성 식각하는 방식, 불화규소(SF6)등의 가스를 리모트 플라즈마 소스(RPS)를 통해 등방성 식각하는 방식, 그리고 액상 식각 방법으로 질산, 불산, 초산의 혼합액을 이용하는 등방성 시각, 그리고 KOH 용액을 이용하는 이방성 식각 방법 등을 고려해볼 수 있다. 액상 식각의 경우 산화막별 식각 선택비가 다르게 나타난다. 이는 산화막 종류별 수소의 농도 및 탄소(carbon)의 농도가 액상 식각률에 영향을 주기 때문이다. 일반적으로 수소 농도가 높을수록 액상에서 식각률이 빠른 것으로 알려져 있다. 이때 실리콘(Si) 등방성 식각시의 용액의 농도를 조절하여 트리밍 시의 실리콘 식각량을 극소량으로 하는 방법을 검토할 수 있다. 실리콘 식각이 큰 경우, 상기 패턴 자체가 식각되어 불량이 발생하는 문제가 생길 수 있기 때문이다.Silicon (Si) can be etched by anisotropically etching gases such as hydrogen chloride (HCl) and hydrogen bromide (HBr) in an RF plasma chamber, and by using a remote plasma source such as silicon fluoride (SF 6 ). The isotropic etching method through (RPS), the liquid phase etching method, isotropic time using a mixture of nitric acid, hydrofluoric acid and acetic acid, and anisotropic etching method using KOH solution can be considered. In the case of liquid etching, the etching selectivity of each oxide layer is different. This is because the concentration of hydrogen and carbon of each oxide film type affect the liquid phase etch rate. Generally, the higher the concentration of hydrogen, the faster the etch rate in the liquid phase. At this time, the method of adjusting the concentration of the solution in the silicon (Si) isotropic etching to minimize the amount of silicon etching during trimming can be examined. This is because when the silicon etching is large, a problem may occur in that the pattern itself is etched.
따라서, 트리밍을 위한 실리콘의 식각시에는 미소량의 실리콘 식각 이외에 실리콘 산화막(104)에 고 선택비인 조건이 요구된다. 액상의 경우 옥사이드(oxide)와의 식각선택비(selectivity)를 확보 할 수 없다.Therefore, in the etching of silicon for trimming, a high selectivity condition is required for the silicon oxide film 104 in addition to the small amount of silicon etching. In the case of liquid phase, the etching selectivity with oxide cannot be secured.
따라서, 본 실시예에서는, 산화막이 제거된 상기 실리콘 기판에 삼불화염소(ClF3)가스(G2)를 공급하여 상기 패턴(102)을 트리밍(trimming)한다. 이러한, 삼불화염소(ClF3)가스를 이용한 식각 등 기상 식각의 경우 액상식각에서와 같은 수소 및 탄소의 농도에 의존하는 반응 메카니즘이 존재 하지 않으므로 산화막 종류에 관계없이 고 식각비를 가질 수 있다.Therefore, in the present embodiment, the pattern 102 is trimmed by supplying chlorine trifluoride (ClF 3 ) gas G 2 to the silicon substrate from which the oxide film is removed. In the case of gas phase etching, such as etching using chlorine trifluoride (ClF 3 ) gas, since there is no reaction mechanism depending on the concentration of hydrogen and carbon as in liquid etching, the etching rate may have a high etching ratio regardless of the type of oxide film.
이때의 반응 메커니즘은 다음과 같다.The reaction mechanism at this time is as follows.
4ClF3+3Si-->2Cl2(g) + 3SiF4(g)4ClF 3 + 3Si-> 2Cl 2 (g) + 3SiF 4 (g)
또한, 상기 삼불화염소(ClF3)가스를 공급하기 전에, 상기 삼불화염소(ClF3)가스를 희석할 수 있으며, 이때, 상기 삼불화염소(ClF3)가스는 질소(N2)가스에 의해 희석될 수 있다. 이때, 상기 삼불화염소(ClF3)가스는 1 내지 30 sccm, 상기 질소(N2)가스는 100 내지 1000 sccm으로 공급하여 트리밍을 진행할 수 있다. 또한, 상기 트리밍하는 단계는, 300m torr 내지 8 torr의 압력하에서 진행될 수 있다.In addition, before supplying the chlorine trifluoride (ClF 3 ) gas, the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted. At this time, the chlorine trifluoride (ClF 3 ) gas may be trimmed by supplying 1 to 30 sccm, the nitrogen (N 2 ) gas at 100 to 1000 sccm. In addition, the trimming may be performed under a pressure of 300 m torr to 8 torr.
이러한 조건하에서 식각되는 양은 대략 10 내지 30 정도이다.The amount etched under these conditions is approximately 10-30.
한편, 본 발명은 또한 폴리실리콘을 1000~10000 이상 에칭하는 공정(high etch amount 공정)에도 활용 할 수 있다. 이때의 특징은 도 11의 식각 선택비 결과에서처럼 실리콘 질화막(SiN) 및 산화막(oxide)은 폴리실리콘 식각시 식각되지 않는다는 특징을 이용한 것으로 반도체 소자 공정 중 특정 패턴 구조의 형성을 위해, 폴리실리콘을 증착한 후 필요에 의해 폴리실리콘만을 식각할 필요가 있는 경우에 사용된다.On the other hand, the present invention can also be utilized in the process of etching polysilicon 1000 ~ 10,000 or more (high etch amount process). In this case, as shown in the etching selectivity result of FIG. 11, the silicon nitride layer (SiN) and the oxide layer (oxide) are not etched during polysilicon etching. Polysilicon is deposited to form a specific pattern structure during a semiconductor device process. After that, it is used when it is necessary to etch only polysilicon as needed.
도 11에서는 폴리실리콘과 실리콘 질화막 및 산화막과의 식각선택비 결과만을 보여 주었지만, 삼불화염소(ClF3)가스는 질화티타늄(TiN)과의 식각선택비도 극단적으로 우수 하므로 폴리실리콘과 질화티타늄(TiN)과의 극단적인 선택도가 요구되는 경우에도 사용 가능하다.11 shows only the results of etching selectivity of polysilicon, silicon nitride film and oxide film, chlorine trifluoride (ClF 3 ) gas is extremely excellent in etching selectivity with titanium nitride (TiN), so that polysilicon and titanium nitride ( It can also be used if extreme selectivity with TiN) is required.
이때 사용되는 조건은, 예컨대 삼불화염소(ClF3)는 300~1000sccm, 질소(N2)는 100~1000sccm, 압력은 1~20 torr 정도이고, 온도는 상온 (25) ~150C 범위를 사용 가능하다.At this time, for example, chlorine trifluoride (ClF 3 ) is 300 ~ 1000sccm, nitrogen (N 2 ) is 100 ~ 1000sccm, pressure is about 1 ~ 20 torr, temperature can be used at room temperature (25) ~ 150C range Do.
이러한 가스를 이용한 트리밍하는 공정이 기상반응이므로, 실리콘과 산화막의 선택비를 높일 수 있다.Since the trimming process using such a gas is a gas phase reaction, the selectivity between silicon and oxide film can be increased.
또한, 위의 공정들은 각각의 챔버에서 매엽식으로 진행될 수 있으므로, 웨이퍼 균일도(wafer-to-wafer uniformity)를 개선할 수 있다.In addition, the above processes can be carried out in each chamber on a single sheet, thus improving wafer-to-wafer uniformity.
또한, 절연막(실리콘 산화막)을 제거한 후, 진공 상태를 깨지 않고 트리밍 공정을 연속적으로 진행하여 자연적으로 생성되는 산화막에 기인하는 공정의 변동을 최소화할 수 있다.Further, after removing the insulating film (silicon oxide film), the trimming process can be continuously performed without breaking the vacuum state, thereby minimizing the variation of the process due to the naturally occurring oxide film.
높은 식각 선택비를 달성할 수 있는 반도체소자 제조방법Semiconductor device manufacturing method that can achieve high etching selectivity
도 12는 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법을 도시하는 순서도이다.12 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with an exemplary embodiment of the present invention.
도 12를 참조하면, 본 발명의 예시적인 실시예에 의한 반도체소자 제조방법에 의하면, 먼저 기판에 질화티타늄(TiN) 막을 형성한다(단계 S210). Referring to FIG. 12, according to the semiconductor device manufacturing method according to the exemplary embodiment of the present invention, first, a titanium nitride (TiN) film is formed on a substrate (step S210).
이후, 질화티타늄(TiN) 막을 패터닝한다(단계 S220). 이렇게 패터닝된 질화티타늄 막은 예컨대 상부 도전층과 하부 도전층을 연결하기 위한 콘택홀 또는 반도체 소자의 캐패시터등의 형성에 적용될 수 있다.Thereafter, a titanium nitride (TiN) film is patterned (step S220). The patterned titanium nitride film may be applied to, for example, forming a contact hole or a capacitor of a semiconductor device for connecting the upper conductive layer and the lower conductive layer.
이후, 패터닝된 질화티타늄(TiN)이 형성된 기판에 실리콘 막을 형성한다(단계 S230). 상기 실리콘 막은 예컨대, 아몰퍼스 실리콘 또는 폴리 실리콘을 포함할 수 있다. 이러한 실리콘 막은 예컨대 스위칭 소자의 활성층 또는 다이오드 등의 형성을 위해 형성될 수 있다.Thereafter, a silicon film is formed on the substrate on which the patterned titanium nitride (TiN) is formed (step S230). The silicon film may include, for example, amorphous silicon or polysilicon. Such a silicon film can be formed, for example, for forming an active layer or a diode of a switching element.
이후, 선택적으로, 상기 실리콘 막 상부에 자연적으로 형성되는 실리콘 산화막을 제거할 수 있다(단계 S240). 예컨대 실리콘 기판이 산소에 노출되는 경우, 실리콘 막 상부에 의도하지 않은 실리콘 산화막이 형성될 수 있는데, 이러한 실리콘 산화막을 제거하는 것이 필요하다. 이를 위하여, 상기 실리콘 산화막에 불화수소(HF) 가스 및 암모니아(NH3)가스를 공급한다.Thereafter, optionally, the silicon oxide film naturally formed on the silicon film may be removed (step S240). For example, when the silicon substrate is exposed to oxygen, an unintended silicon oxide film may be formed on the silicon film, and it is necessary to remove this silicon oxide film. To this end, hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas are supplied to the silicon oxide film.
한편, 이 경우, 상기 실리콘 산화막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물[(NH4)2SiF6(s)]이 생성될 수 있다. 따라서, 이러한 부산물[(NH4)2SiF6(s)]을 히팅하여 제거할 수 있다. 이러한 부산물[(NH4)2SiF6(s)]을 히팅(heating)하기 위하여 예컨대 램프가 사용될 수 있다.In this case, a by-product [(NH 4 ) 2 SiF 6 (s)] generated by reacting the silicon oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas may be generated. Therefore, these by-products ((NH 4 ) 2 SiF 6 (s)) can be removed by heating. Lamps can be used, for example, to heat these byproducts ((NH 4 ) 2 SiF 6 (s)).
이후, 삼불화염소(ClF3)가스를 이용하여 상기 실리콘 막을 식각한다(단계 S250). 이렇게 식각된 상기 실리콘 막은 스위칭 소자의 활성층 또는 다이오드로 형성될 수 있다. 한편, 상기 실리콘 막을 식각하는 과정에서, 상기 질화티타늄(TiN)이 노출되는 경우, 상기 기판은 -76 내지 70의 범위 내로 유지시킨다. -76 보다 낮은 경우, 챔버내의 진공상태에서 예컨대 삼불화염소(ClF3)가스가 액화될 수 있으며, 70 보다 높은 경우, 상기 질화티타늄 패턴이 식각될 수 있다. 따라서, 상기 실리콘 막을 식각하는 과정에서 상기 기판은 -76 내지 70의 범위 내로 유지시키는 것이 바람직하다.Thereafter, the silicon film is etched using chlorine trifluoride (ClF 3 ) gas (step S250). The etched silicon film may be formed of an active layer or a diode of a switching device. On the other hand, during the etching of the silicon film, when the titanium nitride (TiN) is exposed, the substrate is maintained in the range of -76 to 70. When lower than -76, for example, chlorine trifluoride (ClF 3 ) gas may be liquefied in a vacuum in the chamber, and when higher than 70, the titanium nitride pattern may be etched. Therefore, it is preferable to keep the substrate within the range of -76 to 70 in the process of etching the silicon film.
상기 기판을 -76 내지 70의 범위 내로 유지시키기 위해서, 상기 기판을 지지하는 서셉터 등의 기판 지지대를 이용할 수도 있고, 이와 다르게, 상기 실리콘 막을 형성하기 이전에 쿨링 챔버로 이송하여 상기 기판을 상기 온도 범위로 낮출 수 있다. 이때, 상기 쿨링챔버는 상기 실리콘 막의 식각공정에서 온도 상승을 고려하여 기판의 온도를 상기 온도보다 낮은 온도로 유지시킨다.In order to keep the substrate within the range of -76 to 70, a substrate support such as a susceptor for supporting the substrate may be used. Alternatively, the substrate may be transferred to a cooling chamber before the silicon film is formed to transfer the substrate to the temperature. Can be lowered to a range. In this case, the cooling chamber maintains the temperature of the substrate at a temperature lower than the temperature in consideration of the temperature rise in the etching process of the silicon film.
이와 같이, 실리콘 식각시에 기판을 -76 내지 70의 범위 내로 유지시키는 경우, 질화티타늄(TiN) 패턴이 식각되어 데미지가 가해짐이 없이 아몰퍼스 실리콘 막 또는 폴리 실리콘 막을 식각할 수 있다.As such, when the substrate is held in the range of −76 to 70 during silicon etching, the titanium nitride (TiN) pattern may be etched to etch the amorphous silicon film or the polysilicon film without causing any damage.
이하, 도 13 내지 도 19를 참조로, 본 실시예에 의한 반도체 제조방법을 보다 상세히 설명한다.Hereinafter, the semiconductor manufacturing method according to the present embodiment will be described in more detail with reference to FIGS. 13 to 19.
도 13은 도 12에서 도시된 질화티타늄 막을 형성하기 이전, 기판의 일 예를 도시한 단면도이다.FIG. 13 is a cross-sectional view illustrating an example of a substrate before forming the titanium nitride film illustrated in FIG. 12.
도 13을 참조하면, 기판(S)의 표면에는 예컨대 콘택 패드(CP)가 형성되고 그 상부에 절연막(201)이 형성될 수 있다. 상기 절연막(201)은 단위 소자간의 격리, 또는 다층 배선 구조에서의 층간 분리를 위한 층간절연막을 구성할 수 있다. 또한, 상기 절연막(201)은 콘택홀을 형성하여 상기 콘택 패드(CP)를 노출시킬 수 있다. Referring to FIG. 13, for example, a contact pad CP may be formed on a surface of the substrate S, and an insulating film 201 may be formed thereon. The insulating film 201 may constitute an interlayer insulating film for isolation between unit elements or for interlayer separation in a multilayer wiring structure. In addition, the insulating layer 201 may form a contact hole to expose the contact pad CP.
한편, 상기 기판(S)은 도시된 형상에 한정되지 않는다. 즉, 기판(S)과 절연막(201) 사이에 다수의 막들이 형성될 수 있으며, 또한 콘택 패드(CP)의 하부에도 많은 막들이 형성될 수 있다.Meanwhile, the substrate S is not limited to the illustrated shape. That is, a plurality of films may be formed between the substrate S and the insulating film 201, and many films may be formed under the contact pad CP.
도 14는 도 13에서 도시된 기판에, 도 12에서 도시된 질화티타늄 막을 형성하는 단계 이후를 도시한 단면도이다.FIG. 14 is a cross-sectional view after the step of forming the titanium nitride film shown in FIG. 12 on the substrate shown in FIG.
도 14를 참조하면, 도 13에 의한 기판(S) 상부에 질화티타늄 막(202)을 형성한다. 앞서 설명한 바와 같이 상기 기판(S)은 다수의 막을 포함한 기판일 수도 있다. 예컨대 상기 질화티타늄 막(202)은 염화티타늄(TiCl4)및 암모니아(NH3)를 사용하는 열(thermal) 화학기상증착(CVD) 공정에 의하여 형성될 수 있다.Referring to FIG. 14, a titanium nitride film 202 is formed on the substrate S shown in FIG. 13. As described above, the substrate S may be a substrate including a plurality of films. For example, the titanium nitride film 202 may be formed by a thermal chemical vapor deposition (CVD) process using titanium chloride (TiCl 4 ) and ammonia (NH 3 ).
보다 상세히, 예를 들면, 먼저 기판(S)을 예열한 다음, 질소(N2)가스 등을 이용하여 퍼지한다. 다음으로, 반응 가스로서 염화티타늄(TiCl4)및 암모니아(NH3)를 사용하여 기판(S) 상에 소정의 두께로 질화티타늄 막(202)을 형성한다. 그런 다음, 미반응 가스가 방출되도록 질소(N2)가스 등을 이용하여 퍼지한 다음, 암모니아(NH3)가스를 추가적으로 주입하여 형성된 질화티타늄 막(202)에 잔류하는 미반응된 Ti-Cl 결합을 질화(nitridation)시키고, 질화티타늄 막(202)에 잔류할 수 있는 염소(Cl) 등 불순물을 외부로 방출시킨다.In more detail, for example, first, the substrate S is preheated, and then purged using nitrogen (N 2 ) gas or the like. Next, using titanium chloride (TiCl 4 ) and ammonia (NH 3 ) as the reaction gas, a titanium nitride film 202 is formed on the substrate S at a predetermined thickness. Then, purged with nitrogen (N 2 ) gas or the like to release the unreacted gas, and then unreacted Ti-Cl bond remaining in the titanium nitride film 202 formed by additional injection of ammonia (NH 3 ) gas. Is nitrided and impurities such as chlorine (Cl) that may remain in the titanium nitride film 202 are released to the outside.
한편, 상기 질화티타늄 막(202)은 비저항을 증가시키기 위해서, 질화티타늄 베이스 막(도시안됨) 및 그 상부에 형성되는 하나 이상의 도전성 캐핑막(도시안됨) 등으로 형성될 수도 있다. 이 경우, 상기 질화티타늄 베이스 막(도시안됨)은 앞서 설명한 방법으로 형성될 수 있으며, 상기 도전성 캐핑막(도시안됨)은 원자층 증착법(ALD)에 의해 형성될 수 있다.Meanwhile, the titanium nitride film 202 may be formed of a titanium nitride base film (not shown) and one or more conductive capping films (not shown) formed thereon in order to increase specific resistance. In this case, the titanium nitride base film (not shown) may be formed by the method described above, and the conductive capping film (not shown) may be formed by atomic layer deposition (ALD).
도 15는 도 12에서 도시된 질화티타늄 막을 패터닝하는 단계 이후를 도시한 단면도이다.FIG. 15 is a cross-sectional view after the step of patterning the titanium nitride film shown in FIG. 12.
도 15를 참조하면, 이러한 질화티타늄 막을 패터닝하여, 예컨대 배리어 막(202a)을 형성한다. 이러한 배리어 막(202a)은, 이후 형성될 콘택 플러그(도 19의 205)를 구성하는 금속, 예컨대 알루미늄(Al)이 상기 절연막으로 확산되는 것을 방지한다.Referring to FIG. 15, such a titanium nitride film is patterned to form, for example, a barrier film 202a. This barrier film 202a prevents the diffusion of the metal, such as aluminum (Al), that constitutes the contact plug (205 in FIG. 19) to be formed later into the insulating film.
한편, 캐패시터의 전극을 형성하기 위한 전극막(도시안됨)을 형성할 수도 있다.On the other hand, an electrode film (not shown) for forming the electrode of the capacitor may be formed.
도 16은 도 12에서 도시된 실리콘 막을 형성하는 단계 이후를 도시한 단면도이다.16 is a cross-sectional view after the step of forming the silicon film shown in FIG.
도 16을 참조하면, 배리어 막(202a)이 형성된 상기 기판(S) 상부에 실리콘 막(203)을 형성한다. 예컨대 상기 실리콘 막(203)은 아몰퍼스 실리콘 또는 폴리 실리콘으로 형성될 수 있다. 이러한 실리콘 막(203)은 통상의 화학기상증착(CVD)법을 이용하여 형성될 수 있다.Referring to FIG. 16, a silicon film 203 is formed on the substrate S on which the barrier film 202a is formed. For example, the silicon film 203 may be formed of amorphous silicon or polysilicon. The silicon film 203 may be formed using a conventional chemical vapor deposition (CVD) method.
한편, 이러한 실리콘 막(203)은 쉽게 산화되어 표면에 실리콘 산화막(도시안됨)이 생성될 수 있다. 이와 같이 실리콘 산화막이 생성된 경우, 이를 제거하여야 한다. 왜냐하면, 본 발명에 의한 반도체 제조방법에서 적용되는 실리콘 막을 식각하는 공정에서는 실리콘 산화막과 실리콘 막이 높은 식각비를 갖기 때문이다. 즉, 실리콘 막은 용이하게 식각되는 반면, 실리콘 산화막은 쉽게 식각되지 않기 때문에, 상기 실리콘 막을 패터닝하기 위해 식각할 때, 상기 실리콘 막 상부에 실리콘 산화막이 형성된 경우, 용이하게 식각되지 않기 때문이다.Meanwhile, the silicon film 203 may be easily oxidized to generate a silicon oxide film (not shown) on the surface. If the silicon oxide film is thus produced, it must be removed. This is because the silicon oxide film and the silicon film have a high etching ratio in the process of etching the silicon film used in the semiconductor manufacturing method according to the present invention. That is, since the silicon film is easily etched, while the silicon oxide film is not easily etched, when the silicon oxide film is formed on the silicon film when etching to pattern the silicon film, it is not easily etched.
도 17은 도 12에서 도시된 실리콘 산화막을 제거하는 단계 이후를 도시한 단면도이다.FIG. 17 is a cross-sectional view illustrating a process after removing the silicon oxide film illustrated in FIG. 12.
도 17을 참조하면, 실리콘 산화막(204)을 제거하기 위해서, 상기 실리콘 산화막(204)에 불화수소(HF) 가스(G1) 및 암모니아(NH3)가스(G1)를 공급함으로써 상기 실리콘 산화막(204)을 제거할 수 있다. 이러한 공정은 도 9에 대응하는 설명과 실질적으로 동일하므로, 상세한 설명은 생략한다.Referring to FIG. 17, in order to remove the silicon oxide film 204, the silicon oxide film 204 is supplied by supplying hydrogen fluoride (HF) gas (G1) and ammonia (NH 3 ) gas (G1) to the silicon oxide film 204. ) Can be removed. Since this process is substantially the same as the description corresponding to FIG. 9, the detailed description is omitted.
도 18은 도 12에서 도시된 실리콘 막을 식각하는 단계 이후를 도시한 단면도이다.18 is a cross-sectional view illustrating a step after etching the silicon film illustrated in FIG. 12.
도 18을 참조하면, 스위칭 소자의 활성층 또는 다이오드 형성을 위해서 실리콘 막의 존재를 요하는 부분을 제외하고, 실리콘 막을 식각한다. Referring to FIG. 18, the silicon film is etched except for a portion that requires the presence of the silicon film to form an active layer or a diode of the switching device.
따라서, 실리콘 막(도 17의 203)의 식각시에는 실리콘 산화막(204) 및 질화 티타늄 패턴(202a)와 실리콘의 고 선택비인 조건이 요구된다.Therefore, when etching the silicon film (203 in FIG. 17), a condition in which the silicon oxide film 204 and the titanium nitride pattern 202a and silicon have a high selectivity is required.
따라서, 본 실시예에서는, 실리콘 산화막(도 17의 204)이 제거된 상기 실리콘 막(도 17의 203)에 삼불화염소(ClF3)가스(G2)를 공급하여 상기 상기 실리콘 막(도 17의 203)을 식각한다. 이러한, 삼불화염소(ClF3)가스를 이용한 식각 등의 기상 식각의 경우 액상식각에서와 같은 수소 및 탄소의 농도에 의존하는 반응 메카니즘이 존재 하지 않으므로 산화막 종류에 관계없이 고 식각비를 가질 수 있다.Therefore, in this embodiment, the chlorine trifluoride (ClF 3 ) gas G2 is supplied to the silicon film (203 in FIG. 17) from which the silicon oxide film (204 in FIG. 17) has been removed, thereby providing the silicon film ( 203). In the case of gaseous etching such as etching using chlorine trifluoride (ClF 3 ) gas, there is no reaction mechanism that depends on the concentration of hydrogen and carbon as in liquid etching, and thus may have a high etching ratio regardless of the type of oxide film. .
이때의 반응 메커니즘은 다음과 같다.The reaction mechanism at this time is as follows.
4ClF3+3Si-->2Cl2(g) + 3SiF4(g)4ClF 3 + 3Si-> 2Cl 2 (g) + 3SiF 4 (g)
또한, 상기 삼불화염소(ClF3)가스를 공급하기 전에, 상기 삼불화염소(ClF3)가스를 희석할 수 있으며, 이때, 상기 삼불화염소(ClF3)가스는 질소(N2)가스에 의해 희석될 수 있다. 예컨대, 상기 삼불화염소(ClF3)가스는 1 내지 3000 sccm, 상기 질소(N2)가스는 100 내지 3000 sccm으로 공급하여 식각을 진행할 수 있다. 예컨대, 상기 실리콘 막(도 17의 203)을 식각하는 공정은, 300m torr 내지 20 torr의 압력하에서 진행될 수 있다.In addition, before supplying the chlorine trifluoride (ClF 3 ) gas, the chlorine trifluoride (ClF 3 ) gas may be diluted, wherein the chlorine trifluoride (ClF 3 ) gas to the nitrogen (N 2 ) gas Can be diluted. For example, the chlorine trifluoride (ClF 3 ) gas may be 1 to 3000 sccm, and the nitrogen (N 2 ) gas may be supplied at 100 to 3000 sccm to perform etching. For example, the process of etching the silicon film 203 of FIG. 17 may be performed under a pressure of 300 m torr to 20 torr.
이때, 상기 질화티타늄(TiN)이 노출되는 경우, 상기 기판(S)은 -76 내지 70의 범위 내로 유지시킨다. -76 보다 낮은 경우, 챔버 내의 진공상태에서 예컨대 삼불화염소(ClF3)가스가 액화될 수 있으며, 70 보다 높은 경우, 상기 질화티타늄 패턴이 식각될 수 있다. 따라서, 상기 실리콘 막을 식각하는 과정에서 상기 기판은 -76 내지 70의 범위 내로 유지시키는 것이 바람직하다.At this time, when the titanium nitride (TiN) is exposed, the substrate (S) is maintained in the range of -76 to 70. If lower than -76, for example, chlorine trifluoride (ClF 3 ) gas may be liquefied in a vacuum in the chamber, and if higher than 70, the titanium nitride pattern may be etched. Therefore, it is preferable to keep the substrate within the range of -76 to 70 in the process of etching the silicon film.
도 20을 참조하면, 기판의 온도를 40로 유지시키고, 앞서 설명한 식각공정을 진행한 경우, 아몰퍼스 실리콘 및 폴리 실리콘 5000 만큼 식각되는 동안에도 질화티타늄막의 두께 변화는 거의 없는 것을 확인할 수 있다. 즉, 질화티타늄은 식각되지 않는다.Referring to FIG. 20, when the temperature of the substrate is maintained at 40 and the etching process described above is performed, there is almost no change in the thickness of the titanium nitride film even during etching of amorphous silicon and polysilicon 5000. That is, titanium nitride is not etched.
도 21을 참조하면, 온도를 60로 유지시키고, 앞서 설명한 식각 공정을 진행한 경우, 질화티타늄막의 색상(노란색) 변화가 거의 없는 것을 볼 수 있으며, 식각 전후의 질화티타늄막의 면저항의 변화가 거의 없는 것을 확인할 수 있다.Referring to FIG. 21, when the temperature is maintained at 60 and the etching process described above is performed, there is little change in color (yellow) of the titanium nitride film, and there is almost no change in sheet resistance of the titanium nitride film before and after etching. You can see that.
즉, 좌측 그림은 실리콘 식각공정을 곧바로 진행한 상황이고, 우측 그림은 산화막 제거공정을 진행하고, 이후 실리콘 식각공정을 진행한 상황이다. 상부의 그림은 공정의 진행전의 그림이고, 하부의 그림은 공정 진행후의 그림이다.In other words, the figure on the left shows a situation in which the silicon etching process is immediately performed, and the figure on the right shows an oxide removal process and the silicon etching process. The upper figure is the figure before the process progression, and the lower figure is the figure after the process progression.
실리콘 식각공정을 곧바로 진행한 경우, 면저항은 첫 번째 샘플이 식각공정 전에 28.28/sq 이었고, 식각 후 제1차 측정시 28.49/sq, 제2차 측정시 29.28/sq, 제3차 측정시 28.90/sq으로 측정되었고, 두 번째 샘플이 식각공정 전에 25.96/sq 이었고, 식각 후 제1차 측정시 26.54/sq, 제2차 측정시 26.57/sq, 제3차 측정시 29.05/sq으로 측정되어 변화가 거의 없음을 볼 수 있다.When the silicon etching process was performed immediately, the sheet resistance was 28.28 / sq for the first sample before the etching process, 28.49 / sq for the first measurement after etching, 29.28 / sq for the second measurement, and 28.90 / for the third measurement. measured in sq, the second sample was 25.96 / sq before the etching process, 26.54 / sq for the first measurement after the etching, 26.57 / sq for the second measurement, and 29.05 / sq for the third measurement. You can see almost nothing.
산화막 제거공정을 진행하고, 이후 실리콘 식각공정을 진행한 경우, 면저항은 첫 번째 샘플이 식각공정 전에 29.02/sq 이었고, 식각 후 제1차 측정시 30.64/sq, 제2차 측정시 29.35/sq, 제3차 측정시 31.88/sq으로 측정되었고, 두 번째 샘플이 식각공정 전에 26.07/sq 이었고, 식각 후 제1차 측정시 27.60/sq, 제2차 측정시 27.95/sq, 제3차 측정시 27.40/sq으로 측정되어 변화가 거의 없음을 볼 수 있다.In the case of performing the oxide film removal process and then performing the silicon etching process, the sheet resistance was 29.02 / sq in the first sample before the etching process, 30.64 / sq in the first measurement after etching, 29.35 / sq in the second measurement, 31.88 / sq at the 3rd measurement, the second sample was 26.07 / sq before the etching process, 27.60 / sq at the 1st measurement after etching, 27.95 / sq at the 2nd measurement, 27.40 at the 3rd measurement Measured as / sq, we see little change.
도 22를 참조하면, 온도를 80로 유지시키고, 앞서 설명한 식각공정을 진행한 경우, 질화티타늄막의 색상(노란색) 변화가 확연한 것을 볼 수 있으며, 식각 전후의 질화티타늄막의 면저항의 변화가 커진 것을 확인할 수 있다.Referring to FIG. 22, when the temperature is maintained at 80 and the etching process described above is performed, it can be seen that the color (yellow) change of the titanium nitride film is obvious, and the change in the sheet resistance of the titanium nitride film before and after etching is increased. Can be.
즉, 좌측 그림은 실리콘 식각공정을 곧바로 진행한 상황이고, 우측 그림은 산화막 제거공정을 진행하고, 이후 실리콘 식각공정을 진행한 상황이다. 상부의 그림은 공정의 진행전의 그림이고, 하부의 그림은 공정 진행후의 그림이다.In other words, the figure on the left shows a situation in which the silicon etching process is immediately performed, and the figure on the right shows an oxide removal process and the silicon etching process. The upper figure is the figure before the process progression, and the lower figure is the figure after the process progression.
실리콘 식각공정을 곧바로 진행한 경우, 면저항은 첫 번째 샘플이 식각공정 전에 28.97/sq 이었고, 식각 후 제1차 측정시 측정이 불가능하였고, 제2차 측정시 36.05/sq, 제3차 측정시 37.55/sq으로 측정되었고, 두 번째 샘플이 식각공정 전에 42.70/sq 이었고, 식각 후 제1차 측정시 측정이 불가능하였고, 제2차 측정시 53.83/sq, 제3차 측정시 측정이 불가능하여 변화가 매우 큰 것을 볼 수 있다.When the silicon etching process was performed immediately, the sheet resistance was 28.97 / sq in the first sample before the etching process, and it was impossible to measure in the first measurement after etching, 36.05 / sq in the second measurement, and 37.55 in the third measurement. / sq was measured, the second sample was 42.70 / sq before the etching process, the measurement was impossible at the first measurement after etching, the 53.83 / sq at the second measurement, and the measurement was impossible at the third measurement. You can see a very big one.
산화막 제거공정을 진행하고, 이후 실리콘 식각공정을 진행한 경우, 면저항은 첫 번째 샘플이 식각공정 전에 31.16/sq 이었고, 식각 후 제1차 측정시 측정이 불가능하였고, 제2차 측정시 27.09k/sq, 제3차 측정시 8.544k/sq으로 측정되었고, 두 번째 샘플이 식각공정 전에 26.44/sq 이었고, 측정이 불가능하였다.In the case of performing the oxide film removal process and then performing the silicon etching process, the sheet resistance was 31.16 / sq before the first sample, and the measurement was impossible at the first measurement after etching, and 27.09k / at the second measurement. sq, measured at 8.544 k / sq in the third measurement, the second sample was 26.44 / sq before the etching process, and measurement was not possible.
한편, 상기 기판(S)을 -76 내지 70의 범위 내로 유지시키기 위해서, 상기 기판을 지지하는 서셉터 등의 기판 지지대를 이용할 수도 있고, 이와 다르게, 상기 실리콘 막을 형성하기 이전에, 쿨링 챔버로 이송하여 상기 기판(S)을 상기 온도 범위로 낮출 수 있다. 이때, 상기 쿨링 챔버는 상기 실리콘 막의 식각 공정에서 온도 상승을 고려하여 기판(S)의 온도를 상기 온도보다 낮은 온도로 유지시킨다.On the other hand, in order to keep the substrate S in the range of -76 to 70, a substrate support such as a susceptor for supporting the substrate may be used, or alternatively, before the silicon film is formed, it is transferred to a cooling chamber. The substrate S can be lowered to the temperature range. In this case, the cooling chamber maintains the temperature of the substrate S at a temperature lower than the temperature in consideration of the temperature rise in the etching process of the silicon film.
이와 같이, 실리콘 식각시에 기판을 -76 내지 70의 범위 내로 유지시키는 경우, 질화티타늄(TiN) 패턴이 식각되어 데이지가 가해짐이 없이 아몰퍼스 실리콘 막 또는 폴리 실리콘 막을 식각할 수 있다.As such, when the substrate is held within the range of −76 to 70 during silicon etching, the titanium nitride (TiN) pattern may be etched to etch the amorphous silicon film or the polysilicon film without applying a daisy.
도 19는 도 18에서 도시된 배리어 막에 콘택 플러그를 형성한 것을 도시한 단면도이다.FIG. 19 is a cross-sectional view of a contact plug formed on the barrier film illustrated in FIG. 18.
도 19를 참조하면, 상기 배리어 막(202a)이 형성된 기판(S)에 도전성이 좋은 금속막(도시안됨)을 형성하고 이를 패터닝하여, 콘택 플러그(205)를 형성한다. 예컨대 상기 콘택 플러그(205)는 알루미늄(Al)으로 형성될 수 있다.Referring to FIG. 19, a highly conductive metal film (not shown) is formed on the substrate S on which the barrier film 202a is formed and patterned to form a contact plug 205. For example, the contact plug 205 may be formed of aluminum (Al).
이상에서는 질화티타늄 패턴의 형상이 도 15에서 도시된 형태인 경우를 예를 들어 설명하였다. 이하, 도 23, 도 25 및 도 27의 다양한 형태인 경우에도 마찬가지 공정이 적용될 수 있다.In the above, the case where the shape of the titanium nitride pattern is the form shown in FIG. 15 has been described as an example. Hereinafter, the same process may be applied to the various forms of FIGS. 23, 25, and 27.
도 23은 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부에만 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이고, 도 24는 도 23에서 실리콘층이 식각된 모습을 도시한 단면도이다. 도 25는 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부 및 홀 내측의 측면에 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이고, 도 26은 도 25에서 실리콘층이 식각된 모습을 도시한 단면도이다. 도 27은 질화티타늄막을 패터닝하여 형성된 질화티타늄 패턴이 홀 내측의 하부에 형성되고 및 홀 내측의 측면에는 실리콘 질화막이 형성되고, 그 상부에 실리콘층이 형성된 모습을 도시한 단면도이고, 도 28은 도 27에서 실리콘층이 식각된 모습을 도시한 단면도이다.FIG. 23 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed only on a lower portion of an inside of a hole, and a silicon layer formed on an upper portion thereof, and FIG. 24 illustrates a silicon layer being etched in FIG. 23. It is a cross section. FIG. 25 is a cross-sectional view of a titanium nitride pattern formed by patterning a titanium nitride film formed on a lower side of a hole and a side surface of an inside of a hole, and a silicon layer formed on an upper portion thereof. FIG. It is a cross-sectional view showing the appearance. FIG. 27 is a cross-sectional view illustrating a titanium nitride pattern formed by patterning a titanium nitride film, a silicon nitride film formed on a lower side of a hole, and a silicon layer formed on a side of the hole, and FIG. 28. 27 is a cross-sectional view showing the silicon layer is etched.
먼저, 도 23, 25 및 27을 참조하면, 절연막(302)의 홀 내부에 형성된 실리콘 막(301) 상부에 자연적으로 형성된 실리콘 산화막(도시안됨)을 제거한다. 이 공정은 앞서 설명한 바와 같이 불화수소 가스 및 암모니아 가스를 공급함으로써 진행될 수 있다. 이후, 동일 챔버 내에서, 삼불화염소(ClF3)를 공급하여, 각각 도 24, 26, 28에서 도시된 바와 같이, 실리콘 막(301)을 식각한다.First, referring to FIGS. 23, 25, and 27, the silicon oxide film (not shown) naturally formed on the silicon film 301 formed inside the hole of the insulating film 302 is removed. This process can proceed by supplying hydrogen fluoride gas and ammonia gas as described above. Thereafter, in the same chamber, chlorine trifluoride (ClF 3 ) is supplied to etch the silicon film 301, as shown in FIGS. 24, 26, and 28, respectively.
이때, 도 23에서 도시된 바와 같이 질화티타늄 패턴(301)이 상기 절연막(302)의 홀 내측 하부에만 형성되어 있거나, 도 27에서 도시된 바와 같이, 질화티타늄 패턴(301)이 상기 절연막(302)의 홀 내측 하부에 형성되고, 홀 내측의 측면에는 실리콘 질화막(304)이 형성된 경우, 형성실리콘 막(301)의 식각공정에서 질화티타늄 패턴(301)이 노출되기 전까지 70 내지 80의 범위 내로 유지하고, 이후, 질화티타늄 패턴(301)이 노출되는 경우, 앞서 설명한 바와 같이, -76 내지 70의 범위 내로 유지시킨다.In this case, as shown in FIG. 23, the titanium nitride pattern 301 is formed only on the lower inner side of the hole of the insulating film 302, or as shown in FIG. 27, the titanium nitride pattern 301 is formed of the insulating film 302. If the silicon nitride film 304 is formed on the inner side of the hole, the silicon nitride film 304 is formed in the lower side of the hole, and maintained within the range of 70 to 80 until the titanium nitride pattern 301 is exposed in the etching process of the formed silicon film 301. After that, when the titanium nitride pattern 301 is exposed, as described above, the titanium nitride pattern 301 is maintained in the range of -76 to 70.
그러나, 도 25에서 도시된 바와 같이, 실리콘 막(303)의 식각 초기부터 질화티타늄 패턴(301)이 노출되는 경우에는 처음부터 -76 내지 70의 범위 내로 유지하여야 질화티타늄 패턴(301)이 식각되는 것을 방지할 수 있다.However, as shown in FIG. 25, when the titanium nitride pattern 301 is exposed from the initial etching of the silicon film 303, the titanium nitride pattern 301 is etched only when the titanium nitride pattern 301 is exposed within the range of -76 to 70 from the beginning. Can be prevented.
앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 바람직한 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.
앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 바람직한 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (17)

  1. 기판에 실리콘층을 형성하는 단계;Forming a silicon layer on the substrate;
    실리콘층 상부에 포토레지스트막을 형성하는 단계;Forming a photoresist film on the silicon layer;
    상기 포토레지스트막을 노광하는 단계;Exposing the photoresist film;
    노광된 상기 포토레지스트막을 현상하는 단계;Developing the exposed photoresist film;
    현상된 상기 포토레지스트막을 마스크로 이용하여 상기 실리콘층에 패턴을 형성하는 단계;Forming a pattern on the silicon layer using the developed photoresist film as a mask;
    상기 포토레지스트막을 제거하는 단계; Removing the photoresist film;
    절연막을 형성하는 단계; 및Forming an insulating film; And
    상기 실리콘 기판에 형성된 패턴을 트리밍하는 단계를 포함하는 반도체소자 제조방법.A semiconductor device manufacturing method comprising the step of trimming the pattern formed on the silicon substrate.
  2. 제1항에 있어서, 상기 절연막을 형성한 후,The method of claim 1, wherein after forming the insulating film,
    상기 패턴을 노출시키기 위해서, 상기 절연막의 일부를 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.And removing a portion of the insulating film to expose the pattern.
  3. 제2항에 있어서,The method of claim 2,
    상기 절연막은 실리콘 산화막이고,The insulating film is a silicon oxide film,
    상기 절연막의 일부를 제거하는 단계는,Removing a portion of the insulating film,
    상기 절연막에 불화수소(HF) 가스 및 암모니아(NH3)가스를 공급하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조방법.And supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the insulating film.
  4. 제3항에 있어서,The method of claim 3,
    상기 절연막의 일부를 제거하는 단계는,Removing a portion of the insulating film,
    상기 절연막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.And removing by-products generated by the reaction between the insulating film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas.
  5. 제4항에 있어서,The method of claim 4, wherein
    상기 부산물을 제거하는 단계는 램프를 이용한 히팅(heating) 방법에 의한 것을 특징으로 하는 반도체소자 제조방법.Removing the by-products is a semiconductor device manufacturing method, characterized in that by the heating (heating) method using a lamp.
  6. 제5항에 있어서,The method of claim 5,
    상기 히팅 방법에 의해 부산물을 제거한 후, 상기 기판을 냉각 챔버로 이송하여 냉각하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.Removing the by-products by the heating method, and transferring the substrate to a cooling chamber to cool the semiconductor device.
  7. 제1항에 있어서,The method of claim 1,
    상기 트리밍하는 단계는,The trimming step,
    절연막이 일부 제거된 상기 기판에 삼불화염소(ClF3)가스를 공급하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조방법.And supplying chlorine trifluoride (ClF 3 ) gas to the substrate on which the insulating film is partially removed.
  8. 제7항에 있어서,The method of claim 7, wherein
    상기 삼불화염소(ClF3)가스를 공급하기 전에, 상기 삼불화염소(ClF3)가스를 희석하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.The chlorine trifluoride (ClF 3) prior to the gas supply, the chlorine trifluoride (ClF 3) method of manufacturing a semiconductor device the step of diluting the gas, characterized in that it further comprises.
  9. 제8항에 있어서,The method of claim 8,
    상기 삼불화염소(ClF3)는 질소(N2)가스에 의해 희석되고,The chlorine trifluoride (ClF 3 ) is diluted by nitrogen (N 2 ) gas,
    상기 삼불화염소(ClF3)가스는 1 내지 30 sccm, 상기 질소(N2)가스는 100 내지 1000 sccm으로 공급하는 것을 특징으로 하는 반도체소자 제조방법.The chlorine trifluoride (ClF 3 ) gas is 1 to 30 sccm, the nitrogen (N 2 ) gas is a semiconductor device manufacturing method, characterized in that for supplying at 100 to 1000 sccm.
  10. 제9항에 있어서,The method of claim 9,
    상기 트리밍하는 단계는,The trimming step,
    300m torr 내지 8 torr의 압력하에서 진행되는 것을 특징으로 하는 반도체소자 제조방법.A method of manufacturing a semiconductor device, characterized in that proceeds under a pressure of 300m torr to 8 torr.
  11. 제1항에 있어서,The method of claim 1,
    상기 절연막을 제거한 후, 진공 상태를 깨지 않고 상기 트리밍하는 단계가 연속적으로 진행하는 것을 특징으로 하는 반도체소자 제조방법.Removing the insulating film and then continuing the trimming without breaking the vacuum.
  12. 기판에 질화티타늄(TiN) 막을 형성하는 단계;Forming a titanium nitride (TiN) film on the substrate;
    질화티타늄(TiN) 막을 패터닝하는 단계;Patterning a titanium nitride (TiN) film;
    패터닝된 질화티타늄(TiN)이 형성된 기판에 실리콘 막을 형성하는 단계; 및Forming a silicon film on a substrate on which patterned titanium nitride (TiN) is formed; And
    삼불화염소(ClF3)가스를 이용하여 상기 실리콘 막을 식각하는 단계를 포함하고,Etching the silicon film using chlorine trifluoride (ClF 3 ) gas,
    상기 실리콘 막을 식각하는 단계에서, 상기 질화티타늄(TiN)이 노출되는 경우, 상기 기판은 -76 내지 70의 범위 내로 유지시키는 것을 특징으로 하는 반도체소자 제조방법.In the etching of the silicon film, when the titanium nitride (TiN) is exposed, the substrate is maintained in the range of -76 to 70, characterized in that the semiconductor device manufacturing method.
  13. 제12항에 있어서, 상기 실리콘 막을 식각하는 단계에서, The method of claim 12, wherein in the etching of the silicon film,
    상기 질화티타늄이 노출되지 않는 경우, 상기 기판은 70 내지 80의 범위 내로 유지시키는 것을 특징 것을 특징으로 하는 반도체소자 제조방법.If the titanium nitride is not exposed, the substrate is a semiconductor device manufacturing method, characterized in that maintained in the range of 70 to 80.
  14. 제12항에 있어서, 상기 실리콘 막을 식각하는 단계 이전에,The method of claim 12, prior to etching the silicon film,
    상기 기판을 쿨링챔버로 이송하여, 상기 쿨링 챔버에서 상기 기판의 온도를 낮추는 것을 특징으로 하는 반도체소자 제조방법.And transferring the substrate to a cooling chamber to lower the temperature of the substrate in the cooling chamber.
  15. 제12항에 있어서, 상기 실리콘 막을 형성하는 단계 이후,The method of claim 12, after the forming of the silicon film,
    상기 실리콘 막에 자연적으로 형성되는 실리콘 산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.And removing the silicon oxide film formed naturally on the silicon film.
  16. 제15항에 있어서, 상기 실리콘 산화막을 제거하는 단계는,The method of claim 15, wherein removing the silicon oxide film comprises:
    상기 실리콘 산화막에 불화수소(HF) 가스 및 암모니아(NH3)가스를 공급하는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조방법.And supplying hydrogen fluoride (HF) gas and ammonia (NH 3 ) gas to the silicon oxide film.
  17. 제16항에 있어서, 상기 실리콘 산화막을 제거하는 단계는,The method of claim 16, wherein removing the silicon oxide layer comprises:
    상기 실리콘 산화막과 상기 불화수소(HF) 가스 및 상기 암모니아(NH3)가스가 반응하여 생성된 부산물을, 램프를 이용한 히팅(heating) 방법에 의해 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 제조방법.And removing by-products generated by the reaction between the silicon oxide film, the hydrogen fluoride (HF) gas, and the ammonia (NH 3 ) gas by a heating method using a lamp. Manufacturing method.
PCT/KR2012/010508 2011-12-07 2012-12-06 Method for manufacturing semiconductor device WO2013085290A1 (en)

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