WO2013084020A1

WO2013084020A1 - Normally-off high electron mobility transistor and integrated circuit

Info

Publication number: WO2013084020A1
Application number: PCT/IB2011/003327
Authority: WO
Inventors: Philippe Renaud; Christian CARAMEL; Yvon Cordier
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2011-12-09
Filing date: 2011-12-09
Publication date: 2013-06-13

Abstract

A normally-off high electron mobility transistor (20) comprises a channel layer (22), a barrier layer (24), a cap layer (26, 48, 76) and a gate electrode (28). The barrier layer comprises a first III-nitride and is located over the channel layer. The channel layer comprises a second III-nitride and comprises a conductive channel with a two-dimensional electron gas at least in a contact region with the barrier layer. The cap layer is located between the gate electrode and the barrier layer and comprises a material causing a change of charge distribution in the barrier layer depending on a thickness of the cap layer. A ratio of the thickness of the cap layer and a thickness of the barrier layer is selected such that the change of charge distribution causes an interruption in the conductive channel, and the gate electrode is operable to reverse the interruption in response to receiving a voltage.

Description

Title: Normally-off high electron mobility transistor and integrated circuit

Description Field of the invention

This invention relates to a normally-off high electron mobility transistor and an integrated circuit.

Background of the invention

A high electron mobility transistor (HEMT) is a field effect transistor wherein a heterojunction instead of a doped region is used to generate a conductive channel. A heterojunction may occur in a contact region of two layers of semiconductive materials having different bandgaps. A two- dimensional electron gas (2DEG) may be generated within that region, i.e., a gas of electrons free to move in two dimensions, but not in the third. A HEMT may be used as a switching device, for example, for high power applications, e.g, when a fast switching speed may be required.

As shown in FIG. 1 , a prior art HEMT may be normally-on. In the diagram, conduction band energy, measured in electron-volts (eV), vs. the vertical dimension Y, measured in micrometers (μΐη), of a prior art normally-on HEMT is shown. The HEMT may contain a silicon nitride (SiN) passivation layer in a first Y range 10, an aluminium gallium nitride (AIGaN) barrier layer in a second Y range 12 and a gallium nitride (GaN) layer in a third Y range 14. A 2DEG may be generated in a contact region 16, wherein curve 18 may correspond to the conduction band energy measured under a gate electrode of the HEMT, whereas curve 19 may refer to the conduction band energy at drain and source regions of the normally-on HEMT. It can be seen that at least the contact region 16 having the 2DEG may be a region where no energy is required for switching the HEMT device into a conductive state, i.e., due to the automatic generation of the conductive channel, a HEMT is usually a normally-on transistor device, where a voltage or current must be applied to the gate electrode to electrically interrupt a connection between source and drain electrodes. Summary of the invention

The present invention provides a normally-off high electron mobility transistor and an integrated circuit as described in the accompanying claims.

Specific embodiments of the invention are set forth in the dependent claims.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Brief description of the drawings

Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

FIG. 1 schematically shows a diagram of an example of conduction band energy vs. a vertical dimension of a prior art normally-on HEMT.

FIG. 2 schematically shows an example of a first embodiment of a normally-off high electron mobility transistor.

FIG. 3 schematically shows a diagram of a first example of conduction band energy vs. a vertical dimension of a normally-off HEMT.

FIG. 4 schematically shows a diagram of an example of a threshold voltage vs. a thickness of a GaN cap of a normally-off HEMT.

FIG. 5 schematically shows a diagram of an example of a 2DEG concentration vs. a thickness of a GaN cap of a normally-off HEMT.

FIG. 6 schematically shows a diagram of a first example of a 2DEG concentration vs. a gate voltage of a normally-off HEMT.

FIG. 7 schematically shows a diagram of a second example of a 2DEG concentration vs. a gate voltage of a normally-off HEMT.

FIG. 8 schematically shows an example of a second embodiment of a normally-off high electron mobility transistor.

FIG. 9 schematically shows a diagram of a second example of conduction band energy vs. the vertical dimension of a normally-off HEMT.

FIG. 10 schematically shows a diagram of an example of a threshold voltage vs. a drain current of a normally-off HEMT.

FIG. 1 1 schematically shows a diagram of an example of a drain current vs. a drain voltage of a normally-off HEMT.

FIG. 12 schematically shows a diagram of an example of a drain current vs. a gate voltage.

FIG. 13 schematically shows an example of a third embodiment of a normally-off high electron mobility transistor.

FIG. 14 schematically shows an example of an embodiment of an integrated circuit comprising a normally-off high electron mobility transistor.

Detailed description of the preferred embodiments

Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary, as illustrated, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Referring to FIG. 2, an example of a first embodiment of a normally-off high electron mobility transistor 20 (HEMT) is schematically shown. A normally-off high electron mobility transistor 20 comprises a channel layer 22, a barrier layer 24, a cap layer 26 and a gate electrode 28. The barrier layer 24 comprises a first Ill-nitride and is located over the channel layer 22. The channel layer 22 comprises a second Ill-nitride and comprises a conductive channel with a two-dimensional electron gas at least in a contact region with the barrier layer 24; and the cap layer 26 is located between the gate electrode 28 and the barrier layer 24 and comprises a material causing a change of charge distribution in the barrier layer 24 depending on a thickness of the cap layer 26; wherein a ratio of the thickness of the cap layer 26 and a thickness of the barrier layer 24 is selected such that the change of charge distribution causes an interruption in the conductive channel and wherein the gate electrode 28 is operable to reverse the interruption in response to receiving a voltage.

In many applications a normally-off HEMT device may be preferably used instead of a normally-on device. A normally-off HEMT 20 may allow to be compatible with existing systems such as inverters and gate drivers usually based on normally-off integrated circuits. Safety critical applications, such as, for example, automotive applications may often be built using normally-off devices in order to have a defined stable state for integrated circuits, for example, when an uninterrupted power supply cannot be guaranteed.

Thickness of a layer may refer to a vertical dimension or height of a layer of the HEMT. A layer may be a body of material disposed on another layer or a substrate carrying the layers of the HEMT.

A layer comprising an Ill-nitride may refer to a layer comprising aluminium nitride (AIN), gallium nitride (GaN), or indium nitride (InN), or an alloy comprising AIN, GaN or InN, such as, for example, aluminium gallium nitride (AIGaN) or indium aluminium nitride (InAIN). A second Ill-nitride and a first Ill-nitride may be different, i.e., may not refer to the same Ill-nitride.

The material of the cap layer 26 may have an effect on the barrier layer 24 energy or charge distribution that depends on the thickness of the cap layer 26 relative to the thickness of the barrier layer 24, which may cause an interruption in the conductive channel containing the 2DEG in the channel layer 22, i.e., it may interrupt an electrical connection between a source electrode 30 and a drain electrode 32 via the channel layer 22. This interruption may be encountered because the thickness of the cap layer may influence the conduction band.

The thickness of the cap layer 26 relative to the thickness of the barrier layer 24 may be chosen such that the conduction band energy is raised above Fermi level, at least in a region of the channel layer 22 located at least partly below the cap layer 26 and the gate electrode 28. The remaining region may be covered by a passivation layer 36, 38, for example, a silicon nitride (SiN) passivation layer. This passivation may allow to supply electrons and increase the drain current.

The material of the cap layer 26 may, for example, comprise a Ill-nitride. This may allow to generate the change of charge distribution in the barrier layer 24 by means of an additional heterojunction at the opposite side of the barrier layer 24. The material may, for example, comprise gallium nitride (GaN).

The first Ill-nitride, i.e., the material of the barrier layer 24, may, for example, be aluminium nitride. In another embodiment, the barrier layer 24 may comprise AIGaN with a high percentage of aluminium, for example AIGaN with at least 50% aluminium or even more than 75% aluminium. In yet another embodiment, aluminium indium nitride (AllnN) may be used. The barrier layer 24 may be thin. The barrier layer 24 may have a thickness of not more than 5 nm (nanometers). It may, for example, have a thickness of 2 or 3 nm.

Such a thin AIN barrier layer may help to create spontaneous polarization and, thereby, a quantum well within the contact region. The thick GaN cap may counterbalance this polarization and may create a reverse piezoelectric polarization resulting in a normally-off enhancement mode HEMT device.

In order to have the effect of interrupting the conductive channel in a contact region of the channel layer 22 and the barrier layer 24, the ratio of the thickness of the cap layer 26 and a thickness of the barrier layer 24 may be higher than 1 , i.e., the thickness or vertical dimension of the cap layer 26 may be greater than the thickness of the barrier layer 24. The ratio may, for example, be higher than 5 or higher than 10 or even higher. For example, the barrier layer shown in FIG. 2 may comprise AIN and may have a thickness of 2 nm or 3 nm and the cap layer 26 may comprise GaN and may have a thickness of 20 nm. In another embodiment, the thickness of the GaN cap layer may, for example, be 30 nm.

The thickness of the cap layer 26 may be greater or bigger than a thickness of the channel layer 22. For example, the channel layer 22 may consist of GaN and may have a thickness of about 10 nm, wherein a suitable corresponding GaN cap layer may have a thickness of about 20 nm, if the barrier layer is a thin AIN barrier layer having a thickness of, for example, not more than 3 nm.

The normally-off high electron mobility transistor 20 may comprise a buffer layer 34 carrying the channel layer 22.

The buffer layer 34 may comprise AIGaN with less than 10% aluminium, for example, between 1 % and 7% aluminium. In another embodiment, a GaN buffer layer may be used instead of an AIGaN buffer layer.

A normally-off HEMT with a GaN buffer may, for example, be produced by hetero-epitaxy of a GaN buffer on a substrate, followed by an AIN, AIGaN or AllnN barrier and a GaN cap layer under the gate electrode 28. Selective etching, either chemical, reactive, or by evaporation of the GaN cap or selective epitaxy of the GaN cap may be used to obtain a normally-off transistor.

Outside the gate region, the passivation layer 36, 38 may be used for passivation and for supplying electrons to the two-dimensional electron gas (2DEG) to promote a high drain current. The passivation layer 36, 38 may, for example, comprise silicon nitride (SiN).

Referring to FIG. 3, a diagram of a first example of conduction band energy, measured in electron-volts (eV) vs. a vertical dimension Y, measured in μΐη, of a normally-off HEMT is shown. The curve 41 , 43 may represent a measurement of conduction band energy close to the drain electrode, whereas the curve 45, 47 may represent a measurement under the gate electrode. The HEMT may contain a SiN passivation layer with, for example, 5- 10¹³ Cm ³ donor traps. The shown first Y range 40 may, therefore, correspond to the SiN passivation layer or a GaN cap layer, respectively. The second Y range 42 may correspond to an aluminium nitride (AIN) barrier layer, for example having a thickness of 3 nm, and a gallium nitride (GaN) channel layer may correspond to a third Y range 44, followed by fourth Y range 46 corresponding to an AIGaN buffer layer, for example comprising 7% aluminium. It can be seen that the conduction band energy under the gate is raised to values always above 0 eV, whereas next to the drain side under the passivation, a conductive channel having a 2DEG may exist. Due to the absence of a 2DEG under the gate, no conductive channel may exist that connects source and drain, and the HEMT may be normally-off.

Referring to FIG. 4, an experimental diagram realized by C/V measurement of an example of a threshold voltage vs. a thickness of a GaN cap of a normally-off HEMT is schematically shown. It can be seen that a threshold voltage corresponding to a gate voltage required to switching on a HEMT as shown, for example, in FIG. 2, may depend on a thickness of the cap layer. In the shown example, the HEMT may turn into a normally-off HEMT for a GaN cap layer thickness of at least 25 nm.

Referring to FIG. 5, an experimental diagram realized by C/V measurement of an example of a 2DEG concentration Ns vs. a thickness of a GaN cap, measured in nm, of a normally-off HEMT is schematically shown. Correspondingly to FIG. 4, it can be seen that with the 2DEG concentration may be reduced with increasing GaN cap layer thickness, wherein a GaN cap thickness of about 25 nm may at least nearly reduce the 2DEG to 0 and may interrupt a conductive channel between source and drain.

Referring to FIG. 6 and FIG. 7, an experimental diagram of a first example of a 2DEG density vs. a gate voltage of a normally-off HEMT and a diagram of a second example of a 2DEG density vs. a gate voltage of a normally-off HEMT are shown, wherein the first example may correspond to a HEMT with a GaN cap layer thickness of 2 nm, whereas the second example may correspond to a GaN cap layer thickness of 25 nm. It can be seen, for example, that the gate voltage Vg and, thereby, the threshold voltage Vt of the transistor may depend on the thickness of the cap layer for reducing the 2DEG density to 0 and interrupting the conductive channel.

Referring now to FIG. 8, an example of a second embodiment of a normally-off high electron mobility transistor is schematically shown. Only differences to the first embodiment of a normally-off high electron mobility transistor as shown in FIG. 2 may be explained in detail.

The shown normally-off high electron mobility transistor may have a cap layer 48, wherein the material of the cap layer 48 may comprise a dielectric. The dielectric may have confined within a charge, which may interact with the barrier layer 24 and the 2DEG in the conductive channel and may cause an interruption of the conductive channel. The dielectric may, for example, be an aluminium oxide such as Al₂0₃. The cap layer may, for example, additionally extend above the passivation layer 36, 38.

The gate electrode 50 may be a dual gate electrode and may, for example comprise a field plate 52. This may allow to increase a breakdown voltage with normally-off operation. A size of the field plate may be larger than a width of a gate well, for example, 2 μΐη compared to a gate well width of 0.5 μΐη. A dielectric cap layer may be thinner than a corresponding Ill-nitride cap layer. For example, a dielectric cap layer 48 may have a thickness of 5 nm to 20 nm for a HEMT structure with a 2 to 3 nm AIN barrier layer and a 10 nm GaN channel layer. A normally-off high electron mobility transistor may, for example, be used as a power transistor, since it may, for example, provide a high breakdown voltage, high current density and low on resistance. A normally-off HEMT may be used for power switches, for example for inverters, e.g., in electric or hybrid electric vehicles.

Referring to FIG. 9, a diagram of a second example of conduction band energy, measured in electron-volts (eV) vs. a vertical dimension Y, measured in μΐη, of a normally-off HEMT is schematically shown.

The diagram may refer to the second embodiment of a normally-off HEMT as shown in FIG. 8. Curve 55 may represent a measurement of conduction band energy close to the drain electrode, whereas curve 57 may represent a measurement under the gate electrode. The shown first Y range 54 may correspond to an Al₂0₃ cap layer. The second Y range 56 may correspond to an aluminium nitride (AIN) barrier layer, for example having a thickness of 3 nm, and a gallium nitride (GaN) channel layer may correspond to a third Y range 58, followed by fourth Y range 60 corresponding to an AIGaN buffer layer, for example comprising 7% aluminium. It can be seen that the conduction band energy under the gate is raised to values always above 0 eV. The HEMT may be normally-off under the gate due to the high Al₂0₃ bandgap and the presence of negative fixed charges in the dielectric, whereas next to the drain side under the passivation, a conductive channel having a 2DEG exists. Due to the absence of a 2DEG under the gate, no conductive channel may exist that may connect source and drain, and the HEMT may be normally-off.

Referring to FIG. 10, a diagram of an example of a drain current Id versus gate voltage Vg of a normally-off HEMT is schematically shown. A drain voltage Vd may, for example, be 10V. It can be seen that a drain current Id measured in amperes per gate millimeters may depend on a gate voltage Vg, as a threshold voltage is defined when the drain current increases. Here, a positive threshold voltage Vt of 2V is demonstrated, making the device non-conductive at Vg=0, i.e., a normally-off device.

Referring to FIG. 1 1 , a diagram of an example of a drain current vs. a drain voltage of a normally-off HEMT is schematically shown for different gate voltages 2 V, 4 V, 6 V and 8 V corresponding to characteristic curves 62, 64, 66 and 68. Drain current Id may only flow if Vg exceeds 2V.

Referring to FIG. 12, an experimental diagram of an example of a drain current vs. a gate voltage is shown, measured for a Schottky gate contact 70, which may comprise nickel, platinum or titanium compared to a 10 nm Al₂0₃ metal insulator semiconductor 72. It can be seen that the charges in the Al₂0₃ dielectric may lead to a shift of the threshold voltage Vt and the required gate voltage. This may lead to a positive Vt in the case of a thin AIN barrier layer, whereas the Schottky metal contact Vt may be too far away from 0 to shift it to a positive value.

Referring to FIG. 13, an example of a third embodiment of a normally-off high electron mobility transistor is schematically shown. Only differences to the second and the first embodiments of a normally-off high electron mobility transistor as shown in FIG. 8 and FIG. 2 may be explained in detail. Here, the normally-off high electron mobility transistor may comprise a dielectric layer 74 between the cap layer 76 and the gate electrode 50, i.e. the dielectric layer 74 may not be regarded as the cap layer itself but may be located on top of the cap layer 76. The dielectric layer 74 may, for example, comprise Al₂0₃. The cap layer 76 may, for example, comprise a Ill-nitride, such as GaN.

Here, the ratio of the thickness of the cap layer 76 and the thickness of the barrier layer 24 may, for example, be equal to or lower than 1. As shown in FIG. 13, in the case of a dielectric layer 74, e.g., an Al₂0₃ layer, the cap layer 76, e.g. a GaN layer, may be thinner than the barrier layer 24, e.g., an AIN barrier layer, and may still cause an interruption in the conductive channel of the transistor, i.e. a presence of an additional dielectric layer 74, even a very thin dielectric layer, on top of the cap layer 76 may allow to reduce the thickness of the cap layer 76 and still cause an interruption in the conductive channel.

Referring to FIG. 14, an example of an embodiment of an integrated circuit 78 comprising a normally-off high electron mobility transistor 20 is schematically shown. The shown integrated circuit 74 may comprise at least one normally-off high electron mobility transistor 20 as described before. It may, for example, be comprised in a safety critical system, such as an automotive safety critical system, whose possible malfunction or wrong usage may endanger, for example, a user of the system, e.g. a car driver.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

For example, the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on- insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

Moreover, the terms "front," "back," "top," "bottom," "over," "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

Although specific conductivity types or polarity of potentials have been described in the examples, it will be appreciated that conductivity types and polarities of potentials may be reversed.

Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only of way of example and not as a limitation on the scope of the invention.

Claims

1 . A normally-off high electron mobility transistor (20), comprising

a channel layer (22),

a barrier layer (24),

a cap layer (26, 48, 76) and

a gate electrode (28);

said barrier layer comprising a first Ill-nitride and being located over said channel layer; said channel layer comprising a second Ill-nitride and comprising a conductive channel with a two-dimensional electron gas at least in a contact region with said barrier layer; and

said cap layer being located between said gate electrode and said barrier layer and comprising a material causing a change of charge distribution in said barrier layer depending on a thickness of said cap layer;

wherein a ratio of said thickness of said cap layer and a thickness of said barrier layer is selected such that said change of charge distribution causes an interruption in said conductive channel and wherein said gate electrode is operable to reverse said interruption in response to receiving a voltage.

2. The normally-off high electron mobility transistor as claimed in claim 1 , wherein said material comprises a Ill-nitride.

3. The normally-off high electron mobility transistor as claimed in claim 2, wherein said material comprises gallium nitride.

4. The normally-off high electron mobility transistor as claimed in one of the preceding claims, wherein said first Ill-nitride is aluminium nitride.

5. The normally-off high electron mobility transistor as claimed in one of claims 1 to 3, wherein said barrier layer comprises AIGaN with at least 50% aluminium.

6. The normally-off high electron mobility transistor as claimed in one of the preceding claims, wherein said barrier layer has a thickness of not more than 5 nm.

7. The normally-off high electron mobility transistor as claimed in one of the preceding claims, wherein said ratio is higher than 1 .

8. The normally-off high electron mobility transistor as claimed in claim 7, wherein said ratio is higher than 5.

9. The normally-off high electron mobility transistor as claimed in one of the preceding claims, wherein said thickness of said cap layer is bigger than a thickness of said channel layer.

10. The normally-off high electron mobility transistor as claimed in one of the preceding claims, comprising a buffer layer (34) carrying said channel layer.

1 1. The normally-off high electron mobility transistor as claimed in claim 10, wherein said buffer layer comprises AIGaN with less than 10% aluminium.

12. The normally-off high electron mobility transistor as claimed in claim 1 , wherein said material comprises a dielectric.

13. The normally-off high electron mobility transistor as claimed in claim 12, wherein said dielectric is Al₂0₃.

14. The normally-off high electron mobility transistor as claimed in one of the preceding claims, wherein said gate electrode is a dual gate electrode.

15. The normally-off high electron mobility transistor as claimed in claim 1 , comprising a dielectric layer (74) between said cap layer and said gate electrode.

16. The normally-off high electron mobility transistor as claimed in claim 15, wherein said ratio is equal to or lower than 1.

17. An integrated circuit, comprising at least one normally-off high electron mobility transistor as claimed in one of the preceding claims.