WO2013066330A1 - Prise en charge ipv4 différée durant une activation de support eps - Google Patents

Prise en charge ipv4 différée durant une activation de support eps Download PDF

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Publication number
WO2013066330A1
WO2013066330A1 PCT/US2011/059136 US2011059136W WO2013066330A1 WO 2013066330 A1 WO2013066330 A1 WO 2013066330A1 US 2011059136 W US2011059136 W US 2011059136W WO 2013066330 A1 WO2013066330 A1 WO 2013066330A1
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WO
WIPO (PCT)
Prior art keywords
information element
address allocation
deferred
packet data
indication
Prior art date
Application number
PCT/US2011/059136
Other languages
English (en)
Inventor
Giorgi Gulbani
Lewis MILTON
Original Assignee
Nokia Siemens Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Siemens Networks Oy filed Critical Nokia Siemens Networks Oy
Priority to PCT/US2011/059136 priority Critical patent/WO2013066330A1/fr
Publication of WO2013066330A1 publication Critical patent/WO2013066330A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5007—Internet protocol [IP] addresses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2101/00—Indexing scheme associated with group H04L61/00
    • H04L2101/60—Types of network addresses
    • H04L2101/686—Types of network addresses using dual-stack hosts, e.g. in Internet protocol version 4 [IPv4]/Internet protocol version 6 [IPv6] networks

Definitions

  • Embodiments of the invention relate to wireless communications networks, such as the Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (UTRAN) Long Term Evolution (LTE) and Evolved UTRAN (E-UTRAN).
  • UMTS Universal Mobile Telecommunications System
  • UTRAN Terrestrial Radio Access Network
  • LTE Long Term Evolution
  • E-UTRAN Evolved UTRAN
  • Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network refers to a communications network including base stations, or Node-Bs, and radio network controllers (RNC).
  • UTRAN allows for connectivity between the user equipment (UE) and the core network.
  • the RNC provides control functionalities for one or more Node Bs.
  • the RNC and its corresponding Node Bs are called the Radio Network Subsystem (RNS).
  • RNS Radio Network Subsystem
  • LTE Long Term Evolution
  • LTE refers to improvements of the UMTS through improved efficiency and services, lower costs, and use of new spectrum opportunities.
  • LTE is a 3GPP standard that provides for uplink peak rates of at least 50 megabits per second (Mbps) and downlink peak rates of at least 100 Mbps.
  • LTE supports scalable carrier bandwidths from 20 MHz down to 1.4 MHz and supports both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD).
  • FDD Frequency Division Duplexing
  • TDD Time Division Duplexing
  • LTE is also expected to improve spectral efficiency in 3G networks, allowing carriers to provide more data and voice services over a given bandwidth. Therefore, LTE is designed to fulfill future needs for high-speed data and media transport in addition to high- capacity voice support. Advantages of LTE include high throughput, low latency, FDD and TDD support in the same platform, an improved end-user experience, and a simple architecture resulting in low operating costs.
  • LTE is an all internet protocol (IP) based network, supporting both IPv4 and IPv6.
  • IP internet protocol
  • the Evolved 3 GPP Packet Switched Domain which is also known as the Evolved Packet System (EPS), provides IP connectivity using the E- UT AN.
  • EPS Evolved Packet System
  • One embodiment is directed to a method for deferring IP address allocation for a user equipment.
  • the method includes setting a packet data network type in an information element, and encoding internet protocol (IP) address allocation related information into the information element.
  • IP internet protocol
  • the method may then include transmitting the information element encoded with the IP address allocation related information to a gateway.
  • Another embodiment is directed to an apparatus including at least one processor and at least one memory including computer program code.
  • the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus at least to set a packet data network type in an information element, and encode internet protocol (IP) address allocation related information into the information element.
  • IP internet protocol
  • the apparatus may be further controlled to transmit the information element encoded with the IP address allocation related information to a gateway.
  • Another embodiment is directed to an apparatus including means for setting a packet data network type in an information element, and means for encoding internet protocol (IP) address allocation related information into the information element.
  • the apparatus may further include means for transmitting the information element encoded with the IP address allocation related information to a gateway.
  • IP internet protocol
  • Another embodiment is directed to a method including receiving an information element, and determining a packet data network type from the information element.
  • the information element may be encoded with IP address allocation related information.
  • the method then includes deferring IPv4 address allocation when the determined packet data network type indicates that IP address allocation should be deferred.
  • Another embodiment is directed to an apparatus including at least one processor and at least one memory including computer program code.
  • the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus at least to receive an information element, and determine a packet data network type from the information element.
  • the information element may be encoded with internet protocol (IP) address allocation related information.
  • IP internet protocol
  • the apparatus is further controlled to defer IPv4 address allocation when the determined packet data network type indicates that IP address allocation should be deferred.
  • Another embodiment is directed to an apparatus including means for receiving an information element, and means for determining a packet data network type from the information element.
  • the information element may be encoded with IP address allocation related information.
  • the apparatus may further include means for deferring IPv4 address allocation when the determined packet data network type indicates that IP address allocation should be deferred.
  • FIG. 1 illustrates a system according to one embodiment of the invention
  • FIG. 2a illustrates packet data network address allocation, according to an embodiment
  • Fig. 2b illustrates packet data network type values, according to one embodiment
  • FIG. 3 illustrates an apparatus, according to an embodiment
  • FIG. 4a illustrates a flow diagram of a method, according to one embodiment
  • Fig. 4b illustrates a flow diagram of a method, according to another embodiment.
  • the system architecture evolution (SAE) of LTE generally refers to a new system architecture that is an evolution of the core network.
  • SAE offers several advantages including improved data capacity, all internet protocol (IP) architecture, and reduced latency.
  • IP internet protocol
  • EPC evolved packet core
  • EPC 100 connects to enhanced node Bs (eNB) 101.
  • EPC 100 includes a mobility management entity (MME) 110, a serving gateway (SGW) 120, a packet data network (PDN) gateway (PGW) 125, and a policy and charging rules function (PCRF) 115.
  • MME 110 is the main control node for the LTE SAE access network. Some features handled by MME 110 include: bearer activation/de-activation, idle mode UE tracking, choice of SGW for a UE, intra-LTE handover involving core network node location, interacting with the home subscriber server (HSS) to authenticate user on attachment, providing temporary identities for UEs.
  • HSS home subscriber server
  • SGW 120 is a data plane element within the LTE SAE. SGW 120 manages user plane mobility and acts as the main interface between the radio access network (RAN) and the core network. SGW 120 can also maintain the data path between the eNBs 101 and PGW 125. As a result, SGW 120 may form an interface for the data packet network at the E- UTRAN.
  • RAN radio access network
  • PGW 125 provides connectivity for the UE to external PDNs.
  • a UE may have connectivity with more than one PGW 125 for accessing multiple PDNs.
  • PCRF 115 is an entity within the EPC that detects the service flow and enforces charging policy.
  • a UE When a UE is powered-on or otherwise begins to seek access to the network (e.g., UTRAN), the UE sends an attach request to eNB 101.
  • the attach request may be included, for example, in a create session request message and may include one or more information elements (IEs).
  • the eNB 101 forwards the request to MME 110, which in turn may forward the request to the SGW 120 and/or PGW 125. More specifically, during EPS bearer activation, MME 1 10 sends a create session request message to SGW 120. If a general packet radio service (GPRS) tunneling protocol version 2 (GTPv2) S5/S8 interface is used, then SGW 120 forwards the create session request message to PGW 125.
  • GPRS general packet radio service
  • GTPv2 general packet radio service
  • the create session request message may include IP address allocation related information for the UE.
  • the IP address allocation related information may be encoded into one of the IEs included in the create session request message.
  • the IP address allocation related information can be encoded into a PDN address allocation (PAA) IE.
  • PAA PDN address allocation
  • the UE may be using an IPv6 and IPv4 (dual stack) application, but only currently using IPv6.
  • IPv6 dual stack
  • the UE may want an IPv4 address in the future and, therefore, desire a deferred IPv4 address allocation.
  • the MME/S4-SGSN should indicate to the SGW/PGW that the UE is making a request for deferred IP address allocation.
  • Embodiments of the invention are configured to add specific encoding details into the IE in order to support an indication of deferred IPv4 address allocation. Based on the encoding details included in the IE, when the PGW 125 or SGW 120 receives the create session request message it has an indication that IP address allocation for the UE should be deferred.
  • Fig. 2a illustrates an example of a PAA, according to one embodiment.
  • the PDN type value is indicated in bits 3-1 of octet 5, for example.
  • the PDN type may be set to a certain value in order to indicate that deferred IP address allocation is desired.
  • octets 6 to 9 of the PAA IE are set to 0 in order to indicate that IPv4 address allocation should be deferred and, therefore, that the PGW/SGW should not yet assign an IP address to the UE.
  • Fig. 2b illustrates one example of a table showing how bits 3-1 of octet 5 are encoded to indicate each of IPv4, IPv6, and IPv4v6.
  • bit 1 may be set to indicate IPv4
  • bit 2 may be set to indicate IPv6
  • bit 3 may be set to indicate IPv4v6.
  • Fig. 2b only illustrates one example and other alternatives are available for indicating the IP version type. For example, bit 3 could be used to indicate IPv4 and other combinations are also possible.
  • Bits 8-4 of octet 5 are spare and can be coded as 0. PDN address and prefix are indicated in octet 6 to n+4.
  • PDN address and prefix are indicated in octet 6 to n+4.
  • Bit 8 of octet 6 represents the most significant bit of the IPv4 address and bit 1 of octet 9 represents the least significant bit.
  • octets 6 to 9 are set to 0.
  • Octets other than 6 to 9 may be set to 0 to indicate deferred IPv4 address allocation, according to other embodiments.
  • octet 6 contains the IPv6 prefix length.
  • Octets 7 through 22 contain an IPv6 prefix and interface identifier.
  • Bit 8 of octet 7 represents the most significant bit of the IPv6 prefix and interface identifier and bit 1 of octet 22 represents the least significant bit.
  • octet 6 contains the IPv6 prefix length.
  • Octets 7 through 22 contain an IPv6 prefix and interface identifier.
  • Bit 8 of octet 7 represents the most significant bit of the IPv6 prefix and interface identifier and bit 1 of octet 22 represents the least significant bit.
  • Octets 23 through 26 contain an IPv4 address. Bit 8 of octet 23 represents the most significant bit of the IPv4 address and bit 1 of octet 26 represents the least significant bit.
  • octets 6 to 9 are set to 0.
  • other octets may be set to 0 to indicate deferred IPv4 address allocation, according to other embodiments.
  • Fig. 3 illustrates an apparatus 10 according to one embodiment.
  • apparatus 10 may be MME 110 illustrated in Fig. 1.
  • Apparatus 10 includes a processor 22 for processing information and executing instructions or operations.
  • Processor 22 may be any type of general or specific purpose processor. While a single processor 22 is shown in Fig. 3, multiple processors may be utilized according to other embodiments.
  • Apparatus 10 further includes a memory 14, coupled to processor 22, for storing information and instructions to be executed by processor 22.
  • Memory 14 can be comprised of any combination of random access memory (“RAM”), read only memory (“ROM”), static storage such as a magnetic or optical disk, or any other type of non-transitory machine or computer readable media.
  • Apparatus 10 may further include a transmitter 28 for transmitting information, such as data and/or control signals.
  • Apparatus 10 also includes receiver 24 for receiving information including data and/or control signals.
  • the receiver and transmitter functionality may be implemented in a single transceiver unit.
  • memory 14 stores software modules that provide functionality when executed by processor 22.
  • the modules may include an operating system 15 that provides operating system functionality for apparatus 10.
  • the memory may also store one or more functional modules 18, such as an application or program, to provide additional functionality for apparatus 10.
  • the components of apparatus 10 may be implemented in hardware, or as any suitable combination of hardware and software.
  • memory 14 and the computer program code stored thereon may be configured, with processor 22, to cause the apparatus 10 to encode IP address related information into an information element.
  • the information element may be included within a create session request message for a UE.
  • the information element may be a PAA information element.
  • apparatus 10 is controlled to set the PDN type, and to encode the IP address related information by inserting or including an indication of a deferred IPv4 address allocation in the information element.
  • apparatus 10 is controlled to include the indication of the deferred IPv4 address allocation by setting octets 6 to 9 of the PAA information element to 0.
  • apparatus 10 is then controlled to forward or transmit the information element, for example, contained within a create session request message to a gateway.
  • the gateway may be a SGW or PGW, for example.
  • the indication inserted into the information element such as the setting of octets 6 to 9 to 0, conveys to the receiving gateway that IP address allocation for the UE should be deferred.
  • apparatus 10 may be a gateway, such as SGW 120 or PGW 125 as illustrated in Fig. 1.
  • memory 14 and the computer program code stored thereon may be configured, with processor 22, to cause the apparatus 10 to receive a message, which may include an information element, from a network entity.
  • the received message may be a create session request message.
  • Apparatus 10 may then be controlled to determine the PDN type that may be included in the information element of the received message.
  • the PDN type may be encoded with an indication of a deferred IPv4 address allocation.
  • the indication of the deferred IPv4 address allocation may include octets 6 to 9 of the information element being set to 0.
  • apparatus 10 is controlled to defer the allocation of an IPv4 address for the UE.
  • Fig. 4a illustrates a flow diagram for deferring IPv4 address allocation, according to one embodiment.
  • the method of Fig. 4a may be performed by apparatus 10 discussed above.
  • the method includes, at 400, setting a packet data network type in an information element.
  • the method then includes, at 405, encoding IP address allocation related information into the information element.
  • the information element may be included within a create session request message for a UE.
  • the encoding 405 may include inserting or including an indication of a deferred IPv4 address allocation in the information element.
  • the encoding may include inserting the indication of the deferred IPv4 address allocation by setting octets 6 to 9 of a PAA information element to 0.
  • method may further include, at 410, forwarding or transmitting the information element, which may be contained within a create session request message, to a gateway.
  • the gateway may be a SGW or PGW, for example.
  • the receiving gateway is notified to defer IP address allocation.
  • Fig. 4b illustrates a flow diagram of a method, according to another embodiment.
  • the method of Fig. 4b may be performed by apparatus 10 discussed above.
  • the method includes, at 430, receiving an information element and, at 435, determining the PDN type form the received information element.
  • the information element is encoded with IP address allocation related information.
  • the information element may be included within a create session request message, and may include an indication of a deferred IPv4 address allocation.
  • the method then includes, at 440, deferring IPv4 address allocation based on the PDN type.
  • the PDN type may indicate that that IP address allocation should be deferred.
  • the functionality of the flow diagram of Figs. 4a and 4b, or that of any other method described herein, may be implemented by a software stored in memory or other computer readable or tangible media, and executed by a processor.
  • the functionality may be performed by hardware, for example through the use of an application specific integrated circuit (ASIC), a programmable gate array (PGA), a field programmable gate array (FPGA), or any other combination of hardware and software.
  • ASIC application specific integrated circuit
  • PGA programmable gate array
  • FPGA field programmable gate array
  • the computer readable media mentioned above may be at least partially embodied by a transmission line, a compact disk, digital-video disk, a magnetic disk, holographic disk or tape, flash memory, magnetoresistive memory, integrated circuits, or any other digital processing apparatus memory device.
  • modules may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
  • a module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
  • Modules may also be partially implemented in software for execution by various types of processors.
  • An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve its stated purpose.
  • a module of executable code could be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices.
  • operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Un mode de réalisation de l'invention concerne un procédé pour différer une attribution d'adresse IP pour un équipement utilisateur. Le procédé consiste à régler un type de réseau de transmission de données par paquets dans un élément d'informations, et coder des informations relatives à une attribution d'adresse de protocole Internet (IP) dans l'élément d'informations. Le procédé peut ensuite consister à transmettre l'élément d'informations codé avec les informations relatives à l'attribution d'adresse IP à une passerelle.
PCT/US2011/059136 2011-11-03 2011-11-03 Prise en charge ipv4 différée durant une activation de support eps WO2013066330A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103916493A (zh) * 2014-04-15 2014-07-09 大唐移动通信设备有限公司 一种ip地址段分配方法及装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040264474A1 (en) * 2003-06-27 2004-12-30 Sbida Ivan Laloux Method, system and network element for data transmission using a transition mechanism
US20100332625A1 (en) * 2009-06-24 2010-12-30 Zte (Usa) Inc. Method and system for protocol configuration in wireless communication systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040264474A1 (en) * 2003-06-27 2004-12-30 Sbida Ivan Laloux Method, system and network element for data transmission using a transition mechanism
US20100332625A1 (en) * 2009-06-24 2010-12-30 Zte (Usa) Inc. Method and system for protocol configuration in wireless communication systems

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103916493A (zh) * 2014-04-15 2014-07-09 大唐移动通信设备有限公司 一种ip地址段分配方法及装置
CN103916493B (zh) * 2014-04-15 2017-12-08 大唐移动通信设备有限公司 一种ip地址段分配方法及装置

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