WO2013062204A1

WO2013062204A1 - Device and method for controlling a flash memory for storing an error correction code

Info

Publication number: WO2013062204A1
Application number: PCT/KR2012/004566
Authority: WO
Inventors: 송용호; 정상혁; 정재형
Original assignee: 한양대학교 산학협력단
Priority date: 2011-10-24
Filing date: 2012-06-08
Publication date: 2013-05-02
Also published as: KR20130044555A; KR101417827B1

Abstract

The present invention relates to a device and method for controlling a flash memory for storing an error correction code. Data is stored in page units, a host interface sends/transmits a control signal and data from/to a host such that a flash memory in which the page includes a preset number of sectors is controlled, and a memory interface unit stores data to be written that is received along with a write control signal from the host and an error correction code generated in response to the data to be written, in the page of the flash memory, wherein regions corresponding to the preset number of sectors that are among a plurality of sectors corresponding to data regions in which the data to be written is stored are further allocated as a storage region of the error correction code.

Description

Flash memory controller and method for storing error correction codes

The present invention relates to an apparatus and method for controlling a flash memory for storing an error correction code, and more particularly, to an apparatus and method for controlling a process of storing an error correction code used for error correction of data stored in a flash memory. It is about.

Because NAND flash memory has superior random read / write performance compared to hard drives, it is used to build storage on server systems that simultaneously handle a large number of user requests. Recently, due to the low power consumption and large capacity of NAND flash memory, it is widely used as a storage device for solid state drives and portable devices.

On the other hand, as the production technology of NAND flash memory is miniaturized and the Multi Level Cell (MLC) technology, which stores several bits in one storage cell, has been spreading, the manufacturing cost of the device has been reduced. Error detection and correction techniques have been used accordingly, resulting in poor reliability and durability.

The controller of the NAND flash memory uses an error correction code (ECC) for error correction, which is generated during the data transfer time and stored in the spare area along with the data page for the page program time. do. Since the large-capacity NAND flash memory device uses a program command to write to both the data area and the spare area, no additional overhead for storing the error correction code occurs. The error correction code stored as described above is decoded when data is read during the page read time, and the error corrected data is returned to the host by the error correction code. As with the write operation, the information stored in the data area and the spare area can be read by a single read operation.

The controller of the NAND flash memory generally uses a BCH code algorithm as an error correction code. The BCH code algorithm requires a 13 bit error correction code to correct 1 bit of error in a 512 byte sector. In addition, recently produced flash memory based on 3-bit multi-level cells (MLC) and 20 nanometer-class memory manufacturing processes have increased the error rate per sector significantly, and an error correction code of 24 bits or 40 bits per 1024 bytes is recommended.

RAID-5 is a commonly used technique in storage systems that require high reliability. FIG. 1 is a diagram illustrating a conventional RAID-5 technique, in which five storage devices are connected in parallel, of which only four storage devices are used for general data storage, and one storage device has four storage devices. Parity bits for error correction of the stored data are stored.

Thus, according to RAID-5, since 1/5 of the storage areas are used for error correction, a highly reliable storage medium can be implemented, but in terms of storage efficiency, it can be an inefficient structure. In this regard, a scheme for storing an error correction code in an area where parity bits are stored by improving a RAID structure has been proposed. However, there is a problem in that a delay occurs due to an operation of reading and writing a specific page for processing an error correction code during data read / write operation.

In addition, in order to secure a storage area of an error correction code required to apply the BCH code algorithm, a technique of fixing an external extension block is proposed. 2 is a diagram for describing a technique of using an external extension block. Referring to FIG. 2, an error correction code of a low performance BCH code algorithm such as 4 bit error correction is first stored in a spare area of a corresponding page, and an error correction code of a high performance BCH code algorithm such as 24 bit error correction is externally designated. Secondary storage in the extension block. When using this method, the error is usually corrected using the first stored error correction code, but when an error that cannot be corrected first occurs, the error correction code is stored using the second stored error correction code for accurate error correction. Will be performed.

However, in case of using the technique using an external extension block, there is an overhead of generating and storing two error correction codes for one data, and when the number of deletions of the corresponding block is increased due to the end of the storage life. There is a disadvantage in that two pages must be read and restored each time for error correction.

Meanwhile, Korean Laid-Open Patent Publication No. 1998-0038438 encodes the state information of a sector when encoding data together without distinguishing an overhead area so that errors occurring in any part of the sector can be corrected by an error correction code. Is disclosed. However, this method also has a problem that the problem of securing an additional area for storing an error correcting code of increased size cannot be solved.

SUMMARY OF THE INVENTION The present invention provides a flash memory controller for storing an error correction code for storing an error correction code of a large bit in a page in which data of a flash memory is to be stored together so that encoding and decoding can be performed without additional delay. To provide a way.

In order to achieve the above technical problem, a flash memory control apparatus for storing an error correction code according to the present invention is configured to control a flash memory in which data is stored in units of pages, and the page is composed of a predetermined number of sectors. A host interface for transmitting and receiving a control signal and data with the host; And a plurality of data corresponding to a data area in which write target data received together with a write control signal from the host and an error correction code generated corresponding to the write target data are stored in a page of the flash memory, wherein the write target data is stored. And a memory interface unit for further allocating a region corresponding to a preset number of sectors of the sectors to the storage region of the error correction code.

In order to achieve the above technical problem, a method of controlling a flash memory for storing an error correction code according to the present invention is to control a flash memory in which data is stored in units of pages and the page is configured with a predetermined number of sectors. (A) receiving a write target data with a write control signal from the host; (b) generating an error correction code corresponding to the write target data; And (c) storing the write target data and the error correction code in a page of the flash memory, wherein a region corresponding to a predetermined number of sectors is selected from among a plurality of sectors corresponding to a data region in which the write target data is stored. And further allocating to a storage area of the error correction code.

According to the flash memory control apparatus and method for storing an error correction code according to the present invention, a method using an RAID-5 structure or an external expansion block is employed by using a portion of a memory area for data storage for storing an error correction code. Compared with conventional error correction code storage techniques such as the method used, data and error correction codes for the same page can be stored together, thereby reducing the delay time for reading and writing an external page.

1 is a view for explaining a conventional RAID-5 technique,

2 is a diagram for explaining a technique of using an external expansion block;

3 is a block diagram showing the configuration of a preferred embodiment of a flash memory controller for storing error correction codes in accordance with the present invention;

4 is a diagram illustrating a conventional method in which data and an error correction code are stored in one page;

5 is a diagram illustrating a method of storing data and an error correction code in one page according to the present invention;

6 is a graph illustrating a comparison of the number of error correctable bits according to the number of sectors used as spare areas in a page of a flash memory;

7 is a diagram illustrating an example of a clustering page used in an SSD using a multi-chip;

8 is a graph illustrating a relationship between a correctable block error rate (CBER) and a raw bit error rate (RBER) according to the number of error correctable bits;

9 is a graph showing normalized operation delay time according to the conventional error correction code storage scheme and the present invention, and

10 is a flowchart illustrating an exemplary embodiment of a flash memory control method for storing an error correction code according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the flash memory control apparatus and method for storing the error correction code according to the present invention.

3 is a block diagram showing the configuration of a preferred embodiment of a flash memory control apparatus for storing an error correction code according to the present invention.

Referring to FIG. 3, the flash memory controller 100 according to the present invention operates between the host 200 and the flash memory 300 and includes a host interface unit 110 and a memory interface unit 120. In addition, the flash memory controller 100 may further include a buffer unit (not shown) in which data transmitted between the host 200 and the flash memory 300 is stored.

In the flash memory controller 100, the host interface unit 110 transmits and receives a control signal and data to and from the host 200, and the memory interface unit 120 receives the write target data received together with the write control signal from the host 200. And an error correction code generated corresponding to the write target data in a page of the flash memory 300.

The flash memory 300 includes a plurality of blocks that are basic units of a data erase operation, and a block includes a plurality of pages that are basic units of a read and write operation. In addition, the page is composed of a plurality of sectors, each of which consists of a data area in which actual data is stored and a spare area in which information such as an error correction code for managing the data area is stored. .

4 is a diagram illustrating a conventional method in which data and an error correction code are stored in one page. Referring to FIG. 4, a (16K + 512) byte size page is composed of 32 sectors, and each sector is (512 + 16) byte size. Each sector consists of a data area of 512 bytes and a spare area of 16 bytes, and stores data and an error correction code, respectively.

As described above, since the size of the page increases linearly and the probability of error occurrence increases exponentially, the spare area for storing the error correction code is insufficient. Therefore, the memory interface unit 120 of the flash memory controller 100 according to the present invention adjusts the number of sectors constituting the page to further allocate an ECC storage area in which an error correction code is stored, thereby consequently the size of the spare area. You get the same effect as increasing.

FIG. 5 is a diagram illustrating a method of storing data and an error correction code in one page according to the present invention. The page size of FIG. 5 is (16K + 512) bytes, and the page size of FIG. 4 and the flash memory 300 are the same, but the number of sectors is 31, which is reduced by one. In the page of the flash memory 300 shown in FIG. 5, each sector is composed of a data area of 512 bytes and an ECC storage area of (32 + α) bytes, and α = (reduced sector size / number of reduced sectors). )to be.

The number of sectors to be used as the ECC storage area can be adjusted by setting, and preferably, an area corresponding to one sector can be used as the ECC storage area. In addition, as a part of the sector is used as an ECC storage area, another page may be additionally allocated to the data beyond the size of the reduced data area to handle the read / write request of the host.

As such, the memory interface unit 120 uses a portion of the sector of the flash memory 300 as the ECC storage area, so that an error correction code for the write target data is stored together in the same page as the write target data, and further, for each sector. Since the error correction code is stored in succession to the data, error correction can be performed without delay in accordance with the sector-by-sector operation of the host.

Thereafter, when a read control signal of data stored in the flash memory 300 is received from the host 200, the memory interface 120 flashes the read target data corresponding to the read control signal and the error correction code corresponding to the read target data. After reading from the same page of the memory 300 and performing error correction on the data to be read, the memory 300 is output to the host 200 through the host interface 110.

6 is a graph illustrating a comparison of the number of error correctable bits according to the number of sectors used as an ECC storage area in one page of the flash memory 300. Referring to FIG. 6, by adjusting the number of sectors for data storage to secure an error correction code storage area, an error correction code of an increased bit may be stored for high performance error correction in an error correction scheme such as a BCH code algorithm. It can be confirmed.

However, as the flash memory controller 100 according to the present invention reduces the size of the data area and increases the size of the ECC storage area, the read / write request of the host is allocated in the same unit as the page size of the flash memory 300. If so, performance degradation can be expected. However, the flash memory 300 included in the recently-used SSD products is used to extend the page size to 16 KB or more, and furthermore, eight or 16 pages are clustered and used as one clustering page. In practice, performance degradation does not occur much because page clustering is required to easily manage SSDs equipped with dozens of NAND flash memory or to reduce the size of the FTL map table.

FIG. 7 is a diagram illustrating an example of a clustering page used in an SSD using multiple chips. In the four flash memory chips, pages of the same location are clustered and used as one page. Therefore, the effect of actually increasing the size of the page will occur.

8 is a graph illustrating a relationship between a correctable block error rate (CBER) and a raw bit error rate (RBER) according to the number of error correctable bits. The graph of FIG. 8 shows the CBER that the RBER of currently produced flash memory products has according to the 24-bit or 40-bit error correction technique. Here, CBER is a value calculated by Equation 1 below.

Equation 1

Where N is the number of bits in the block, E is the number of errors in the block, and p is the bit error rate.

9 is a graph showing normalized operation delay time according to the conventional error correction code storage scheme and the present invention. Referring to FIG. 9, when the page size is small, the delay time increases rapidly as the number of sectors used for storing the error correction code increases. However, when the page size increases, some sectors are used for storing the error correction code. Even if the delay time does not show a difference.

Meanwhile, like a hard disk drive, a NAND flash memory based storage device may use a volatile memory buffer to improve performance. In such a system, the memory controller temporarily stores data of a write object in a buffer or outputs data of a read object to be output to the host in response to an I / O access command of the host. Using buffer memory in this way reduces the latency that occurs while processing I / O access, and allows you to combine instructions for the same block or page.

One of the buffer management algorithms, the Clean-first LRU (CFLRU), is an LRU-based buffer management algorithm for storage systems with NAND flash memory.It is clean when the NAND flash memory has no empty slots due to the erase and write characteristics. Use pages or blocks

Such a CRLRU buffer management technique may be applied to the flash memory management apparatus 100 according to the present invention. Hereinafter, the CFLRU technique applied to the present invention is referred to as an O-CFLRU technique. Specifically, in the O-CFLRU scheme, sector-by-sector instructions for the same page are grouped together regardless of the timing and type, thereby performing buffer allocation or flushing in units of pages. In addition, the O-CFLRU classifies the received command according to the size of the command, that is, the size of the sector. If the size of the sector is larger than the preset reference value (for example, 32), the command is directly transmitted to the NAND flash memory. In other words, commands smaller than the reference value are stored in a buffer and merged or 'in-place' updated.

When the O-CFLRU technique, which is the above-described buffer management algorithm, is applied to the present invention, when the buffer is used for temporary data storage as shown in FIG. 9, as the size of the buffer increases, the delay time decreases, thereby reducing performance. The width becomes smaller.

Referring to FIG. 10, when the host interface unit 110 of the flash memory controller 100 according to the present invention receives a data write control signal from the host 200 (S1010), it writes to the write target data that is the target of the write control signal. A corresponding error correction code is generated (S1020). The error correction code may be generated by an error correction unit (not shown) separately provided in the memory interface 120 or the flash memory controller 100.

The memory interface unit 120 stores the write target data and the error correction code corresponding thereto in the flash memory 300, and as described above, some sectors of the page where the write target data is to be stored, for example, 1 to 2 sectors. An area corresponding to the Mn is allocated as an ECC storage area for storing an error correction code (S1030).

Thereafter, when a read control signal for the stored data is received from the host 200 (S1040), the memory interface unit 120 may read an error correction code stored together on the same page as the read target data and the read target data corresponding to the read control signal. The flash memory 300 reads the data from the flash memory 300 (S1050), corrects an error of the data to be read using the error correction code, and outputs the error to the host 200 (S1060). The error correction process may also be performed by an error correction unit (not shown) provided in the flash memory controller 100 separately.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

Claims

In the flash memory controller for controlling the flash memory in which data is stored in units of pages and the page is composed of a predetermined number of sectors,

A host interface for transmitting and receiving control signals and data with the host; And

A plurality of write target data received with a write control signal from the host and an error correction code generated corresponding to the write target data in a page of the flash memory, and corresponding to a data area in which the write target data is stored; And a memory interface unit for allocating an area corresponding to a predetermined number of sectors among the sectors as a storage area of the error correction code.
The method of claim 1,

And the memory interface unit reads from the flash memory the read target data corresponding to the read control signal received from the host and the error correction code stored in the same page as the read target data.
The method according to claim 1 or 2,

And the memory interface unit continuously stores an error correction code corresponding to data stored in the page in a sector in which the data is stored.
The method according to claim 1 or 2,

And the page is a clustering page in which a page in different flash memories is clustered and processed in a single operation in a storage device having a plurality of flash memories.
In the flash memory control method for controlling the flash memory in which data is stored in units of pages and the page is composed of a predetermined number of sectors,

(a) receiving write target data together with a write control signal from a host;

(b) generating an error correction code corresponding to the write target data; And

(c) storing the write object data and the error correction code in a page of the flash memory, wherein the error area corresponds to a predetermined number of sectors among a plurality of sectors corresponding to a data area in which the write object data is stored; And further allocating to a storage area of the correction code.
The method of claim 5,

(d) reading from the flash memory the read object data corresponding to the read control signal received from the host and an error correction code stored in the same page as the read object data; And

and (e) correcting an error of the data to be read by the error correcting code read from the flash memory and outputting the corrected error to the host.
The method according to claim 5 or 6,

And in the step (c), continuously storing an error correction code corresponding to data stored in each sector of the page in a sector in which the data is stored.
The method according to claim 5 or 6,

And the page is a clustering page in which pages in different flash memories are clustered and processed in a single operation in a storage device having a plurality of flash memories.