WO2013058960A4 - Compact sense amplifier for non-volatile memory - Google Patents
Compact sense amplifier for non-volatile memory Download PDFInfo
- Publication number
- WO2013058960A4 WO2013058960A4 PCT/US2012/057836 US2012057836W WO2013058960A4 WO 2013058960 A4 WO2013058960 A4 WO 2013058960A4 US 2012057836 W US2012057836 W US 2012057836W WO 2013058960 A4 WO2013058960 A4 WO 2013058960A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- node
- latch
- bit line
- sense amp
- circuit
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
Claims
AMENDED CLAIMS
received by the International Bureau on 06 June 2013 (06.06.13)
IT IS CLAI MED:
1 . A sense amplifier lor a memory circuit., comprising:
a latch circuit;
an intermediate circuit, including a first node selectively connectable to one or more bit lines, a second node connectable to the latch circuit, and an internal node connectable to the first and second nodes;
bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;
a first switch connected to die latch circuit and the second node, whereby a value held in the latch circuit can be connected to the second node when on and isolate the latch circuit from the second node when off;
a second switch, whereby the latch circuit can be connected lo a data bus; and a reset switch connected to ground and the latch circuit, whereby the latch can be reset.
2. The sense amp circuit of claim 1 , wherein the reset switch is connected to a node of the latch that holds this inverse of said value held in the latch circuit.
3. The sense amp circuit of claim 2, wherein the value held in the latch circuit can be set to float by turning on the reset switch.
4. The sense amp circuit of claim 1 , wherein the intermediate circuit includes a first transistor connected between the second node and a high voltage supply level whose control gate is connected to receive the value held in the latch.
5. The sense amp circuit of claim 4, wherein the first transistor is connected to second node through a third switch.
6. The sense amp circuit of claim 1 , wherein the first switch is a transistor having a gate settable to control the level of the first node relative to the level of the value held in the latch circuit.
7. The sense amp circiii i of claim 1 , further comprising:
1
a third switch whereby the internal node is selectively connectable 10 the second node.
8. The sense amp circuit of claim 7, further comprising:
a capaciior connected between the internal node and a third node.
9. The sense amp circuit of claim S, further comprising:
a first transistor and a fourth switch connected in series between the third node and the second node, where the control gate of the first iransislor is connected to the internal node.
1 0. The sense amp circuit of claim 1 , further comprising:
a third switch whereby the first node is selectively connectable to the internal node.
1 1 . The sense amp circui t of claim 1 , further comprising:
a third switch whereby ihe fi rst node is selectively connectable to the second node.
12. The sense amp circui t o f claim 1 , further comprising:
a third switch whereby the fi rst node is selectively connectable to a high voltage supply level independently of the value held in the latch circuit.
13. A method of performing a sensing operation on a non-volatile memory device having a plurality of memory cells formed along bit lines, the method comprising:
performing a first sensing operation for a selected memory cel l by a sense amp connectable to a bit line corresponding to the selected memory cel l;
storing the result of the first sensing operation as a value in a latch in the sense amp, wherein the larch receives the result through a first internal node of the sense amp and wherein the value stored in the latch controls a fi rst switch connected between the first internal node and a high voltage supply level of the sense amp;
2
subsequently turning off a second switch by which the first internal node is connected to ihe latch, thereby isolating the val ue siored in the latch from the first internal node; and
while isolating the value stored in the latch from the first internal node, biasing the corresponding bit line to either inhi bit or allow further sensing of the selected memory cell based upon the value stored in the latch, by turning on a third switch connected between the first switch and the first internal node,
wherein the value stored in the latch can be supplied from the latch to a data bus concurrently with said biasing of the corresponding bit line.
14. The method of claim 1 3. wherein the first sensing operation includes: pre-charging an internal node of the sense amp;
subsequently connecting the node to the bit line; and
subsequently performing a determination of the extent to which the bit line discharges the internal node.
1 5. The method of claim 14, wherein storing the result of the first sensing operation i cludes:
resetting the latch; and
transferring the result of the determination through the second switch to the latch.
16. The method of claim 1 3, wherein the value stored in the latch is supplied to the data bus by selective turning on a switch connected between the latch and the data bus.
1 7. The method o f claim 1 3, wherein biasing the corresponding bit line to inhibit further sensing of the selected memory cell includes:
the value stored in the latch circuit turning the first switch off and connecting the first internal node to a voltage received from a node external to the sense amp.
1 8. The method of claim 1 3, wherein biasing the corresponding bit line to allow further sensing of the selected memory cell includes:
ihe value stored in the latch circuit aiming the first switch on and connecting the first internal node to receive the high voltage supply level of the sense amp.
1 . The method οΓ claim 13, wherein ihe sensing operation is a data read operation.
20. The method of claim 1 3, wherein the sensing operation is a program verify operation.
21. A method of operating a non- volatile memory circuit, the memory circuit having a plurality of non-volatile memory cells formed along word lines and bit lines, the bit lines connectable to a corresponding sense amp circuit, where each of the sense amp circuits including a latch connectable to a bus and to intermediate circuitry whereby the corresponding bit line can be connected to the latch, the method comprising:
receiving at the latch a first data programming value from the bus;
connecting the latch by the intermediate circuitry to the bit line through a first node of the sense amp circuit, thereby biasing the bit line according to the first data programming value;
while the bit line is biased according to the first data programming value, isolating the latch from the first node by a first switch connected therebetween; and while the bit line is biased according to the first data programming value and subsequent to isolating the latch, receiving at the latch a second data programming value from the bus.
22. The method of claim 21 , further comprising:
subsequently connecting the latch by the intermediate circuitry to the bit line through the first node, thereby biasing the bit line according to the second data programming value.
23. The method of claim 22, wherein the first switch is a first transistor whereby the latch is connected lo the first node and biasing the bit l ine according to
4
the second data programming value includes setting the gate voltage of the first transistor to a voltage level to bias the bit l ine to partially inhibit programming.
24. The method of claim 21 , wherein the fust data programming value is one of a high voltage supply level or a low voltage level and the second data programming value is one o f a high voltage supply level or a low voltage level .
25. The method of claim 21 , further comprising:
subsequent to receiving the first data programming value and prior connecting the latch to the bit line, transferring the iirst data programming value through the first node to an internal node of the intermediate circuitry, wherein the internal node is connected to a first plate of a capacitance whose second plate is connected to a second node, and wherein the second node is connectable to the first node through a first transistor whose control gate is connected to the internal node; and
while connecting the latch to the bit l ine:
biasing a second transistor whereby the first node is connected to the internal node to be weakly on;
raising the voltage level on the second node to a high voltage supply level; and
subsequently connecting the second node to the first node through the first transistor.
26. The method of claim 25, further comprising:
subsequently connecting the latch by the intermediate circuitry to the bit line through the first node, thereby biasing the bit line according to the second data programming value.
27. The method of claim 26, wherein the first switch is a third transistor whereby the latch is connected to the first node and biasing the bit line according to the second data programming value includes setting the gate vol tage of the third transistor to a voltage level to bias the bit line to partial ly inhibit programming.
5
28. The method of claim 26, whereby if second data programming value is the high voltage supply level, the bit line is set to the high voltage supply level if programming is be inhibited thereby.
29. The method of claim 26, whereby if second data programm ing value is a low voltage supply level, the bit line is set to the low voltage supply level.
30. The method of claim 21 , further comprising:
subsequent to receiving the first data programming value and prior connecting the latch to the bit line, transferring the lirst data programming value through the first node to an internal node of the intermediate circuitry, wherein the internal node is connected lo a first plave of a capacitance whose second plate is connected to a second node, and wherein the second node is connectable to the first node through a first transistor whose control gate is connected to the internal node;
while connecting the latch to the bi t line:
biasing a second transistor whereby the first node is connected to the internal node to be weakly on; and
raising the voltage level on the second node to a voltage offset by a lirst amount below a high voltage supply level;
subsequently turning off the second transistor prior to receiving the second data programming value;
subsequent to receiving the second data programming value, connecting the second node to the first node through the first Lransistor and connecting the latch by the intermediate circuitry to the bit line through the first node;
subsequently turning isolating the latch from the first node by the first switch; and
subsequently raising the voltage level on the second node to the high voltage supply level.
3 1 . The method of claim 30, wherein the first amount is a scttable parameter.
32. The method of claim 30, wherein the first switch is a third transistor whereby the latch is connected to the first node and biasing the bit line according to
6
the second data programming value includes setting the gale voltage of the third Transistor to a vol tage level to bias the bi i line to partial ly inhi bit programming.
33. The method of claim 30, whereby if second data programming value is the high voltage supply level, the bit l ine is set ιο the high voltage supply level if programming is to be inhibited thereby
34. The method of claim 30, whereby i second data programming value is a low voltage supply level, the bit line is set to the low voltage supply level.
35. A method of measuring the current of a meniory cell on a selected bit line of a non- volatile memory circuit, the non-volatile memory circuit including a plurality of bit lines, each having one or more meniory cells fomied thercalong, connectable to a con-esponding sense amp circuit, where each of the sense amp circuits including a latch circuit having a node connectable lo a bus and to intermediate circuitry whereby the con-esponding bit line can be connected to the node, the method comprising:
selecting a bit line from the plurality of bit lines;
for the selected bit line, setting the latch of the corresponding sense amp circuit to allow the level on the node lo float;
applying a bias voltage on the bus;
for the non-selected bit lines o f the plurality of bits lines, selling the intermediate circuitry of each of the corresponding sense amp circuits so that the bit line is not connected to the node while the bias voltage is applied on ihe bus,
connecting the selected bit line by the corresponding sense amp to the node thereof and while the bias voltage is applied on the bus; and
subsequently determining the amount of current drawn by the selected bit line in response to the bias voltage.
36. The method of claim 35, wherein the bias voltage is an external voltage applied lo a pin of the memory circuit.
37. The method of claim 36, wherein the method is performed as part of a test operation for the memory circuit.
7
38. The method of claim 35, further comprising:
for the non-selected bit lines, setting the node of the latch of the corresponding sense amp circuit low.
39. The method of claim 35, wherein each of the sense amp circuits further includes a reset switch connected between the latch circuit and ground, and wherein setting the latch of the sense amp circuit corresponding to the selected bit line to allow the level on the node to float comprises turning on the reset switch thereof.
40. The method of claim 35, wherein the intermediate circuitry includes a switch whereby the intermediate circuitry can be connected to the node.
41. The method of claim 35, further comprising:
connecting the non-selected bit lines to receive a high voltage level through the corresponding intermediate circuitry.
8
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/277,966 | 2011-10-20 | ||
| US13/277,915 | 2011-10-20 | ||
| US13/277,915 US8630120B2 (en) | 2011-10-20 | 2011-10-20 | Compact sense amplifier for non-volatile memory |
| US13/277,966 US8705293B2 (en) | 2011-10-20 | 2011-10-20 | Compact sense amplifier for non-volatile memory suitable for quick pass write |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2013058960A2 WO2013058960A2 (en) | 2013-04-25 |
| WO2013058960A3 WO2013058960A3 (en) | 2013-06-13 |
| WO2013058960A4 true WO2013058960A4 (en) | 2013-08-08 |
Family
ID=47116346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2012/057836 WO2013058960A2 (en) | 2011-10-20 | 2012-09-28 | Compact sense amplifier for non-volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2013058960A2 (en) |
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| US5172338B1 (en) | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
| US5343063A (en) | 1990-12-18 | 1994-08-30 | Sundisk Corporation | Dense vertical programmable read only memory cell structure and processes for making them |
| US6222762B1 (en) | 1992-01-14 | 2001-04-24 | Sandisk Corporation | Multi-state memory |
| US5313421A (en) | 1992-01-14 | 1994-05-17 | Sundisk Corporation | EEPROM with split gate source side injection |
| US5315541A (en) | 1992-07-24 | 1994-05-24 | Sundisk Corporation | Segmented column memory array |
| KR0169267B1 (en) | 1993-09-21 | 1999-02-01 | 사토 후미오 | Nonvolatile semiconductor memory device |
| US5661053A (en) | 1994-05-25 | 1997-08-26 | Sandisk Corporation | Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
| US5903495A (en) | 1996-03-18 | 1999-05-11 | Kabushiki Kaisha Toshiba | Semiconductor device and memory system |
| US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
| US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US7046568B2 (en) | 2002-09-24 | 2006-05-16 | Sandisk Corporation | Memory sensing circuit and method for low voltage operation |
| US6657891B1 (en) | 2002-11-29 | 2003-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
| JP3920768B2 (en) * | 2002-12-26 | 2007-05-30 | 株式会社東芝 | Nonvolatile semiconductor memory |
| US7120051B2 (en) | 2004-12-14 | 2006-10-10 | Sandisk Corporation | Pipelined programming of non-volatile memories using early data |
| US20060140007A1 (en) | 2004-12-29 | 2006-06-29 | Raul-Adrian Cernea | Non-volatile memory and method with shared processing for an aggregate of read/write circuits |
| US7173854B2 (en) | 2005-04-01 | 2007-02-06 | Sandisk Corporation | Non-volatile memory and method with compensation for source line bias errors |
| KR100634458B1 (en) * | 2005-07-04 | 2006-10-16 | 삼성전자주식회사 | Flash memory device capable of performing multi-bit and single-bit program operations with a single page buffer structure |
| KR101073116B1 (en) * | 2006-07-20 | 2011-10-13 | 샌디스크 코포레이션 | Compensating for coupling based on sensing a neighbor using coupling |
| US7532516B2 (en) | 2007-04-05 | 2009-05-12 | Sandisk Corporation | Non-volatile storage with current sensing of negative threshold voltages |
| US7593265B2 (en) | 2007-12-28 | 2009-09-22 | Sandisk Corporation | Low noise sense amplifier array and method for nonvolatile memory |
| US7957197B2 (en) | 2008-05-28 | 2011-06-07 | Sandisk Corporation | Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node |
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2012
- 2012-09-28 WO PCT/US2012/057836 patent/WO2013058960A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013058960A2 (en) | 2013-04-25 |
| WO2013058960A3 (en) | 2013-06-13 |
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