WO2013055399A1 - Surveillance et gestion d'unité centrale de traitement basées sur un histogramme d'occupation/activité - Google Patents

Surveillance et gestion d'unité centrale de traitement basées sur un histogramme d'occupation/activité Download PDF

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Publication number
WO2013055399A1
WO2013055399A1 PCT/US2012/023352 US2012023352W WO2013055399A1 WO 2013055399 A1 WO2013055399 A1 WO 2013055399A1 US 2012023352 W US2012023352 W US 2012023352W WO 2013055399 A1 WO2013055399 A1 WO 2013055399A1
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WIPO (PCT)
Prior art keywords
processor
data structure
histogram
workload
computing device
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PCT/US2012/023352
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English (en)
Inventor
Qing Li
Sumit Sur
Jeffrey A. NIEMANN
Bohuslav Rychlik
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Qualcomm Incorporated
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Publication date
Priority claimed from US13/301,480 external-priority patent/US8650423B2/en
Priority claimed from US13/349,139 external-priority patent/US20130097415A1/en
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of WO2013055399A1 publication Critical patent/WO2013055399A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G06F11/3423—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time where the assessed time is active or idle time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the various aspects include methods of dynamically adjusting the operations of a computing device having a processor, including measuring busy or idle durations of the processor, generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations, and using the histogram-like data structure to adjust at least one operational parameter of the computing device.
  • generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations includes incrementing by a predefined amount a particular value within a multi-value data structure that corresponds to a measured busy or idle duration, and decrementing all values within the multi-value data structure by a decay factor.
  • generating a histogram-like data structure characterizing the processor's workload includes generating the histogram-like data structure in two central processing unit (CPU) cycles or less.
  • using the histogram-like data structure includes adjusting a frequency of voltage of the processor based on the histogram-like data structure.
  • using the histogram-like data structure includes determining a longest workload quantum based on the histogram-like data structure, generating a model of a predicted future workload based on the histogram-like data structure, and adjusting operational parameters of the processor to be commensurate with the predicted future workloads.
  • adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes adjusting an operating frequency of the processor based on the longest workload quantum. In a further aspect, adjusting an operating frequency of the processor includes scaling the voltage or frequency of the processor. In a further aspect, adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes changing at least one quality of service value. In a further aspect, using the histogram-like data structure includes determining a longest workload quantum within the histogram-like data structure, and determining a quality of service value based on the determined longest workload quantum. In a further aspect, the method further includes controlling a component of the computing device based on the determined quality of service value. In a further aspect, using the histogram-like data structure includes determining a longest workload quanta, comparing the longest workload quantum with a workload natural period, and determining a quality of service value based on this comparison.
  • the means for generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations includes means for incrementing by a predefined amount a particular value within a multi-value data structure that corresponds to a measured busy or idle duration, and
  • means for generating a histogram-like data structure characterizing the processor's workload includes means for generating the histogram-like data structure in two central processing unit (CPU) cycles or less.
  • means for using the histogram-like data structure includes means for adjusting a frequency of voltage of the processor based on the histogram-like data structure.
  • means for using the histogram-like data structure includes means for determining a longest workload quantum based on the histogram-like data structure, means for generating a model of a predicted future workload based on the histogram-like data structure, and means for adjusting operational parameters of the processor to be commensurate with the predicted future workloads.
  • means for adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes means for adjusting an operating frequency of the processor based on the longest workload quantum.
  • means for adjusting an operating frequency of the processor includes means for scaling the voltage or frequency of the processor.
  • means for adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes means for changing at least one quality of service value.
  • means for using the histogram-like data structure includes means for determining a longest workload quantum within the histogram-like data structure, and means for determining a quality of service value based on the determined longest workload quantum.
  • the computing device further includes means for controlling a component of the computing device based on the determined quality of service value.
  • means for using the histogram-like data structure includes means for determining a longest workload quanta, means for comparing the longest workload quantum with a workload natural period, and means for determining a quality of service value based on this comparison.
  • the processor is configured with processor-executable instructions such that generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations includes incrementing by a predefined amount a particular value within a multi-value data structure that corresponds to a measured busy or idle duration, and decrementing all values within the multi-value data structure by a decay factor.
  • the processor is configured with processor-executable instructions such that generating a histogramlike data structure characterizing the processor's workload includes generating the histogram-like data structure in two central processing unit (CPU) cycles or less.
  • CPU central processing unit
  • the processor is configured with processor-executable instructions such that using the histogram-like data structure includes adjusting a frequency of voltage of the processor based on the histogram-like data structure.
  • the processor is configured with processor-executable instructions such that using the histogram-like data structure includes determining a longest workload quantum based on the histogram-like data structure, generating a model of a predicted future workload based on the histogram-like data structure, and adjusting operational parameters of the processor to be commensurate with the predicted future workloads.
  • the processor is configured with processor-executable instructions such that adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes adjusting an operating frequency of the processor based on the longest workload quantum.
  • the processor is configured with processor-executable instructions such that adjusting an operating frequency of the processor includes scaling the voltage or frequency of the processor.
  • the processor is configured with processor-executable instructions such that adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes changing at least one quality of service value.
  • the processor is configured with processor-executable instructions such that using the histogram-like data structure includes determining a longest workload quantum within the histogram-like data structure, and determining a quality of service value based on the determined longest workload quantum.
  • the processor is configured with processor-executable instructions to perform operations further including controlling a component of the computing device based on the determined quality of service value.
  • the processor is configured with processor-executable instructions such that using the histogram-like data structure includes determining a longest workload quanta, comparing the longest workload quantum with a workload natural period, and determining a quality of service value based on this comparison.
  • FIG. 1 Further aspects include a non-transitory computer readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations including measuring busy or idle durations of the processor, generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations, and using the histogram-like data structure to adjust at least one operational parameter of the computing device.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that generating a histogram-like data structure characterizing the processor's workload using the measured busy or idle durations includes incrementing by a predefined amount a particular value within a multi-value data structure that corresponds to a measured busy or idle duration, and decrementing all values within the multi-value data structure by a decay factor.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that generating a histogram-like data structure characterizing the processor's workload includes generating the histogram- like data structure in two central processing unit (CPU) cycles or less.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that using the histogram-like data structure includes adjusting a frequency of voltage of the processor based on the histogram-like data structure.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that using the histogram-like data structure includes determining a longest workload quantum based on the histogram-like data structure, generating a model of a predicted future workload based on the histogram-like data structure, and adjusting operational parameters of the processor to be commensurate with the predicted future workloads.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes adjusting an operating frequency of the processor based on the longest workload quantum.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that adjusting an operating frequency of the processor includes scaling the voltage or frequency of the processor.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that adjusting the operational parameters of the processor to be commensurate with the predicted future workloads includes changing at least one quality of service value.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations such that using the histogram-like data structure includes determining a longest workload quantum within the histogram-like data structure, and determining a quality of service value based on the determined longest workload quantum.
  • the stored processor-executable software instructions are configured to cause the processor to perform operations further including controlling a component of the computing device based on the determined quality of service value.
  • the stored processor- executable software instructions are configured to cause the processor to perform operations such that using the histogram-like data structure includes determining a longest workload quanta, comparing the longest workload quantum with a workload natural period, and determining a quality of service value based on this comparison.
  • FIG. 1 is a diagram of processor activity of a typical mobile device processor that may be used to implement the various aspects.
  • FIG. 2 is a diagram of the histogram-like statistics that may be collected, analyzed, and used to control quality of service values, processor frequency and/or voltage.
  • FIG. 3 is a process flow diagram of an aspect method for generating
  • histogram-like data structure that reflects a current distribution of busy and/or idle durations.
  • FIG. 4 is a process flow diagram of an aspect method for dynamically adjusting the operational parameters of a mobile computing device.
  • FIG. 5 is a process flow diagram of an aspect method for dynamically adjusting the frequency/voltage of a mobile computing device.
  • FIG. 6 is a process flow diagram of an aspect method for dynamically adjusting communication parameters of a mobile computing device in response to a computed quality of service.
  • FIG. 7 is an architectural diagram of an example system on chip suitable for implementing the various aspects.
  • FIG. 8 is a component block diagram of a mobile device suitable for implementing the various aspects.
  • FIG. 9 is a component block diagram of a lap top computer suitable for implementing the various aspects.
  • mobile device and “computing device” are used interchangeably herein to refer to any one or all of cellular telephones, personal data assistants
  • PDA's palm-top computers
  • wireless electronic mail receivers e.g., the Internet
  • Blackberry® and Treo® devices multimedia Internet enabled cellular telephones (e.g., the Blackberry Storm®), Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor and operate under battery power such that power
  • kernel is used herein to refer to a component of an operating system that performs operating system tasks and serves as a bridge between software applications and the hardware.
  • a typical kernel's responsibilities may include managing system resources and facilitating the communications between the hardware components and the software components, which may be achieved via various inter-process communication mechanisms and system calls.
  • Kernels are commonly organized into user space (where non-privileged code runs) and kernel space (where privileged code runs) segments. This separation is of particular importance in Android and other general public license (GPL) environments where code that is part of the kernel space must be GPL licensed, while code running in user- space doesn't need to be GPL licensed.
  • GPL general public license
  • SOC system on chip
  • a single SOC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions.
  • a single SOC may also include any number of general purpose and/or specialized processors (DSP, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, Flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.).
  • DSP general purpose and/or specialized processors
  • memory blocks e.g., ROM, RAM, Flash, etc.
  • resources e.g., timers, voltage regulators, oscillators, etc.
  • SOCs may also include software for controlling the integrated resources and processors, as well as for controlling peripheral devices.
  • resource is used herein to refer to any of a wide variety of circuits (e.g., ports, clocks, buses, oscillators, etc.), components (e.g., memory), signals (e.g., clock signals), and voltages (e.g., voltage rails) which are used to support processors and clients running on a computing device.
  • circuits e.g., ports, clocks, buses, oscillators, etc.
  • components e.g., memory
  • signals e.g., clock signals
  • voltages e.g., voltage rails
  • Mobile device users expect their mobile devices to be able to perform a wide variety of tasks, such as those for making calls, playing music, browsing the Internet, playing games, watching movies, etc. Each of these activities demands a certain amount of processing, a certain quality of service, and a specific number of resources from the mobile device processor. Each activity may also place a specific workload on the processor that varies considerably from the workloads of the other activities and/or of other times.
  • the various aspects provide methods of characterizing processor workloads and adjusting a mobile device's operating parameters (e.g., voltage, quality of service values, etc.) to adjust the device's performance and/or power consumption characteristics such that they are commensurate with the processor workloads.
  • the workloads may be characterized using a histogram-like data structure that stores statistic information, which may be collected and computed at runtime based on the processor's busy/idle cycles and such that they do not add overhead or otherwise impact the device's performance.
  • maximizing processor performance requires setting the supply voltage at the maximum allowable level.
  • a typical mobile device does not require the maximum achievable performance at all times.
  • Dynamic clock and voltage scaling (DCVS) methods may be implemented to reduce the power consumption of the processors when peak performance is not necessary. These methods take advantage of periods of low processor utilization by scaling the supply voltage and clock frequency such that the device's overall power consumption is reduced.
  • existing scaling methods simply adjust the frequency/voltage of the processor such that power consumption is minimized, performance is maximized, or such that the system alternates between these two objectives. Simply configuring a computing device to maximize power saving or to maximize performance (or to alternate between the two objectives) does not always result in the most efficient utilization of the mobile device processor.
  • maximizing the processor's performance may require adjusting the processor's quality of service (QoS) parameters.
  • QoS quality of service
  • Quality of service is a broad term that describes the quality of a connection between two or more communicating network devices. There may be many different factors that determine the ultimate quality of service provided to a mobile device, and the quality of service required by the device may fluctuate over time. Efficient utilization of network and mobile devices requires dynamically adapting the processors and resources to the required quality of service, which may include varying various quality of service values (e.g., measured error rates, frequency of dropped frames or packets, performance metrics, etc.) to meet the operational needs of the mobile device. While controlling the quality of service may help conserve power and processing resources, these same resources may be drained by overly complicated methods of measuring a connection's quality of service. The various aspects utilize network devices efficiently by computing the required levels of quality of service and adjusting the quality of service values to achieve the required quality of service without adding overhead or otherwise impacting the device's performance.
  • various quality of service values e.g., measured error rates, frequency of dropped frames or packets, performance metrics, etc.
  • the various aspects provide methods and systems for controlling various processor and computing device processes based on a histogram-like data structure which is generated with a low-overhead process but yields a complex picture of the processor workloads, and busy/idle operations.
  • This data structure can be used to control or manage a variety of parameters, such as voltage or frequency, or to infer information regarding a current operating state, such as determining a current quality of service, predicting processors workloads, and adjusting various operational parameters.
  • Various aspects use the histogram-like data structure to determine an appropriate processor operating frequency and/or voltage to accommodate current workloads.
  • Various aspects use the histogram-like data structure to estimate quality of service values in the context of other demands on the processor to enable better decision making on optimizing device performance using information not available via standard quality of service determinations.
  • Various aspects predict upcoming workloads based on recent processor workload history and other statistics collected and/or calculated during runtime.
  • Various aspects dynamically adjust the processor's performance level to be commensurate with the current workload and the required quality of service.
  • Various aspects determine when to adjust the quality of service and/or frequency- voltage settings based upon the histogram-like data structure which reflects the dynamic nature of busy and idle durations.
  • the histogramlike data structure may be used to model, characterize and/or predict future workloads, and the modeled workloads may be used to select/implement adaptive quality of service/voltage scaling methods that balance power consumption and performance levels such that they are commensurate with predicted future workloads.
  • the various aspects may implement methods suitable for adjusting the processor's operations to the specific workloads present on a mobile device. This targeted approach enables the generation and implementation of quality of service and scaling methods that are more efficient and adaptive than existing solutions.
  • FIG. 1 illustrates processor activity of a typical mobile device processor that may be analyzed using the various aspects.
  • the processor activity may include a sequence of alternating busy and idle periods (which may also be referred to herein as "busy/idle cycles").
  • FIG. 1 illustrates that each of the busy or idle periods may be of varying durations, and that these durations may vary a great deal over time depending upon the processes and applications being accomplished by the device processor(s) at any given instant.
  • These busy/idle duration variations make it difficult to accurately predict future busy/idle cycles with certainty and/or to accurately model/characterize the workloads of device processor(s) without performing a significant number of power intensive computations.
  • there is no net energy saved by adjusting the quality of service or performing dynamic voltage scaling operations if the amount of energy required to model the workload is greater than or equal to the amount of energy saved by adjusting the operating parameters (e.g., scaling the
  • an operating system kernel is aware of processor busy and idle conditions, and may be configured to track and/or log each time a processor switches from a busy period to an idle period, and vice versa.
  • an operating system kernel may be configured to store timestamp information each time the processor transitions between busy and idle cycles. This timestamp information may be used to calculate previous busy and/or idle durations, and the duration values may be used to generate predictive models of current and future workloads based upon statistical calculations using these durations. Since the input information (e.g., timestamp information) is obtained from or made available by the kernel, the statistic values may be calculated using light weight processor operations which involve performing relatively simple calculations/operations (e.g., using shift operations instead of multiply operations).
  • busy and idle lengths/durations may be calculated based on timestamps stored or available in the operating system kernel that are noted each time the processor switches from busy to idle and vice versa.
  • Various aspects use the calculated busy or idle durations to generate a histogram-like data structure that can be used for determining a quality of service value.
  • the histogram-like data structure provides a compact data set containing information regarding the overall processor workload, variability in the busy/idle ratio, and characteristics of the processor workload. This data structure, while relatively compact, may provide a
  • workload models may be generated using histogram-like data structures that represent the processor's busy/idle cycles.
  • the histogram-like data structures may be implemented using a variety of known data structures (e.g., vectors, arrays, maps, lists, multimaps, graphs, etc.).
  • the various aspects take advantage of an observation that the demand on the processor (which may be reflected in the collected/calculated busy vs. idle statistics), may be correlated to a quality of service value. This is because the error correction algorithms required to recover lost bits consume processing time, but these processes are only required when bits are being lost in the communication channel. Thus, with better quality of service, fewer lost bits will be lost in communication, and there will be less processor demands to recover lost bits. On the other hand, as quality of service degrades, the bit-error-rate increases, thereby increasing the amount of processing required for recovering lost bits. Using this information, the various aspects measure quality of service in the context of other demands on the processor such that more actuate optimization decisions may be made using information and structures not available in standard quality of service determinations.
  • FIG. 2 is a graph illustrating the histogram-like statistics that may be collected, analyzed, and used to control quality of service values, operating parameters, and processor performance (e.g., via adjustments to processor frequency and/or voltage).
  • the duration of a processor activity (i.e., busy and/or idle) measurement cycle may be divided up into a number of "bins" associated with duration increments.
  • the measurement cycle is 3.2 ms and the histogram-like structure contains 32 data fields ("bins"). Each of these bins may correspond to a range of busy (and/or idle) durations.
  • bin 1 may store an integer value representative of the fraction of time the busy (and/or idle) duration is between zero (0) and ninety nine (99) microseconds
  • bin 2 may store a value representative of the fraction of time the busy (and/or idle) duration is between one hundred (100) and one hundred and ninety nine (199) microseconds
  • bin 3 may store a value representative of the fraction of time the busy (and/or idle) duration is between two hundred (200) and two hundred and ninety nine (299) microseconds, etc.
  • the values in each bin may be calculated such that a time- averaging histogram representation of the distribution of the processor busy (and/or idle) durations may be generated efficiently.
  • the various aspects provide mechanisms for generating histogram-like statistics data structures such that they may be
  • the generated histogram-like data structures may be time weighted so that more recent information is more represented in the data set than old information. For example, in each cycle that one of the duration bins may be incremented based on the determined busy and/or idle duration, the remaining bins may be decremented by a decay factor, such as by multiplying the value in each bin by a fraction (e.g., 63/64).
  • the bins and the busy or idle durations they represent may correspond to a workload quantum. Generally, a repetitive workload has a number of repeated operations, and each repeated operations may take a certain amount of busy duration to finish.
  • the repeated operations and their respective workload quanta may be represented in the peaks of the histogram, and the largest workload quantum (i.e., "LWLQ”) may be identified from the histogram-like structure as the right most peak.
  • LWLQ largest workload quantum
  • the largest/longest workload quantum within the histogram data structure may be used as an indication of the quality of service. If the longest workload quantum is in a long-duration bin, which is far to the right in the illustrated histogram (i.e., a high bin number in the example described above), this may indicate that there have been frequent long-duration processor busy cycles within the measurement cycle. This may be the case when the processor is being tasked frequently to perform long-duration calculations, which may be typical of various error correcting algorithms. Thus, frequent long duration calculations indicated by a far-right LWLQ value may correspond to low quality of service because the processor is frequently performing error-correction calculations.
  • LWLQ longest/longest workload quantum
  • the largest/longest workload quantum may be compared with the natural period of the workload.
  • a ratio of longest workload quantum to the workload natural period above a certain value (e.g., a value of 1) may correspond to a bad quality of service value, whereas a ratio below the value may indicate a good quality of service.
  • FIG. 3 illustrates an aspect method 300 for using information derived from a histogram-like data structure to characterize processor workloads and adjust or control a processor or an operational parameter.
  • a mobile device processor may measure, calculate or otherwise determine busy and/or idle durations for a calculation cycle.
  • the busy and/or idle durations may be calculated from the information known to the kernel, and determining such durations may include performing time-weighting (i.e., continuous decaying of values) operations to provide a current picture of the processing environment.
  • time-weighting i.e., continuous decaying of values
  • a bin in the busy and/or idle duration histogram-like data structure corresponding to the value may be incremented by a standard amount. For example, the bin may be incremented by 0x1000000.
  • the remaining bins, or all bins may be decremented or decayed by a decay factor (e.g., 63/64).
  • the histogram generation loop 320 may then be repeated, and as a result of this loop 320, within a relatively short time (e.g., 64 cycles), the bins making up the data structure may reflect a current distribution of busy and/or idle durations of the processor time averaged over the past cycles (e.g., the past ⁇ 64 cycles) with emphasis on the most recent cycles.
  • the resulting data structure may be used to adjust or control a device processor or parameter.
  • a mobile device may be configured to model/characterize the processor workloads by first calculating and generating a histogram-like data structure using busy/idle time stamps or duration information obtained from the operating system kernel. The models/characterizations of the workloads may then be used to more accurately adjust the quality of service and/or scale the frequency and voltage via voltage/frequency scaling methods with the objective of balancing power savings against processor performance on the current workload.
  • an optimal operating frequency rate may be selected such that the processor performance is commensurate with the actual/predicted workload while power savings are maximized and/or the impact on the user experience is minimized (e.g., users do not experience noticeable performance loss).
  • statistic values may be calculated in terms of an idle/busy ratio.
  • the idle/busy ratio may be calculated as being equal to an average of the idle (or busy) durations divided by the sum of the average idle duration and the average busy duration.
  • a target idle/busy ratio may be set based on the calculated average statistics and/or the identified workload.
  • the frequency (and/or voltage) of the processor may be adjusted in a control loop configured to steer the current idle/busy ratio towards a target ratio.
  • the target busy/idle ratio may be a value that provides an optimum balance between processor performance and power savings.
  • the frequency/voltage of the processor may be adjusted a bit higher than the value indicated by the running average idle/busy ratio in order to provide extra processing capability to accommodate occasional peaks in processor workload.
  • the competing parameters of processor speed and power consumption may be evaluated in view of the current busy/idle cycle statistics. If the processor is operated at or near its maximum frequency (i.e., CPU cycles per second), it will rapidly complete each processor or operation; however, it will operate at higher voltage and thus exhibit a higher power consumption rate. If the processor is not particularly busy and is operated at or near the maximum frequency, it will quickly accomplish each of the operations, and the idle durations between operations will be long (i.e., the busy- to- idle ratio will be small). While the processor is idle but operating at high voltage, its power consumption will be high even though it is not actively working most of the time. Thus, operating the processor at high frequency /high voltage when the workload is light (i.e., the busy- to-idle ratio is small) may result in unnecessary battery drain with no performance benefit to the user.
  • the processor is operated at or near its maximum frequency (i.e., CPU cycles per second)
  • the processor is not particularly busy and is operated at or near the maximum frequency, it will quickly accomplish each of the operations
  • the processor will consume more power on average than necessary because such peaks may occur infrequently, and thus on average, the processor is operating at an unnecessarily high frequency/voltage. If the peaks in processor workload (i.e., shortest idle durations), then the processor will consume more power on average than necessary because such peaks may occur infrequently, and thus on average, the processor is operating at an unnecessarily high frequency/voltage. If the peaks in processor workload (i.e., shortest idle durations), then the processor will consume more power on average than necessary because such peaks may occur infrequently, and thus on average, the processor is operating at an unnecessarily high frequency/voltage. If the peaks in processor workload (i.e., shortest idle durations), then the processor will consume more power on average than necessary because such peaks may occur infrequently, and thus on average, the processor is operating at an unnecessarily high frequency/voltage. If the peaks in processor workload (i.e., shortest idle durations
  • frequency /voltage is set according to valleys in processor workload (i.e., longest idle durations), then the processor will save more power but frequently will exhibit poor performance when it is unable to keep up with the peaks in workload.
  • the voltage and frequency of the processor may be adjusted in a dynamic clock and voltage scaling (DCVS) algorithm based on the comparison between the target ratio and the actual idle/busy ratio.
  • DCVS dynamic clock and voltage scaling
  • the processor frequency may be decreased to save power, or increased to insure adequate
  • FIG. 4 illustrates an aspect method 400 for dynamically adjusting the operational parameters of a mobile device processor.
  • a histogram generation loop 320 similar to the a histogram generation loop 320 illustrated in FIG.
  • the bins making up the histogram-like data structure reflect a current distribution of busy and/or idle durations of the processor time averaged over the past cycles (e.g., the past ⁇ 64 cycles) with emphasis on the most recent cycles.
  • the lengths, recurrence, and other characteristics of the idle and/or busy durations may be measured, and an idle/busy ratio may be calculated.
  • the idle/busy ratio may be calculated as the average of the idle (or busy) durations divided by the sum of the average idle duration and the average busy duration.
  • other formulas may also be used to calculate the running averages.
  • the target idle/busy ratio may be calculated or adjusted based upon the statistic values in order to provide an optimum balance between processor performance and power savings in view of the current operating conditions.
  • collected statistic values may be used to identify future processor demands and/or to identify circumstances in which the target ratio is not likely be accurate and adjust the target ratio accordingly.
  • one or more portions of the histogram-like data structure may be accessed to determine the processor's workload.
  • a control algorithm may be applied to the accessed portions to predict a future workload.
  • the operation parameters may be set by mobile device processor such that the quality of service (and/or frequency/voltage) of the mobile device processor is adjusted to match the processor workload.
  • These operations may be repeated in a control loop 410 configured to steer the current idle/busy ratio towards a desired target ratio in a continuous, dynamic manner.
  • the target ratio may be adjusted dynamically. Adjustments to the target idle/busy ratio may occur before, at the same time or after the adjustments are made to the
  • the adjustments to the operational parameters may be accomplished in a parallel process such that they occur concurrently with the adjustments to the target idle/busy ratio.
  • FIG. 5 illustrates an aspect method 500 for scaling the frequency/voltage of a mobile device processor.
  • a histogram generation loop 320 may be repeated such that the bins making up the histogram-like data structure reflect a current distribution of busy and/or idle durations, similar to the a histogram generation loop 320 illustrated in FIGs. 3 and 4.
  • one or more portions of the histogram-like data structure may be accessed to determine the processor's workload.
  • a dynamic clock and voltage scaling algorithm may be applied to the accessed portions to determine the optimal voltage or frequency for the predicted workloads.
  • the frequency /voltage of the mobile device processor may be adjusted to match the predicted processor workload.
  • Blocks 504-508 may be repeated in a control loop 510.
  • a quality of service value may be determined or estimated (or a proxy for quality of service may be determined) based on the longest workload quantum bin within the histogram-like data structure, or the ratio of the longest workload quantum bin to the workload natural period.
  • determined/estimated quality of service may be used to control or adjust the device (e.g., to change an error encoding scheme), boost or reduce transceiver power, increase or reduce transmission rates, etc. Since the histogram-like data structure may be continuously upgraded (e.g., via the histogram generation loop 320), the measure of quality of service provided by the longest workload quantum may be used to continuously monitor and react to changes in the quality of service experienced by the device.
  • FIG. 6 illustrates an aspect method 600 for adjusting communication parameters based on estimated quality of service values.
  • a histogram generation loop 320 similar to the a histogram generation loop 320 illustrated in FIG. 3 may be repeated such that the bins making up the histogram-like data structure reflect a current distribution of busy and/or idle durations of the processor time averaged over the past cycles (e.g., the past ⁇ 64 cycles) with emphasis on the most recent cycles.
  • one or more portions of the histogram-like data structure may be accessed to determine a processor workload.
  • a largest workload quantum, or the ratio of the largest workload quantum bin to the workload natural period may be computed.
  • a quality of service value may be determined or estimated (or a proxy for quality of service may be determined) based on the longest workload quantum bin, or the ratio of the longest workload quantum bin to the workload natural period, in block 610, the determined/estimated quality of service may be used to control or adjust the device (e.g., to change an error encoding scheme), boost or reduce transceiver power, increase or reduce transmission rates, etc.
  • the histogram-like data structure may be continuously upgraded (e.g., via the histogram generation loop 320), the measure of quality of service provided by the longest workload quantum may be used to continuously monitor and react to changes in the quality of service experienced by the device via control loop 612.
  • the various aspects utilize histogram-like statistics and structures to capture and model a running, busy, idle duration distribution over past history for a processor.
  • the time span may divided into a number of intervals (e.g., 32 intervals), the weight of each interval may be represented by an integer, and all integers may be initialized to the same value (e.g., 0x2000000).
  • Each weight may be updated on every busy/idle cycle. For example, if the time span is divided into 32 segments, all the elements may decay as:
  • Nj Nj - (Nj » 6); // shift by 6 bits, x 63/64
  • Nj + 0x1000000 for the element the duration falls in (large increment reduce rounding error and gives record of rare event history).
  • mapping the time durations to an array element may results in:
  • Nj may be decayed to half of what it was in 45 busy/idle cycles if it is not hit.
  • a residual value below 0x1000000 may measure how old a rare event happened in the past. Every 45 cycles, the element value may have one more leading zero in its binary form. This may be used keep a history of about 900 cycles before the residual value reduces to the minimum value of 63.
  • the busy duration may be weighted by a current CPU_freq parameter.
  • a fixed workload quanta may show up at same distribution point regardless current CPU_freq.
  • a repetitive workload may include fixed types of repeated operation, and each type of repeated operation may require a certain amount of CPU cycles to finish.
  • This amount of CPU work is a workload quanta, which shows up as a peak in the workload histogram structure.
  • the largest workload quanta (LWLQ) for a given workload e.g.., the right most peak illustrated in FIG. 2 scaled by current CPU Freq can be a good measure of QoS.
  • the relative value of the LWLQ and the natural period (WLNP) of the workload gives a good measure of current WL QoS. Larger than 100% of LWLQ to WLNP ratio means less than satisfying QoS.
  • FIG. 7 is an architectural diagram illustrating an example system-on-chip (SOC) 700 architecture that may be used to implement the various aspects.
  • the SOC 700 may include a number of heterogeneous processors, such as a digital signal processor (DSP) 702, a modem processor 704, a graphics processor 706, and an application processor 708.
  • DSP digital signal processor
  • the SOC 700 may also include one or more coprocessors 710 (e.g., vector co-processor) connected to one or more of the processors.
  • Each processor may include one or more cores, and each processor/core may perform operations
  • the SOC 700 may include a processor that executes a first type of operating system (e.g., FreeBSD, LTNIX, OS X, etc.) and a processor that executes a second type of operating system (e.g., Microsoft Windows 7).
  • a first type of operating system e.g., FreeBSD, LTNIX, OS X, etc.
  • a second type of operating system e.g., Microsoft Windows 7
  • the SOC 700 may also include analog circuitry and custom circuitry 714 for managing sensor data, analog-to-digital conversions, wireless data transmissions, and performing other specialized operations, such as processing encoded audio signals for games and movies.
  • the SOC 700 may further include system components and resources 716, such as voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components used to support the processors and clients running on a computing device.
  • the system components 716 and custom circuitry 714 may include circuitry to interface with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.
  • the processors 702, 704, 706, 708 may be interconnected to one or more memory elements 712, system components, and resources 716 and custom circuitry 714 via an interconnection/bus module, which may include an array of reconfigurable logic gates and/or implement a bus architecture (e.g., CoreConnect, AMBA, etc.). Communications may be provided by advanced interconnects, such as high performance networks-on chip (NoCs).
  • NoCs network-on chip
  • the SOC 700 may include an input/output module (not illustrated) for communicating with resources external to the SOC, such as a clock 718 and a voltage regulator 720.
  • Resources external to the SOC e.g., clock 718, voltage regulator 720
  • an exemplary mobile receiver device 850 may include a processor 851 coupled to internal memory 852, a display 853, and to a speaker 859. Additionally, the mobile device 850 may have an antenna 854 for sending and receiving electromagnetic radiation that is connected to a mobile multimedia receiver 856 coupled to the processor 851.
  • the mobile multimedia receiver 856 may include an internal processor 858, such as a digital signal processor (DSP) for controlling operations of the receiver 856 and communicating with the device processor 851.
  • DSP digital signal processor
  • Mobile devices typically also include a key pad 856 or miniature keyboard and menu selection buttons or rocker switches 857 for receiving user inputs.
  • FIG. 9 illustrates an example personal laptop computer 900.
  • a personal computer 900 generally includes a processor 901 coupled to volatile memory 902 and a large capacity nonvolatile memory, such as a disk drive 903.
  • the computer 900 may also include a compact disc (CD) and/or DVD drive 904 coupled to the processor 901.
  • the computer device 900 may also include a number of connector ports coupled to the processor 901 for establishing data connections or receiving external memory devices, such as a network connection circuit 905 for coupling the processor 901 to a network.
  • the computer 900 may further be coupled to a keyboard 908, a pointing device such as a mouse 910, and a display 909 as is well known in the computer arts.
  • the processors 801, 901 may be any programmable microprocessor, microcomputer or multiple processor chip or chips that may be configured by software instructions (applications) to perform a variety of functions, including the functions of the various aspects described herein. In some mobile devices, multiple processors 801, 901 may be provided, such as one processor dedicated to wireless
  • the processor 801, 901 may include internal memory sufficient to store the application software instructions.
  • the secure memory may be in a separate memory chip coupled to the processor 801, 901.
  • the internal memory 802, 902 may be a volatile or nonvolatile memory, such as flash memory, or a mixture of both.
  • a general reference to memory refers to all memory accessible by the processor 801, 901, including internal memory 802, 902, removable memory plugged into the mobile device, and memory within the processor 801, 901 itself.
  • the hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), a DSP within a multimedia broadcast receiver chip, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.
  • a general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of
  • microprocessors one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • some steps or methods may be performed by circuitry that is specific to a given function.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that may be accessed by a computer.
  • such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
  • any connection is properly termed a computer-readable medium.
  • Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and/or instructions on a machine readable medium and/or computer-readable medium, which may be incorporated into a computer program product.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Debugging And Monitoring (AREA)

Abstract

Les aspects de l'invention permettent à un dispositif informatique ou à un microprocesseur d'ajuster les opérations d'un processeur en tenant compte d'une charge de travail actuelle d'un processeur d'après une structure de données semblable à un histogramme. Une structure de données semblable à un histogramme caractérisant des durées d'occupation (et/ou d'inactivité) et/ou des taux d'occupation (et/ou d'inactivité) d'un processeur est générée lors de l'exécution et sert à modéliser la charge de travail du processeur. La charge de travail du processeur est utilisée pour prédire les futures exigences de traitement et pour ajuster les opérations du processeur de sorte qu'elles soient proportionnelles aux exigences du traitement et de la charge de travail. La structure de données semblable à l'histogramme peut servir autrement à estimer une qualité de service (QoS) actuelle d'un lien de communication de façon à pouvoir entreprendre des actions de gestion des liens.
PCT/US2012/023352 2011-10-12 2012-01-31 Surveillance et gestion d'unité centrale de traitement basées sur un histogramme d'occupation/activité WO2013055399A1 (fr)

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US201261583386P 2012-01-05 2012-01-05
US61/583,386 2012-01-05
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