WO2013038958A1 - Clamp circuit and signal processing system using same - Google Patents

Abstract

The clamp circuit of the present invention comprises a capacitor, a first transistor connected to the capacitor, a second transistor, a first resistor, a first voltage source, a second resistor, a second voltage source and a third resistor. The second transistor has an electric current control terminal for applying a specific voltage and is of the same conductivity type as the first transistor. The first resistor has a first terminal and a second terminal, is connected to one of the main terminals of the pair of main terminals of each of the first transistor and the second transistor, and the first main terminal to which is applied a reference voltage for specifying an electric current amount is connected to the first terminal. The first voltage source is connected to the second terminal of the first resistor. The second resistor is disposed between the electric current control terminal of the first transistor and the second main terminal different from the first main terminal of the pair of main terminals. The second voltage source is connected to the second main terminal of the second transistor. The third resistor is disposed between the second main terminal of the first transistor and the second voltage source. The clamp circuit presents an external signal to the electric current control terminal of the first transistor through the capacitor.

Description

Clamp circuit and signal processing system using the same

The present invention relates to a clamp circuit and a signal processing system using the clamp circuit.
This application claims priority based on Japanese Patent Application No. 2011-198502 filed in Japan on September 12, 2011, the contents of which are incorporated herein by reference.

The clamp circuit is used for various applications. For example, a clamp circuit is also used in a television receiver that receives an analog television broadcast. To explain this point, when the received analog video signal (analog input signal) is input to the digital system in the television receiver, it is necessary to convert the analog input signal into a digital signal. An analog / digital converter (sometimes referred to as an “A / D conversion circuit”) is used for performing “A / D conversion”. In this analog-digital conversion, a clamp circuit is required to accurately convert an analog input signal into a digital signal.
FIG. 9 shows a circuit configuration of a conventional clamp circuit (FIG. 2 of Patent Document 1), and FIG. 10 shows a waveform of an analog input signal input to the clamp circuit.
As shown in FIG. 9, the analog input signal 1 of an analog television broadcast receiver is impedance-converted by an emitter follower circuit (NPN type transistor 15 and resistor 16), and the converted signal is DC-converted by a clamping capacitor 17. The component (DC component) is cut and applied to the input terminal 21 of the video signal processing digital system 18. The AD conversion circuit 24 digitizes the voltage level appearing at the input terminal 21. However, the AD converter circuit 24 has a predetermined voltage range that can be digitized.
Therefore, the clamp circuit 50 is configured by the clamp capacitor 17, the resistor 19, the current source 22, and the switch element 23. The clamp circuit 50 reproduces the reference voltage of the AD conversion circuit 24 from the analog input signal 1 from which the DC component is cut by the capacitor 17 so that the voltage level appearing at the input terminal 21 falls within the voltage range of the AD conversion circuit 24.

The conventional clamp circuit will be further explained. As a method of reproducing the reference voltage of the AD conversion circuit 24, an analog signal 1 as shown in FIG. 10, for example, a composite video signal (CVBS; Composite Video, Blanking, and Sync, a composite image including a video signal, a blanking period, and a synchronization signal) Signal) pedestal period (burst signal period indicated by point G) and CVBS synchronization period (indicated by point F).
Returning to FIG. 9, the circuit configuration of the clamp circuit 50 shown in FIG. 9 is a circuit configuration for regenerating the reference voltage using the pedestal period. In this circuit configuration, the pedestal level detection circuit 25 detects the voltage level (pedestal level) of the analog signal 1 during the pedestal period. At this time, the pedestal level detection circuit 25 performs the conversion based on the digital data after the AD conversion circuit 24 converts the analog signal 1 into a digital signal. The comparison circuit 26 compares the detection result of the pedestal level detection circuit 25 with the reference data 27. The clamp pulse generation circuit 28 generates a clamp pulse according to the comparison result of the comparison circuit 26 and turns on the switch element 23 to make the pedestal level constant.
However, in the circuit configuration of the clamp circuit 50, the AD conversion circuit 24 does not operate unless the voltage at the input terminal 21 is within the voltage range that the AD conversion circuit 24 can digitize.

FIG. 11 shows a circuit configuration of a clamp circuit 51 that uses a synchronization period in order to solve this problem (FIG. 1 of Patent Document 1).
The clamp circuit 51 includes a capacitor 4, a PNP transistor 6 (PNP bipolar transistor), a resistor 7, an NPN transistor 8 (NPN bipolar transistor), a resistor 12, and a bias circuit 13. The clamp circuit 51 converts the impedance of the analog input signal 1 by an emitter follower circuit (NPN type transistor 2 and resistor 3), cuts the DC component of the signal after the impedance conversion by the capacitor 4, and supplies it to the emitter of the NPN type transistor 8. Giving. The output voltage VB of the bias circuit 13 is applied to the base of the NPN transistor 8.
The explanation will be supplemented as follows.
As shown in the following equation (1), when the voltage VE of the emitter (indicated by point A) of the NPN transistor 8 becomes lower than the output voltage VB by the threshold voltage Vbe of the NPN transistor 8, the NPN transistor 8 is turned on. To do.
VE <VB-Vbe (1)

In the clamp circuit 51, when the NPN transistor 8 is turned on, a current flows through the resistor 7, so that the base voltage of the PNP transistor 6 decreases. Therefore, the PNP transistor 6 is turned on to charge the capacitor 4, and the emitter voltage of the NPN transistor 8, that is, the voltage VE at the point A rises to (VB−Vbe). Here, the minimum voltage of the analog signal 1 (CVBS) is given during the synchronization signal period of the analog signal 1 indicated by a point F in FIG. Therefore, the minimum value of the emitter voltage of the NPN transistor 8 indicated by the point A in the synchronization signal period, that is, the output voltage of the clamp circuit (the input voltage to the AD conversion circuit provided in the next stage) is (VB−Vbe).

FIG. 12 shows a circuit configuration of another conventional clamp circuit (FIG. 5 of Patent Document 2).
The clamp circuit 52 includes a capacitor C1, a diode D1, a resistor R1, and a resistor R2. In the circuit configuration of the clamp circuit 52, an analog signal including direct current is input to the input terminal I, the DC component of the analog signal is cut by the capacitor C1, and input to the cathode of the diode D1. The anode of the diode D1 is at the GND potential VG. Therefore, as shown in the following equation (2), when the voltage at the cathode (indicated by point H) of the diode D1 is lowered by the threshold voltage Vca of the diode D1, the diode D1 becomes conductive.
VH <VG-Vca (2)
For this reason, the clamp circuit 52 sets the minimum value of the output voltage of the clamp circuit (the voltage of the output terminal O1) in the synchronization signal period of the analog signal 1 indicated by the point F in FIG. 10 to (VG−Vca).

JP-A-6-62275 Japanese Unexamined Patent Publication No. 7-46101

Incidentally, the threshold voltage Vbe of the NPN transistor changes under the influence of the environmental temperature where the LSI is placed.
FIG. 13 is a graph showing a relationship between a voltage between a base and an emitter (base-emitter voltage) and a base current in an NPN transistor. The graph shown in FIG. 13 shows the dependency of the base current IB on the base-emitter voltage VBE when the environmental temperature Ta at which the clamp circuit operates is changed to −25 ° C., 25 ° C., and 100 ° C. As shown in FIG. 13, when the base-emitter voltage VBE when the base current IB is 10 μA, for example, is the threshold voltage Vbe of the NPN transistor, the threshold voltage Vbe has an environmental temperature Ta of −25 ° C. to 100 ° C. When it changes, it changes about ± 0.1V.
Therefore, in the circuit configuration of the clamp circuit 51 of FIG. 11, the output voltage of the clamp circuit (hereinafter referred to as the synchronization signal voltage) during the synchronization period of the analog signal 1 becomes (VB−Vbe). It will change about 0.1V.
For this reason, for example, when the input voltage range of the AD converter circuit in the next stage is determined based on Ta = 25 ° C., Vbe decreases by about 0.1 V at 100 ° C., and accordingly, the synchronization signal voltage level increases accordingly. The voltage range that can be digitized by the AD conversion circuit is wasted.

In addition, depending on an ASIC (Application Specific Integrated Circuit) process including a plurality of manufacturing steps for manufacturing an LSI, there is a process in which only a PNP transistor or a p-type FET (p-channel field effect transistor) can be manufactured. The configuration of the clamp circuit 51 shown in FIG. 11 is not applicable to such a process because an NPN transistor is used.
On the other hand, since the clamp circuit 52 shown in FIG. 12 is composed of a diode, there is no problem caused by the ASIC process, but the threshold voltage Vca of the diode also changes under the influence of the environmental temperature.
FIG. 14 is a graph showing the relationship between the voltage (forward voltage VF) between the anode and the cathode in the PN diode and the current flowing from the anode to the cathode (forward current IF). The graph shown in FIG. 14 shows the dependency of the forward current IF on the forward voltage VF when the environmental temperature Ta at which the clamp circuit 52 operates is changed to −25 ° C., 25 ° C., and 100 ° C. as in FIG. ing. As shown in FIG. 14, for example, if the forward voltage VF when the forward current IF is 1 mA is the threshold voltage Vca of the PN diode, the threshold voltage Vca is ±± when the environmental temperature Ta changes from −25 ° C. to 100 ° C. It changes about 0.1V.
For this reason, for example, when the input voltage range of the AD converter circuit in the next stage is determined based on Ta = 25 ° C., Vca decreases by about 0.1 V at 100 ° C., and accordingly, the synchronization signal voltage level increases accordingly. The voltage range that can be digitized by the AD conversion circuit is wasted.
According to one embodiment of the present invention, a clamp circuit that clamps an analog input voltage to a voltage with little temperature change with a simple circuit configuration is provided. In the conventional circuit configuration shown in FIG. 15 (FIG. 1 of Patent Document 2), the output terminal O1 of the clamp circuit 52 is connected to the input terminal Ia1 of the differential amplifier circuit A, and the bias circuit is connected to the other input terminal Ia2. A circuit configuration is shown in which the output of B is connected and a clamped signal is output from the output terminal Oa1 of the differential amplifier circuit A. However, since the bias circuit B outputs a clamp voltage or a voltage that swings around the clamp voltage to the input terminal Ia2, the level of the clamp voltage output from the output terminal Oa1 is the same as that of the clamp circuit 52. The level includes the threshold voltage Vca of the diode and has temperature dependency.

A clamp circuit according to an aspect of the present invention includes a capacitor, a first transistor connected to the capacitor, a current control terminal to which a specified voltage is applied, and a second transistor having the same conductivity type as the first transistor. And a first resistor having a first terminal and a second terminal, the first resistor being connected to one of a pair of main terminals of each of the first transistor and the second transistor, A first resistor having a first main terminal to which a prescribed reference voltage is applied connected to the first terminal; a first voltage source connected to the second terminal of the first resistor; A second resistor disposed between a current control terminal of one transistor and a second main terminal different from the first main terminal of the pair of main terminals; and the second resistor of the second transistor. Connected to main terminal A second voltage source, and a third resistor disposed between the second main terminal of the first transistor and the second voltage source, and the current control terminal of the first transistor includes the second voltage source. An external signal is given through a capacitor.

In the clamp circuit, a specified voltage (VD) is applied to the current control terminal of the second transistor so that the second transistor becomes conductive. The first main terminal is one of a pair of main terminals of each of the first transistor and the second transistor, and is a terminal to which a reference voltage that defines an amount of current is applied. Therefore, the voltage of the first main terminal is the specified voltage VD applied to the current control terminal of the second transistor and the voltage between the current control terminal of the second transistor and the reference voltage terminal (referred to as threshold voltage Vbe or Vth). Determined by the sum.
Since the first transistor and the second transistor are transistors of the same conductivity type, a transistor having equivalent performance can be obtained. Therefore, when the voltage of the current control terminal of the first transistor becomes equal to or lower than the specified voltage VD during the synchronization signal period, the voltage between the current control terminal of the first transistor and the reference voltage terminal also becomes the threshold voltage Vbe or Vth, The transistor becomes conductive. As a result, the potential of the second main terminal rises due to the third resistor, and the voltage of the current control terminal of the first transistor connected to the second main terminal via the second resistor is equal to or lower than the specified voltage VD. And is clamped to the specified voltage VD.
That is, since the temperature characteristics of the first transistor and the second transistor are the same, the current control terminal voltage of the first transistor is a clamped voltage having the specified voltage VD as a peak regardless of the temperature.

In the clamp circuit, the first transistor and the second transistor may be a PNP transistor or a p-channel field effect transistor.

The input analog signal (CVBS) is a signal that keeps the voltage during the synchronization signal period constant. If the first and second transistors are PNP transistors or p-type FETs, in the case of a positive CVBS, the synchronization period voltage is the minimum voltage, so that the minimum voltage is the specified voltage VB.

In the clamp circuit, the first transistor and the second transistor may be an NPN transistor or an n-channel field effect transistor.

If the first and second transistors are NPN type transistors or n-type FETs, in the case of negative polarity CVBS, the synchronization period voltage is the maximum voltage, so the maximum voltage is set to the specified voltage VB.

In addition, a signal processing system according to another aspect of the present invention includes the clamp circuit and an AD conversion circuit connected to the clamp circuit.

In the above signal processing system, the clamp circuit is arranged immediately before the AD conversion circuit, so that the signal obtained by cutting the DC component of the input analog signal is within the input voltage range of the AD conversion circuit.

The signal processing system may further include a digital clamp circuit that further performs pedestal clamp processing on the signal after AD conversion by the AD conversion circuit.

By arranging a digital clamp circuit that performs pedestal clamp processing, a back porch period (pedestal period) after AD conversion is detected, and a digital clamp is applied again so that the value of the period becomes a predetermined value, whereby a video signal To reproduce the minimum signal level more accurately.

According to the clamp circuit of one aspect of the present invention, the minimum value or the maximum value of the voltage after clamping the input analog signal becomes equal to the specified voltage VD, and the threshold voltage of the first or second transistor becomes the clamped voltage. Since it is not included, the temperature dependence of the voltage after clamping is reduced.
For this reason, there is an effect that the voltage range that can be digitized by the AD conversion circuit connected to the next stage of the clamp circuit can be effectively used.
In addition, since the voltage range in which AD conversion can be performed can be used effectively, in a signal processing system including a clamp circuit, the gradation resolution of the AD conversion circuit can be used effectively, and a smooth image with little quantization error can be displayed. .

2 is a block diagram showing an overall configuration of a liquid crystal display device 111. FIG. 3 is a block diagram showing a configuration of a Y / C separation circuit 115. FIG. 3 is a circuit diagram of a clamp circuit 120. FIG. 6 is a diagram for explaining temperature characteristics of a clamp circuit 120. FIG. 2 is a block diagram illustrating an overall configuration of an imaging apparatus 211. FIG. 3 is a circuit diagram of a clamp circuit 215. FIG. It is a signal waveform diagram of negative polarity CVBS. 3 is a circuit diagram of a clamp circuit 311. FIG. 6 is a circuit configuration diagram of a clamp circuit described in Patent Document 1. FIG. It is a signal waveform diagram of positive CVBS. 6 is a circuit configuration diagram of a clamp circuit described in Patent Document 1. FIG. 6 is a circuit configuration diagram of a clamp circuit described in Patent Document 2. FIG. It is a figure which shows the base-emitter voltage VBE dependence of the base current IB in an NPN type transistor. It is a figure which shows the forward voltage VF dependence of the forward current IF in a PN diode. 6 is a circuit configuration diagram of a clamp circuit described in Patent Document 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing the overall configuration of a liquid crystal display device 111 to which the clamp circuit of the present invention is applied.
As shown in FIG. 1, the liquid crystal display device 111 includes a liquid crystal module 112 for displaying an image, and an image processing engine 113 (SoC; System-on-a-) for supplying a video signal for display to the liquid crystal module 112. Chip) and a tuner 114 for detecting an RF signal (video signal) supplied to the image processing engine 113. Here, a description will be given assuming a broadcast wave as the video signal. The broadcast wave is an interlace signal such as NTSC or PAL.

The image processing engine 113 includes a Y / C separation circuit 115, an NR circuit 116 (noise reduction processing device), and an I / P conversion circuit 117, and performs predetermined processing on the detected RF signal (video signal). To the subsequent liquid crystal module (display device) 112.
That is, the liquid crystal display device 111 detects an RF signal received from an antenna or a cable by the tuner 114 and transmits a CVBS (composite video signal) to the image processing engine 113.

In the image processing engine 113, the CVBS is separated into the luminance signal Y and the color signal C by the Y / C separation circuit 115. The NR circuit 116 removes noise from the Y / C signal and outputs it to the I / P conversion circuit 117. The I / P conversion circuit 117 converts the resolution of the input video in accordance with the resolution of the liquid crystal and outputs it to the liquid crystal module 112.

In the liquid crystal module 112, the input video signal is received by the TCON circuit 118 (timing controller), converted into a signal and timing according to the specifications of the LCD 119 (liquid crystal panel), and displayed on the LCD 119. The LCD 119 is a display panel (display unit) arranged in a matrix and having pixels corresponding to input image data.

FIG. 2 is a diagram showing a block configuration of the Y / C separation circuit 115.
As shown in FIG. 2, the Y / C separation circuit 115 shifts the voltage level of the analog CVBS (composite video signal) by the clamp circuit 120, digitizes the analog CVBS by the ADC circuit 121 (Analog to Digital Converter), and decodes the decoder. At 122, the luminance signal Y and the color signal CbCr are separated.

FIG. 3 is a diagram illustrating a circuit configuration of the clamp circuit 120 and a relationship with the ADC circuit 121 and the like at the next stage.
As shown in FIG. 3, the analog CVBS is once DC-cut by the capacitor 101, multiplied by LPF as necessary, and input to the ADC circuit 121.
The ADC circuit 121 converts an analog signal into a digital signal. The input level of the ADC circuit 121 is in the range of 0V to 2V. Therefore, the clamp circuit 120 adjusts the voltage at the connection point (point E) between the clamp circuit 120 and the ADC circuit 121 after the DC cut to fall within a range of, for example, 0V to 2V.

The problem solving means of the present invention is applied to the clamp circuit 120.
In the present embodiment, a clamp circuit 120 whose circuit configuration is shown in FIG. 3 is used as means for solving the problems of the present invention.
That is, the clamp circuit 120 supplies CVBS to the base terminal of the PNP transistor 102 (first transistor) through the capacitor 101, and the emitter terminals (each transistor of each transistor) of the PNP transistor 102 and PNP transistor 103 (second transistor). A first main terminal that is connected to either one of the pair of main terminals and to which a reference voltage that defines a current amount is applied is connected to one terminal (first terminal) of the first resistor 104. The other terminal (second terminal) of the first resistor 104 is connected to a positive voltage source (+ power supply), and a specified voltage VD is applied to the base terminal (current control terminal) of the PNP transistor 103. A second resistor 105 is disposed between the base terminal of the PNP transistor 102 and the collector terminal (a second main terminal different from the first main terminal of the pair of main terminals). The third resistor 106 is arranged between the collector terminal and the negative voltage source (-power supply).
The collector terminal of the PNP transistor 103 is also connected to the negative voltage source.
The specified voltage VD of the PNP transistor 103 is set to a value lower than the positive voltage source by the constant voltage source 108 by Vbe3 or more. Here, Vbe3 is a base-emitter threshold voltage of the PNP transistor 103. The capacitor 107 is a capacitor for preventing the fluctuation of the specified voltage VD.

In the clamp circuit 120 shown in FIG. 3, the voltage VB of the emitter terminals (indicated by point B) of the PNP transistor 102 and PNP transistor 103 (PNP bipolar transistor) is the base terminal (indicated by point D) of the PNP transistor 103. ) And the base-emitter threshold voltage Vbe3 of the PNP transistor 103, the value is represented by the following equation (3).
VB = VD + Vbe3 (3)
In FIG. 10, the minimum voltage of the positive CVBS is a voltage in the synchronization period indicated by the point F.
When the voltage VE at the point E becomes equal to or lower than the voltage represented by the following equation (4) during this synchronization period, the PNP transistor 102 becomes conductive.
VE <VB−Vbe2 = VD + Vbe3−Vbe2 (4)
Here, Vbe2 is a base-emitter threshold voltage of the PNP transistor 102.

When the voltage during this synchronization period becomes VE <VB−Vbe2, the voltage at the collector terminal (indicated by point C) of the PNP transistor 102 increases due to the collector current of the PNP transistor 102 flowing through the resistor 106. In addition, the resistor 105 provided between the collector terminal and the base terminal of the PNP transistor 102 increases the voltage at point E. When VE≈VB−Vbe2, the PNP transistor 102 becomes non-conductive.
In this manner, the clamp circuit 120 can set the input voltage to the ADC circuit 121 to a value that does not include the threshold voltage of the first or second transistor in the synchronization period in which the CVBS signal is the minimum voltage. That is, by making the first transistor and the second transistor have the same structure, the threshold voltage Vbe3 of the second transistor and the threshold voltage Vbe2 of the first transistor can be made equal in the above equation (4). Accordingly, the clamp circuit 120 can output a clamp voltage (voltage level VD) that does not depend on temperature to the ADC circuit 121 in the synchronization period of the CVBS signal.

After that, the voltage at the point E changes as VE ≧ VB−Vbe2 due to the CVBS signal in the actual video signal transmission period. However, since the charge of the capacitor 101 flows out through the resistors 105 and 106, the voltage at the point E is eventually reached. When VE <VB−Vbe2, the PNP transistor 102 becomes conductive again. However, the PNP transistor 102 cannot be turned on during the actual video signal transmission period.
Therefore, the time constant τ is increased by sufficiently increasing the value of the capacitor 101 and the value of the resistor 105 that determine the charge discharge period.
Specifically, the value of each element constituting the clamp circuit 120 was set as follows. For example, the capacitor 101 is 0.047 μF, the resistor 105 is 1 MΩ, the resistor 106 is 80 kΩ, the resistor 104 is 3.9 kΩ, the positive voltage is +5 V, and the negative voltage is −2 V.
For this reason, the time constant τ of the charge discharge period is about 0.047 seconds obtained by the product of the capacitor 101 and the resistor 105, and can be made sufficiently larger than the 1H period (for example, 60 μs) of CVBS. Accordingly, the clamp circuit 120 can set the voltage at the point E to the voltage of the specified voltage VD every time the CVBS signal is in the synchronization period. In addition, since the clamp circuit 120 suppresses the voltage fluctuation at the point E every 1H period, the minimum resolution of the ADC circuit 121 that is the next stage of the clamp circuit 120 can be kept within 1 LSB.

FIG. 4 shows a graph comparing the temperature characteristics of the synchronization period voltage between the clamp circuit 120 of the present invention shown in FIG. 3 and the conventional clamp circuit shown in FIG.
FIG. 4 shows how much the output voltage (synchronization period voltage) deviates from the output voltage of 25 ° C. between the ambient temperature between −25 ° C. and 70 ° C. (relative deviation). In FIG. 4, the temperature dependency of the “temperature compensation type” indicated by the symbol X is the temperature dependency of the clamp circuit 120, and the temperature dependency of the “diode type” indicated by the symbol Y is the temperature dependency of the conventional clamp circuit. is there.
As shown in FIG. 4, the synchronization period voltage of the conventional clamp circuit has a temperature dependence of about ± 100 mV, whereas in the clamp circuit 120 of the present application shown in FIG. It turns out that it is almost constant regardless.
For this reason, in the prior art, considering the temperature dependence, the input voltage range at 25 ° C. of the AD converter circuit in the next stage had to be 0.1 V to 1.9 V. In the present invention, however, the temperature dependence is reduced. Without consideration, the input voltage range at 25 ° C. of the AD converter circuit in the next stage can be set to 0V to 2.0V.
In other words, by arranging the clamp circuit 120 of the present invention immediately before the ADC circuit 121 as shown in FIG. 3, the input voltage range of the AD converter circuit is not affected by the temperature dependence of the output voltage of the clamp circuit. Effective use.
Note that the voltage difference between the synchronization period voltage indicated by point F in FIG. 10 and the back porch period (pedestal period) indicated by point G varies depending on the broadcast environment in which the CVBS is transmitted. Therefore, after AD conversion of the video signal by the ADC circuit 121, the timing of the back porch period is detected, and the value of the video signal is changed so that the average value of the period becomes a predetermined value. Since the minimum signal level of the video signal can be more accurately reproduced by such pedestal clamp processing, it is more preferable to dispose the pedestal clamp circuit 123 after the ADC circuit 121 as shown in FIG.

[Second Embodiment]
In the second embodiment, an example in which the clamp circuit of the present invention is applied to another image processing system will be described.
FIG. 5 shows a configuration of the imaging device 211.
In the imaging device 211, an optical signal is converted into an RGB analog signal by a CCD 212 (Charge Coupled Device), and the converted RGB analog signal is converted into a video signal or a CVBS digital signal by a signal processing circuit 213.
In the IF circuit 214, the video signal output from the signal processing circuit 213 is converted into an HDMI signal (digital signal conforming to the High-Definition Multimedia Interface standard) by the HDMI_IF circuit 219, and the CVBS digital signal is converted into a CVBS analog signal by the DAC circuit 220. Convert.
The signal processing circuit 213 clamps the input RGB analog signal by the clamp circuit 215, digitally converts it by the ADC circuit 216, converts it to a YCbCr signal by the image processing circuit 217, and converts it to a CVBS digital signal by the encoder 218. The YCbCr signal is a signal for displaying an image, and is a luminance signal (Y) representing brightness, a color difference signal (Cb) that is a difference between the luminance signal and blue, and a difference between the luminance signal and red. This is a video signal that expresses a color with three pieces of information of a certain color difference signal (Cr).

The clamp circuit of the present invention can also be applied to such an RGB signal clamp circuit 215. In the present embodiment, an example in which the clamp circuit is configured by an FET (Field Effect Transistor) will be described.
FIG. 6 is a diagram illustrating a circuit configuration of the clamp circuit 120 and a relationship with the ADC circuit 216 and the like at the next stage. The pedestal clamp circuit 223 is a circuit having the same function as that of the pedestal clamp circuit 123 in the first embodiment, and thus the description thereof is omitted.
A clamp circuit 215 shown in FIG. 6 is a circuit in which the PNP transistor 102 and the PNP transistor 103 in the clamp circuit 120 shown in FIG. 3 are replaced with p-type FET 202 and p-type FET 203 which are p-channel field effect transistors, respectively. .
That is, the clamp circuit 215 applies CVBS to the gate terminal of the p-type FET 202 (first transistor) through the capacitor 201, and the source terminals (a pair of main terminals of each transistor) of the p-type FET 202 and the p-type FET 203 (second transistor). And a first main terminal to which a reference voltage defining a current amount is applied is connected to one terminal of the first resistor 204. Further, the other terminal of the first resistor 204 is connected to a positive voltage source (+ power supply), and a specified voltage VD is applied to the gate terminal of the p-type FET 203. Further, a second resistor 205 is disposed between the gate terminal (current control terminal) of the p-type FET 202 and the drain terminal (second main terminal different from the first main terminal among the pair of main terminals), In this configuration, a third resistor 206 is disposed between the drain terminal of the p-type FET 202 and a negative voltage source (-power supply).
The drain terminal of the p-type FET 203 is also connected to the negative voltage source.
In addition, the specified voltage VD of the p-type FET 203 is set to a value lower than the positive voltage source by the constant voltage source 208 by Vgs3 or more. Here, Vgs3 is a gate-source threshold voltage of the FET 203. The capacitor 207 is a capacitor for preventing the fluctuation of the specified voltage VD.

Also in the clamp circuit 215 shown in FIG. 6, the voltage VB of the source terminal (indicated by point B) of the p-type FET 202 and p-type FET 203 is equal to the voltage VD of the gate terminal (indicated by point D) of the p-type FET 203. Using the gate-source threshold voltage Vgs3 of the FET 203, the value is expressed by the following equation (5).
VB = VD + Vgs3 (5)
Since the analog RGB signal also has a positive blanking period like the positive CVBS, if the voltage VE of the gate terminal (indicated by point E) of the p-type FET 202 becomes equal to or lower than the following voltage during that period, the p-type FET 202 Conduct.
VE <VB−Vgs2 = VD + Vgs3−Vgs2 (6)
Here, Vgs <b> 2 is a gate-source threshold voltage of the p-type FET 202.

When the voltage during the blanking period is VE <VB−Vgs2, the voltage at the drain terminal (indicated by point C) of the p-type FET 202 increases, the voltage at point E is increased through the resistor 205, and VE≈VB−Vgs2 The FET 202 becomes non-conductive.
Thereby, the clamp circuit 215 sets the input voltage to the ADC circuit 216 at the next stage to a value not including the threshold voltage of the p-type FET 202 or the p-type FET 203 in the positive blanking period in which the analog RGB signal is the minimum voltage. can do. That is, in the above equation (6), the p-type FET 202 and the p-type FET 203 have the same structure, whereby the threshold voltage Vgs3 of the p-type FET 203 and the threshold voltage Vgs2 of the p-type FET 202 can be made equal. Thereby, the clamp circuit 215 can output the clamp voltage VD with little temperature dependence to the ADC circuit 216 during the positive blanking period of the analog RGB signal.

After that, the voltage at the point E changes as VE ≧ VB−Vgs2, but since the electric charge of the capacitor 201 flows out through the resistors 205 and 206, VE <VB−Vgs2 is eventually reached in the synchronization period, and the p-type FET 202 again becomes Conduct.
Thus, in the clamp circuit 215, the same effect as the clamp circuit 120 can be obtained even if a p-type FET is used instead of the NPN transistor of the clamp circuit 120.
In particular, since the p-type FET can be realized by an ASIC process that forms only a CMOS transistor, the clamp circuit of the present invention can be incorporated in an LSI manufactured using only a CMOS transistor.

[Third Embodiment]
In the third embodiment, a case where negative CVBS is handled will be described.
FIG. 7 is a signal waveform diagram of negative polarity CVBS.
In the negative CVBS shown in FIG. 7, the maximum voltage is the voltage in the synchronization period.
For such a negative CVBS, if the clamp circuit 120 shown in FIG. 3 or the clamp circuit 215 shown in FIG. 6 is used, the voltage during the period of the video signal peak in FIG. It becomes VD. However, since the peak of the video signal varies depending on the video, even if this period is constant, the voltage during the synchronization period indicated by point F in FIG.
Therefore, a clamp circuit that can keep the positive maximum voltage constant is required.
FIG. 8 is a diagram illustrating a relationship between the circuit configuration of the clamp circuit 311 that makes the positive maximum voltage constant, the ADC circuit 312 that is the next stage circuit of the clamp circuit 311, and the like. The ADC circuit 312, the pedestal clamp circuit 313, and the decoder 314 are circuits having the same functions as the ADC circuit 121, the pedestal clamp circuit 123, and the decoder 122 in the first embodiment, and thus description thereof is omitted. .

The clamp circuit 311 shown in FIG. 8 applies CVBS through the capacitor 301 to the gate terminal of an n-type FET 302 (first transistor) which is an n-channel field effect transistor, and the sources of the n-type FET 302 and the n-type FET 303 (second transistor). A terminal (a first main terminal connected to either one of a pair of main terminals of each transistor and to which a reference voltage defining a current amount is applied) is connected to one terminal of the first resistor 304. Further, the other terminal of the first resistor 304 is connected to a negative voltage source (−power supply), and a specified voltage VD is applied to the gate terminal of the n-type FET 303. Also, a second resistor 305 is disposed between the gate terminal (current control terminal) of the n-type FET 302 and the drain terminal (second main terminal different from the first main terminal of the pair of main terminals), The third resistor 306 is arranged between the drain terminal of the n-type FET 302 and the positive voltage source (+ power supply).
Note that the drain terminal of the n-type FET 303 is also connected to a positive voltage source.
Also, the specified voltage VD of the n-type FET 303 is set to a value higher than the negative voltage source by the constant voltage source 308 by Vgs3 or more. Here, Vgs3 is the gate-source threshold voltage of the FET 303.

Also in the clamp circuit 311 shown in FIG. 8, the voltage VB of the source terminals (indicated by point B) of the n-type FET 302 and the n-type FET 303 is equal to the voltage VD of the gate terminal (indicated by point D) of the n-type FET 303. Using the gate-source threshold voltage Vgs3 of the FET 303, the value is expressed by the following equation (7).
VB = VD−Vgs3 (7)
In FIG. 7, the maximum voltage of the negative CVBS is the voltage during the synchronization period indicated by the point F.
When the voltage VE at the point E becomes equal to or higher than the voltage represented by the following expression (4) during this synchronization period, the n-type FET 302 becomes conductive.
VE> VB + Vgs2 = VD−Vgs3 + Vgs2 (8)
When the voltage during this synchronization period is VE> VB + Vgs2, the voltage at point C decreases, the voltage at point E is decreased through the resistor 305, and when VE≈VB + Vgs2, the n-type FET 302 becomes non-conductive.
After that, the voltage at the point E changes as VE ≦ VB + Vgs2, but since the capacitor 301 is charged through the resistors 305 and 306, the voltage in the synchronization period eventually becomes VE> VB + Vgs2, and the n-type FET 302 becomes conductive again. To do.
Thus, the clamp circuit of the present invention is also effective for negative polarity signals.
Of course, as described in the first embodiment and the second embodiment, the FET and the bipolar transistor can be replaced. Therefore, the n-type FET in the third embodiment is replaced with an NPN transistor, and the negative polarity CVBS is replaced. A clamp circuit may be configured.

The aspect of the present invention can be applied to an apparatus that processes an image signal and an audio signal. In particular, the present invention can be suitably applied to a display device that displays a moving image.

2, 8, 9, 15 NPN type transistor 6, 102, 103 PNP type transistor 3, R1, R2, 7, 10, 12, 16, 19, 104, 105, 106, 204, 205, 206, 304, 305, 306 Resistor 17, 4, C1, 101, 107, 201, 207, 301, 307 Capacitor 5 Sync separation circuit 13 Bias circuit 21, I input terminal 22 Current source 23 Switch element 24 AD conversion circuit 25 Pedestal level detection circuit 26 Comparison circuit 27 Reference data 28 Clamp pulse generation circuit 108, 208, 308 Constant voltage source 111 Liquid crystal display device 112 Liquid crystal module 113 Image processing engine 114 Tuner 115 Y / C separation circuit 116 NR circuit 117 I / P conversion circuit 118 TCON circuit 120, 21 , 311,50,51,52 clamp circuit 123,223,313 pedestal clamp circuit 121,216,312 ADC circuit 213 a signal processing circuit 214,219 IF circuit 217 the image processing circuit 218 encoder 220 DAC circuit 202, 203 p-type FET
302,303 n-type FET
119 LCD

Claims (5)

1. A capacitor,
   A first transistor connected to the capacitor;
   A current control terminal to which a specified voltage is applied; a second transistor having the same conductivity type as the first transistor;
   A first resistor having a first terminal and a second terminal, which is connected to one of a pair of main terminals of each of the first transistor and the second transistor, and defines a current amount. A first resistor to which a first main terminal to which a reference voltage is applied is connected to the first terminal;
   A first voltage source connected to the second terminal of the first resistor;
   A second resistor disposed between a current control terminal of the first transistor and a second main terminal different from the first main terminal of the pair of main terminals;
   A second voltage source connected to the second main terminal of the second transistor;
   A third resistor disposed between the second main terminal of the first transistor and the second voltage source;
   Including
   A clamp circuit that applies an external signal to the current control terminal of the first transistor through the capacitor.
2. The clamp circuit according to claim 1, wherein the first transistor and the second transistor are PNP bipolar transistors or p-channel field effect transistors.
3. 2. The clamp circuit according to claim 1, wherein the first transistor and the second transistor are an NPN bipolar transistor or an n-channel field effect transistor.
4. The clamp circuit according to any one of claims 1 to 3,
   A signal processing system including an AD conversion circuit connected to the clamp circuit.
5. 5. The signal processing system according to claim 4, further comprising a digital clamp circuit for further performing a pedestal clamp process on the signal after AD conversion by the AD conversion circuit.

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