WO2013021571A1 - Physical quantity detecting apparatus - Google Patents

Abstract

This physical quantity detecting apparatus is provided with a physical quantity sensor, a correction voltage generating circuit, and an adding circuit. The correction voltage generating circuit is provided with a voltage generator, a plurality of comparators, a plurality of OR circuits, a plurality of switches, and an output circuit. The physical quantity detecting apparatus is capable of excellently correcting nonlinearity between a physical quantity that operates to the physical quantity sensor, and a voltage that corresponds to the physical quantity.

Description

Physical quantity detection device

The present invention relates to a physical quantity detection device that outputs electrical signals corresponding to various physical quantities.

FIG. 12A is a block diagram of a current detection device 500 which is a conventional physical quantity detection device. The photocurrent sensor 2 detects a measured current I flowing in a conductor 1 such as a distribution line. The photocurrent sensor 2 includes a core 3, a photocurrent element 4 disposed in a gap between the cores 3, a light emitting element 5, and a light receiving element 6. When the current I to be measured flows through the conductor 1, a magnetic field is generated around the conductor 1, and the magnetic field is collected by the core 3 and applied to the photocurrent element 4. Light input from the light emitting element 5 to the photocurrent element 4 is subjected to intensity modulation by this magnetic field. The light whose intensity is modulated is converted into an electric signal by the light receiving element 6 and amplified, and an output signal corresponding to the current I to be measured is output to the output terminal 7.

FIG. 12B shows a characteristic 7 a that is a relationship between the current I to be measured and the output signal from the output terminal 7 of the photocurrent sensor 2. The input / output characteristics of each element constituting the photocurrent sensor 2 have nonlinearity, and the nonlinearity itself has individual differences. Therefore, as shown in FIG. 12B, the output signal is not strictly proportional to the current I to be measured, and an error occurs in the measurement result of the current I. In the current detection device 500, an A / D converter 8 and a CPU 10 to which a writable read-only memory 9 such as an EEPROM is connected are connected to the subsequent stage of the output terminal 7. The CPU 10 compensates for nonlinearity of the photocurrent sensor 2. That is, the output signal characteristic 7a at the output end 7 of the photocurrent sensor 2 is divided into a plurality of blocks in advance. A plurality of first-order correction equations approximating those blocks of the characteristic 7a are set. These correction formulas are written and stored in the memory 9, and the CPU 10 is installed with a program for executing correction using these correction formulas.

The output signal at the output terminal 7 of the photocurrent sensor 2 is converted into a digital signal by the A / D converter 8 and input to the CPU 10. The CPU 10 discriminates one of the plurality of blocks having the characteristic 7a into which the output signal is input, reads a correction formula corresponding to the block from the memory 9, and calculates a correction value. As a result, the output signal at the output terminal 11 of the CPU 10 has a characteristic 7b that is exactly proportional to the measured current I as shown in FIG. 12B.

In the conventional current detection device 500, the correction formula set for each of the plurality of blocks of the characteristic 7a of the photocurrent sensor 2 is stored in the memory 9, and the output signal of the photocurrent sensor 2 is output from the A / D converter 8. After being converted into a digital signal, it is corrected using a correction formula by calculation by the CPU 10. Therefore, the current detection device 500 is complicated, expensive, and large. In addition, since the calculation by the CPU 10 takes time, the current detection device 500 may not be able to measure the current I accurately when the change in the measured current I is fast.

Patent Document 1 describes a conventional physical quantity detection device similar to the current detection device 500.

JP-A-63-79016

The physical quantity detection device includes a physical quantity sensor, a correction voltage generation circuit, and an addition circuit. The physical quantity sensor outputs a voltage V (x) corresponding to an arbitrary physical quantity x between the physical quantity a and the physical quantity b on a one-to-one basis. The correction voltage generation circuit generates a correction voltage. The adder circuit adds a correction voltage to the voltage V (x). The physical quantity sensor outputs a voltage V (a) corresponding to the physical quantity a, and outputs a voltage V (b) higher than the voltage V (a) corresponding to the physical quantity b. The physical quantity sensor is expressed by the following formula:
Y (x) = V (a) + {V (b) -V (a)}. (Xa) / (ba)
The absolute value of the difference voltage Z (x), which is the difference between the voltage Y (x) and the voltage V (x) indicated by the formula, takes the maximum value Z (c) in the physical quantity c, and is between the physical quantity a and the physical quantity c. The differential voltage Z (x) is monotonously changed with respect to an arbitrary physical quantity, and the differential voltage Z (x) is monotonously changed with respect to the arbitrary physical quantity x. The correction voltage generation circuit includes a voltage generator that generates a voltage V (a), a voltage V (b), and a voltage V (c).

The correction voltage generation circuit includes: a voltage generator that generates a voltage V (a), a voltage V (b), and a voltage V (c); a plurality of first resistors that are connected in series; 2n comparators (n is a predetermined constant satisfying n ≧ 3), a plurality of second resistors connected in series with each other, a first to n-th OR circuit, and a plurality of switches in series with each other. A plurality of connected third resistors, fourth and fifth resistors, and an output circuit are provided.

The first connection point to which the voltage V (a) is applied, the second connection point, ..., the kth connection point, ..., the n-1th connection point, and the voltage V (c) is applied The plurality of first resistors are connected to the second connection point from the first connection point to the nth connection point,..., The kth connection point, so that the nth connection points connected in this order. ..., connected in series with the (n−1) th connection point (k is an arbitrary integer satisfying 2 ≦ k ≦ n−1).

The first comparator compares the voltage V (a) with the voltage V (x). The kth comparator compares the voltage at the kth connection point with the voltage V (x). The nth comparator compares the voltage V (c) with the voltage V (x).

The (n + 1) th connection point, the (n + 2) th connection point,..., The (n + k) connection point, the (2n-1) th connection point, and the voltage V (c) are applied. The plurality of second resistors are connected to the (n + 2) -th connection point from the (n + 1) -th connection point to the (2n) -th connection point,..., The (n + k) -th connection point. ..., connected in series with the 2n-1th connection point.

The (n + 1) th comparator compares the voltage V (b) with the voltage V (x). The n + k comparator compares the voltage at the n + k connection point with the voltage V (x). The 2nth comparator compares the voltage V (c) with the voltage V (x).

The first OR circuit takes the OR of the signals output from the first and (n + 1) th comparators. The kth OR circuit calculates the logical sum of the signals output from the kth and n + k comparators. The nth OR circuit calculates the logical sum of signals output from the nth and 2nth comparators.

The plurality of switches are controlled by the first OR circuit to the nth OR circuit, respectively.

The plurality of third resistors are respectively connected in parallel to the plurality of switches, and are connected in series between the 2n + 1 connection point to which the first predetermined voltage is applied and the 2n + 2 connection point. ing.

The fourth resistor is connected in series to the plurality of third resistors between the (n + 1) th connection point and the (n + 2) th connection point.

The fifth resistor is connected between the n + 3 connection point to which the second predetermined voltage is applied and the n + 2 connection point. The output circuit outputs a correction voltage based on the voltage at the (n + 2) th connection point.

This physical quantity detection device can satisfactorily correct non-linearity between a physical quantity such as a current and an electric signal corresponding to the physical quantity without providing a complicated arithmetic device, and can follow a high-speed change in the physical quantity.

FIG. 1A is a block diagram of a physical quantity detection device according to Embodiment 1 of the present invention. FIG. 1B is a diagram illustrating a relationship between a physical quantity and an output voltage of the physical quantity sensor in the physical quantity detection device according to the first exemplary embodiment. FIG. 2 is a circuit diagram of a correction voltage generation circuit of the physical quantity detection device according to the first embodiment. FIG. 3A is a conceptual diagram showing the relationship between the input voltage of the correction voltage generation circuit and the voltage at the connection point in the first embodiment. FIG. 3B is a conceptual diagram showing the relationship between the voltage input to the correction voltage generation circuit and the correction voltage in the first exemplary embodiment. FIG. 4A is a circuit diagram of an addition circuit of the physical quantity detection device according to the first exemplary embodiment. FIG. 4B is a conceptual diagram showing a voltage output from the adder circuit in the first embodiment. FIG. 4C is a circuit diagram of an inverting circuit connected to the output terminal of the adder circuit in the first embodiment. 4D is a conceptual diagram showing an output voltage of the inverting circuit shown in FIG. 4C. FIG. 5 is a circuit diagram of another correction voltage generation circuit of the physical quantity detection device according to the first exemplary embodiment. FIG. 6A is a circuit diagram of the physical quantity detection device according to Embodiment 2 of the present invention. FIG. 6B is a diagram showing a relationship between the output voltage of the physical quantity detection device and the current to be measured in the second embodiment. FIG. 7 is a circuit diagram of a correction voltage generation circuit of the physical quantity detection device according to the second embodiment. FIG. 8A is a conceptual diagram showing an input voltage of the correction voltage generating circuit in the second embodiment. FIG. 8B is a conceptual diagram showing the relationship between the voltage input to the correction voltage generation circuit and the output correction voltage in the second embodiment. FIG. 9 is a circuit diagram of another correction voltage generation circuit according to the second embodiment. FIG. 10 is a diagram illustrating a simulation result of the correction voltage generation circuit according to the second embodiment. FIG. 11 is a circuit diagram of still another correction voltage generation circuit of the physical quantity detection device according to the second embodiment. FIG. 12A is a block diagram of a conventional physical quantity detection device. FIG. 12B is a diagram showing the relationship between the output of the photocurrent sensor of the conventional physical quantity detection device and the current I to be measured.

(Embodiment 1)
FIG. 1A is a block diagram of the physical quantity detection device 21 according to Embodiment 1 of the present invention. The physical quantity detection device 21 includes a physical quantity sensor 22, a correction voltage generation circuit 23, and an addition circuit 24. Physical quantities such as angular velocity, current, and magnetic field act on the physical quantity sensor 22 and output a voltage from the output terminal 25 in response to the physical quantity. The inspection device 26 is used in the manufacturing process of the physical quantity detection device 21, measures the voltage output from the physical quantity sensor 22 corresponding to the physical quantity, and designates a parameter for causing the correction voltage generation circuit 23 to generate the correction voltage. The inspection device 26 causes the known physical quantity 26 a to continuously act on the physical quantity sensor 22 within a predetermined range, and sequentially stores the voltage 22 a output from the physical quantity sensor 22.

FIG. 1B is a diagram showing the relationship between the physical quantity acting on the physical quantity sensor 22 and the output voltage 22 a of the physical quantity sensor 22. The physical quantity sensor 22 outputs a voltage V (a) corresponding to the physical quantity a, and outputs a voltage V (b) higher than the voltage V (a) corresponding to the physical quantity b. The physical quantity sensor 22 outputs a voltage V (x) corresponding to an arbitrary physical quantity x between the physical quantity a and the physical quantity b. At this time, the voltage V (x) has an output characteristic that is convex downward between the physical quantities a and b. A voltage Y (x) represented by Formula 1A representing a straight line connecting coordinates (a, V (a)) and (b, V (b)) is obtained.

Y (x) = V (a) + {V (b) −V (a)} · (x−a) / (b−a) (Formula 1A)
A difference voltage Z (x), which is a difference obtained by subtracting the voltage Y (x) from the voltage V (x), takes a maximum value Z (c) in the physical quantity c. The difference voltage Z (x) monotonously changes between the physical quantity a and the physical quantity c with respect to the arbitrary physical quantity x, and the difference voltage Z (x between the physical quantity c and the physical quantity b with respect to the arbitrary physical quantity x. ) Is changing monotonously. The inspection device 26 detects four parameters: voltages V (a), V (b), differential voltage Z (c), and voltage V (c).

The correction voltage generation circuit 23 has an input terminal 23a and an output terminal 23b. A voltage V (x) that is a voltage 22a output from the physical quantity sensor 22 is input to the input terminal 23a. The correction voltage V123 is output from the output terminal 23b. The voltage 22a output from the physical quantity sensor 22 is input to the adder circuit 24 to the input terminal 24a of the adder circuit 24, and the correction voltage V123 output from the correction voltage generator circuit 23 is input to the input terminal 24b.

FIG. 2 is a circuit diagram of the correction voltage generation circuit 23. The voltage generator 40 includes a DC power supply 41 and resistors 42a, 42b, 43a, 43b, 44a, 44b. The inspection device 26 uses a laser adjustment device or the like to adjust the resistance values of the resistors 42a to 44b, and the voltage at the connection point where the resistors 42a and 42b are connected, and the connection point where the resistors 43a and 43b are connected. And the voltage at the connection point where the resistors 44a and 44b are connected are set to voltages V (b), V (c), and V (a), respectively.

The resistors 50a, 50b, 50c, 50d, and 50e are connected in series in this order. The voltage V (a) is applied to the connection point P1, which is one end 51 of the resistor 50a opposite to the connection point P2 to which the resistors 50a and 50b are connected. The voltage V (c) is applied to the connection point P6 which is one end 52 of the resistor 50e on the opposite side of the connection point P5 to which the resistors 50d and 50e are connected. Similarly, the resistors 53a, 53b, 53c, 53d, and 53e are connected in series in this order. The voltage V (c) is applied to the connection point P12 which is one end 54 of the resistor 53a on the side opposite to the connection point P11 to which the resistors 53a and 53b are connected. A voltage V (b) is applied to a connection point P7 which is one end 55 of the resistor 53e on the opposite side of the connection point P8 to which the resistors 53d and 53e are connected.

The comparator 56a compares the voltage V (x) (voltage 22a) from the physical quantity sensor 22 input to the input terminal 23a with the voltage V (a) applied to one end 51 of the resistor 50a, and the voltage V (x) is When the voltage V (a) is lower than “1”, an active level signal is output, and when it is higher, “0”, an inactive level signal is output. The comparator 56b compares the voltage V (x) with the voltage V1 at the connection point P2 to which the resistors 50a and 50b are connected. When the voltage V (x) is lower than the voltage V1, it is “1”, that is, the active level. When the signal is high, a signal of “0”, that is, an inactive level is output. Similarly, the comparator 56c compares the voltage V (x) with the voltage V2 at the connection point P3 to which the resistors 50b and 50c are connected. When the voltage V (x) is lower than the voltage V2, “1”, that is, active A level signal is output, and when it is high, a signal of “0”, that is, an inactive level is output. Similarly, the comparator 56d compares the voltage V (x) with the voltage V3 at the connection point P4 to which the resistors 50c and 50d are connected. When the voltage V (x) is lower than the voltage V3, the comparator 56d is active. A level signal is output, and when it is high, a signal of “0”, that is, an inactive level is output. Similarly, the comparator 56e compares the voltage V (x) with the voltage V4 at the connection point P5 to which the resistors 50d and 50e are connected. When the voltage V (x) is lower than the voltage V4, “1”, that is, active A level signal is output, and when it is high, a signal of “0”, that is, an inactive level is output. The comparator 56f compares the voltage V (x) with the voltage V (c) applied to the one end 52 of the resistor 50e. When the voltage V (x) is lower than the voltage V (c), the comparator 56f is “1”, that is, the active level. When the signal is high, a signal of “0”, that is, an inactive level is output.

The comparator 57a compares the voltage V (x) with the voltage V (c) applied to the one end 54 of the resistor 53a. When the voltage V (x) is lower than the voltage V (c), the comparator 57a is “0”, that is, an inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output. The comparator 57b compares the voltage V (x) with the voltage V5 at the connection point P11 to which the resistors 53a and 53b are connected. When the voltage V (x) is lower than the voltage V5, the comparator 57b is inactive. A level signal is output, and when it is high, an active level signal is output. Similarly, the comparator 57c compares the voltage V (x) with the voltage V6 at the connection point P10 to which the resistors 53b and 53c are connected. When the voltage V (x) is lower than the voltage V6, the comparator 57c is “0”. An active level signal is output, and when it is high, “1”, that is, an active level signal is output. The comparator 57d compares the voltage V (x) with the voltage V7 at the connection point P9 to which the resistors 53c and 53d are connected. When the voltage V (x) is lower than the voltage V7, “0”, that is, the inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output. The comparator 57e compares the voltage V (x) with the voltage V8 at the connection point P8 to which the resistors 53d and 53e are connected. When the voltage V (x) is lower than the voltage V8, “0”, that is, the inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output. The comparator 57f compares the voltage V (x) with the voltage V (b) applied to the one end 55 of the resistor 53e. When the voltage V (x) is lower than the voltage V (b), the comparator 57f is “0”, that is, inactive. A level signal is output, and when it is high, an active level signal is output.

The OR circuit 58a calculates the logical sum of the signals output from the comparators 56a and 57f, outputs an inactive level signal only when both of these signals are at the inactive level, and outputs at least one of these signals. An active level signal is output when the signal is at an active level. Similarly, the OR circuit 58b calculates the logical sum of the signals output from the comparators 56b and 57e, and outputs an inactive level signal only when both of these signals are at the inactive level. When at least one of the signals is at an active level, an active level signal is output. The OR circuit 58c calculates the logical sum of the signals output from the comparators 56c and 57d, outputs an inactive level signal only when both of these signals are at the inactive level, and at least one of these signals. An active level signal is output when the signal of is active level. The OR circuit 58d calculates the logical sum of the signals output from the comparators 56d and 57c, and outputs an inactive level signal only when both of these signals are at an inactive level, and at least one of these signals. An active level signal is output when the signal of is active level. The OR circuit 58e calculates the logical sum of the signals output from the comparators 56e and 57b, and outputs an inactive level signal only when both of these signals are at an inactive level, and at least one of these signals. An active level signal is output when the signal of is active level. The logical sum circuit 58f calculates the logical sum of the signals output from the comparators 56f and 57a, outputs an inactive level signal only when both of these signals are at the inactive level, and at least one of these signals. An active level signal is output when the signal of is active level.

The switch 59a is operated and closed when the signal output from the OR circuit 58a is at the active level, and is not operated and opened when the signal is at the inactive level. Similarly, the switches 59b, 59c, 59d, 59e, and 59f operate and close when the signals output from the OR circuits 58b, 58c, 58d, 58e, and 58f are at the active level, and these signals are inactive. At the time of non-operation and open. The switches 59a, 59b, 59c, 59d, 59e, and 59f are connected in series in this order. One end 60 of the switch 59f is connected to the DC power supply 41, and one end 61 of the switch 59a is connected to one end of the resistor 62. The other end of the resistor 62 is connected to one end of the resistor 63, and the other end of the resistor 63 is connected to the ground.

The resistors 64a, 64b, 64c, 64d, 64e, and 64f are respectively connected to both ends of the switches 59a, 59b, 59c, 59d, 59e, and 59f, that is, parallel to the switches 59a, 59b, 59c, 59d, 59e, and 59f, respectively. It is connected.

The sign of the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected is inverted by the output circuit 65, and the voltage V9 whose sign is inverted is output from the output terminal 23b as the correction voltage V123.

The operation of the correction voltage generation circuit 23 shown in FIG. 2 will be described. When an arbitrary physical quantity x between the physical quantity a and the physical quantity b acts on the physical quantity sensor 22, a voltage V (x) is generated from the physical quantity sensor 22 and input to the input terminal 23 a of the correction voltage generation circuit 23. The voltage V (x) is compared with the voltages V (a), V1, V2, V3, V4, V (c), V5, V6, V7, V8, V (b) in the comparators 56a to 56f and 57a to 57f, respectively. The

When the voltage V (x) is the voltage V (a), the signals output from the comparators 56a to 56f are “1”, that is, the active level, and the signals output from the comparators 57a to 57f are “0”, that is, the inactive level. The signals output from all the OR circuits 58a to 58f are "1", that is, the active level, and all the switches 59a to 59f are operated and closed. When the resistors 62 and 63 have the resistance value R, the voltage V9 of the connection point 901b to which the resistors 62 and 63 are connected is determined by the voltage Vcc of the DC power supply 41.
{R / (2.R)}. Vcc = Vcc / 2 (Formula 1B)
It becomes.

When the voltage V (x) is between the voltages V (a) and V1, the signals output from the comparator 56a and the comparators 57a to 57f are “0”, that is, inactive levels, and the signals output from the comparators 56b to 56f are “1”, that is, the active level. As a result, only the signal output from the OR circuit 58a is "0", that is, the inactive level, and the signals output from the OR circuits 58b to 58f are "1", that is, the active level, so that only the switch 59a is inoperative. The other switches 59b to 59f are operated and closed. When the resistors 64a, 64b, 64c, 64d, 64e, and 64f have the resistance value r1, the voltage V9 is
{R / (2.R + r1)}. Vcc (Formula 2)
Thus, the voltage V (x) is lower than the voltage Vcc / 2 shown in Expression 1B when the voltages V (x) and V (a) are equal.

When the voltage V (x) further increases and is between the voltages V4 and V (c), only the signal output from the comparator 56f becomes “1”, that is, the active level, and the other comparators 56a to 56e and 57a to 57f. All of the signals output by “0” are “0”, that is, inactive level. As a result, only the signal output from the OR circuit 58f is “1”, that is, the active level, and the signals output from the other OR circuits 58a to 58e are set to the inactive level. Thereby, the switches 59a, 59b, 59c, 59d, and 59e are inoperative and opened, and only the switch 59f is operated and closed. Therefore, the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected is {R / (2 · R + 5 · r1)} · Vcc (Equation 3)
And then further decrease.

When the voltage V (x) coincides with V (c), the signals output from the comparators 56a to 56f and the comparators 57a to 57f are all “0”, that is, the inactive level. As a result, all the signals output from the OR circuits 58a to 58f become “0”, that is, inactive level. As a result, all of the switches 59a, 59b, 59c, 59d, 59e, and 59f are inoperative and opened. Therefore, the voltage V9 is {R / (2 · R + 6 · r1)} · Vcc (Equation 4)
It becomes. The voltage V9 shown in Expression 4 is the lowest voltage V9min of the voltage V9. The inspection device 26 has a difference between Vcc / 2 and the minimum voltage V9min shown in Equation 5,
Vcc / 2− {R / (2 · R + 6 · r1)} · Vcc (Formula 5)
Is set equal to the differential voltage Z (c) shown in FIG. 1B by using a laser adjusting device or the like to set the resistance value R of the resistors 62 and 63 or the resistance value r1 of the resistors 64a to 64f.

Next, when the voltage V (x) is between the voltages V (c) and V5, only the signal output from the comparator 57a becomes “1”, that is, the active level, and the other comparators 56a to 56f, 57b to 57f. All of the signals output by “0” are “0”, that is, inactive level. As a result, the signal output from the OR circuit 58a is “1”, that is, the active level, and the signals that are output from the other OR circuits 58b to 58f are “0”, that is, the inactive level. As a result, the switch 59a is operated and closed, and the other switches 59b to 59f are all inactivated and opened. Therefore, the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected is {R / (2 · R + 5 · r1)} · Vcc (Expression 6).
Thus, the voltage rises again from the minimum voltage V9min shown in Equation 5.

Next, when the voltage V (x) is between the voltages V8 and V (b), the signals output from the comparators 56a to 56f and 57f are “0”, that is, inactive levels, and the outputs of the comparators 57a to 57e are output. Signal to be "1", that is, an active level. As a result, only the signal output from the OR circuit 58f is "0", that is, the inactive level, and the signals output from the other OR circuits 58a to 58e are "1", that is, the active level. As a result, only the switch 59f is deactivated and opened, and the other switches 59a to 59e are all activated and closed. Therefore, the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected is again
{R / (2.R + r1)}. Vcc (Expression 7)
It becomes.

Next, when the voltages V (x) and V (b) match, all the signals output from the comparators 56a to 56f are “0”, that is, inactive, and all the signals output from the comparators 57a to 57f are “1”. That is, it becomes an active level. As a result, all the signals output from the OR circuits 58a to 58f become “1”, that is, the active level. As a result, all the switches 59a to 59f are operated to be in a closed state. Therefore, the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected is again
{R / (2 · R)} · Vcc = Vcc / 2 (Formula 8)
It becomes.

FIG. 3A is a conceptual diagram showing a change of the voltage V9 at the connection point 901b to which the resistors 62 and 63 are connected with respect to the voltage V (x). FIG. 3B is a conceptual diagram showing the correction voltage V123 output from the output terminal 23b of the correction voltage generation circuit 23. The output circuit 65 includes an operational amplifier having a non-inverting input terminal to which the voltage Vcc / 2 is applied. The voltage V9 is input to the inverting input terminal of the operational amplifier, is inverted with respect to the voltage Vcc / 2, and is output from the output circuit 65 as the correction voltage V123 shown in Expression 8A.
V123 = Vcc / 2−V9 (Formula 8A)
As shown in Expression 8A, the sign of the voltage V9 is inverted in the correction voltage V123, that is, the output circuit 65 inverts the sign of the voltage V9 and outputs it as the correction voltage V123. Thereby, the correction voltage generation circuit 23 can output the correction voltage V123 approximate to the difference voltage Z (x) between the voltage Y (x) shown in FIG. 1B and the expression 1A from the output terminal 23b.

FIG. 4A is a circuit diagram of the adder circuit 24. In the addition circuit 24, the correction voltage V123 from the correction voltage generation circuit 23 applied to the input terminal 24b is added to the voltage V (x) from the physical quantity sensor 22 applied to the input terminal 24a. The adder circuit 24 includes an operational amplifier having a non-inverting input terminal to which the voltage Vcc / 2 is input. FIG. 4B shows the voltage output to the output terminal 25 of the adder circuit 24. As shown in FIG. 4B, physical quantity detection is performed in the physical quantity sensor 22 having non-linear output characteristics in which the voltage V (x) output by the action of the physical quantity x between the two physical quantities a and b has a downward convexity. The device 21 can correct the nonlinearity satisfactorily and output a voltage having an output characteristic having linearity from the output terminal 25.

The physical quantity detection device 21 may invert the output of the addition circuit 24 and output it. FIG. 4C is a circuit diagram of the inverting circuit 66 connected to the output terminal 25 of the adder circuit 24. The inverting circuit 66 includes an operational amplifier having a non-inverting input terminal to which the voltage Vcc / 2 is input. FIG. 4D is a diagram conceptually showing the voltage output from the output terminal 67 of the inverting circuit 66. The voltage output from the output terminal 67 is obtained by inverting the voltage output from the output terminal of the adder circuit 24 with respect to the voltage Vcc / 2. As shown in FIGS. 4D and 1B, the physical quantity detection device 21 has an output characteristic such that the voltage V (x) output by the physical quantity x between the two physical quantities a and b acts downward. The nonlinearity of the physical quantity sensor 22 can be corrected well.

As is apparent from the above description, the physical quantity detection device 21 according to the first embodiment is configured so that a physical quantity and a voltage corresponding to the physical quantity can be obtained without providing a complicated arithmetic device such as an A / D converter, a semiconductor memory, or a CPU. Nonlinearity can be corrected well. Since a CPU that requires a certain amount of calculation time is not provided, the physical quantity detection device 21 has a very high response speed, and can easily follow even when the physical quantity changes at high speed. It can be measured accurately. In the first embodiment, the correction voltage generation circuit 23 includes five resistors 50a to 50e that divide the voltages V (a) and V (c), and the voltages V (c) and V (b). Five resistors 53a to 53e for dividing the voltage between them, and twelve comparators 56a to 56f and 57a to 57f for comparing the voltage divided by these resistors with the voltage V (x) output from the physical quantity sensor 22 6 OR circuits 58a to 58f to which signals output from these comparators are input, 6 switches 59a to 59f controlled by these OR circuits, and these switches are connected in parallel. The six resistors 64a to 64f are provided. The number of these components is not limited to the above. Assuming that n is a predetermined integer satisfying n ≧ 3, the physical quantity detection device according to the first embodiment generally includes n−1 resistors that divide the voltages V (a) and V (c), and the voltage V ( c) n-1 resistors for dividing the voltage between V (b), 2n comparators for comparing the voltage divided by these resistors with the voltage V (x) output from the physical quantity sensor, , N logical sum circuits to which the outputs of these comparators are input, n switches respectively controlled by these logical sum circuits, and n resistors respectively connected in parallel to these switches. Prepare.

Specifically, the correction voltage generating circuit 23 shown in FIG. 2 generally has the following configuration, where k is an arbitrary integer satisfying 2 ≦ k ≦ n−1.

The voltage generator 40 generates a voltage V (a), a voltage V (b), and a voltage V (c).

The plurality of resistors (50a to 50e) include a first connection point (P1) to which the voltage V (a) is applied,..., A kth connection point (P2 to P5), and a voltage V (c). Is connected in series from the first connection point (P1) to the nth connection point (P6) at the kth connection point (P2 to P5) so that the nth connection point (P6) to which N is applied is connected in this order. It is connected to the.

The first comparator (56a) compares the voltage V (a) with the voltage V (x). The kth comparators (56b to 56e) compare the voltage at the kth connection point (P2 to P5) with the voltage V (x). The nth comparator (56f) compares the voltage V (c) with the voltage V (x).

The plurality of resistors (53e to 53a) are connected to the (n + 1) th connection point (P7) to which the voltage V (b) is applied,..., The (n + k) connection point (P8 to P11), and the voltage V (c). Are connected in series from the (n + 1) th connection point (P7) to the (2n) th connection point (P12) at the (n + k) th connection points (P8 to P11). It is connected to the.

The n + 1th comparator (57f) compares the voltage V (b) with the voltage V (x). The n + k comparators (57e to 57b) compare the voltage at the connection point of the n + k with the voltage V (x). The nth comparator (57a) compares the voltage V (c) with the voltage V (x).

The first OR circuit (58a) takes the OR of the signal output from the first comparator (56a) and the signal output from the (n + 1) th comparator (57f). The kth OR circuit (58b to 58e) takes the logical sum of the signal output from the kth comparator (56b to 56e) and the signal output from the n + k comparator (57e to 57b). The nth OR circuit calculates the logical sum of the signal output from the nth comparator (56f) and the signal output from the 2nth comparator (57a).

The plurality of switches (59a to 59f) are controlled by OR circuits 58a to 58f, respectively. The plurality of resistors 64a to 64f are connected in parallel to the plurality of switches 59a to 59f, respectively, and are connected in series to each other between the connection point 901a and the connection point 901b to which a predetermined voltage (Vcc) is applied. ing. The resistor 62 is connected in series with a plurality of resistors 64a to 64f between the connection points 901a and 901b. The resistor 63 is connected between a connection point 901c and a connection point 901b to which a predetermined voltage (ground voltage) is applied. The output circuit 65 outputs a correction voltage V123 based on the voltage V9 at the connection point 901b.

FIG. 5 is a circuit diagram of another correction voltage generation circuit 23P of the physical quantity detection device 21 in the first embodiment. In FIG. 5, the same reference numerals are assigned to the same portions as those of the correction voltage generation circuit 23 shown in FIG.

In the correction voltage generation circuit 23 shown in FIG. 2, the voltage Vcc is applied to the connection point 901a, and the connection point 901c is connected to the ground. That is, the predetermined voltage applied to the connection point 901a is the voltage Vcc, which is higher than the predetermined voltage applied to the connection point 901c. The output circuit 65 inverts the voltage V9 at the connection point 901b with respect to the voltage Vcc / 2 to generate a correction voltage V123, and inverts the sign of the voltage V9.

In the correction voltage generation circuit 23P shown in FIG. 5, the connection point 901a is connected to the ground, and the voltage Vcc is applied to the connection point 901c. That is, the predetermined voltage applied to the connection point 901a is a ground voltage and is lower than the predetermined voltage Vcc applied to the connection point 901c. The correction voltage generation circuit 23P has an output circuit 65P instead of the output circuit 65 shown in FIG. In the output circuit 65P, the connection point 901b is connected to the non-inverting input terminal of the operational amplifier, and the voltage V9 is applied. The operational amplifier outputs the voltage V9 as it is as the correction voltage V123, and does not invert the sign of the voltage V9. The correction voltage generation circuit 23P functions similarly to the correction voltage generation circuit 23 shown in FIG. 2 and has the same effect.

(Embodiment 2)
FIG. 6A is a circuit diagram of the physical quantity sensor 22 according to Embodiment 2 of the present invention. In the second embodiment, the physical quantity sensor 22 is a current sensor. In the second embodiment, the same parts as those in the physical quantity detection device in the first embodiment shown in FIG.

The physical quantity sensor 22 includes a magnetoresistive element unit 70, a differential amplifier 72, a signal processing unit 73, and a bias magnet 70f that applies a bias magnetic field to the magnetoresistive element unit 70. The magnetoresistive element unit 70 includes magnetoresistive elements 70a, 70b, 70c, and 70d made of magnetoresistive thin films connected in a bridge. The connection point 170a to which the magnetoresistive elements 70a and 70d are connected is connected to a power source, and the connection point 170b to which the magnetoresistive elements 70b and 70c are connected is connected to the ground. In a state where no magnetic field is applied to the magnetoresistive element unit 70 from the outside, the bridge composed of the magnetoresistive elements 70a, 70b, 70c, and 70d is balanced, and the connection point 170c to which the magnetoresistive elements 70a and 70b are connected, and the magnetoresistive element The characteristics of the magnetoresistive elements 70a to 70d are set so as to have the same potential as the connection point 170d to which the elements 70c and 70d are connected. When the current I to be measured flows through the conductor 71 placed in the vicinity of the magnetoresistive element portion 70, the resistance values of the magnetoresistive elements 70a, 70b, 70c, and 70d change due to the magnetic field generated around the conductor, and the magnetoresistance The balance of the bridge composed of the elements 70a, 70b, 70c, and 70d is broken, and a potential difference is generated between the connection point 170c between the magnetoresistive elements 70a and 70b and the connection point 170d between the magnetoresistive elements 70c and 70d. This potential difference is amplified by the differential amplifier 72, adjusted to 0 set and adjusted in sensitivity by the signal processing unit 73, and corresponds to the magnetic field acting on the magnetoresistive element unit 70 at the output terminal 74, that is, the measured current I flowing through the conductor 71. Output voltage.

FIG. 6B is a diagram showing the relationship between the physical quantity x, which is the value of the current I to be measured, and the voltage V (x) output from the physical quantity sensor 22. 6A and 6B, the value of the maximum current I of the measured current I flowing through the conductor 71 in the direction D1 is the physical quantity a, and the maximum current of the measured current I flowing through the conductor 71 in the direction D2 opposite to the direction D1. The value is the physical quantity b. The physical quantity x takes an arbitrary value between the physical quantities a and b. As shown in FIG. 6B, the voltage V (x) has a so-called S-shaped characteristic in which a downward convex portion and an upward convex portion are continuous with respect to the physical quantity x.

Similar to the physical quantity detection device 21 in the first embodiment shown in FIG. 1, the inspection device 26 causes the physical quantity sensor 22 to act on the physical quantity sensor 22 while continuously changing the known physical quantity x from the physical quantity a to the physical quantity b. Are sequentially stored. Then, the inspection device 26 calculates a voltage Y (x) represented by Expression 9A representing a straight line connecting the coordinates (a, V (a)), (b, V (b)).
Y (x) = V (a) + {V (b) -V (a)}. (Xa) / (ba) (Equation 9A)
The inspection device 26 uses a physical quantity c that is a current at which a difference voltage Z (x) that is a difference between the voltage Y (x) and the voltage V (x) becomes zero, and a difference voltage Z (x) between the physical quantities a and c. A physical quantity d that is the current with the maximum absolute value, a physical quantity e that is the current with the maximum absolute value of the difference voltage Z (x) between the physical quantities c and b, and a physical quantity a that is the value of the current I to be measured. , B, c, d and e, the voltages V (a), V (b), V (c), V (d) and V (e) output from the physical quantity sensor 22 and the differential voltage Z ( d) The seven parameters Z (e) are detected and stored.

FIG. 7 is a circuit diagram of the correction voltage generation circuit 23 according to the second embodiment. The voltage generator 80 includes a DC power supply 81 and resistors 82a, 82b, 82c, 82d, 83a, 83b, 83c, and 83d. The inspection device 26 adjusts the resistors 82a to 83d using a laser adjusting device or the like, and the voltage at the connection point to which the resistors 82a and 83d are connected, the voltage at the connection point to which the resistors 82a and 82b are connected, and the resistor 82c. , 82b, the voltage at the connection point to which the resistors 83c and 83d are connected, and the voltage at the connection point to which the resistors 83a and 83b are connected are the voltages V (a) and V (b ), V (c), V (d), and V (e).

The resistors 90a, 90b, 90c, 90d, and 90e are connected in series in this order. The voltage V (a) is applied to the connection point P21 which is one end 91 of the resistor 90a on the opposite side of the connection point P22 to which the resistors 90a and 90b are connected. The voltage V (d) is applied to the connection point P26 which is one end 92 of the resistor 90e on the opposite side of the connection point P25 to which the resistors 90d and 90e are connected. Similarly, the resistors 93a, 93b, 93c, 93d, and 93e are connected in series in this order. The voltage V (d) is applied to the connection point P32 which is one end 94 of the resistor 93a on the opposite side of the connection point P31 to which the resistors 93a and 93b are connected. The voltage V (c) is applied to the connection point P27 which is one end 95 of the resistor 93e on the opposite side of the connection point P28 to which the resistors 93d and 93e are connected.

The comparator 96a compares the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a with the voltage V (a) applied to one end 91 of the resistor 90a, and the voltage V (x) is the voltage V (a "1", that is, an active level signal is output when it is lower, and "0", that is, an inactive level signal, when it is higher. The comparator 96b compares the voltage V (x) with the voltage V21 at the connection point P22 to which the resistors 90a and 90b are connected. When the voltage V (x) is lower than the voltage V21, the comparator 96b is “1”, that is, an active level signal. When the signal is high, a signal of “0”, that is, an inactive level is output. Similarly, the comparator 96c compares the voltage V (x) with the voltage V22 at the connection point P23 to which the resistors 90b and 90c are connected. When the voltage V (x) is lower than the voltage V22, the comparator 96c is “1”, that is, the active level. When the signal is high, a signal of “0”, that is, an inactive level is output. The comparator 96d compares the voltage V (x) with the voltage V23 at the connection point P24 to which the resistors 90c and 90d are connected. When the voltage V (x) is lower than the voltage V23, the comparator 96d is “1”, that is, the active level. A signal is output, and when it is high, a signal of “0”, that is, an inactive level is output. The comparator 96e compares the voltage V (x) with the voltage V24 at the connection point P25 to which the resistors 90d and 90e are connected. When the voltage V (x) is lower than the voltage V24, the comparator 96e outputs “1”, that is, an active level signal. When it is high, a signal of “0”, that is, an inactive level is output. The comparator 96f compares the voltage V (x) with the voltage V (d) applied to the one end 92 of the resistor 90e. When the voltage V (x) is lower than the voltage V (d), the comparator 96f is “1”, that is, the active level. When the signal is high, a signal of “0”, that is, an inactive level is output.

The comparator 97a compares the voltage V (x) with the voltage V (d) applied to one end 94 of the resistor 93a. When the voltage V (x) is lower than the voltage V (d), the comparator 97a is “0”, that is, an inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output. The comparator 97b compares the voltage V (x) with the voltage V25 at the connection point P31 to which the resistors 93a and 93b are connected, and when the voltage V (x) is lower than the voltage V25, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 97c compares the voltage V (x) with the voltage V26 at the connection point P30 to which the resistors 93b and 93c are connected, and when the voltage V (x) is lower than the voltage V26, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 97d compares the voltage V (x) with the voltage V27 at the connection point P29 to which the resistors 93c and 93d are connected. When the voltage V (x) is lower than the voltage V27, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 97e compares the voltage V (x) with the voltage V28 at the connection point P28 to which the resistors 93d and 93e are connected, and when the voltage V (x) is lower than the voltage V28, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 97f compares the voltage V (x) with the voltage V (c) applied to the one end 95 of the resistor 93e. When the voltage V (x) is lower than the voltage V (c), the comparator 97f is “0”, that is, an inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output.

The OR circuit 98a calculates the logical sum of the signals output from the comparators 96a and 97f, and outputs an inactive level signal when both of the signals output from the comparators 96a and 97f are at an inactive level. When at least one of them is at the active level, an active level signal is output. The logical sum circuit 98b takes the logical sum of the signals output from the comparators 96b and 97e, and outputs an inactive level signal when both the signals output from the comparators 96b and 97e are at the inactive level. When at least one of them is at the active level, an active level signal is output. Similarly, the OR circuit 98c calculates the logical sum of the signals output from the comparators 96c and 97d, and outputs an inactive level signal when both the signals output from the comparators 96c and 97d are at the inactive level. An active level signal is output when at least one of the signals is at an active level. The OR circuit 98d calculates the logical sum of the signals output from the comparators 96d and 97c, and outputs an inactive level signal when both of the signals output from the comparators 96d and 97c are at the inactive level. When at least one of them is at the active level, an active level signal is output. The OR circuit 98e calculates the logical sum of the signals output from the comparators 96e and 97b, and outputs an inactive level signal when both the signals output from the comparators 96e and 97b are in an inactive level. When at least one of them is at the active level, an active level signal is output. The OR circuit 98f calculates the logical sum of the signals output from the comparators 96f and 97a, and outputs an inactive level signal when both the signals output from the comparators 96f and 97a are at the inactive level. When at least one of them is at the active level, an active level signal is output.

The switch 99a is operated and closed when the signal output from the OR circuit 98a is "1", that is, active level, and is not operated and opened when the signal is "0", that is, inactive level. The switches 99b, 99c, 99d, 99e, and 99f are closed when the signals output from the OR circuits 98b, 98c, 98d, 98e, and 98f are “1”, that is, at the active level, and these signals are “0”. In other words, it is inoperative and opened at the inactive level. The switches 99a, 99b, 99c, 99d, 99e, 99f are connected in series with each other. One end 100 of the switch 99f is connected to the DC power supply 81, and one end 101 of the switch 99a is connected to one end of the resistor 102. The other end of the resistor 102 is connected to one end of the resistor 103. Resistors 104a, 104b, 104c, 104d, 104e, and 104f are connected to both ends of the switches 99a, 99b, 99c, 99d, 99e, and 99f, and are connected in parallel with the switches 99a, 99b, 99c, 99d, 99e, and 99f, respectively. Yes.

The resistors 110a, 110b, 110c, 110d, and 110e are connected in series in this order. A voltage V (c) is applied to a connection point P41 which is one end 111 of the resistor 110a on the opposite side of the connection point P42 to which the resistors 110a and 110b are connected. A voltage V (e) is applied to a connection point P46 which is one end 112 of the resistor 110e on the opposite side of the connection point P45 to which the resistors 110d and 110e are connected. Similarly, the resistors 113a, 113b, 113c, 113d, and 113e are connected in series in this order. The voltage V (e) is applied to P52 which is one end 114 of the resistor 113a on the side opposite to the connection point P51 to which the resistors 113a and 113b are connected. The voltage V (b) is applied to the connection point P47 which is one end 115 of the resistance 113e on the side opposite to the connection point P48 to which the resistors 113d and 113e are connected.

The comparator 116a compares the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a with the voltage V (c) applied to the one end 111 of the resistor 110a, and the voltage V (x) is the voltage V (c "1", that is, an active level signal is output when it is lower, and "0", that is, an inactive level signal, when it is higher. The comparator 116b compares the voltage V (x) with the voltage V41 at the connection point P42 to which the resistors 110a and 110b are connected. When the voltage V (x) is lower than the voltage V41, the comparator 116b is “1”, that is, an active level signal. When the signal is high, a signal of “0”, that is, an inactive level is output. The comparator 116c compares the voltage V (x) with the voltage V42 at the connection point P43 to which the resistors 110b and 110c are connected. When the voltage V (x) is lower than the voltage V42, the comparator 116c outputs a signal of “1”, that is, an active level. When it is high, a signal of “0”, that is, an inactive level is output. The comparator 116d compares the voltage V (x) with the voltage V43 at the connection point P44 to which the resistors 110c and 110d are connected. When the voltage V (x) is lower than the voltage V43, the comparator 116d outputs “1”, that is, an active level signal. When it is high, a signal of “0”, that is, an inactive level is output. The comparator 116e compares the voltage V (x) with the voltage V44 at the connection point P45 to which the resistors 110d and 110e are connected. When the voltage V (x) is lower than the voltage V44, the comparator 116e outputs “1”, that is, an active level signal. When it is high, a signal of “0”, that is, an inactive level is output. The comparator 116f compares the voltage V (x) with the voltage V (e) applied to the one end 112 of the resistor 110e. When the voltage V (x) is lower than the voltage V (e), the comparator 116f is “1”, that is, the active level. A signal is output, and when it is high, a signal of “0”, that is, an inactive level is output.

The comparator 117a compares the voltage V (x) with the voltage V (e) applied to the one end 114 of the resistor 113a. When the voltage V (x) is lower than the voltage V (e), “0”, that is, an inactive level. A signal is output, and when it is high, a signal of “1”, that is, an active level is output. The comparator 117b compares the voltage V (x) with the voltage V45 at the connection point P51 to which the resistors 113a and 113b are connected. When the voltage V (x) is lower than the voltage V45, a signal of “0”, that is, an inactive level. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 117c compares the voltage V (x) with the voltage V46 at the connection point P50 to which the resistors 113b and 113c are connected. When the voltage V (x) is lower than the voltage V46, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 117d compares the voltage V (x) with the voltage V47 at the connection point P49 to which the resistors 113c and 113d are connected, and when the voltage V (x) is lower than the voltage V47, it is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 117e compares the voltage V (x) with the voltage V48 at the connection point P48 to which the resistors 113d and 113e are connected. When the voltage V (x) is lower than the voltage V48, the comparator 117e is “0”, that is, an inactive level signal. When the signal is high, a signal of “1”, that is, an active level is output. The comparator 117f compares the voltage V (x) with the voltage V (b) applied to the one end 115 of the resistor 113e. When the voltage V (x) is lower than the voltage V (b), the comparator 117f is “0”, that is, the inactive level. The signal of “1”, that is, an active level signal is output when the signal is high.

The OR circuit 118a calculates the logical sum of the signals output from the comparators 116a and 117f, and outputs an inactive level signal when both the signals output from the comparators 116a and 117f are in an inactive level. An active level signal is output when at least one of them is at an active level. The OR circuit 118b calculates the logical sum of the signals output from the comparators 116b and 117e, and outputs an inactive level signal when both of the signals output from the comparators 116b and 117e are at an inactive level. An active level signal is output when at least one of them is at an active level. The OR circuit 118c calculates the logical sum of the signals output from the comparators 116c and 117d, and outputs an inactive level signal when both the signals output from the comparators 116c and 117d are in an inactive level. An active level signal is output when at least one of them is at an active level. The logical sum circuit 118d calculates the logical sum of the signals output from the comparators 116d and 117c, and outputs an inactive level signal when both the signals output from the comparators 116d and 117c are in an inactive level. An active level signal is output when at least one of them is at an active level. The logical sum circuit 118e calculates the logical sum of the signals output from the comparators 116e and 117b, and outputs an inactive level signal when both the signals output from the comparators 116e and 117b are in an inactive level. An active level signal is output when at least one of them is at an active level. The logical sum circuit 118f calculates the logical sum of the signals output from the comparators 116f and 117a, and outputs an inactive level signal when the signals output from the comparators 116f and 117a are both in an inactive level. An active level signal is output when at least one of them is at an active level.

The switch 119a is closed when the signal output from the OR circuit 118a is "1", that is, active level, and is not operated when the signal output from the OR circuit 118a is "0", that is, when it is inactive level. Become. Similarly, the switches 119b, 119c, 119d, 119e, and 119f are closed when the signals output from the OR circuits 118b, 118c, 118d, 118e, and 118f are “1”, that is, at the active level. When it is “0”, that is, inactive level, it is inoperative and opened. The switches 119a, 119b, 119c, 119d, 119e, and 119f are connected in series with each other. One end 120 of the switch 119f is connected to the ground, and one end 121 of the switch 119a is connected to the other end of the resistor 103. The resistors 122a, 122b, 122c, 122d, 122e, and 122f are respectively connected to both ends of the switches 119a, 119b, 119c, 119d, 119e, and 119f. It is connected to the.

The operation of the correction voltage generation circuit 23 shown in FIG. When an arbitrary physical quantity x between physical quantities a and b acts on the physical quantity sensor 22, a voltage V (x) is generated from the physical quantity sensor 22 and is input to the input terminal 23 a of the correction voltage generation circuit 23. The voltage V (x) is applied to the voltages V (a), V21, V22, V23, V24, V (d), V25, V26, V27, V28, V (c), V41, in the comparators 96a to 96f and 97a to 97f. It is compared with V42, V43, V44, V (e), V45, V46, V47, V48, V (b).

When the voltage V (x) is the voltage V (a), the signals output from the comparators 96a to 96f and 116a to 116f are “1”, that is, the active level, and the signals output from the comparators 97a to 97f and 117a to 117f are “0”. In other words, all the signals output from the OR circuits 98a to 98f and 118a to 118f are set to "1", that is, the active level, and the switches 99a to 99f and 119a to 119f are all operated and closed. Thereby, one end 101 of the switch 99a is directly connected to the DC power supply 81, and one end 121 of the switch 119a is directly connected to the ground. When the resistors 102 and 103 have the resistance value R and the voltage of the DC power supply 81 is Vcc, the voltage V29 at the connection point 902b to which the resistors 102 and 103 are connected is
{R / (2 · R)} · Vcc = Vcc / 2 (Equation 9B)
It becomes.

When the voltage V (x) is between the voltages V (a) and V21, the signals output from the comparators 96a and 97a to 97f are “0”, that is, the inactive level, and the comparators 96b to 96f and 116a to 116f output. The signal is “1”, that is, an active level. As a result, only the signal output from the OR circuit 98a is “0”, that is, the inactive level, and the signals output from the other OR circuits 98b to 98f and 118a to 118f are at the active level. Operates and opens, and the other switches 99b to 99f and 119a to 119f operate and close. When the resistors 104a, 104b, 104c, 104d, 104e, and 104f have the resistance value r1, the voltage V29 at the connection point 902b to which the resistors 102 and 103 are connected is
{R / (2.R + r1)}. Vcc (Formula 10)
Thus, the voltage drops below the voltage Vcc / 2 shown in Equation 9B.

Hereinafter, as with the physical quantity detection device in the first embodiment, as the voltage V (x) approaches the voltage V (d) from the voltage V (a), the switches 99b, 99c, 99d, 99e, and 99f are sequentially provided in this order. It opens when it does not operate, and the voltage V29 decreases to reach the minimum voltage V29min shown in Equation 11.
V29min = {R / (2.R + 6.r1)}. Vcc (Formula 11)
The inspection device 26 shown in FIG. 1A uses a laser adjusting device or the like so that the difference obtained by subtracting the minimum voltage V29min from the voltage Vcc / 2 shown in Equation 12 is equal to the difference voltage Z (d) shown in FIG. 6B. A resistance value r1 of ~ 104f is set.
Vcc / 2− {R / (2 · R + 6 · r1)} · Vcc (Formula 12)
Next, as the voltage V (x) becomes higher than the voltage V (d) and approaches the voltage V (c), the switches 99f, 99e, 99d, 99c, 99b are sequentially operated and closed in this order, and the voltage V ( When x) becomes the voltage V (c), the voltage V29 is again
{R / (2.R)}. Vcc = Vcc / 2 (Formula 13)
It becomes.

When the voltage V (x) is between the voltages V (c) and V41, the signals output from the comparators 96a to 96f, 116a, 117a to 117f are “0”, that is, inactive levels, and the comparators 97a to 97f, 116b. The signals output from .about.116f are "1", that is, the active level. As a result, the outputs of the logical sum circuits 98a to 98f are 1, the output of the logical sum circuit 118a is 0, and the logical sum circuits 118b to 118f are 1. Therefore, only the switch 119a is inoperative and opened, and the other switches 99a to 99a All of 99f, 119b to 119f are operated and closed. When the resistors 122a to 122f have the resistance value r2, the voltage V29 at the connection point 902b to which the resistors 102 and 103 are connected is
{(R + r2) / (2 · R + r2)} · Vcc = [1/2 + r2 / {2 · (2 · R + r2)}] · Vcc (Formula 14)
Thus, the voltage rises from the voltage Vcc / 2 shown in Equation 13.

Hereinafter, as the voltage V (x) approaches the voltage V (e) from the voltage V (c), the switches 119b, 119c, 119d, 119e, and 119f are sequentially deactivated and opened in this order, and the voltage V29 increases. The maximum voltage V29max shown in Equation 15 is reached.
V29max = {(R + 6 · r2) / (2 · R + 6 · r2)} · Vcc = [1/2 + 6 · r2 / {2 · (2 · R + 6 · r2)}] · Vcc (Formula 15)
The inspection device 26 shown in FIG. 1A uses a laser adjustment device or the like so that the difference obtained by subtracting the maximum voltage V29max shown in Equation 16 from the voltage Vcc / 2 is equal to the difference voltage Z (e) shown in FIG. 6B. A resistance value r2 of 122f is set.
Vcc / 2− {1/2 + r2 / (2 · R + 6 · r2)} · Vcc (Equation 16)
Next, as the voltage V (x) becomes higher than the voltage V (e) and approaches the voltage V (b), the switches 119f, 119e, 119d, 119c, and 119b are sequentially operated and closed in this order, and the resistors 102, The voltage V29 at the connection point 902b to which 103 is connected is again
{R / (2 · R)} · Vcc = Vcc / 2 (Equation 17)
Return to.

FIG. 8A is a conceptual diagram showing a change in the voltage V29 at the connection point 902b to which the resistors 102 and 103 are connected with respect to the voltage V (x). FIG. 8B is a conceptual diagram showing the correction voltage V123 output from the output terminal 23b of the correction voltage generation circuit 23. The output circuit 65 shown in FIG. 7 includes an operational amplifier having a non-inverting input terminal to which the voltage Vcc / 2 is input. The voltage V29 is input to the inverting input terminal of the operational amplifier, is inverted with respect to the voltage Vcc / 2, and is output from the output terminal 23b as the correction voltage V123. That is, the sign of the voltage V29 is inverted by the output circuit 65. As a result, the correction voltage generation circuit 23 determines the difference between the voltage V (x) generated when an arbitrary physical quantity x between the physical quantities a and b acts on the physical quantity sensor 22 and the voltage Y (x) shown in Expression 9A. A correction voltage V123 approximate to a certain difference voltage Z (x) can be generated.

By inputting the correction voltage V123 into the adder circuit 24 shown in FIG. 4A, a so-called S-shaped characteristic in which the voltage V (x) has a downwardly convex portion and an upwardly convex portion with respect to the physical quantity x. Can be corrected satisfactorily.

As is apparent from the above description, in the physical quantity detection device 21 according to the second embodiment, the physical quantity sensor 22 that generates a voltage corresponding to a physical quantity such as a current is used for any physical quantity x between the two physical quantities a and b. Even if the output voltage has a first interval that protrudes upward and a second interval that protrudes downward, an arbitrary physical quantity x and an output voltage corresponding to this can be obtained without providing a complicated arithmetic unit. Can be corrected well. Since the physical quantity detection device 21 does not have a complicated arithmetic device, it has a very high response speed and can easily follow even when the physical quantity changes at high speed. In the second embodiment, the correction voltage generation circuit 23 divides the voltage V (a) and V (d) between five resistors and the voltage V (d) and V (c) 5. Are divided by these resistors, five resistors that divide the voltages V (c) and V (e), five resistors that divide the voltages V (e) and V (b), and these resistors. 24 comparators that compare the pressed voltage with the voltage V (x) output from the physical quantity sensor 22, 12 OR circuits to which the outputs of these comparators are input, and these OR circuits It includes 12 switches to be controlled and 12 resistors connected in parallel to each of these switches. The physical quantity detection device according to the second embodiment is not limited to this. If n is a predetermined integer satisfying n ≧ 3, generally n−1 pieces that divide the voltage between V (a) and V (d). , N−1 resistors dividing voltage V (d), V (c), n−1 resistors dividing voltage V (c), V (e), and voltage V (E) n-1 resistors for dividing the voltage between V (b) and 4n comparators for comparing the voltage divided by these resistors and the voltage V (x) output from the physical quantity sensor, respectively. 2n logical sum circuits to which signals output from these comparators are respectively input, 2n switches controlled by these logical sum circuits, and 2n number of switches connected in parallel to these switches, respectively. Provide resistance.

Specifically, the correction voltage generation circuit 23 shown in FIG. 7 generally has the following configuration, where k is an arbitrary integer satisfying 2 ≦ k ≦ n−1.

The voltage generator 80 generates a voltage V (a), a voltage V (b), a voltage V (c), a voltage V (d), and a voltage V (e).

The plurality of resistors (90a to 90e) are applied with the first connection point (P21) to which the voltage V (a) is applied, the kth connection point (P22 to P25), and the voltage V (d). The nth connection point (P26) is connected in series at the kth connection point (P2 to P5) from the first connection point (P1) to the nth connection point (P6) so as to be connected in this order. Yes.

The first comparator (96a) compares the voltage V (a) with the voltage V (x). The kth comparators (96b to 96e) compare the voltage at the kth connection point (P22 to P25) with the voltage V (x). The nth comparator (96f) compares the voltage V (d) with the voltage V (x).

The plurality of resistors (93e to 93a) are connected to the (n + 1) th connection point (P27) to which the voltage V (c) is applied,..., The (n + k) connection point (P28 to P31), and the voltage V (e). N + k connection points (P28 to P31) from the (n + 1) th connection point (P27) to the 2nth connection point (P32) so that the 2nth connection points (P32) to which N is applied are connected in this order. Connected in series.

The n + 1th comparator (97f) compares the voltage V (c) with the voltage V (x). The kth comparators (97e to 97b) compare the voltage at the n + k connection points (P28 to P31) with the voltage V (x). The 2nth comparator (97a) compares the voltage V (d) with the voltage V (x).

The first OR circuit (98a) takes the OR of the signal output from the first comparator (96a) and the signal output from the (n + 1) th comparator (97f). The kth OR circuit (98b to 98e) takes the OR of the signal output from the kth comparator (96b to 96e) and the signal output from the n + k comparator (97e to 97b). The nth OR circuit (98f) takes a logical sum of the signal output from the nth comparator (96f) and the signal output from the 2nth comparator (97a).

The plurality of resistors (110a to 110e) include a second n + 1 connection point (P41) to which the voltage V (c) is applied,..., A second n + k connection point (P42 to P45), and a voltage V (e). Are connected in series at the 2n + k connection points (P42 to P45) from the 2n + 1 connection point (P41) to the 3n connection point (P46) so that the 3n connection points (P46) to which N is applied are connected in this order. It is connected to the.

The 2n + 1th comparator (116a) compares the voltage V (c) with the voltage V (x). The second n + k comparators (116b to 116e) compare the voltage at the second n + k connection points (P42 to P45) with the voltage V (x). The third n comparator (116f) compares the voltage V (e) with the voltage V (x).

The plurality of resistors (113e to 113a) are connected to the third n + 1 connection point (P47) to which the voltage V (b) is applied,..., The third n + k connection point (P48 to P51), and the voltage V (e). Are connected in series at the 3n + k connection points (P48 to P51) from the 3n + 1 connection point (P47) to the 4n connection point (P52) so that the 4n connection points (P52) to which N is applied are connected in this order. It is connected to the.

The 3n + 1th comparator (117f) compares the voltage V (b) with the voltage V (x). The third n + k comparator compares the voltage at the third n + k connection point (P48 to P51) with the voltage V (x). The fourth n comparator (117a) compares the voltage V (e) with the voltage V (x).

The n + 1th logical sum circuit (118a) takes a logical sum of the signal output from the 2n + 1th comparator (116a) and the signal output from the 3n + 1th comparator (117f). The n + k logical sum circuit takes a logical sum of signals output from the second n + k comparators (116b to 116e) and signals output from the third n + k comparators (117e to 117b). The 2nth OR circuit calculates the logical sum of the signal output from the 3nth comparator (116f) and the signal output from the 4nth comparator (117a).

The plurality of switches (119a to 119f) are controlled by OR circuits (118a to 118f), respectively. The plurality of resistors (112a to 112f) are connected in parallel to the plurality of switches (119a to 119f), respectively, and between a connection point (P902a) and a connection point P902b) to which a predetermined voltage (Vcc) is applied. Are connected in series with each other. The resistor (102) is connected in series to a plurality of resistors (104a to 104f) between the connection points 902a and 902b.

The plurality of switches (119a to 119f) are controlled by OR circuits (118a to 118f), respectively. The plurality of resistors (122a to 122f) are connected in parallel to the plurality of switches (119a to 119f), respectively, and a connection point (902c) and a connection point 902b to which a predetermined voltage (ground potential) is applied. Are connected in series with each other. The resistor 103 is connected in series with a plurality of resistors 122a to 122f) between the connection points 902b and 902c. The output circuit 65 outputs the correction voltage V123 based on the voltage at the connection point 902b.

FIG. 9 is another circuit diagram of the correction voltage generation circuit 23 according to the second embodiment. In FIG. 9, the same reference numerals are assigned to the same portions as those in FIG. In the correction voltage generation circuit 23 shown in FIG. 9, the comparator, the OR circuit, and the switch are composed of transistors. In FIG. 9, the voltage V (a) is 0 V, and the voltage V (b) is the voltage Vcc of the DC power supply 131. The power supply unit 130 includes a DC power supply 131, resistors 132a, 132b, 133a, 133b, 133c, and 133d, and buffers 134a, 134b, and 134c. The inspection device 26 adjusts the resistance values of the resistors 132a to 133d using a laser adjustment device or the like, and the voltage at the connection point to which the resistors 132a and 132b are connected and the voltage at the connection point to which the resistors 133a and 133b are connected. The voltages at the connection points where the resistors 133c and 133d are connected are set to voltages V (c), V (d), and V (e), respectively. The voltage level conversion unit 135 includes a transistor having a base and a collector connected to each other and a bias resistor, and is based on the voltage VD between the base and emitter of the transistor from the voltages V (c), V (d), and V (e). Then, voltage + VD, voltage V (c) -VD, voltage V (d) + VD, voltage V (c) + VD, voltage V (e) -VD, and voltage Vcc-VD are output.

The resistors 136a, 136b, 136c, 136d, and 136e are connected in series in this order. The voltage + VD is applied to one end 137 of the resistor 136a opposite to the connection point to which the resistors 136a and 136b are connected. The voltage V (d) + VD is applied to one end 138 of the resistor 136e opposite to the connection point to which the resistors 136d and 136e are connected. Similarly, the resistors 139a, 139b, 139c, 139d, and 139e are connected in series in this order. A voltage V (d) + VD is applied to one end 140 of the resistor 139a opposite to the connection point to which the resistors 139a and 139b are connected. A voltage V (c) + VD is applied to one end 141 of the resistor 139e opposite to the connection point to which the resistors 139d and 139e are connected.

Similar to the voltage level conversion unit 135, the voltage level conversion unit 142 includes a transistor having a base and a collector connected to each other and a bias resistor, and the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a is used to determine the transistor level. The voltage V (x) + 2 · VD, the voltage V (x), and the voltage V (x) −2 · VD are output by the base-emitter voltage VD.

Switch 143a is inoperative and opens when voltage V (x) is higher than zero. The switch 143b is activated and closed when the voltage V (x) is lower than the voltage V61 at the connection point to which the resistors 136a and 136b are connected, and is deactivated and opened when the voltage V (x) is higher. The switch 143c is closed when the voltage V (x) is lower than the voltage V62 at the connection point to which the resistors 136b and 136c are connected, and is opened when the voltage V (x) is high. The switch 143d is activated and closed when the voltage V (x) is lower than the voltage V63 at the connection point to which the resistors 136c and 136d are connected, and is deactivated and opened when the voltage V (x) is higher. The switch 143e closes when the voltage V (x) is lower than the voltage V64 at the connection point to which the resistors 136d and 136e are connected, and opens when the voltage V (x) is high. The switch 143f is activated and closed when the voltage V (x) is also lower than the voltage V (d), and is deactivated and opened when the voltage V (x) is higher.

The switch 144a is activated and closed when the voltage V (x) is higher than the voltage V (d), and is deactivated and opened when the voltage V (x) is lower. The switch 144b is closed when the voltage V (x) is higher than the voltage V65 at the connection point to which the resistors 139a and 139b are connected, and is opened when the voltage V (x) is low. The switch 144c is activated and closed when the voltage V (x) is higher than the voltage V66 at the connection point to which the resistors 139b and 139c are connected, and is deactivated and opened when the voltage is low. The switch 144d is activated and closed when the voltage V (x) is higher than the voltage V67 at the connection point to which the resistors 139c and 139d are connected, and is deactivated and opened when the voltage is low. The switch 144e is closed when the voltage V (x) is higher than the voltage V68 at the connection point to which the resistors 139d and 139e are connected, and is opened when the voltage V (x) is low. The switch 144f is activated and closed when the voltage V (x) is higher than the voltage V (c), and is deactivated and opened when the voltage V (x) is lower.

The switch 145a is closed when the switch 144f is operated and closed, and is opened when the switch 144f is not operated and opened. Similarly, the switch 145b is activated and closed when the switch 144e is activated and closed, and is deactivated and opened when the switch 144e is deactivated and opened. The switch 145c is activated and closed when the switch 144d is operated and closed, and is deactivated and opened when the switch 144d is not operated and opened. The switch 145d is activated and closed when the switch 144c is operated and closed, and is deactivated and opened when the switch 144c is not operated and opened. The switch 145e is activated and closed when the switch 144b is activated and closed, and is deactivated and opened when the switch 144b is deactivated and opened. The switch 145f is operated and closed when the switch 144a is operated and closed, and is inactivated and opened when the switch 144a is not operated and opened.

The switch 146a is inactivated and opened only when both the switches 143a and 145a are inactive and open, and is operated and closed when at least one of the switches 143a and 145a is in operation and closed. That is, the switch 146a is controlled by the logical sum of the switches 143a and 145a. The switch 146b is inactivated and opened only when both the switches 143b and 145b are inactive and opened, and is activated and closed when at least one of the switches 143b and 145b is in operation and closed. That is, the switch 146b is controlled by the logical sum of the switches 143b and 145b. The switch 146c is inactivated and opened only when both the switches 143c and 145c are inactive and open, and is activated and closed when at least one of the switches 143c and 145c is in operation and closed. That is, the switch 146c is controlled by the logical sum of the switches 143c and 145c. The switch 146d is inactivated and opened only when both the switches 143d and 145d are inactive and open, and is activated and closed when at least one of the switches 143d and 145d is in operation and closed. That is, the switch 146d is controlled by the logical sum of the switches 143d and 145d. The switch 146e is inactivated and opened only when both the switches 143e and 145e are inactive and open, and is operated and closed when at least one of the switches 143e and 145e is in operation and closed. That is, the switch 146e is controlled by the logical sum of the switches 143e and 145e. The switch 146f is inactivated and opened only when both the switches 143f and 145f are inactive and open, and is operated and closed when at least one of the switches 143f and 145f is in operation and closed. That is, the switch 146f is controlled by the logical sum of the switches 143f and 145f. The switches 146a, 146b, 146c, 146d, 146e, and 146f are connected in series in this order. A connection point 903a, which is one end 147 of the switch 146f on the opposite side of the connection point to which the connection points 146e and 146f are connected, is connected to the DC power supply 131 and applied with the voltage Vcc. One end 148 of the switch 146a opposite to the connection point to which the switches 146a and 146b are connected is connected to one end of the resistor 149.

The resistor 150a is connected between the collector of the transistor constituting the switch 146a and the collector of the transistor constituting the switch 146b. The resistor 150b is connected between the collector of the transistor constituting the switch 146b and the collector of the transistor constituting the switch 146c. The resistor 150c is connected between the collector of the transistor constituting the switch 146c and the collector of the transistor constituting the switch 146d. The resistor 150d is connected between the collector of the transistor constituting the switch 146d and the collector of the transistor constituting the switch 146e. The resistor 150e is connected between the collector of the transistor constituting the switch 146e and the collector of the transistor constituting the switch 146f. The resistor 150f is connected between the collector of the transistor constituting the switch 146f and one end 147 of the switch 146f.

The resistors 151a, 151b, 151c, 151d, and 151e are connected in series in this order. A voltage V (c) -VD is applied to one end 152 of the resistor 151a on the side opposite to the connection point to which the resistors 151a and 151b are connected. A voltage V (e) -VD is applied to one end 153 of the resistor 151e on the side opposite to the connection point to which the resistors 151d and 151e are connected. Similarly, the resistors 154a, 154b, 154c, 154d, and 154e are connected in series in this order. A voltage V (e) -VD is applied to one end 155 of the resistor 154a opposite to the connection point to which the resistors 154a and 154b are connected. A voltage Vcc-VD is applied to one end 156 of the resistor 154e opposite to the connection point to which the resistors 154d and 154e are connected.

The switch 157a closes when the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a is lower than the voltage V (c), and closes when the voltage V (x) is high. The switch 157b is activated and closed when the voltage V (x) is lower than the voltage V69 at the connection point to which the resistors 151a and 151b are connected, and is deactivated and opened when the voltage V (x) is higher. The switch 157c closes when the voltage V (x) is lower than the voltage V70 at the connection point to which the resistors 151b and 151c are connected, and opens when the voltage V (x) is high. The switch 157d closes when the voltage V (x) is lower than the voltage V71 at the connection point to which the resistors 151c and 151d are connected, and closes when the voltage V (x) is high. The switch 157e is activated and closed when the voltage V (x) is lower than the voltage V72 at the connection point to which the resistors 151d and 151e are connected, and is deactivated and opened when the voltage V (x) is higher. The switch 157f is activated and closed when the voltage V (x) is lower than the voltage V (e), and is deactivated and opened when the voltage V (x) is higher.

The switch 158a is activated and closed when the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a is higher than the voltage V (e), and is deactivated and opened when the voltage V (e) is low. The switch 158b is closed when the voltage V (x) is higher than the voltage V73 at the connection point to which the resistors 154a and 154b are connected, and is opened when it is low. The switch 158c is closed when the voltage V (x) is higher than the voltage V74 at the connection point to which the resistors 154b and 154c are connected, and is opened when it is low. The switch 158d is closed when the voltage V (x) is higher than the voltage V75 at the connection point to which the resistors 154c and 154d are connected, and is opened when it is low. The switch 158e is closed when the voltage V (x) is higher than the voltage V76 at the connection point to which the resistors 154d and 154e are connected, and is opened when it is low. The switch 158f is inoperative and opens when the voltage V (x) is lower than the voltage Vcc.

The switch 159a operates and closes when the switch 158f is operated and closed, and opens when the switch 158f is not operated and opened. The switch 159b is activated and closed when the switch 158e is operated and closed, and is deactivated and opened when the switch 158e is not operated and opened. The switch 159c is operated and closed when the switch 158d is operated and closed, and is inactivated and opened when the switch 158d is not operated and opened. The switch 159d is operated and closed when the switch 158c is operated and closed, and is inactivated and opened when the switch 158c is not operated and opened. The switch 159e is activated and closed when the switch 158b is operated and closed, and is inactivated and opened when the switch 158b is not operated and opened. The switch 159f is operated and closed when the switch 158a is operated and closed, and is inactivated and opened when the switch 158a is not operated and opened.

The switch 160a is inactivated and opened only when both the switches 157a and 159a are inactive and open, and is operated and closed when at least one of the switches 157a and 159a is in operation and closed. That is, the switch 160a is controlled by the logical sum of the switches 157a and 159a. The switch 160b is deactivated and opened only when both the switches 157b and 159b are deactivated and opened, and is activated and closed when at least one of the switches 157a and 159a is activated and closed. That is, the switch 160b is controlled by the logical sum of the switches 157b and 159b. The switch 160c is inactivated and opened only when both the switches 157c and 159c are inactive and open, and is activated and closed when at least one of the switches 157c and 159c is in operation and closed. That is, the switch 160c is controlled by the logical sum of the switches 157c and 159c. The switch 160d is inactivated and opened only when both the switches 157d and 159d are inactive and open, and is operated and closed when at least one of the switches 157d and 159d is in operation and closed. That is, the switch 160d is controlled by the logical sum of the switches 157d and 159d. The switch 160e is inactivated and opened only when both the switches 157e and 159e are inactive and open, and is operated and closed when at least one of the switches 157e and 159e is in operation and closed. That is, the switch 160e is controlled by the logical sum of the switches 157e and 159e. The switch 160f is inactivated and opened only when both the switches 157f and 159f are inactive and open, and is operated and closed when at least one of the switches 157f and 159f is in operation and closed. That is, the switch 160f is controlled by the logical sum of the switches 157f and 159f. The switches 160a, 160b, 160c, 160d, 160e, and 160f are connected in series in this order. A connection point 903c, which is one end 161 of the switch 160f on the opposite side of the connection point to which the switches 160e and 160f are connected, is connected to the ground. One end 162 of the switch 160a opposite to the connection point to which the switches 160a and 160b are connected is connected to one end of the resistor 163.

The resistor 164a is connected between one end 162 of the switch 160a and the collector of the transistor constituting the switch 160a. The resistor 164b is connected between the collector of the transistor constituting the switch 160a and the collector of the transistor constituting the switch 160b. The resistor 164c is connected between the collector of the transistor constituting the switch 160b and the collector of the transistor constituting the switch 160c. The resistor 164d is connected between the collector of the transistor constituting the switch 160c and the collector of the transistor constituting the switch 160d. The resistor 164e is connected between the collector of the transistor constituting the switch 160d and the collector of the transistor constituting the switch 160e. The resistor 164f is connected between the collector of the transistor constituting the switch 160e and the collector of the transistor constituting the switch 160f.

The resistors 149 and 163 are connected at a connection point 903b.

The operation of the correction voltage generation circuit 23 shown in FIG. 9 will be described. When an arbitrary physical quantity x between the physical quantities a and b acts on the physical quantity sensor 22, a voltage V (x) is generated from the physical quantity sensor 22 and input to the input terminal 23 a of the correction voltage generation circuit 23.

The voltages V (x) and the voltages V (x) + 2 · VD and V (x) −2 · VD output from the voltage level conversion unit 142 are switches 143a to 143f, 144a to 144f, 157a to 157f, and 158a to 158f. , Voltage + VD, V61, V62, V63, V64, V (d) + VD, V65, V66, V67, V68, V (c) + VD, V (c) −VD, V69, V70, V71, V72, V (e ) -VD, V73, V74, V75, V76, Vcc-VD, and the correction voltage V123 is output from the output terminal 23b of the output circuit 65.

For example, when the voltage V (x) generated by the physical quantity sensor 22 is between the voltages V63 and V64, the switches 143e, 143f, 157a to 157f are operated and closed, and the other switches 143a to 143d are not operated. Since it opens, the switches 146e, 146f, 164a to 164f are operated and closed, and the switches 146a to 146d are not operated and opened. When the resistors 149 and 163 have the resistance value R and the resistors 150a to 150f have the resistance value r1, the voltage V29 at the connection point 903b to which the resistors 149 and 163 are connected is
{R / (2.R + 4.r1)}. Vcc (Formula 18)
It becomes. At the output terminal 23b of the output circuit 65, a correction voltage V123 obtained by inverting the voltage V29 with respect to the voltage Vcc / 2 is generated.

When the voltage V (x) generated from the physical quantity sensor 22 is between the voltages V69 and V70, the switches 143a to 143f, 144a to 144f, 157c to 157f are operated and closed, and the switches 157a, 157b, 158a to 158f is deactivated and opened. Accordingly, the switches 146a to 146f, 159c to 159f are operated to be closed, and the switches 159a and 159b are not operated to be opened. When the resistors 164a to 164f have the resistance value r2, the voltage V29 at the connection point 903b to which the resistors 149 and 163 are connected is
{(R + 2 · r2) / (2 · R + 2 · r2)} · Vcc (Equation 19)
It becomes. At the output terminal 23b of the output circuit 65, a correction voltage V123 obtained by inverting the voltage V29 with respect to the voltage Vcc / 2 is generated.

FIG. 10 shows a simulation result of the correction voltage V123 showing the effect of correcting the nonlinearity of the voltage V (x) from the physical quantity sensor 22 input to the input terminal 23a using the correction voltage generation circuit 23 shown in FIG. . Here, the voltage V (a) is 0V, the voltage V (b), that is, the voltage Vcc is 5V, the voltage V (c) is 2.5V, and the voltage V (d) is 1.25V. The voltage V (e) is 3.75V, the differential voltage Z (d) is 0.25V, and the differential voltage Z (e) is 0.25V, that is, the voltage V (x) exhibits an S-shaped characteristic. Have. The resistance value R of the resistors 149 and 163, the resistance value r1 of the resistors 150a to 150f, and the resistance value r2 of the resistors 164a to 164f are a voltage V (d) of 1.25V and a differential voltage Z (e) of 0.25V. Therefore, they are set to 50 kΩ, 1 kΩ, and 1 kΩ, respectively.

In FIG. 10, the characteristic PA indicates the voltage V (x) from the physical quantity sensor 22, and the characteristic PB indicates a straight line connecting the coordinates (a, V (a)) and (b, V (b)) shown in Expression 9A. The characteristic PC is a simulation result of the correction voltage V123 output from the output terminal of the correction voltage generation circuit 23 shown in FIG. As shown in FIG. 10, the characteristic PA having the nonlinearity of the voltage V (x) is corrected well and approximated to the characteristic PB.

FIG. 11 is a circuit diagram of another correction voltage generation circuit 23Q of the physical quantity detection device 21 in the second embodiment. 11, the same parts as those of the correction voltage generation circuit 23 shown in FIG.

7, the voltage Vcc is applied to the connection point 902a, and the connection point 902c is connected to the ground. That is, the predetermined voltage applied to the connection point 902a is the voltage Vcc, which is higher than the predetermined voltage applied to the connection point 902c. The output circuit 65 inverts the voltage V29 at the connection point 902b with respect to the voltage Vcc / 2 to generate a correction voltage V123, and inverts the sign of the voltage V29.

In the correction voltage generation circuit 23Q shown in FIG. 11, the connection point 902a is connected to the ground, and the voltage Vcc is applied to the connection point 902c. That is, the predetermined voltage applied to the connection point 902a is a ground voltage and is lower than the predetermined voltage Vcc applied to the connection point 902c. The correction voltage generation circuit 23Q has an output circuit 65P instead of the output circuit 65 shown in FIG. In the output circuit 65P, the connection point 902b is connected to the non-inverting input terminal of the operational amplifier, and the voltage V29 is applied. The operational amplifier outputs the voltage V29 as it is as the correction voltage V123, and does not invert the sign of the voltage V29. The correction voltage generation circuit 23Q functions similarly to the correction voltage generation circuit 23 shown in FIG. 7 and has the same effect.

The physical quantity detection device according to the present invention can satisfactorily correct non-linearity between a physical quantity and a voltage corresponding to the physical quantity without providing a complex arithmetic device such as an A / D converter, a semiconductor memory, or a CPU, and has a response speed. Is very fast. Therefore, this physical quantity detection device has an effect that it can easily follow even when the physical quantity changes at high speed, and is useful, for example, as a current detection device for detecting current in vehicles, industrial equipment, and the like.

22 Physical quantity sensor 23 Correction voltage generation circuit 24 Addition circuit 40 Voltage generators 50a to 50e Resistance (first resistance)
53a to 53e Resistance (second resistance)
56a to 56f Comparator (first comparator to nth comparator)
57a to 57f comparators (n + 1th comparator to 2nth comparator)
58a to 58f OR circuit (first OR circuit to nth OR circuit)
59a to 59f Switch 62 Resistance (fourth resistance)
63 Resistance (fifth resistance)
64a to 64f resistors (third resistors)
65 Output circuit 80 Voltage generators 90a to 90e Resistance (first resistance)
93a to 93e Resistance (second resistance)
96a to 96f Comparator (first comparator to nth comparator)
97a to 97f comparators (n + 1th comparator to 2nth comparator)
98a to 98f OR circuit (first OR circuit to nth OR circuit)
99a to 99f switch (first switch)
102 Resistance (sixth resistance)
103 Resistance (8th resistance)
104a to 104f Resistance (fifth resistance)
110a to 110e Resistance (third resistance)
133a to 133e Resistance (fourth resistance)
116a to 116f Comparator (2n + 1th comparator to 3nth comparator)
117a to 117f Comparator (3n + 1 comparator to 4n comparator)
118a to 118f OR circuit (n + 1th OR circuit to 2n OR circuit)
119a to 119f switch (second switch)
122a to 122f Resistance (seventh resistance)
901a to 901c connection point (2n + 1 connection point to 2n + 3 connection point)
902a to 902c connection point (4n + 1 connection point to 4n + 3 connection point)
P1 to P6 connection points (first connection point to nth connection point)
P7 to P12 connection points (n + 1th connection point to 2nth connection point)
P21 to P26 connection point (first connection point to nth connection point)
P27 to P32 connection point (n + 1th connection point to 2nth connection point)
P41 to P46 connection point (2n + 1 connection point to 3n connection point)
P47 to P52 connection points (3n + 1 connection point to 4n connection point)

Claims (8)

1. A physical quantity sensor that outputs a voltage V (x) corresponding to an arbitrary physical quantity x between the physical quantity a and the physical quantity b;
   A correction voltage generating circuit for generating a correction voltage;
   An adding circuit for adding the correction voltage to the voltage V (x);
   With
   The physical quantity sensor is
   A voltage V (a) is output corresponding to the physical quantity a,
   A voltage V (b) higher than the voltage V (a) corresponding to the physical quantity b is output,
   The following formula,
   Y (x) = V (a) + {V (b) -V (a)}. (Xa) / (ba)
   The absolute value of the difference voltage Z (x), which is the difference between the voltage Y (x) and the voltage V (x) shown in FIG.
   The difference voltage Z (x) monotonously changes with respect to an arbitrary physical quantity between the physical quantity a and the physical quantity c,
   The differential voltage Z (x) monotonously changes with respect to the arbitrary physical quantity x.
   Works like
   The correction voltage generation circuit includes:
   A voltage generator for generating the voltage V (a), the voltage V (b), and the voltage V (c);
   n is a predetermined integer satisfying n ≧ 3, k is an arbitrary integer satisfying 2 ≦ k ≦ n−1, the first connection point to which the voltage V (a) is applied, The first connection point, the kth connection point, the n-1th connection point, and the nth connection point to which the voltage V (c) is applied are connected in this order. A plurality of first connections connected in series from the second connection point to the nth connection point, the kth connection point, and the n-1th connection point. Resistance of
   A first comparator that compares the voltage V (a) and the voltage V (x), a second comparator that compares the voltage at the second connection point and the voltage V (x), A k-th comparator for comparing the voltage at the k-th connection point with the voltage V (x),..., An n-th for comparing the voltage at the n-th connection point with the voltage V (x). -1 comparator, an nth comparator for comparing the voltage V (c) and the voltage V (x),
   The (n + 1) th connection point to which the voltage V (b) is applied, the (n + 2) th connection point, the (n + k) connection point, the (2n-1) th connection point, and the voltage V (c) N + 2 connection points from the (n + 1) th connection point to the (2n) th connection point,..., The (n + k) connection point, and so on. A plurality of second resistors connected in series with the second n-1 connection point;
   An (n + 1) th comparator for comparing the voltage V (b) and the voltage V (x), an n + 2th comparator for comparing the voltage at the n + 2 connection point and the voltage V (x), An n + k comparator that compares the voltage at the n + k connection point and the voltage V (x),..., A second n that compares the voltage at the second n−1 connection point and the voltage V (x). -1 comparator, a second n comparator for comparing the voltage V (c) and the voltage V (x),
   A first OR circuit that takes a logical sum of a signal output from the first comparator and a signal output from the (n + 1) th comparator;..., A signal output from the kth comparator and an n + k comparator A k-th logical sum circuit that performs a logical sum with a signal output from the n-th comparator,..., An n-th logical sum that performs a logical sum between a signal output from the n-th comparator and a signal output from the second n-th comparator. Circuit,
   A plurality of switches respectively controlled by the first OR circuit to the nth OR circuit;
   A plurality of third switches connected in parallel to each of the plurality of switches and connected in series between a second n + 1 connection point and a second n + 2 connection point to which a first predetermined voltage is applied. Resistance,
   A fourth resistor connected in series with the plurality of third resistors between the second n + 1 connection point and the second n + 2 connection point;
   A fifth resistor connected between a second n + 3 connection point to which a second predetermined voltage is applied and the second n + 2 connection point;
   An output circuit that outputs the correction voltage based on a voltage at the second n + 2 connection point;
   A physical quantity detection device.
2. The first predetermined voltage is higher than the second predetermined voltage;
   The physical quantity detection device according to claim 1, wherein the output circuit inverts the sign of the voltage at the second end to generate the correction voltage.
3. The first predetermined voltage is lower than the second predetermined voltage;
   The physical quantity detection device according to claim 1, wherein the output circuit outputs the voltage at the second end as the correction voltage.
4. The first comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (a), and outputs an inactive level signal when the voltage is low.
   The kth comparator outputs an active level signal when the voltage V (x) is higher than the voltage at the kth connection point, and outputs an inactive level signal when the voltage is low.
   The nth comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (c), and outputs an inactive level signal when the voltage is low.
   The n + 1 th comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (b), and outputs an active level signal when the voltage V (x) is lower,
   The n + k comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage at the n + k connection point, and outputs an active level signal when the voltage is low.
   The second n comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (c), and outputs an active level signal when the voltage is low.
   The first OR circuit outputs an inactive level signal when the signal output from the first comparator and the signal output from the n + 1 comparator are both in an inactive level. When at least one of the signal output from the comparator and the signal output from the n + 1 comparator is at an active level, an active level signal is output.
   The kth OR circuit outputs an inactive level signal when the signal output from the kth comparator and the signal output from the n + k comparator are both inactive, and the kth OR circuit An active level signal is output when at least one of the signal output from the comparator and the signal output from the n + k comparator is at an active level;
   The n-th OR circuit outputs an inactive level signal when both the signal output from the n-th comparator and the signal output from the 2n comparator are in an inactive level. An active level signal is output when at least one of the signal output by the comparator and the signal output by the 2n comparator is an active level;
   The plurality of switches are closed when the nth OR circuit outputs an active level signal from the first OR circuit, and the nth OR circuit from the first OR circuit is closed. The physical quantity detection device according to claim 1, wherein the physical quantity detection device opens each time an inactive level signal is output.
5. A physical quantity sensor that outputs a voltage V (x) corresponding to an arbitrary physical quantity x between the physical quantity a and the physical quantity b;
   A correction voltage generating circuit for generating a correction voltage;
   An adding circuit for adding the correction voltage to the voltage V (x);
   With
   The physical quantity sensor is
   A voltage V (a) is output corresponding to the physical quantity a,
   A voltage V (b) higher than the voltage V (a) corresponding to the physical quantity b is output,
   The following formula,
   Y (x) = V (a) + {V (b) -V (a)}. (Xa) / (ba)
   The difference voltage Z (x), which is the difference between the voltage Y (x) and the voltage V (x) shown in FIG.
   The absolute value of the differential voltage Z (x) takes the maximum value Z (d) in the physical quantity d between the physical quantity a and the physical quantity c,
   The difference voltage Z (x) monotonously changes with respect to the arbitrary physical quantity x between the physical quantity a and the physical quantity d,
   The difference voltage Z (x) monotonously changes with respect to the arbitrary physical quantity x between the physical quantity d and the physical quantity c,
   The absolute value of the differential voltage Z (x) takes the maximum value Z (e) in the physical quantity e between the physical quantity c and the physical quantity b,
   The difference voltage Z (x) monotonously changes with respect to the arbitrary physical quantity x between the physical quantity c and the physical quantity e,
   The difference voltage ZV (x) monotonously changes between the physical quantity e and the physical quantity b with respect to the arbitrary physical quantity x.
   Works like
   The correction signal generation circuit includes:
   A voltage generator for generating the voltage V (a), the voltage V (b), the voltage V (c), the voltage V (d), and the voltage V (e);
   n is a predetermined integer satisfying n ≧ 3, k is an arbitrary integer satisfying 2 ≦ k ≦ n−1, the first connection point to which the voltage V (a) is applied, and the second The first connection point, the k-th connection point, the n-th connection point, and the n-th connection point to which the voltage V (d) is applied are connected in this order. A plurality of first connections connected in series from the second connection point to the nth connection point, the kth connection point, and the n-1th connection point. Resistance of
   A first comparator that compares the voltage V (a) and the voltage V (x), a second comparator that compares the voltage at the second connection point and the voltage V (x), A k-th comparator for comparing the voltage at the k-th connection point with the voltage V (x),..., An n-th for comparing the voltage at the n-th connection point with the voltage V (x). -1 comparator, an nth comparator for comparing the voltage V (d) and the voltage V (x),
   The (n + 1) th connection point to which the voltage V (c) is applied, the (n + 2) th connection point, the (n + k) connection point, the (2n-1) th connection point, and the voltage V (e) N + 2 connection points from the (n + 1) th connection point to the (2n) th connection point,..., The (n + k) connection point, and so on. A plurality of second resistors connected in series with the second n-1 connection point;
   An (n + 1) th comparator for comparing the voltage V (c) and the voltage V (x), an n + 2 comparator for comparing the voltage at the n + 2 connection point and the voltage V (x), An n + k comparator that compares the voltage at the n + k connection point and the voltage V (x),..., A second n that compares the voltage at the second n−1 connection point and the voltage V (x). -1 comparator, a second n comparator for comparing the voltage V (d) and the voltage V (x),
   A first OR circuit that takes a logical sum of a signal output from the first comparator and a signal output from the (n + 1) th comparator;..., A signal output from the kth comparator and an n + k comparator A k-th logical sum circuit that performs a logical sum with a signal output from the n-th comparator,..., An n-th logical sum that performs a logical sum between a signal output from the n-th comparator and a signal output from the second n-th comparator. Circuit,
   The 2n + 1 connection point to which the voltage V (c) is applied, the 2n + 2 connection point, ..., the 2n + k connection point, ..., the 3n-1 connection point, and the voltage V (e) Are connected in this order so that the second n + 2 connection point from the second n + 1 connection point to the third n connection point, the second n + k connection point, and so on. A plurality of third resistors connected in series with the third n-1 connection point;
   A second n + 1 comparator that compares the voltage V (c) and the voltage V (x), a second n + 2 comparator that compares the voltage at the second n + 2 connection point and the voltage V (x),. A second n + k comparator that compares the voltage at the second n + k connection point and the voltage V (x),..., A third n that compares the voltage at the third n−1 connection point and the voltage V (x). -1 comparator, a third n comparator for comparing the voltage V (e) and the voltage V (x),
   The 3n + 1 connection point to which the voltage V (b) is applied, the 3n + 2 connection point, the 3n + k connection point, the 4n-1 connection point, and the voltage V (e) Are connected in this order so that the 3n + 2 connection point from the 3n + 1 connection point to the 4nth connection point, the 3n + k connection point, and so on. A plurality of fourth resistors connected in series at the fourth n-1 connection point;
   A third n + 1 comparator for comparing the voltage V (b) and the voltage V (x), a third n + 2 comparator for comparing the voltage at the third n + 2 connection point and the voltage V (x), A third n + k comparator for comparing the voltage at the third n + k connection point with the voltage V (x),..., A fourth n for comparing the voltage at the fourth n-1 connection point with the voltage V (x). -1 comparator, a fourth n comparator for comparing the voltage V (e) and the voltage V (x),
   An (n + 1) -th OR circuit that takes a logical sum of a signal output from the (2n + 1) th comparator and a signal output from the (3n + 1) th comparator;..., A signal output from the second (n + k) comparator and the third (n + k) comparator An (n + k) OR circuit that takes a logical sum with the signal output from the second nth, and a second n logical sum that takes a logical sum between the signal output from the third n comparator and the signal output from the fourth n comparator. Circuit,
   A plurality of first switches respectively controlled by the first OR circuit to the nth OR circuit;
   The plurality of first switches connected in parallel to each other and connected in series between the 4n + 1 connection point to which the first predetermined voltage is applied and the 4n + 2 connection point. A fifth resistor;
   A sixth resistor connected in series to the plurality of fifth resistors between the 4n + 1 connection point and the 4n + 2 connection point;
   A plurality of second switches respectively controlled by the (n + 1) th OR circuit and the (2n) th OR circuit;
   The plurality of second switches connected in parallel to each other and connected in series between a third connection point to which a second predetermined voltage is applied and the second connection point. A seventh resistance of
   An eighth resistor connected in series with the plurality of seventh resistors between the second connection point and the third connection point;
   An output circuit that outputs the correction voltage based on the voltage at the second connection point;
   A physical quantity detection device.
6. The first predetermined voltage is higher than the second predetermined voltage;
   The physical quantity detection device according to claim 5, wherein the output circuit generates the correction voltage by inverting the sign of the voltage at the second end.
7. The first predetermined voltage is lower than the second predetermined voltage;
   The physical quantity detection device according to claim 5, wherein the output circuit outputs the voltage at the second end as the correction voltage.
8. The first comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (a), and outputs an inactive level signal when the voltage is low.
   The kth comparator outputs an active level signal when the voltage V (x) is higher than the voltage at the connection point where the k-1th resistor and the kth resistor are connected. Output inactive level signal when low,
   The nth comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (d), and outputs an inactive level signal when the voltage V (x) is low,
   The (n + 1) th comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (c), and outputs an active level signal when the voltage V (x) is lower,
   The n + k comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage at the connection point where the n + k−1 resistor and the n + k resistor are connected. And output an active level signal when it is low,
   The second n comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (d), and outputs an active level signal when the voltage V (x) is lower,
   The 2n + 1th comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (c), and outputs an inactive level signal when the voltage V (x) is low.
   The second n + k comparator outputs an active level signal when the voltage V (x) is higher than the voltage at the connection point where the second n + k−1 resistor and the second n + k resistor are connected. Output inactive level signal when low,
   The third n comparator outputs an active level signal when the voltage V (x) is higher than the voltage V (e), and outputs an inactive level signal when the voltage is low.
   The 3n + 1th comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (b), and outputs an active level signal when the voltage V (x) is lower,
   The third n + k comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage at the connection point where the third n + k−1 resistor and the third n + k resistor are connected. And output an active level signal when it is low,
   The fourth n comparator outputs an inactive level signal when the voltage V (x) is higher than the voltage V (e), and outputs an active level signal when the voltage V (x) is lower,
   The first OR circuit outputs an inactive level signal when the signal output from the first comparator and the signal output from the n + 1 comparator are both in an inactive level. When at least one of the signal output from the comparator and the signal output from the n + 1 comparator is at an active level, an active level signal is output.
   The kth OR circuit outputs an inactive level signal when the signal output from the kth comparator and the signal output from the n + k comparator are both inactive, and the kth OR circuit An active level signal is output when at least one of the signal output from the comparator and the signal output from the n + k comparator is at an active level;
   The n-th OR circuit outputs an inactive level signal when both the signal output from the n-th comparator and the signal output from the 2n comparator are in an inactive level. An active level signal is output when at least one of the signal output by the comparator and the signal output by the 4n + 2 comparator is an active level;
   The plurality of first switches are closed when the n-th OR circuit outputs an active level signal from the first OR circuit, and the n-th logic circuit from the first OR circuit. Open when each sum circuit outputs a signal of inactive level,
   The (n + 1) th OR circuit outputs an inactive level signal when both the signal output from the (2n + 1) comparator and the signal output from the (3n + 1) comparator are in an inactive level. An active level signal is output when at least one of the signal output from the comparator and the signal output from the 3n + 1 comparator is at an active level;
   The n + k OR circuit outputs an inactive level signal when both the signal output from the second n + k comparator and the signal output from the 3n + k comparator are in an inactive level. An active level signal is output when at least one of the signal output by the comparator and the signal output by the 3n + k comparator is an active level;
   The 2n-th OR circuit outputs an inactive level signal when both the signal output from the 3n-th comparator and the signal output from the 4n-comparator are inactive level, An active level signal is output when at least one of the signal output by the comparator and the signal output by the 4n comparator is at an active level;
   The plurality of second switches are closed when the 2n-th OR circuit outputs an active level signal from the (n + 1) -th OR circuit, and the n + 1-th OR circuit outputs the active level signal. The physical quantity detection device according to claim 5, wherein each of the sum circuits opens when outputting a signal of an inactive level.

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