WO2012173573A1 - Transmetteur à modulation par déplacement de fréquence - Google Patents

Transmetteur à modulation par déplacement de fréquence Download PDF

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Publication number
WO2012173573A1
WO2012173573A1 PCT/SG2012/000212 SG2012000212W WO2012173573A1 WO 2012173573 A1 WO2012173573 A1 WO 2012173573A1 SG 2012000212 W SG2012000212 W SG 2012000212W WO 2012173573 A1 WO2012173573 A1 WO 2012173573A1
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WIPO (PCT)
Prior art keywords
frequency
logic gate
clock
arrangement
shift keying
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PCT/SG2012/000212
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English (en)
Inventor
San Jeow CHENG
Yuan Gao
Yuanjin Zheng
Chun Huat Heng
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Agency For Science, Technology And Research
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Priority to US14/125,456 priority Critical patent/US9331878B2/en
Publication of WO2012173573A1 publication Critical patent/WO2012173573A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width

Definitions

  • Various embodiments relate to a frequency shift keying transmitter.
  • Narrowband applications like telemetry in the Medical Implant Communication Service (MICS) band require a power efficient, relatively high data rate transmitter for short range communication.
  • Low-power transceivers capable of delivering reasonably high communication data rate 1 Mbps are often required for short range communication of 1 m to 5 m.
  • battery-less remote control applications where energy is harvested from a push button piezoelectric or other mechanical means, more stringent requirements on power consumption is imposed.
  • frequency shift keying (FSK) where binary bits are represented by 2 different frequencies, is often adopted as the signaling scheme for short range communication for its robustness and ease in performing modulation and demodulation operations, power efficiency still poses a great challenge in the transmitter design, especially for the above-mentioned applications.
  • a frequency shift keying (FSK) transmitter is often based on the fractional-N PLL (phase-locked loop) [M. Perrott, Tet al., "A 27 -mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation " IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997].
  • This architecture consumes few to tens of mW as it involves dividing down from a high frequency domain that is often tens of times of the desired frequency to minimize quantization noise for good phase noise performance.
  • the architecture includes a power hungry modulus divider circuit which often consists of flip- flops and logic counters to obtain the required division ratio.
  • the transmitter is energy- inefficient due to complexity and higher operation frequency.
  • the PLL is not inherently stable, so design effort to ensure loop stability has to be enforced. However, high data- rate is often achievable with these designs.
  • the control word, K determines the fractional division ratio between N and N+1, so that the output frequency of the VCO will be a N+fraction multiple of the reference frequency.
  • Another FSK architecture is the open-loop voltage or digitally controlled oscillator (VCO/DCO) based transmitter having only a voltage or digitally controlled oscillator (VCO/DCO) directly driving the inductive antenna
  • VCO/DCO voltage or digitally controlled oscillator
  • a further FSK transmitter has an injection locked ring oscillator (RO) with hybrid edge combiner/power amplifier (EC/PA) architecture [J. Pandey and B. Otis, "A 90 ⁇ MICS/ISM band transmitter with 22% global efficiency," IEEE Proc. of Radio Frequency Integrated Circuits (RFIC) Symp., May 2010, pp. 285-288].
  • the transmitter uses crystal frequency pulling for frequency modulation and employs injection locking twice, serially to 2 ring oscillators (RO) to stabilize the generated signal.
  • the signal is then multiplied up 9 times to its desired frequency via an edge combiner (EC) before transmission through a power amplifier (PA) driven antenna.
  • EC edge combiner
  • PA power amplifier
  • the power consumption is in the sub- 100 ⁇ range.
  • the system is very rigid as the frequency generating circuit only produces 2 fixed frequencies depending on the physical properties of the crystal, making frequency selection very limited, which inhibits frequency hopping.
  • the frequency range crystal pulling can achieve is typically in the range of 10s to 100s of kHz.
  • a high factor frequency multiplier is required. A data rate of 200 kbps for the transmitter is reported.
  • Another FSK transmitter is the delta-sigma modulator ( ⁇ ) phase interpolator based transmitter, providing phase interpolation [Y.-H. Liu and T.-H. Lin, "A wideband PLL-based G/FSK transmitter in 0.18 ⁇ CMOS," IEEE J. of Solid-State Circuits, vol.44, no.9, pp. 2452-2462, Sep. 2009].
  • An integer-N PLL generates 4 equally spaced clock edges and through a ⁇ controlled phase rotator (PR), it is able to generate fractional delays by performing a dithered selection among the 4 clock phases. Although it can cover a wide frequency range due to ⁇ /2 separation of each clock phase, it suffers from larger quantization noise, resulting in higher in-band noise.
  • a frequency shift keying transmitter may include a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement, a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal, and a sampling arrangement coupled to the logic gate arrangement, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement is configured to be controlled by the data signal to have the logic gate arrangement select periodic waveforms that are delayed from each other by one of a set of intervals associated with the data signal, to be used as the input signals to the logic gate arrangement to produce the output signal.
  • a frequency shift keying receiver adapted to receive and extract the data signal from a phase shift keying transmitter as described herein is provided.
  • a frequency shift keying transmitter may include a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement, a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal, and a sampling arrangement coupled to the logic gate arrangement, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement is configured to be controlled by the data signal to have the logic gate arrangement select two of the periodic waveforms that are delayed from each other by a predefined interval associated with the data signal, to be used as the input signals to the logic gate arrangement to produce the output signal.
  • a frequency shift keying transmitter may include a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement, a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal, and a sampling arrangement coupled to the logic gate arrangement and the clock generator, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample different intervals within the clock signal to cause the clock generator to generate periodic waveforms, which are offset from one another, wherein the data signal controls the sampling arrangement to select which two of the periodic waveforms, offset from each other by a predefined interval, are to be used as the input signals to the logic gate arrangement to produce the output signal, so that the frequency of the output signal depends on the data signal.
  • FIG. 1 shows a schematic block diagram of a frequency shift keying transmitter, according to various embodiments.
  • FIG. 2 shows a schematic of a frequency shift keying transmitter, according to various embodiments.
  • FIGS. 3A and 3B show the operations of a frequency interpolator, according to various embodiments.
  • FIG. 3C shows a schematic of a frequency interpolator, according to various embodiments.
  • FIG. 4 shows a schematic of a delay line (VCDL) and an edge combiner (EC) block for a matching design, according to various embodiments.
  • FIG. 5 shows a die photograph of a frequency shift keying transmitter, according to various embodiments.
  • FIG. 6A shows a plot illustrating three frequency tones after injection locking at the injection lock oscillator (ILO) using different control words, according to various embodiments.
  • FIG. 6B shows a plot illustrating a frequency modulated output spectrum of two frequency tones spaced apart by about 100 kHz at a data rate of about 125 kbps at the injection lock oscillator (ILO), according to various embodiments.
  • ILO injection lock oscillator
  • FIG. 6C shows a plot illustrating a frequency modulated output spectrum of two frequency tones spaced apart by about 1 MHz at a data rate of about 1 Mbps at the injection lock oscillator (ILO), according to various embodiments.
  • ILO injection lock oscillator
  • FIG. 7 shows a plot of measured power for the digital portion of the FSK transmitter of various embodiments at various sampling frequencies.
  • the term "about” or “approximately” as applied to a numeric value encompasses the exact value and a variance of +/- 5% of the value.
  • Various embodiments relate to circuit implementations of a low-power, multichannel, frequency shift keying (FSK) transmitter for narrowband applications such as Medradio, medical implant communication service (MICS), and/or industrial, scientific and medical (ISM).
  • FSK frequency shift keying
  • Various embodiments may provide a frequency shift keying (FSK) transmitter architecture implemented using a digital delta-sigma ( ⁇ ) modulator based frequency interpolator for frequency tunability.
  • the architecture may incorporate sub-harmonic injection locking, thereby allowing operation of the clock generation circuit in low frequency, thus saving power without compromising the performance of the transmitter.
  • Various embodiments may provide a frequency shift keying (FSK) transmitter, for example a multi-channel delta-sigma ( ⁇ ) FSK radio frequency (RF) transmitter, for example with a resultant transmitted signal having a frequency range of about 400 MHz to about 436.4 MHz, e.g. for narrowband applications.
  • Various embodiments may provide an energy efficient FSK transmitter, e.g. a sub-mW FSK RF transmitter.
  • Various embodiments may provide a highly reconfigurable multi-channel, ultra- low-power frequency-shift keying (FSK) transmitter for narrowband applications such as battery-less remote control applications, designed using the 0.18- ⁇ CMOS technology with a 1.2 V power supply. The power requirements may be stringent due to limited harvested energy.
  • the transmitter of various embodiments may incorporate a 21 -bit input delta-sigma modulator ( ⁇ ) which controls the frequency modulation.
  • the transmitter may generate a clock pulse with an average frequency between about 133.33 MHz and about 145.5 MHz from a multi-phase delay line using a frequency or period interpolation technique.
  • the pulse is then sub-harmonically injected into an LC oscillator, which drives an antenna for direct transmission.
  • the resultant transmitted signal may have a frequency range of about 400 MHz to about 436.4 MHz, which encompasses the medical implant communication service (MICS) frequency band and the industrial, scientific and medical (ISM) frequency band, paving the way for various usages for the transmitter.
  • MICS medical implant communication service
  • ISM industrial, scientific and medical
  • the sub-harmonic injection enables the frequency generation circuit to operate in the low- frequency domain, and through the use of high-quality-factor (high-Q) external inductive antenna for the injection-locked LC oscillator, the total power consumption may be reduced to about 3 mW or less at a data rate of about 1 Mbps.
  • the delta-sigma modulator ( ⁇ ) also provides flexibility in frequency channel selection, with a resolution of about 16 Hz and frequency tunability of at least 100 kHz.
  • the FSK transmitter of various embodiments may incorporate a ⁇ modulator with delay-locked loop (DLL) edge generation, a frequency interpolator for frequency or period interpolation, and injection locking with average frequency.
  • DLL delay-locked loop
  • the FSK transmitter of various embodiments is designed to have relatively good performance in terms of high data rate and frequency flexibility while sustaining power efficiency.
  • Various embodiments may provide a low-power, narrowband solution, with frequency selection.
  • the FSK transmitter of various embodiments may offer low-complexity, cost effectiveness, low power and high efficiency.
  • the FSK transmitter of various embodiments may be used for low power, multichannel, narrowband applications (eg. Medradio, battery-less remote control), for wireless communication systems, for example in low-power bio-medical applications, and for portable wireless and/or wearable devices.
  • low power, multichannel, narrowband applications eg. Medradio, battery-less remote control
  • wireless communication systems for example in low-power bio-medical applications, and for portable wireless and/or wearable devices.
  • FIG. 1 shows a schematic block diagram of a frequency shift keying transmitter 100, according to various embodiments.
  • the frequency shift keying transmitter 100 includes a logic gate arrangement 102 that produces an output signal having a frequency that depends on input signals to the logic gate arrangement 102, a clock generator 104 coupled to the logic gate arrangement 102, the clock generator 104 adapted to produce a clock signal, and a sampling arrangement 106 coupled to the logic gate arrangement 102.
  • the line represented as 108 is illustrated to show the relationship between the different components, which may include electrical coupling and/or mechanical coupling.
  • the sampling arrangement 106 is adapted to receive a data signal, wherein the sampling arrangement 106 is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement 106 is configured to be controlled by the data signal to have the logic gate arrangement 102 select periodic waveforms that are delayed from each other by one of a set of intervals associated with the data signal, to be used as the input signals to the logic gate arrangement 102 to produce the output signal.
  • the logic gate arrangement may include one or more logic gates.
  • the logic gate arrangement may further include other elements, e.g. adders or mixers.
  • the clock signal includes equally spaced apart clock edges.
  • Each of the clock edges may have a frequency of around 1600 MHz.
  • each of the periodic waveforms may have a period equal to 12 of the clock edges.
  • Each periodic waveform may have a leading edge corresponding to each clock edge of the clock signal, and that 12 periodic waveforms may be generated.
  • the logic gate arrangement 102 may randomly select the periodic waveforms.
  • the interval between periodic waveforms that are successively selected may be any one of an interval of 10, 11, 12 or 13 of the clock edges.
  • the output signal may have an average frequency (or period) of the selected periodic waveforms.
  • the delay between two successively generated periodic waveforms may be l/12th of the period of the periodic waveforms.
  • the respective leading edges of the two successive periodic waveforms may differ from each other by a duration of l/12th of the period of the periodic waveforms.
  • the logic gate arrangement 102 may include logic gates having a programmable interconnection, the programmable interconnection configured to connect the logic gates that are used to process two selected periodic waveforms to produce the output signal.
  • the data signal includes at least two different words, each word representative of binary data to be transmitted.
  • the clock generator 104 may include clock edge combiner circuitry.
  • the clock generator 104 may include delay circuitry coupled to the clock edge combiner circuitry.
  • the frequency shift keying transmitter 100 further includes a transmission stage coupled to the logic gate arrangement 102 to receive the output signal from the logic gate arrangement 102 for transmission.
  • the transmission stage may include an oscillator to receive the output signal from the logic gate arrangement 102, and an inductive antenna coupled to the oscillator, wherein the inductive antenna transmits the output signal.
  • the oscillator may include circuitry that is configured to generate a transmission signal based on the third harmonic of the output signal from the logic gate arrangement 102.
  • the sampling arrangement 106 is adapted to receive a data signal, wherein the sampling arrangement 106 is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement 106 is configured to be controlled by the data signal to have the logic gate arrangement 102 select two of the periodic waveforms that are delayed from each other by a predefined interval associated with the data signal, to be used as the input signals to the logic gate arrangement 102 to produce the output signal.
  • the sampling arrangement 106 is coupled to the logic gate arrangement 102 and the clock generator 104, the sampling arrangement 106 adapted to receive a data signal, wherein the sampling arrangement 106 is configured to sample different intervals within the clock signal to cause the clock generator 104 to generate periodic waveforms, which are offset from one another, wherein the data signal controls the sampling arrangement 106 to select which two of the periodic waveforms, offset from each other by a predefined interval, are to be used as the input signals to the logic gate arrangement 102 to produce the output signal, so that the frequency of the output signal depends on the data signal.
  • Various embodiments may provide a frequency shift keying receiver adapted to receive and extract the data signal from the frequency shift keying transmitter 100.
  • FIG. 2 shows a schematic of a frequency shift keying (FSK) transmitter (e.g. a delta-sigma ( ⁇ ) based FSK transmitter) 200, according to various embodiments.
  • the FSK transmitter 200 includes a delay-locked loop (DLL) 202, an edge combiner/multiplexer hybrid block (EC/MUX) 204, a delta-sigma modulator ( ⁇ ) 206, a frequency interpolator 208, which may be controlled by the ⁇ 206, and an injection lock oscillator (ILO) (e.g. an LC oscillator) 210 directly driving an inductive antenna (e.g. a printed circuit board (PCB) loop antenna) 212.
  • DLL delay-locked loop
  • EC/MUX edge combiner/multiplexer hybrid block
  • ⁇ delta-sigma modulator
  • ⁇ frequency interpolator
  • ILO injection lock oscillator
  • ILO injection lock oscillator
  • PCB printed circuit board
  • a buffer may be provided or coupled between the ILO 210 and the antenna 212.
  • the buffer may be used to store and/or enhance the signal from the ILO 210 prior to transmission to the antenna 212.
  • the buffer may be or may be realized by a power amplifier (PA).
  • PA power amplifier
  • the DLL 202 may include a phase detector (PD), a charge pump (CP) and a loop filter (LF), as represented by the PD/CP/LF block 214, and a voltage controlled delay line (VCDL) (or delay circuitry) 216.
  • PD phase detector
  • CP charge pump
  • LF loop filter
  • VCDL voltage controlled delay line
  • Each of the PD/CP/LF block 214, and the VCDL 216 may receive a reference clock, (J> re f, from a crystal oscillator 218, as an input.
  • An output signal from the PD/CP/LF block 214 is also inputted to the VCDL 216, and the output of the VCDL 216 is fed back as an input to the PD/CP/LF block 214.
  • the phase detector (PD), the charge pump (CP) and the loop filter (LF) combine functionally to form a feedback control loop such that the eventual loop filter voltage of the loop filter (LF) may settle or stabilise and may result in the total delay of the VCDL 216 to be at least substantially equal to or close to or approaching to one clock period of the reference clock, ⁇ f> ref , of the crystal oscillator 218.
  • the ⁇ 206 may form part of a sampling arrangement.
  • the ⁇ 206 includes a quantizer to receive, for example, a sequence of bits.
  • the frequency interpolator 208 may form part of a logic gate arrangement.
  • the ⁇ 206 receives an input waveform, ⁇ , and a data signal or control word (or control input), K.
  • the frequency interpolator 208 may receive the output of the ⁇ 206 as an input signal and may, for example, output a select signal, SEL 0- n, for selecting a clock phase.
  • the ⁇ 206 controls the frequency interpolator (or edge selector) 208 for selecting a clock phase or signal.
  • the edge combiner/multiplexer hybrid block (EC/MUX) 204 may include a multiplexer (MUX) 218 and an edge combiner (or a clock edge combiner circuitry) (EC) 220.
  • MUX multiplexer
  • EC clock edge combiner circuitry
  • the DLL 202 and the EC 220 may form part of a clock generator and may be utilized as a multi-phase reference generator.
  • the DLL 202 may, for example, include a plurality of delay cells to generate a plurality of clock phases of the reference clock, ⁇ ,-ef, where the plurality of clock phases may be different relative each other by their respective phases.
  • the ILO 210 and the antenna 212 may form part of a transmission stage.
  • ILO 210 may be used for injection locking onto the frequency interpolated signal generated via clock period averaging.
  • the ILO 210 also receives the waveform ⁇ .
  • the FSK transmitter 200 may be digital logic intensive, making it amenable to future digital CMOS process scaling.
  • the total delay in the VCDL 216 of the DLL 202 locks to exactly 1 (one) clock period (e.g. 66.67 MHz) of the reference clock, ref, of the crystal oscillator 218. Once locked, the DLL 202 produces or generates
  • the 24 clock phases may then be combined using the EC 220 to form 12 equally spaced or separated clock phases or periodic waveforms ( ⁇ - ⁇ ), effectively doubling the reference frequency to about 133.33 MHz (e.g. F c ik - 133.33 MHz).
  • the 12 clock phases ( ⁇ - ⁇ ) may be provided to the MUX 218.
  • the dithering phase selection sequence produces an output waveform, ⁇ , with an average clock period that is related to the input or control input, K, of the ⁇ 206, where the average clock period may be between 1 1/12 T c ik and T c ik, where
  • ⁇ may have a frequency of between about 133.33 MHz and about 145.45 MHz.
  • ⁇ may then be injection locked into the ILO 210 via its third harmonic, thereby causing the free running ILO 210 to lock to 3 times the frequency of ⁇ , generating an oscillator output waveform (e.g. a transmission signal) having frequencies ranging from about 400 MHz to about 436.4 MHz.
  • the ILO 210 then drives the antenna 212 directly to achieve FSK modulation. As the ILO 210 drives the antenna 212 directly, an output waveform with tunable frequency may be transmitted.
  • ⁇ is used for injection locking for the ILO 210 as well as being a clock to drive the ⁇ 206.
  • the same signal ⁇ is used for the ⁇ 206 and the ILO 210.
  • the combination of DLL 202 and the EC 220 doubles the input reference frequency and provides 12 evenly spaced clock phases.
  • the ⁇ controlled frequency interpolator 208 may be used to interpolate between two clock periods. Through averaging, frequencies ranging from 133.33MHz to 144.33MHz may be generated with very fine resolution. Sub-harmonic (3rd) injection-locking of the average output frequency triples the frequency at the output. The frequency may be tuned by changing the digital control word, K. Thus, narrowband tuning may be achieved.
  • FIG. 3A shows an operation of a frequency interpolator (e.g. 208, FIG. 2), according to various embodiments, which enables quantification of the frequency control.
  • a clock phase is selected from the clock phases generated by the EC (e.g. 220).
  • the frequency interpolator e.g. 208, FIG. 2 selects in the next cycle, the period of the overall waveform has a certain clock period.
  • the difference between the current clock phase and the previous clock phase may determine the current clock period.
  • the clock signal may include equally spaced apart clock edges, as represented by the dotted lines (e.g. 330 illustrated for one clock edge), such that the clock phase or periodic waveform (e.g. 332, 334, 336 illustrated for the waveforms A, B and L respectively) may have a leading edge ( ⁇ ) and a falling edge ( ] ) that correspond to a clock edge 330.
  • the clock signal may have 12 equally spaced apart clock edges 330. As shown in FIG.
  • Each clock phase ⁇ ; + ⁇ leads a clock phase ⁇ ; (e.g. periodic waveform A 332) by (or about 1600 MHz).
  • the output of the ⁇ 206 may determine the desired current clock period. By adding the current clock period to the previous clock phase or period, the current clock phase could be deduced. As an example, assuming the previous clock phase is A 332 and the output of the ⁇ 206 is zero, the clock period is (r c3 ⁇ 4 +0xr c3 ⁇ 4 /12) and therefore the current clock phase remains as A 332.
  • the ⁇ 206 may have a 2-bit output (e.g. -2, -1, 0 and 1), which corresponds respectively to clock periods of 107 c3 ⁇ 4 /12, and 133 ⁇ 4/12. In this implementation, the ⁇ 206 may have an average output of between -1 and 0.
  • the next phase may be the clock phase or signal L 336 and every subsequent 11th clock phase may then be selected, i.e. A 332, L 336, K, J, /, H, G, F, E, D, C, B, and back to A 332 and so on. Therefore, the waveform may have an overall clock period of 11/123 ⁇ 4.
  • FIG. 3A also shows a merged waveform 338 of the waveforms A 332 and L 336, where the waveform 338 has a clock period of 11/12 J 1 ⁇ .
  • every successive 10th, 11th, 12th or 13th chosen clock phase may correspond to a clock signal having a corresponding period of 10/12T C3 ⁇ 4 , 1 ⁇ l 1T c ik, c 3 ⁇ 4 or 13/12 Talk respectively.
  • the ⁇ modulator controlled frequency interpolator 208 may select any of the 10th, 11th, 12th or 13th successive phases randomly to generate an average clock period.
  • Each control word, K results in a unique average clock period or frequency.
  • the two frequency tones used in binary FSK transmission may hence be generated using two different control words, e.g. K0 and Kl, to represent the '0' and T data.
  • FIG. 3B shows the operation of a frequency interpolator, according to various embodiments, as a further non-limiting example.
  • FIG. 3B shows an output signal or waveform, based on the sequence of the selected clock phases or periodic waveforms A 332, L 336, A 332, L 336, K, L 336 of FIG. 3A, having an average clock period (or frequency) after 6 clock cycles of about 0.986 ⁇ ⁇ 3 ⁇ 4 (average T c ik 362 + n/llTcik 364 + ⁇ ⁇ l ⁇ 2T cIk 366 + 11/127 ⁇ 368 +13/127k 370)/6).
  • the ILO 210 transmits the third harmonic of ⁇ .
  • the ⁇ (e.g. 206) may be a digital element and may have a 2-bit output, which may be designed to pick every subsequent 10th to 13th clock phases, such that the input control word, K, for the ⁇ may result in a dithered sequence that results in an average phase selection that is an interpolation between the 11th and 12th successive phase.
  • FIG. 3C shows a schematic 300 of a frequency interpolator (e.g. 208, FIG. 2), illustrating a wrap around adder such that its output selects only one of the phases, ⁇ to ⁇ , during each sampling cycle.
  • the schematic 300 illustrates the algorithmic implementation of the frequency interpolator, as shown below:
  • a "Modulo 12 operation”, as represented by the block 308 is employed at the adder 310, after the adder 302 to ensure only these 12 phases, ⁇ 0 to ⁇ , may be selected at any time. Therefore, the frequency interpolator includes logic gates having a programmable interconnection.
  • the digital ⁇ (e.g. 206) may be a 2nd order modulator with dithering.
  • the ⁇ may have an input range of 21 -bits, with an internal bus width of 28-bits to account for logic or arithmetic overflow.
  • a pseudo random sequence of 23 -bits may also be applied at the input of the quantizer of the ⁇ (e.g. 206) for dithering.
  • the output frequency of the frequency interpolator, F inj corresponding to ⁇ , may be given by
  • K and m are the input control word and the input bit resolution of the delta- modulator ( ⁇ ) respectively.
  • each frequency step, Af inj may be given by
  • equation (2) may be approximated to
  • the relationship may be approximated to be close to linear.
  • the output frequency step may have approximately a resolution of 3 times of 4f nj . Due to the digital controllability and high resolution, the FSK transmitter 200 of various embodiments may be highly reconfigurable in terms of modulation index, frequency channel spacing, data rate, amongst others.
  • the FSK transmitter 200 employs frequency interpolation, where the architecture of the FSK transmitter 200 simplifies clock phase generation and does not include any scheme where the frequency of the signal is multiplied upwards and divided down, making it more efficient.
  • a multiply-up circuit e.g. the frequency multiplier circuit or the edge combiner (EC) (e.g. 220)
  • the design of a multiply-up circuit may be less complicated as it contains AND-OR combinational logic, in contrast to complex flip-flop networks of a frequency divider, thereby making the FSK transmitter 200 less power consuming compared to the fractional-N PLL based transmitter [M. Perrott, Tet a ⁇ ., "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation ,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec.
  • the delta-sigma modulator ( ⁇ ) phase interpolator based transmitter [Y.- H. Liu and T.-H. Lin, "A wideband PLL-based G/FSK transmitter in 0.18 ⁇ CMOS " IEEE J. of Solid-State Circuits, vol.44, no.9, pp. 2452-2462, Sep. 2009] employs ⁇ phase interpolation, the need of a high frequency PLL and phase switching at high output frequency make it energy inefficient.
  • the FSK transmitter 200 of various embodiments employs phase/clock phase generation using a DLL, and clock period interpolation.
  • a DLL based architecture as in the FSK transmitter 200 is more energy efficient in generating multiple taps than a PLL since a higher frequency reference is not needed.
  • the FSK transmitter 200 employs the ⁇ 206 to improve the frequency resolution.
  • the quantization error of the FSK transmitter 200 may be made smaller, as compared to the delta-sigma modulator ( ⁇ ) phase interpolator based transmitter where a higher ⁇ sampling frequency is used to reduce the quantization noise due to the limited number of phases, by increasing the number of delay taps or cells in the DLL 202 without employing a higher sampling frequency.
  • the average frequency is injection locked prior to transmission, therefore allowing low frequency operation.
  • the FSK transmitter 200 may not suffer from the shortcomings of the open-loop VCO/DCO based transmitter [J. L. Bohorquez, et al., "A 350 ⁇ CMOS MSK transmitter and 400 ⁇ OOK super-regenerative receiver for medical implant communications " IEEE J. of Solid-State Circuits, vol.44, no.4, pp. 1248-1259, Apr. 2009; J. Bae, et al., "A 490 ⁇ fully MICS compatible FSK transceiver for implantable devices," IEEE Proc. of Symp. on VLSI Circuits, pp.
  • the FSK transmitter 200 includes a sub-harmonic injection locking mechanism, which ensures both accurate frequency locking and good phase noise without the complexity of PLL.
  • the FSK transmitter 200 also offers stability as an injection locked output is more stable than the output from a free running oscillator since injection- locking behaves like a simple closed loop phase-locked loop (PLL).
  • PLL phase-locked loop
  • the FSK transmitter 200 also offers frequency flexibility through the use of ⁇ 206 for frequency modulation. Furthermore, frequency tuning through the ⁇ 206 is more area efficient than frequency tuning through sub-ranging capacitor banks in the open-loop VCO/DCO based transmitter.
  • the FSK transmitter 200 offers frequency selection and a high data rate of at least
  • FSK transmitter 200 is generally digital in nature with the bulk of the power going to the
  • the DLL 202, the ILO 210 and the crystal oscillator 218 constitute the analog blocks of the architecture of the FSK transmitter 200, which typically consume less than 1 mW altogether.
  • the FSK transmitter 200 uses a delay-locked loop (DLL) (e.g. 202), as DLL does not have accumulated jitter and is inherently stable, making it easy to implement, as compared to a phase-locked loop (PLL) as used in the fractional-N PLL based transmitter [M. Perrott, Tet al., "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation " IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997].
  • DLL delay-locked loop
  • PLL phase-locked loop
  • the EC (or frequency multipliers) 220 are easier to design as compared to dividers, for speed and power optimizations due to its logic simplicity over dividers.
  • the FSK transmitter 200 of various embodiments achieve frequency agility through the use of the ⁇ 206, as compared to the injection locking with hybrid EC/PA based transmitter [J. Pandey and B. Otis, "A 90 ⁇ MICS/ISM band transmitter with 22% global efficiency " IEEE Proc. of Radio Frequency Integrated Circuits (RFIC) Symp., May 2010, pp. 285-288] which does not have frequency tunability, where there is only a single channel with a fixed deviation, thereby preventing multi-channel operations and rendering the transmitter more susceptible to interference.
  • the ⁇ 206 in the FSK transmitter 200 of various embodiments allows fine frequency tuning and multi-channel operation and helps circumvent interference issues.
  • the FSK transmitter 200 of various embodiments employs frequency interpolation, thereby achieving frequency tunability.
  • the FSK transmitter 200 of various embodiments also employs DLL based clock generation.
  • each analog block e.g. the DLL 202, the ILO 210 and the crystal oscillator 218, may be chosen or designed for low power consumption minimize power consumption.
  • CMOS logic may be employed to minimise or eliminate static currents.
  • current starved inverters may be employed in the delay line of the DLL 202.
  • differential delay cells may be employed for better noise rejection compared to the single ended counterparts, they consume more power. Therefore, in order to have better supply noise rejection, a pseudo- differential type of delay cell (e.g. 402) architecture using pseudo differential current- starved inverters 404 as shown in FIG. 4 may be adopted for the delay line (VCDL) 400, consuming about 399 ⁇ at about 1.2 V.
  • the differential architecture is adopted for better supply noise immunity. Mismatch for each delay cell 402 has to be taken care of since large mismatches in delay may result in unwanted frequency spurs in the vicinity of the operating frequency. It should be appreciated that any number of delay cells 402 may be provided.
  • Dummy differential- to-single ended buffers e.g. 406
  • PD phase detector
  • each EC cell e.g. 422
  • each EC cell may be an arrangement 424 of logic gates (e.g. including AND gates, OR gates). It should be appreciated that any number of EC cells 422 may be provided, which may depend on the number of the delay cells 402 employed in the VCDL 400.
  • the select signal (e.g. SELo, SEL 1 ; ..., SELu) may be used to turn the AND-OR blocks of each arrangement 424 ON/OFF, for example to enable the AND-OR blocks of the chosen clock phase and disable the AND-OR blocks of unselected clock phases or signals to be inactive to minimize dynamic switching power and conserve power.
  • the edge combiner (EC) 420 takes the 24 equally spaced clock phases from the VCDL 400 and combines the clock phases to form 12 evenly spaced clock signals or phases, where each of the 12 clock phases from the EC 420 has double the frequency of each of the 24 clock phases from the VCDL 400.
  • the ILO e.g.
  • a capacitor bank may be provided, for example as part of the ILO (e.g. 210), to digitally tune the free running frequency to the required band since a small locking range is expected.
  • FIG. 5 shows a die photograph 500 of a frequency shift keying transmitter, according to various embodiments.
  • the die has dimensions of approximately 1.8 mm x
  • the active die area of all the blocks may occupy approximately 0.2mm .
  • FIG. 6A shows a plot 600 illustrating three frequency tones after injection locking at the ILO using different control words, according to various embodiments.
  • the output spectra 602, 604, 606 show that every increment in the control word, K, causes a step increase of about 16 Hz in the output frequency. The results match closely to the expected output frequency based on equation (1).
  • FIG. 6B shows a plot 620 illustrating a frequency modulated output spectrum of two frequency tones spaced apart by about 100 kHz at a data rate of about 125 kbps at the ILO, according to various embodiments.
  • a randomized data stream is employed, switching at a data rate of about 125 kbps.
  • the frequencies are about 100 kHz apart, resulting in a modulation index of 0.8.
  • the highest measured data rate is about 1 Mbps.
  • a modulation index of 1 may be needed to clearly distinguish the 2 tones in the modulated spectrum.
  • FIG. 6C shows a plot 630 illustrating a frequency modulated output spectrum of two frequency tones spaced apart by about 1 MHz at a data rate of about 1 Mbps at the ILO, according to various embodiments.
  • a randomized data stream is employed, switching at a data rate of 1 Mbps.
  • the two frequency tones may be distinguished.
  • the phase noise at different frequencies range from about -92 dBc/Hz to about -104 dBc/Hz.
  • a tuning resolution of about 100 kHz may be achievable as the actual attained resolution is much smaller.
  • the frequency resolution may be limited by the resolution of the delta-sigma modulator ( ⁇ ).
  • the power consumption at a data rate of about 1 Mbps is about 3 mW.
  • the power level may be reduced by using a more advanced technology node and reducing the resolution of the delta-sigma modulator ( ⁇ ) to a level sufficient to meet the required resolution.
  • the major portion of the power is consumed by the digital logic or portion of the FSK transmitter of various embodiments due to the high sampling frequency of about 133.3 MHz, which may be needed to obtain an accurate average output frequency.
  • the averaging number of 133 employed may be too high and therefore may be lowered to reduce the sampling frequency and switching power.
  • the 21 -bit delta-sigma modulator ( ⁇ ) resolution may also be further reduced at the expense of a poorer frequency resolution, where a higher resolution allows for tuning potential. This may reduce the digital logics and reduce the switching power. Moreover, if a high data rate is not required, the ⁇ clock rate may be reduced. This may decrease the power consumed, because the ⁇ and the interpolator constitute a substantial part of power consumption.
  • FIG. 7 shows a plot 700 of measured power for the digital portion of the FSK transmitter of various embodiments at various sampling frequencies. As shown in the plot 700, the relationship between the measured power (power consumption) and the sampling frequency (operating frequency) is almost or approaching a linear relationship.
  • the transmitter power may also scale down linearly.
  • the sampling frequency may be reduced by about 10 times compared to that for a 1 Mbps transmission.
  • the digital power consumption may be less than about 0.3 mW, which may give rise to a total transmitter power of about 0.8 mW.
  • the FSK transmitter of various embodiments may also lead to efficient power usage according to data rates.
  • the performance of the FSK transmitter of various embodiments is summarised in Table 1.
  • the FSK transmitter of various embodiments offers multi- channel capability with a frequency resolution of about 0.016 kHz and a smaller active area.
  • analog and digital refer respectively to the analog and digital portions of the FSK transmitter of various embodiments.
  • power consumption may be dependent on the technology node which the FSK transmitter of various embodiments is implemented. Using 0.18 ⁇ CMOS technology, the power consumption may be dominated by the digital portion (approximately 80 %). By migrating the design of the FSK transmitter of various embodiments to a more advanced technology (e.g.
  • FSK transmitter of various embodiments may remain substantially the same, the power consumed by the digital portion of the FSK transmitter of various embodiments may be reduced substantially, such that a sub-mW FSK transmitter may be provided.
  • the FSK transmitter of various embodiments is a delay-locked loop (DLL) based architecture, suitable for low power applications.
  • the transmitter incorporates a digital delta-sigma modulator ( ⁇ ) and a ⁇ based frequency interpolator to interpolate clock phases to generate different output frequencies, to achieve frequency tunability or selection. With the frequency interpolation, frequency channelization with relatively equal spacing may be achieved.
  • the transmitter also uses average frequencies for sub-harmonic injection locking, thereby providing good frequency stability and power efficiency. A combination of injection locking and edge combining enables multiplication of the output frequency to the desired range, enabling power efficiency while sustaining good performance.
  • Various embodiments may provide a high resolution 400 MHz to 436.4 MHz FSK transmitter suitable for narrowband applications, such as battery-less remote control applications, implemented using the 0.18- ⁇ CMOS process.
  • the FSK transmitter employs frequency interpolator with a delta-sigma modulator ( ⁇ ), coupled with sub- harmonic injection to keep the frequency generation circuit in the low frequency domain, to achieve FSK modulation.
  • the transmitter may consume about 3 mW at about 1.2 V, while transmitting at a data rate of about 1 Mbps.
  • the FSK transmitter offers frequency stability, frequency tunability, reasonably high data rate, and high reconfigurability such as modulation index, data rate, channel spacing, power consumption, amongst others.
  • the modulation noise may be reduced by using more delay cells.
  • the FSK transmitter of various embodiments offers reasonably high data rate, application flexibility, coupled with easy-to-design, synthesizable blocks.
  • the output frequency may be digitally controllable, making it easier to calibrate. With the design being predominantly digital in nature, power consumption may be reduced using a more advanced deep-submicron CMOS technology.
  • the transmitter of various embodiments also offers portability, robustness, and being less susceptible to process-voltage- temperature (PVT) variations as compared to the delta-sigma modulator ( ⁇ ) phase interpolator based transmitter [Y.-H. Liu and T.-H. Lin, "A wideband PLL-based G/FSK transmitter in 0.18 ⁇ CMOS " IEEE J. of Solid-State Circuits, vol.44, no.9, pp. 2452- 2462, Sep. 2009].

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Abstract

Dans ses modes de réalisation, la présente invention se rapporte à un transmetteur à modulation par déplacement de fréquence. Le transmetteur à modulation par déplacement de fréquence comprend : un module à porte logique qui produit un signal de sortie dont la fréquence dépend de signaux d'entrée transmis au module à porte logique ; un générateur d'horloge qui est couplé au module à porte logique, le générateur d'horloge étant adapté pour produire un signal d'horloge ; et un module d'échantillonnage qui est couplé au module à porte logique, le module d'échantillonnage étant adapté pour recevoir un signal de données. L'invention est caractérisée en ce que le module d'échantillonnage est configuré de façon à échantillonner le signal d'horloge dans le but de produire des formes d'onde périodiques qui sont retardées, les unes par rapport aux autres, d'un intervalle de temps déterminé par le point correspondant à l'échantillonnage du signal d'horloge. L'invention est caractérisée d'autre part en ce que le module d'échantillonnage est configuré de façon à être contrôlé par le signal de données de telle sorte que le module à porte logique sélectionne des formes d'onde périodiques qui sont retardées, les unes par rapport aux autres, par l'un d'un ensemble d'intervalles associé au signal de données. Ceci a pour but d'utiliser les formes d'onde périodiques en tant que les signaux d'entrée qui sont transmis au module à porte logique de sorte à produire le signal de sortie.
PCT/SG2012/000212 2011-06-14 2012-06-14 Transmetteur à modulation par déplacement de fréquence WO2012173573A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015097405A1 (fr) * 2013-12-26 2015-07-02 Grdf Procede de transmission de donnees par liaison radiofrequence dans une installation de telereleve
US9148323B2 (en) 2012-09-07 2015-09-29 Agency For Science, Technology And Research Transmitter
US9537516B1 (en) * 2013-09-26 2017-01-03 The United States Of America As Represented By Secretary Of The Navy Edge combining transmitter
EP3130121A4 (fr) * 2014-04-11 2017-12-27 Texas Instruments Incorporated Modulation par déplacement de fréquence binaire comprenant des données modulées dans un domaine numérique et une porteuse générée à partir d'une fréquence intermédiaire

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BOOM, N. ET AL.: "A 5.0mW OdBm FSK transmitter for 315/433 MHz ISM applications in 0.25mum CMOS", PROCEEDING OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, ESSCIRC 2004, 21 September 2004 (2004-09-21) - 23 September 2004 (2004-09-23), pages 199 - 202 *
YAO-HONG, L. ET AL.: "A Wideband PLL-Based G/FSK Transmitter in 0.18mum CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 9, September 2009 (2009-09-01), pages 2452 - 2462 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9148323B2 (en) 2012-09-07 2015-09-29 Agency For Science, Technology And Research Transmitter
US9537516B1 (en) * 2013-09-26 2017-01-03 The United States Of America As Represented By Secretary Of The Navy Edge combining transmitter
WO2015097405A1 (fr) * 2013-12-26 2015-07-02 Grdf Procede de transmission de donnees par liaison radiofrequence dans une installation de telereleve
FR3016107A1 (fr) * 2013-12-26 2015-07-03 Grdf Procede de transmission de donnees par liaison radiofrequence dans une installation de telereleve
US9935801B2 (en) 2013-12-26 2018-04-03 Grdf Method for transmitting data by radiofrequency link in a remote-reading apparatus
EP3130121A4 (fr) * 2014-04-11 2017-12-27 Texas Instruments Incorporated Modulation par déplacement de fréquence binaire comprenant des données modulées dans un domaine numérique et une porteuse générée à partir d'une fréquence intermédiaire

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