WO2012172825A1 - Power module and power conversion circuit - Google Patents

Power module and power conversion circuit Download PDF

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Publication number
WO2012172825A1
WO2012172825A1 PCT/JP2012/051622 JP2012051622W WO2012172825A1 WO 2012172825 A1 WO2012172825 A1 WO 2012172825A1 JP 2012051622 W JP2012051622 W JP 2012051622W WO 2012172825 A1 WO2012172825 A1 WO 2012172825A1
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layer
gan
diode
semiconductor switch
transistor
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PCT/JP2012/051622
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French (fr)
Japanese (ja)
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林　秀樹
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住友電気工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0051—Diode reverse recovery losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a power module and a power conversion circuit, and more particularly, to a power module including a semiconductor switch element and a diode, and a power conversion circuit including the power module.
  • power conversion circuits such as inverters and converters include transistors and diodes.
  • these semiconductor power devices have been formed of silicon (Si).
  • Si silicon
  • the performance of Si power devices eg, low loss, high operating speed, etc.
  • SiC power devices are attracting attention as semiconductor power devices having performance superior to Si power devices.
  • 4H—SiC has a bandgap about 3 times that of silicon, a breakdown voltage about 10 times that of silicon, and a thermal conductivity about 3 times that of silicon. Therefore, it is expected that the SiC power device can realize high breakdown voltage, low loss, high speed operation, and stable operation in a high temperature environment as compared with the current Si power device.
  • Patent Document 1 discloses a conversion circuit including at least one switching element and a SiC diode.
  • the SiC diode conducts when the switching element is turned off and is reverse-biased when the switching element is turned on.
  • Power conversion circuits are always required to improve performance such as low loss, operating speed, and operational stability.
  • An object of the present invention is to improve the performance of a power conversion circuit.
  • a power module includes a semiconductor switch element and a diode.
  • the diode is arranged to be reverse-biased when the semiconductor switch element is in an on state and to conduct when the semiconductor switch element is in an off state.
  • the diode is either a gallium nitride diode or a diamond diode.
  • the semiconductor switch element is any one of a silicon carbide transistor, a gallium nitride transistor, and a diamond transistor.
  • the power conversion circuit according to the present invention includes a semiconductor switch element and a diode.
  • the diode is arranged to be reverse-biased when the semiconductor switch element is in an on state and to conduct when the semiconductor switch element is in an off state.
  • the diode is either a gallium nitride diode or a diamond diode.
  • FIG. 7 is a perspective view of the GaN Schottky barrier diode which can be applied to the power module according to the embodiment of the present invention.
  • FIG. 7 is a perspective view of the GaN Schottky barrier diode shown in FIG.
  • power conversion circuit includes a circuit that changes at least one form of power.
  • Power form includes, for example, frequency (including direct current), number of phases, voltage, and current.
  • FIG. 1 is a circuit diagram of a basic unit constituting a power module according to an embodiment of the present invention.
  • unit 10 includes semiconductor switch elements 1 and 2 and diodes 3 and 4.
  • the semiconductor switch elements 1 and 2 are connected in series between the terminals 5 and 6. Terminal 5 has a positive polarity and terminal 6 has a negative polarity. The connection point of the semiconductor switch elements 1 and 2 is connected to the terminal 7.
  • the diodes 3 and 4 are connected in reverse parallel to the semiconductor switch elements 1 and 2, respectively. That is, the forward direction of the diodes 3 and 4 is opposite to the direction of the current flowing through the semiconductor switch elements 1 and 2.
  • FIG. 2 is a diagram showing an example of a power conversion circuit including the power module shown in FIG. Referring to FIG. 2, the power conversion circuit is a single-phase inverter, and converts direct current into single-phase alternating current.
  • Single phase load 9A is an inductive load, for example, a single phase motor.
  • the type of the single-phase load 9A is not particularly limited.
  • the power conversion circuit includes a power module 101.
  • the power module 101 includes units 10A and 10B.
  • the units 10A and 10B are provided in parallel between the terminals 5 and 6. Terminals 5 and 6 are connected to a positive electrode and a negative electrode of DC power supply 8, respectively. Terminal 7A of unit 10A and terminal 7B of unit 10B are connected to single-phase load 9A.
  • unit 10A includes semiconductor switch elements 1A and 2A and diodes 3A and 4A.
  • the diodes 3A and 4A are connected in antiparallel to the semiconductor switch elements 1A and 2A, respectively.
  • Unit 10B includes semiconductor switch elements 1B and 2B and diodes 3B and 4B.
  • the diodes 3B and 4B are connected in antiparallel to the semiconductor switch elements 1B and 2B, respectively.
  • FIG. 3 is a diagram for explaining the operation of the power conversion circuit (single-phase inverter) shown in FIG. 2 and 3, for each phase ⁇ (rad), the set of semiconductor switch elements 1A and 2B and the set of semiconductor switch elements 2A and 1B are alternately turned on / off.
  • the voltage V and current i of the single-phase load 9A are shown in FIG. Since the single-phase load 9A is an inductive load, the response of the current i to the change of the voltage V is delayed.
  • the semiconductor switch elements 2A and 1B are turned off.
  • a negative current i flows through the diodes 3A and 4B and is returned to the DC power supply 8.
  • the semiconductor switch elements 1A and 2B are turned on, and the voltage V is switched from negative to positive.
  • the semiconductor switch elements 1A and 2B are turned off at ⁇ (rad).
  • a positive current i flows through the diodes 3B and 4A and is returned to the DC power supply 8.
  • the semiconductor switch elements 1B and 2A are turned on, and the voltage V is switched from positive to negative.
  • the diodes 3A, 4A, 3B, and 4B ensure a path of the current i that changes with a change in the voltage V.
  • Such a diode is generally called a feedback diode (freewheeling diode).
  • the diode 4A conducts when the semiconductor switch element 1A is off ( ⁇ to ⁇ + ⁇ ).
  • the diode 3A becomes conductive.
  • the diode 4A is reverse-biased when the semiconductor switch element 1A is on ( ⁇ ⁇ ).
  • the diode 3A is reverse-biased when the semiconductor switch element 2A is on ( ⁇ + ⁇ ⁇ 2 ⁇ ).
  • FIG. 4 is a diagram showing another example of a power conversion circuit including a power module configured by the basic unit shown in FIG. Referring to FIG. 4, the power conversion circuit is a three-phase inverter, and converts direct current into three-phase alternating current.
  • the three-phase load 9B is an inductive load, for example, a three-phase AC motor.
  • the power conversion circuit includes a power module 102.
  • the power module 102 includes units 10A, 10B, and 10C.
  • the units 10A to 10C are provided in parallel between the terminals 5 and 6. Terminals 5 and 6 are connected to a positive electrode and a negative electrode of DC power supply 8, respectively.
  • the terminals (7A to 7C) of the units 10A to 10C are connected to the three-phase load 9B.
  • Each of the units 10A to 10C has the configuration shown in FIG. Therefore, description of each configuration of units 10A to 10C will not be repeated hereinafter.
  • FIGS. 2 and 4 show an inverter, that is, a power conversion circuit for converting DC power into AC power.
  • the power module shown in FIGS. 2 and 4 can also be applied to a power conversion circuit for converting AC power into DC power.
  • an AC power source is connected to the power module instead of the AC load.
  • a DC load resistive load is connected to the power module instead of the DC power supply.
  • the power module according to an embodiment of the present invention is not limited to that used in a circuit that converts power between direct current and alternating current.
  • FIG. 5 is a diagram showing another example of the power conversion circuit including the power module configured by the basic unit shown in FIG. Referring to FIG. 5, the power conversion circuit is a DC / DC converter, and boosts or steps down a DC voltage.
  • the power conversion circuit includes a power module 103.
  • the power module 103 includes the unit 10 shown in FIG. Terminal 7 is connected to one end of inductive element 9 (for example, a reactor). The other end of the inductive element 9 is connected to the terminal 5A.
  • Terminal 5B is connected to terminal 6.
  • the power conversion circuit converts the DC voltage V1 between the terminals 5 and 6 into the DC voltage V2, and outputs the DC voltage V2 between the terminals 5A and 5B.
  • V2 > V1.
  • the power conversion circuit may convert the DC voltage V2 between the terminals 5A and 5B into the DC voltage V1 and output the DC voltage V1 between the terminals 5 and 6.
  • the semiconductor switch elements included in the units shown in FIGS. 4 and 5 operate according to the method shown in FIG. Furthermore, the control method for turning on / off the semiconductor switch element described above is not particularly limited. For example, a pulse width modulation (PWM) method can be applied to the embodiment of the present invention.
  • PWM pulse width modulation
  • Typical loss of the power conversion circuit is 1) loss due to the on-resistance of each of the diode and the semiconductor switching element, 2) switching loss (turn-on loss and turn-off loss), and 3) reverse recovery loss of the diode. is there.
  • the power module according to the embodiment of the present invention includes a gallium nitride (GaN) diode or a diamond diode.
  • these diodes are Schottky barrier diodes.
  • the Schottky barrier diode is formed using a GaN substrate or a diamond substrate.
  • GaN and diamond are wide gap semiconductors having a band gap larger than that of Si. Therefore, by applying the GaN Schottky barrier diode or the diamond Schottky barrier diode to the power module, low loss, high breakdown voltage, high speed operation, and stable operation in a high temperature environment can be realized.
  • GaN Schottky barrier diodes and diamond Schottky barrier diodes have lower on-resistance values than SiC Schottky barrier diodes. Therefore, according to the embodiment of the present invention, it is possible to further promote the reduction of the loss of the power conversion circuit.
  • Diodes 3 and 4 can be realized by the same kind of Schottky barrier diode. Therefore, in the following, an example of the structure of the diode 3 will be representatively described, and detailed description of the structure of the diode 4 will not be repeated.
  • FIG. 6 is a cross-sectional view of one example of a GaN Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention.
  • FIG. 7 is a perspective view of the GaN Schottky barrier diode shown in FIG.
  • the Schottky barrier diode (SBD) 3-1 includes a GaN free-standing substrate 22 as a gallium nitride substrate and a GaN epitaxial layer 23 as an epitaxial layer.
  • the GaN epitaxial layer 23 is formed on the surface 22a of the GaN free-standing substrate 22 as the main surface.
  • the SBD 3-1 also includes an insulating layer 24.
  • the insulating layer 24 is formed on the surface 23 a of the GaN epitaxial layer 23.
  • the SBD 3-1 further includes an electrode 25 formed so as to contact the surface 23a of the GaN epitaxial layer 23 and overlap the insulating layer 24, and an electrode 26 formed on the back surface 22b side of the GaN free-standing substrate 22. .
  • An opening is formed in the insulating layer 24, and the electrode 25 is formed inside the opening of the insulating layer 24.
  • the electrode 25 is formed, for example, so that the planar shape is circular.
  • the electrode 25 includes a Schottky electrode that is in contact with the surface 23a of the GaN epitaxial layer 23 inside the opening of the insulating layer 24 and a field plate that is overlapped with the insulating layer 24 (hereinafter referred to as “FP”). Electrodes.
  • the FP electrode and the insulating layer 24 form an FP structure.
  • the Schottky electrode forms a Schottky junction with the GaN epitaxial layer 23.
  • the electrode 26 is an ohmic electrode that forms an ohmic junction with the GaN free-standing substrate 22.
  • the dislocation density in the GaN free-standing substrate 22 is 1 ⁇ 10 8 cm ⁇ 2 or less.
  • the material of the electrode 25 includes at least one substance selected from the group consisting of gold, platinum, nickel, palladium, cobalt, copper, silver, tungsten, and titanium.
  • the FP structure is used under the condition that the reverse leakage current is reduced and the Schottky electrode such as gold that can realize the low leakage current is used. Electric field relaxation occurs remarkably. As a result, the reverse leakage current is further reduced and the reverse withstand voltage can be increased.
  • the dislocation density can be measured by, for example, counting the number of pits formed by etching in molten KOH and dividing by the unit area.
  • the SBD 3-1 has a vertical structure in which current flows from one of the Schottky electrode and the ohmic electrode to the other.
  • the vertical structure can pass a larger current than the horizontal structure, and therefore the vertical structure is a structure more suitable for the power device.
  • the GaN free-standing substrate 22 and the GaN epitaxial layer 23 are conductive, a vertical structure in which an ohmic electrode is formed on the back side is possible.
  • the insulating layer 24 can be formed of a silicon nitride film (SiN x ).
  • the hydrogen concentration in the insulating layer 24 can be less than 3.8 ⁇ 10 22 cm ⁇ 3 , more preferably less than 2.0 ⁇ 10 22 cm ⁇ 3 .
  • SiN x having a low hydrogen concentration in the film can be applied as an insulating film for forming the FP structure.
  • SBD3-1 can provide a large electric field relaxation effect and can increase the reverse withstand voltage.
  • FIG. 6 shows the thickness of the insulating layer 24 as the film thickness t.
  • the thickness t of the insulating layer 24 is desirably 10 nm or more and 5 ⁇ m or less. If the thickness t of the insulating layer 24 is less than 10 nm, the withstand voltage of the insulating layer 24 is low, and the insulating layer 24 is destroyed first, so that the effect of the FP structure cannot be obtained. Moreover, if the thickness of the insulating layer 24 exceeds 5 ⁇ m, the electric field relaxation itself by the FP structure cannot be obtained.
  • the FP length is a length where the FP electrode overlaps the insulating layer 24.
  • the FP length is a length in which the FP electrode overlaps the insulating layer 24 in a cross section passing through the center of the electrode 25 having a circular planar shape as shown in FIG. It is. That is, when the planar shape of the opening of the insulating layer 24 is circular and the planar shape of the Schottky electrode that is a part of the electrode 25 is circular, the FP length is the radial direction of the Schottky electrode. The length of the FP electrode overlaps with the insulating layer 24.
  • the FP length is the length in which the FP electrode overlaps the insulating layer in the direction of a straight line connecting the center of gravity of the Schottky electrode with respect to the planar shape and a certain point on the outer periphery of the planar shape.
  • Such an FP length is desirably 1 ⁇ m or more and 1 mm or less. If the FP length is less than 1 ⁇ m, control becomes difficult, and the effect of the FP structure cannot be obtained stably. Moreover, if the FP length exceeds 1 mm, the electric field relaxation itself by the FP structure cannot be obtained.
  • the insulating layer 24 includes an end face 24 a that faces an opening that is a portion where the electrode 25 contacts the GaN epitaxial layer 23.
  • the end face 24a is inclined with respect to the surface 23a of the GaN epitaxial layer 23 so as to form an angle ⁇ .
  • the FP electrode which is a portion of the electrode 25 that overlaps the insulating layer 24, is overlaid on the insulating layer 24 so as to adhere to the end face 24a.
  • the effect of electric field relaxation by the FP structure can be increased.
  • the reverse breakdown voltage of the SBD 3-1 can be further improved.
  • Such an inclination of the end surface 24a of the insulating layer 24 can be formed by wet etching or dry etching.
  • the end face 24a is formed so that the angle ⁇ is in the range of 0.1 ° to 60 °. If the angle of inclination is less than 0.1 °, the angle reproducibility becomes difficult to obtain, and more raw materials are required, which may cause problems in manufacturing. On the other hand, if the inclination angle exceeds 60 °, the effect of electric field relaxation is reduced.
  • FIG. 8 is a cross-sectional view of one example of a diamond Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention.
  • the SBD 3-2 includes a diamond substrate 30, a first metal layer 31, and a second metal layer 32.
  • the diamond substrate 30 may be a bulk single crystal, a thin film polycrystal by a vapor phase synthesis method, or a thin film single crystal (epitaxial film) by a vapor phase growth method.
  • the diamond substrate may be either n-type or p-type.
  • the diamond substrate may be a natural or artificial (high pressure synthesis) bulk single crystal.
  • the resistivity of diamond is preferably 1 ⁇ 10 5 ⁇ ⁇ cm or less, more preferably 1000 ⁇ ⁇ cm or less, and still more preferably 100 ⁇ ⁇ cm or less.
  • a metal having a work function of 5 eV or less is used as the first metal layer 31 .
  • “Work function” refers to the minimum energy required to extract electrons in the Fermi level into a vacuum. Examples of such work functions include S.I. M.M. The work function values described in Sze's "Physics of Semiconductor Devices” (2nd edition) John Wiley & Sons (1981), page 251 can be suitably used.
  • a metal having a work function of 5 eV or less for example, aluminum (Al), magnesium (Mg), zinc (Zn), or the like can be suitably used.
  • the work function of the first metal layer 31 is more preferably 2.5 eV to 4.5 eV.
  • the melting point of the first metal layer 31 is preferably 700 ° C. or lower.
  • a refractory metal having a melting point of 1000 ° C. or higher is used.
  • a metal for example, tungsten (W), zirconium (Zr), tantalum (Ta), molybdenum (Mo), niobium (Nb) and the like can be suitably used.
  • the thickness t1 of the first metal layer 31 in contact with the diamond substrate 30 is 0.5 nm or more, preferably 5 nm or more. Furthermore, the thickness t1 of the first metal layer 31 is 100 nm or less, and preferably 50 nm or less.
  • the second metal layer 32 is in contact with the first metal layer 31.
  • the thickness t2 of the second metal layer 32 is preferably larger than the thickness t1 of the first metal layer 31 (t2> t1).
  • the thickness of the second metal layer 32 is preferably 10 nm or more, and more preferably 30 to 200 nm.
  • the ratio (t2 / t1) of the thickness t2 of the second metal layer to the thickness t1 of the first metal layer is preferably 4 or more, and more preferably 10 to 50.
  • FIG. 9 is a cross-sectional view of another example of a diamond Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention.
  • the SBD 3-3 includes a diamond substrate 30, a first p-type diamond layer 35, a second p-type diamond layer 36, a Schottky electrode 37, and an ohmic electrode 38. .
  • the first p-type diamond layer 35 is formed on the surface of the diamond substrate 30.
  • the second p-type diamond layer 36 is formed on the first p-type diamond layer 35.
  • the first p-type diamond layer 35 and the second p-type diamond layer 36 are diamond layers doped with boron.
  • the boron concentration of the first p-type diamond layer 35 is higher than the boron concentration of the second p-type diamond layer 36.
  • the second p-type diamond layer 36 is processed by photolithography and etching as shown in FIG.
  • the Schottky electrode 37 is formed on the second p-type diamond layer 36.
  • the Schottky electrode 37 is formed, for example, by laminating an aluminum (Al) film and a tungsten (W) film in this order.
  • the ohmic electrode 38 is formed on the first p-type diamond layer 35.
  • the ohmic electrode 38 is formed, for example, by laminating titanium (Ti), molybdenum (Mo), and gold (Au) in this order.
  • the semiconductor switch element is a transistor.
  • the transistor is a SiC transistor or a GaN transistor.
  • the SiC transistor or the GaN transistor may be a horizontal transistor or a vertical transistor, but is more preferably a vertical transistor. That is, preferably, the semiconductor switch element has a vertical structure in which a current flows in the depth direction of the semiconductor switch element.
  • the SiC transistor or the GaN transistor has a vertical structure
  • a larger current can flow than in the horizontal structure.
  • the loss of the power conversion circuit can be further reduced.
  • the semiconductor switch elements 1 and 2 can be realized by the same kind of transistors. Therefore, in the following, an example of the structure of the semiconductor switch element 1 will be representatively described, and detailed description of the structure of the semiconductor switch element 2 will not be repeated.
  • SiC transistor 1-1 is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes substrate 40, buffer layer 41, breakdown voltage holding layer 42, and p region 43. , N + region 44, p + region 45, oxide film 46, source electrode 47a, upper source electrode 47b, gate electrode 48, and drain electrode 49.
  • DiMOSFET Double Implanted Metal Oxide Semiconductor Field Effect Transistor
  • the substrate 40 is an n-type SiC substrate.
  • the buffer layer 41 is made of n-type SiC and is formed on the surface of the substrate 40.
  • the thickness of the buffer layer 41 is, for example, 0.5 ⁇ m.
  • the concentration of the n-type conductive impurity in the buffer layer 41 can be set to 5 ⁇ 10 17 cm ⁇ 3 , for example.
  • the breakdown voltage holding layer 42 is formed on the buffer layer 41.
  • the breakdown voltage holding layer 42 is made of n-type SiC.
  • the thickness of the breakdown voltage holding layer 42 is, for example, 10 ⁇ m.
  • concentration of the n-type conductive impurity in the breakdown voltage holding layer 42 for example, a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
  • the p regions 43 are formed on the surface of the breakdown voltage holding layer 42 with a space therebetween, and the conductivity type is p-type.
  • the n + region 44 is formed in the surface layer of the p region 43, and its conductivity type is n type.
  • a p + region 45 is formed at a position adjacent to the n + region 44.
  • Oxide film 46, and two n + regions 44 and exposed between the two n + regions 44 are formed so as to cover a portion and two p regions 43 of the breakdown voltage holding layer 42.
  • the gate electrode 48 is formed on the oxide film 46.
  • Source electrode 47 a is formed on n + region 44 and p + region 45.
  • An upper source electrode 47b is formed on the source electrode 47a.
  • the drain electrode 49 is formed on the back surface of the substrate 40.
  • the back surface of the substrate 40 is the surface opposite to the surface on which the buffer layer 41 is formed.
  • SiC transistor 1-1 shown in FIG. 10 includes a SiC substrate, a semiconductor layer formed on the surface of the SiC substrate, and an electrode formed on the back surface of the SiC substrate.
  • the “semiconductor layer” includes the buffer layer 41 and the breakdown voltage holding layer 42 (including the p region 43, the n + region 44, and the p + region 45). That is, preferably, the semiconductor switch element is a silicon carbide transistor.
  • JFET lateral junction field effect transistor
  • FIG. 11 is a cross-sectional view of one example of a GaN transistor that can be applied to the power module according to the embodiment of the present invention.
  • GaN transistor 1-2 is an FET, and includes a conductive GaN substrate 51, an n ⁇ -type GaN drift layer 52, a p-type GaN layer 53, and an n + -type cap layer 54.
  • a conductive GaN substrate 51 an n ⁇ -type GaN drift layer 52, a p-type GaN layer 53, and an n + -type cap layer 54.
  • the n ⁇ -type GaN drift layer 52, the p-type GaN layer 53, and the n + -type cap layer 54 are formed on the surface of the GaN substrate 51 by epitaxial growth, and constitute a GaN-based stacked body 55.
  • a buffer layer made of an AlGaN layer or a GaN layer may be inserted between the GaN substrate 51 and the n ⁇ -type GaN drift layer 52. Further, a p-type AlGaN layer can be used in place of the p-type GaN layer 53.
  • the regrowth layer 62 is formed by epitaxial growth so as to cover the wall surface of the opening 61 and the surface of the GaN-based stacked body 55.
  • the regrowth layer 62 includes an i (intrinsic) GaN electron transit layer 63 and an AlGaN electron supply layer 64.
  • An intermediate layer such as AlN may be inserted between the iGaN electron transit layer 63 and the AlGaN electron supply layer 64.
  • the gate electrode 56 is positioned so as to overlap the regrowth layer 62.
  • the drain electrode 58 is located on the back surface of the GaN substrate 51.
  • the source electrode 57 is in ohmic contact with the regrown layer 62 above the GaN-based stacked body 55. In the configuration shown in FIG. 11, the source electrode 57 is located on the regrowth layer 62 in contact with the regrowth layer 62. However, the source electrode 57 may be positioned on the n + -type cap layer 54 in contact with the n + -type cap layer 54 and may be in ohmic contact with the end face of the regrowth layer 62.
  • the GaN transistor 1-2 electrons flow from the source electrode 57 through the electron transit layer 63 to the drain electrode 58 through the n ⁇ -type GaN drift layer 52.
  • the p-type GaN layer 53 is sandwiched between the n ⁇ -type GaN drift layer 52 and the n + -type cap layer 54.
  • the p-type GaN layer 53 exhibits a back gate effect such as raising the band energy of electrons and improving the breakdown voltage characteristics.
  • the p-type GaN layer 53 is disposed so as to be buried under the source electrode 57, and a conductive portion 59 that is in ohmic contact with the p-type GaN layer 53 and the source electrode 57 is disposed.
  • the conductive portion 59 passes through the n + -type cap layer 54 and reaches the p-type GaN layer 53 and is in ohmic contact with the p-type GaN layer 53. Due to the conductive portion 59, the p-type GaN layer 53 and the source electrode 57 have a common potential.
  • the p-type GaN layer 53 is fixed at, for example, the ground potential.
  • the p-type GaN layer 53 exhibits the following effects as described above: (1) Improvement of pinch-off characteristics by shifting the band in the positive direction; (2) Improvement of longitudinal pressure resistance performance; (3) Prevention of the kink phenomenon.
  • the above (1) and (2) can obtain the action by the above-mentioned back gate effect even without the conductive part 59.
  • the conductive portion 59 in ohmic contact with the p-type GaN layer 53, holes generated between the channel and the drain electrode can be extracted to the outside when the drain voltage is increased. ) Can be obtained.
  • (3) will be described in detail.
  • the conductive portion 59 is not provided, even if the p-type GaN layer 53 is disposed, a high electric field region is formed on the drain side of the channel when the drain voltage is increased. In this case, avalanche breakdown occurs due to high-energy electrons, and high-concentration holes are generated. Since the GaN-based semiconductor is a wide band gap semiconductor, the recombination time constant is long. Accordingly, holes are accumulated in high concentration in the GaN-based stacked body 55, particularly the n ⁇ -type GaN drift layer 52. As a result, a runaway such as an increase in drain current occurs in the drain current-drain voltage saturation region. By providing the conductive portion 59 in the p-type GaN layer 53, even if a large number of holes are formed by avalanche breakdown, the holes can be extracted outside through the conductive portion 59. Thereby, the kink phenomenon can be prevented.
  • the p-type GaN layer 53 can obtain the actions shown in (1) to (3) above. As a result, it is possible to overcome limitations such as the kink phenomenon and vertical pressure resistance, expand the degree of freedom, and operate a large current vertically through 2DEG (two-dimensional electron gas) formed in the opening. It becomes.
  • 2DEG two-dimensional electron gas
  • FIG. 12 is a plan view of the GaN transistor shown in FIG. Referring to FIG. 12, GaN transistor 1-2 has a hexagonal shape. Therefore, the GaN transistors 1-2 can be densely arranged in a plane. Furthermore, the conductive portion 59 and the source electrode 57 have an annular hexagonal shape. The conductive portion 59 is completely covered with the source electrode 57. Therefore, the p-type GaN layer 53 can be electrically connected to the source electrode 57 without increasing the area.
  • the thickness of the n ⁇ -type GaN drift layer 52 can be 1 ⁇ m to 25 ⁇ m.
  • the carrier concentration of the n ⁇ -type GaN drift layer 52 can be 0.2 ⁇ 10 16 cm ⁇ 3 to 20.0 ⁇ 10 16 cm ⁇ 3 .
  • the thickness of the p-type GaN layer 53 can be 0.1 ⁇ m to 10 ⁇ m.
  • the carrier concentration of the p-type GaN layer 53 can be set to 0.5 ⁇ 10 16 cm ⁇ 3 to 50 ⁇ 10 16 cm ⁇ 3 .
  • the carrier concentration is set higher than the above value, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3.
  • the thickness of the n + -type cap layer 54 can be 0.1 ⁇ m to 3 ⁇ m.
  • the carrier concentration of the n + -type cap layer 54 can be 1.0 ⁇ 10 17 cm ⁇ 3 to 30.0 ⁇ 10 17 cm ⁇ 3 .
  • the thickness of the electron transit layer 63 can be about 5 nm to 100 nm.
  • the thickness of the electron supply layer 64 can be about 1 nm to 100 nm. If the thickness of the electron transit layer 63 is less than 5 nm, the interface between the 2DEG and the electron supply layer 64 / the electron transit layer 63 is too close to reduce the mobility of the 2DEG. When the thickness of the electron transit layer 63 exceeds 100 nm, the effect of the p-type GaN layer 53 is reduced and the pinch-off characteristics are deteriorated. Therefore, the thickness of the electron transit layer 63 is preferably 100 nm or less.
  • SiC transistor 1-1 shown in FIGS. 11 and 12 includes a GaN substrate, a semiconductor layer formed on the surface of the GaN substrate, and an electrode formed on the back surface of the GaN substrate.
  • the “semiconductor layer” is the GaN-based stacked body 55 (the n ⁇ -type GaN drift layer 52, the p-type GaN layer 53, and the n + -type cap layer 54).
  • the semiconductor switch element is a gallium nitride transistor.
  • a gallium nitride transistor is formed on a gallium nitride substrate having a first main surface and a second main surface located opposite to the first main surface, and on the first main surface of the gallium nitride substrate.
  • a GaN diode or a diamond diode is used for the power module. That is, preferably, the diode is a gallium nitride diode. Or, preferably, the diode is a diamond diode.
  • the diode is a gallium nitride diode.
  • the diode is a diamond diode.
  • a GaN transistor or a SiC transistor is used for the power module. That is, in this embodiment, any one of (SiC transistor, GaN Schottky diode), (SiC transistor, diamond Schottky diode), (GaN transistor, GaN Schottky diode), (GaN transistor, diamond Schottky diode) The combination is adopted for the power module. Both the GaN transistor and the SiC transistor can reduce loss, increase the operation speed, increase the breakdown voltage, and operate at high temperature, as compared with the Si transistor. Therefore, the performance of the power conversion circuit can be further improved.
  • the SiC transistor and the GaN transistor are specifically shown as the semiconductor switch elements.
  • a diamond transistor may be applied to the power module instead of the SiC transistor or the GaN transistor. That is, preferably, the semiconductor switch element is a diamond transistor.
  • the transistor is shown as the semiconductor switching element.
  • the semiconductor switching element is not limited to the transistor as long as it is a semiconductor switching element formed of SiC, GaN, or diamond, and is applied to the power module according to the present embodiment. be able to.

Abstract

A unit (10) is provided with semiconductor switch elements (1, 2), and diodes (3, 4). The diode (3) is reversely biased when the semiconductor switch element (2) is in the on-state, and a current is carried to the diode when the semiconductor switch element (2) is in the off-state. The diode (4) is reversely biased when the semiconductor switch element (1) is in the on-state, and a current is carried to the diode when the semiconductor switch element (1) is in the off-state. The diodes (3, 4) are gallium nitride (GaN) diodes or diamond diodes. A power module provided with the unit (10) is applied to power conversion circuits, such as converters and inverters. Consequently, performances of the power conversion circuits are improved.

Description

パワーモジュールおよび電力変換回路Power module and power conversion circuit
　本発明はパワーモジュールおよび電力変換回路に関し、特に、半導体スイッチ素子とダイオードとを備えたパワーモジュール、およびそのパワーモジュールを備える電力変換回路に関する。 The present invention relates to a power module and a power conversion circuit, and more particularly, to a power module including a semiconductor switch element and a diode, and a power conversion circuit including the power module.
　一般に、インバータおよびコンバータ等の電力変換回路は、トランジスタとダイオードとを備える。従来、これらの半導体パワーデバイスは、シリコン（Ｓｉ）により形成されてきた。しかしながらＳｉパワーデバイスの性能（例えば、低損失、高い動作速度など）は、理論上の限界に近付きつつある。したがって、今後は、Ｓｉパワーデバイスの性能の大幅な改善を期待することが難しい。 Generally, power conversion circuits such as inverters and converters include transistors and diodes. Conventionally, these semiconductor power devices have been formed of silicon (Si). However, the performance of Si power devices (eg, low loss, high operating speed, etc.) is approaching theoretical limits. Therefore, it is difficult to expect significant improvement in the performance of Si power devices in the future.
　炭化珪素（ＳｉＣ）パワーデバイスは、Ｓｉパワーデバイスよりも優れた性能を有する半導体パワーデバイスとして注目されている。たとえば４Ｈ－ＳｉＣは、シリコンの約３倍のバンドギャップ、シリコンの約１０倍の絶縁破壊電圧、およびシリコンの約３倍の熱伝導度を有する。したがって、ＳｉＣパワーデバイスによって、現在のＳｉパワーデバイスに比べて、高耐圧、低損失、高速動作、高温環境での安定動作を実現できることが期待される。 Silicon carbide (SiC) power devices are attracting attention as semiconductor power devices having performance superior to Si power devices. For example, 4H—SiC has a bandgap about 3 times that of silicon, a breakdown voltage about 10 times that of silicon, and a thermal conductivity about 3 times that of silicon. Therefore, it is expected that the SiC power device can realize high breakdown voltage, low loss, high speed operation, and stable operation in a high temperature environment as compared with the current Si power device.
　たとえば、米国特許第５６６１６４４号明細書（特許文献１）は、少なくとも１つのスイッチング素子と、ＳｉＣダイオードとを含む変換回路を開示する。ＳｉＣダイオードは、スイッチング素子がオフしたときに導通して、スイッチング素子がオンしたときに逆バイアスされる。 For example, US Pat. No. 5,661,644 (Patent Document 1) discloses a conversion circuit including at least one switching element and a SiC diode. The SiC diode conducts when the switching element is turned off and is reverse-biased when the switching element is turned on.
米国特許第５６６１６４４号明細書US Pat. No. 5,661,644
　低損失、動作速度、動作の安定性などといった性能を改善することが電力変換回路には常に要求される。本発明の目的は、電力変換回路の性能を高めることである。 ∙ Power conversion circuits are always required to improve performance such as low loss, operating speed, and operational stability. An object of the present invention is to improve the performance of a power conversion circuit.
　１つの局面において、本発明に係るパワーモジュールは、半導体スイッチ素子と、ダイオードとを備える。ダイオードは、半導体スイッチ素子がオン状態である時に逆バイアスされ、半導体スイッチ素子がオフ状態である時に導通するように配置される。ダイオードは、窒化ガリウムダイオードおよびダイヤモンドダイオードのいずれかである。 In one aspect, a power module according to the present invention includes a semiconductor switch element and a diode. The diode is arranged to be reverse-biased when the semiconductor switch element is in an on state and to conduct when the semiconductor switch element is in an off state. The diode is either a gallium nitride diode or a diamond diode.
　好ましくは、半導体スイッチ素子は、炭化珪素トランジスタ、窒化ガリウムトランジスタ、およびダイヤモンドトランジスタのいずれかである。 Preferably, the semiconductor switch element is any one of a silicon carbide transistor, a gallium nitride transistor, and a diamond transistor.
　別の局面において、本発明に係る電力変換回路は、半導体スイッチ素子と、ダイオードとを備える。ダイオードは、半導体スイッチ素子がオン状態である時に逆バイアスされ、半導体スイッチ素子がオフ状態である時に導通するように配置される。ダイオードは、窒化ガリウムダイオードおよびダイヤモンドダイオードのいずれかである。 In another aspect, the power conversion circuit according to the present invention includes a semiconductor switch element and a diode. The diode is arranged to be reverse-biased when the semiconductor switch element is in an on state and to conduct when the semiconductor switch element is in an off state. The diode is either a gallium nitride diode or a diamond diode.
　本発明によれば、電力変換回路の低損失化等の性能を高めることができる。 According to the present invention, it is possible to improve performance such as reduction in loss of the power conversion circuit.
本発明の一実施形態に係るパワーモジュールを構成する基本ユニットの回路図である。It is a circuit diagram of the basic unit which constitutes the power module concerning one embodiment of the present invention. 図１に示したパワーモジュールを含む電力変換回路の１つの例を示した図である。It is the figure which showed one example of the power converter circuit containing the power module shown in FIG. 図２に示した電力変換回路（単相インバータ）の動作を説明するための図である。It is a figure for demonstrating operation | movement of the power converter circuit (single phase inverter) shown in FIG. 図１に示した基本ユニットにより構成されたパワーモジュールを含む電力変換回路の別の例を示した図である。It is the figure which showed another example of the power converter circuit containing the power module comprised by the basic unit shown in FIG. 図１に示した基本ユニットにより構成されたパワーモジュールを含む電力変換回路の別の例を示した図である。It is the figure which showed another example of the power converter circuit containing the power module comprised by the basic unit shown in FIG. 本発明の実施の形態に従うパワーモジュールに適用されうるＧａＮショットキーバリアダイオードの１つの例の断面図である。It is sectional drawing of one example of the GaN Schottky barrier diode which can be applied to the power module according to the embodiment of the present invention. 図６に示すＧａＮショットキーバリアダイオードの斜視図である。FIG. 7 is a perspective view of the GaN Schottky barrier diode shown in FIG. 6. 本発明の実施の形態に従うパワーモジュールに適用されうるダイヤモンドショットキーバリアダイオードの１つの例の断面図である。It is sectional drawing of one example of the diamond Schottky barrier diode which can be applied to the power module according to the embodiment of the present invention. 本発明の実施の形態に従うパワーモジュールに適用されうるダイヤモンドショットキーバリアダイオードの他の例の断面図である。It is sectional drawing of the other example of the diamond Schottky barrier diode which can be applied to the power module according to the embodiment of the present invention. 本発明の実施の形態に従うパワーモジュールに適用されうるＳｉＣトランジスタの１つの例の断面図である。It is sectional drawing of one example of the SiC transistor which can be applied to the power module according to the embodiment of the present invention. 本発明の実施の形態に従うパワーモジュールに適用されうるＧａＮトランジスタの１つの例の断面図である。It is sectional drawing of one example of the GaN transistor which can be applied to the power module according to the embodiment of the present invention. 図１１に示すＧａＮトランジスタの平面図である。It is a top view of the GaN transistor shown in FIG.
　以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。なお、図中同一または相当部分には同一符号を付してその説明は繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.
　本明細書では、「電力変換回路」との用語は、電力の少なくとも１つの形態を変化させる回路を含む。「電力の形態」とは、たとえば、周波数（直流を含む）、相数、電圧、電流を含む。 In this specification, the term “power conversion circuit” includes a circuit that changes at least one form of power. “Power form” includes, for example, frequency (including direct current), number of phases, voltage, and current.
　図１は、本発明の一実施形態に係るパワーモジュールを構成する基本ユニットの回路図である。図１を参照して、ユニット１０は、半導体スイッチ素子１，２と、ダイオード３，４とを備える。 FIG. 1 is a circuit diagram of a basic unit constituting a power module according to an embodiment of the present invention. Referring to FIG. 1, unit 10 includes semiconductor switch elements 1 and 2 and diodes 3 and 4.
　半導体スイッチ素子１，２は、端子５，６の間に直列接続される。端子５は正の極性を有し、端子６は負の極性を有する。半導体スイッチ素子１，２の接続点は端子７に接続される。 The semiconductor switch elements 1 and 2 are connected in series between the terminals 5 and 6. Terminal 5 has a positive polarity and terminal 6 has a negative polarity. The connection point of the semiconductor switch elements 1 and 2 is connected to the terminal 7.
　ダイオード３，４は半導体スイッチ素子１，２にそれぞれ逆並列接続される。すなわち、ダイオード３，４の順方向は、半導体スイッチ素子１，２に流れる電流の方向とは逆である。 The diodes 3 and 4 are connected in reverse parallel to the semiconductor switch elements 1 and 2, respectively. That is, the forward direction of the diodes 3 and 4 is opposite to the direction of the current flowing through the semiconductor switch elements 1 and 2.
　図２は、図１に示したパワーモジュールを含む電力変換回路の１つの例を示した図である。図２を参照して、電力変換回路は単相インバータであり、直流を単相交流に変換する。単相負荷９Ａは、誘導性負荷であり、たとえば単相モータである。ただし単相負荷９Ａの種類は特に限定されるものではない。 FIG. 2 is a diagram showing an example of a power conversion circuit including the power module shown in FIG. Referring to FIG. 2, the power conversion circuit is a single-phase inverter, and converts direct current into single-phase alternating current. Single phase load 9A is an inductive load, for example, a single phase motor. However, the type of the single-phase load 9A is not particularly limited.
　電力変換回路は、パワーモジュール１０１を含む。パワーモジュール１０１は、ユニット１０Ａ，１０Ｂを含む。ユニット１０Ａ，１０Ｂは、端子５，６の間に並列に設けられる。端子５，６は直流電源８の正極および負極にそれぞれ接続される。ユニット１０Ａの端子７Ａおよびユニット１０Ｂの端子７Ｂは単相負荷９Ａに接続される。 The power conversion circuit includes a power module 101. The power module 101 includes units 10A and 10B. The units 10A and 10B are provided in parallel between the terminals 5 and 6. Terminals 5 and 6 are connected to a positive electrode and a negative electrode of DC power supply 8, respectively. Terminal 7A of unit 10A and terminal 7B of unit 10B are connected to single-phase load 9A.
　ユニット１０Ａ，１０Ｂの各々は、図１に示した構成を有する。具体的には、ユニット１０Ａは、半導体スイッチ素子１Ａ，２Ａと、ダイオード３Ａ，４Ａとを含む。ダイオード３Ａ，４Ａは、半導体スイッチ素子１Ａ，２Ａにそれぞれ逆並列接続される。ユニット１０Ｂは、半導体スイッチ素子１Ｂ，２Ｂと、ダイオード３Ｂ，４Ｂとを含む。ダイオード３Ｂ，４Ｂは、半導体スイッチ素子１Ｂ，２Ｂにそれぞれ逆並列接続される。 Each of the units 10A and 10B has the configuration shown in FIG. Specifically, unit 10A includes semiconductor switch elements 1A and 2A and diodes 3A and 4A. The diodes 3A and 4A are connected in antiparallel to the semiconductor switch elements 1A and 2A, respectively. Unit 10B includes semiconductor switch elements 1B and 2B and diodes 3B and 4B. The diodes 3B and 4B are connected in antiparallel to the semiconductor switch elements 1B and 2B, respectively.
　図３は、図２に示した電力変換回路（単相インバータ）の動作を説明するための図である。図２および図３を参照して、位相π（ｒａｄ）ごとに、半導体スイッチ素子１Ａ，２Ｂの組と、半導体スイッチ素子２Ａ，１Ｂの組とが交互にオン／オフする。単相負荷９Ａの電圧Ｖおよび電流ｉは、図３に示される。単相負荷９Ａが誘導性負荷であるため、電圧Ｖの変化に対する電流ｉの応答が遅れる。 FIG. 3 is a diagram for explaining the operation of the power conversion circuit (single-phase inverter) shown in FIG. 2 and 3, for each phase π (rad), the set of semiconductor switch elements 1A and 2B and the set of semiconductor switch elements 2A and 1B are alternately turned on / off. The voltage V and current i of the single-phase load 9A are shown in FIG. Since the single-phase load 9A is an inductive load, the response of the current i to the change of the voltage V is delayed.
　０（ｒａｄ）において、半導体スイッチ素子２Ａ，１Ｂがオフする。その一方で、０～θ（ｒａｄ）の期間には、負の電流ｉが、ダイオード３Ａ，４Ｂを流れて直流電源８に戻される。ダイオード３Ａ，４Ｂが導通することにより、半導体スイッチ素子１Ａ，２Ｂがオンするとともに、電圧Ｖが負から正へと切り換わる。 At 0 (rad), the semiconductor switch elements 2A and 1B are turned off. On the other hand, during a period of 0 to θ (rad), a negative current i flows through the diodes 3A and 4B and is returned to the DC power supply 8. When the diodes 3A and 4B are turned on, the semiconductor switch elements 1A and 2B are turned on, and the voltage V is switched from negative to positive.
　同様に、π（ｒａｄ）において、半導体スイッチ素子１Ａ，２Ｂがオフする。その一方で、π～π＋θ（ｒａｄ）の期間には、正の電流ｉが、ダイオード３Ｂ，４Ａを流れて直流電源８に戻される。ダイオード３Ｂ，４Ａが導通することにより、半導体スイッチ素子１Ｂ，２Ａがオンするとともに、電圧Ｖが正から負へと切り換わる。 Similarly, the semiconductor switch elements 1A and 2B are turned off at π (rad). On the other hand, during the period of π to π + θ (rad), a positive current i flows through the diodes 3B and 4A and is returned to the DC power supply 8. When the diodes 3B and 4A are turned on, the semiconductor switch elements 1B and 2A are turned on, and the voltage V is switched from positive to negative.
　ダイオード３Ａ，４Ａ，３Ｂ，４Ｂは、電圧Ｖの変化に遅れて変化する電流ｉの経路を確保する。このようなダイオードは、一般に、帰還ダイオード（freewheeling　diode）と呼ばれる。 The diodes 3A, 4A, 3B, and 4B ensure a path of the current i that changes with a change in the voltage V. Such a diode is generally called a feedback diode (freewheeling diode).
　ユニット１０Ａでは、半導体スイッチ素子１Ａのオフ時（π～π＋θ）にダイオード４Ａが導通する。半導体スイッチ素子２Ａのオフ時（０～θ）にダイオード３Ａが導通する。一方、半導体スイッチ素子１Ａのオン時（θ～π）にダイオード４Ａが逆バイアスされる。半導体スイッチ素子２Ａのオン時（π＋θ～２π）にダイオード３Ａが逆バイアスされる。ユニット１０Ｂに含まれる各半導体スイッチ素子および各ダイオードも上記と同じ方式で動作する。 In the unit 10A, the diode 4A conducts when the semiconductor switch element 1A is off (π to π + θ). When the semiconductor switch element 2A is off (0 to θ), the diode 3A becomes conductive. On the other hand, the diode 4A is reverse-biased when the semiconductor switch element 1A is on (θ˜π). The diode 3A is reverse-biased when the semiconductor switch element 2A is on (π + θ˜2π). Each semiconductor switch element and each diode included in the unit 10B operate in the same manner as described above.
　図４は、図１に示した基本ユニットにより構成されたパワーモジュールを含む電力変換回路の別の例を示した図である。図４を参照して、電力変換回路は三相インバータであり、直流を三相交流に変換する。三相負荷９Ｂは、誘導性負荷であり、たとえば三相交流モータである。 FIG. 4 is a diagram showing another example of a power conversion circuit including a power module configured by the basic unit shown in FIG. Referring to FIG. 4, the power conversion circuit is a three-phase inverter, and converts direct current into three-phase alternating current. The three-phase load 9B is an inductive load, for example, a three-phase AC motor.
　電力変換回路は、パワーモジュール１０２を含む。パワーモジュール１０２は、ユニット１０Ａ，１０Ｂ，１０Ｃを含む。ユニット１０Ａ～１０Ｃは、端子５，６の間に並列に設けられる。端子５，６は直流電源８の正極および負極にそれぞれ接続される。一方、ユニット１０Ａ～１０Ｃの各々の端子（７Ａ～７Ｃ）は、三相負荷９Ｂに接続される。ユニット１０Ａ～１０Ｃの各々は、図１に示した構成を有する。したがって、ユニット１０Ａ～１０Ｃの各々の構成の説明は以後繰り返さない。 The power conversion circuit includes a power module 102. The power module 102 includes units 10A, 10B, and 10C. The units 10A to 10C are provided in parallel between the terminals 5 and 6. Terminals 5 and 6 are connected to a positive electrode and a negative electrode of DC power supply 8, respectively. On the other hand, the terminals (7A to 7C) of the units 10A to 10C are connected to the three-phase load 9B. Each of the units 10A to 10C has the configuration shown in FIG. Therefore, description of each configuration of units 10A to 10C will not be repeated hereinafter.
　図２および図４は、インバータ、すなわち直流電力を交流電力に変換するための電力変換回路を示す。しかしながら、図２および図４に示されたパワーモジュールを、交流電力を直流電力に変換するための電力変換回路に適用することも可能である。この場合には、交流負荷に代えて交流電源がパワーモジュールに接続される。さらに、直流電源に代えて直流負荷（抵抗性負荷）がパワーモジュールに接続される。 2 and 4 show an inverter, that is, a power conversion circuit for converting DC power into AC power. However, the power module shown in FIGS. 2 and 4 can also be applied to a power conversion circuit for converting AC power into DC power. In this case, an AC power source is connected to the power module instead of the AC load. Further, a DC load (resistive load) is connected to the power module instead of the DC power supply.
　さらに、本発明の一実施形態に係るパワーモジュールは、直流と交流との間で電力を変換する回路に用いられるものと限定されない。 Furthermore, the power module according to an embodiment of the present invention is not limited to that used in a circuit that converts power between direct current and alternating current.
　図５は、図１に示した基本ユニットにより構成されたパワーモジュールを含む電力変換回路の別の例を示した図である。図５を参照して、電力変換回路はＤＣ／ＤＣコンバータであり、直流電圧を昇圧または降圧する。電力変換回路は、パワーモジュール１０３を含む。パワーモジュール１０３は、図１に示したユニット１０を含む。端子７は、誘導性要素９（たとえばリアクトル）の一方端に接続される。誘導性要素９の他方端は、端子５Ａに接続される。端子５Ｂは、端子６に接続される。 FIG. 5 is a diagram showing another example of the power conversion circuit including the power module configured by the basic unit shown in FIG. Referring to FIG. 5, the power conversion circuit is a DC / DC converter, and boosts or steps down a DC voltage. The power conversion circuit includes a power module 103. The power module 103 includes the unit 10 shown in FIG. Terminal 7 is connected to one end of inductive element 9 (for example, a reactor). The other end of the inductive element 9 is connected to the terminal 5A. Terminal 5B is connected to terminal 6.
　この例では、電力変換回路は、端子５，６間の直流電圧Ｖ１を直流電圧Ｖ２に変換して、端子５Ａ，５Ｂ間に直流電圧Ｖ２を出力する。たとえばＶ２＞Ｖ１である。さらに、電力変換回路は、端子５Ａ，５Ｂ間の直流電圧Ｖ２を直流電圧Ｖ１に変換して、端子５，６間に直流電圧Ｖ１を出力してもよい。 In this example, the power conversion circuit converts the DC voltage V1 between the terminals 5 and 6 into the DC voltage V2, and outputs the DC voltage V2 between the terminals 5A and 5B. For example, V2> V1. Further, the power conversion circuit may convert the DC voltage V2 between the terminals 5A and 5B into the DC voltage V1 and output the DC voltage V1 between the terminals 5 and 6.
　図４および図５に示されたユニットに含まれる半導体スイッチ素子は、図３に示された方式に従って動作する。さらに、上述した半導体スイッチ素子をオン／オフするための制御方式は特に限定されるものではない。たとえばパルス幅変調（ＰＷＭ）方式を本発明の実施の形態に適用することができる。 The semiconductor switch elements included in the units shown in FIGS. 4 and 5 operate according to the method shown in FIG. Furthermore, the control method for turning on / off the semiconductor switch element described above is not particularly limited. For example, a pulse width modulation (PWM) method can be applied to the embodiment of the present invention.
　これらの電力変換回路の効率を高めるためには、スイッチング速度の高速化および損失の低減が要求される。電力変換回路の損失として代表的なものは、１）ダイオードおよび半導体スイッチ素子の各々のオン抵抗に起因する損失、２）スイッチング損失（ターンオン損失およびターンオフ損失）および、３）ダイオードの逆回復損失である。 In order to increase the efficiency of these power conversion circuits, it is required to increase the switching speed and reduce the loss. Typical loss of the power conversion circuit is 1) loss due to the on-resistance of each of the diode and the semiconductor switching element, 2) switching loss (turn-on loss and turn-off loss), and 3) reverse recovery loss of the diode. is there.
　本発明の実施の形態に係るパワーモジュールは、窒化ガリウム（ＧａＮ）ダイオードまたはダイヤモンドダイオードを備える。本発明の実施の形態では、これらのダイオードは、ショットキーバリアダイオードである。ショットキーバリアダイオードは、ＧａＮ基板あるいはダイヤモンド基板を用いて形成される。 The power module according to the embodiment of the present invention includes a gallium nitride (GaN) diode or a diamond diode. In the embodiment of the present invention, these diodes are Schottky barrier diodes. The Schottky barrier diode is formed using a GaN substrate or a diamond substrate.
　ＳｉＣと同様に、ＧａＮおよびダイヤモンドは、Ｓｉのバンドギャップより大きなバンドギャップを有するワイドギャップ半導体である。したがって、ＧａＮショットキーバリアダイオードあるいはダイヤモンドショットキーバリアダイオードをパワーモジュールに適用することによって、低損失、高耐圧、高速動作、および高温環境での安定動作を実現できる。 Similar to SiC, GaN and diamond are wide gap semiconductors having a band gap larger than that of Si. Therefore, by applying the GaN Schottky barrier diode or the diamond Schottky barrier diode to the power module, low loss, high breakdown voltage, high speed operation, and stable operation in a high temperature environment can be realized.
　特に、ＧａＮショットキーバリアダイオードおよびダイヤモンドショットキーバリアダイオードは、ＳｉＣショットキーバリアダイオードに比べて低いオン抵抗値を有する。したがって本発明の実施の形態によれば、電力変換回路の損失の低減をより一層促進できる。 In particular, GaN Schottky barrier diodes and diamond Schottky barrier diodes have lower on-resistance values than SiC Schottky barrier diodes. Therefore, according to the embodiment of the present invention, it is possible to further promote the reduction of the loss of the power conversion circuit.
　ダイオード３，４は同種のショットキーバリアダイオードにより実現可能である。したがって以下では、ダイオード３の構造の例を代表的に説明し、ダイオード４の構造については詳細な説明を繰り返さない。 Diodes 3 and 4 can be realized by the same kind of Schottky barrier diode. Therefore, in the following, an example of the structure of the diode 3 will be representatively described, and detailed description of the structure of the diode 4 will not be repeated.
　（ＧａＮショットキーバリアダイオード）
　図６は、本発明の実施の形態に従うパワーモジュールに適用されうるＧａＮショットキーバリアダイオードの１つの例の断面図である。図７は、図６に示すＧａＮショットキーバリアダイオードの斜視図である。図６および図７に示すように、ショットキーバリアダイオード（ＳＢＤ）３－１は、窒化ガリウム基板としてのＧａＮ自立基板２２と、エピタキシャル層としてのＧａＮエピタキシャル層２３とを備える。ＧａＮエピタキシャル層２３は、主表面としてのＧａＮ自立基板２２の表面２２ａ上に形成されている。ＳＢＤ３－１はまた、絶縁層２４を備える。絶縁層２４は、ＧａＮエピタキシャル層２３の表面２３ａ上に形成されている。 (GaN Schottky barrier diode)
FIG. 6 is a cross-sectional view of one example of a GaN Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention. FIG. 7 is a perspective view of the GaN Schottky barrier diode shown in FIG. As shown in FIGS. 6 and 7, the Schottky barrier diode (SBD) 3-1 includes a GaN free-standing substrate 22 as a gallium nitride substrate and a GaN epitaxial layer 23 as an epitaxial layer. The GaN epitaxial layer 23 is formed on the surface 22a of the GaN free-standing substrate 22 as the main surface. The SBD 3-1 also includes an insulating layer 24. The insulating layer 24 is formed on the surface 23 a of the GaN epitaxial layer 23.
　ＳＢＤ３－１はさらに、ＧａＮエピタキシャル層２３の表面２３ａに接触するとともに絶縁層２４に重なるように形成されている電極２５と、ＧａＮ自立基板２２の裏面２２ｂ側に形成されている電極２６とを備える。絶縁層２４には開口部が形成されており、電極２５は絶縁層２４の開口部の内部に形成されている。電極２５は、たとえば平面形状が円形となるように、形成されている。 The SBD 3-1 further includes an electrode 25 formed so as to contact the surface 23a of the GaN epitaxial layer 23 and overlap the insulating layer 24, and an electrode 26 formed on the back surface 22b side of the GaN free-standing substrate 22. . An opening is formed in the insulating layer 24, and the electrode 25 is formed inside the opening of the insulating layer 24. The electrode 25 is formed, for example, so that the planar shape is circular.
　電極２５は、絶縁層２４の開口部の内部においてＧａＮエピタキシャル層２３の表面２３ａに接触する部分であるショットキー電極と、絶縁層２４に重なる部分であるフィールドプレート（以下、「ＦＰ」と称する）電極とを含む。ＦＰ電極と、絶縁層２４とは、ＦＰ構造を形成する。また、上記ショットキー電極は、ＧａＮエピタキシャル層２３とショットキー接合を形成する。一方、電極２６は、ＧａＮ自立基板２２とオーミック接合を形成する、オーミック電極である。 The electrode 25 includes a Schottky electrode that is in contact with the surface 23a of the GaN epitaxial layer 23 inside the opening of the insulating layer 24 and a field plate that is overlapped with the insulating layer 24 (hereinafter referred to as “FP”). Electrodes. The FP electrode and the insulating layer 24 form an FP structure. The Schottky electrode forms a Schottky junction with the GaN epitaxial layer 23. On the other hand, the electrode 26 is an ohmic electrode that forms an ohmic junction with the GaN free-standing substrate 22.
　ＧａＮ自立基板２２中の転位密度は、１×１０8ｃｍ-2以下である。また電極２５の材質（すなわち、ショットキー電極の材質）は、金、プラチナ、ニッケル、パラジウム、コバルト、銅、銀、タングステン、およびチタンからなる群より選ばれた少なくとも一種の物質を含む。１×１０8ｃｍ-2以下という低転位密度を有するＧａＮ自立基板２２を用いることで、ＧａＮエピタキシャル層２３中の転位密度もＧａＮ自立基板２２と同等の１×１０8ｃｍ-2以下となる。このため、ＦＰ構造を有するＳＢＤ３－１において、逆方向リーク電流が減少しているという条件下で、かつ、低リーク電流を実現できる金などのショットキー電極を用いるという条件下で、ＦＰ構造による電界緩和が顕著に起こる。その結果、逆方向リーク電流がさらに減少し、逆方向耐電圧を上昇させることができる。なお、転位密度は、たとえば溶融ＫＯＨ中のエッチングによりできるピットの個数を数えて、単位面積で割るという方法によって測定することができる。 The dislocation density in the GaN free-standing substrate 22 is 1 × 10 8 cm −2 or less. The material of the electrode 25 (that is, the material of the Schottky electrode) includes at least one substance selected from the group consisting of gold, platinum, nickel, palladium, cobalt, copper, silver, tungsten, and titanium. By using the GaN free-standing substrate 22 having a low dislocation density of 1 × 10 8 cm −2 or less, the dislocation density in the GaN epitaxial layer 23 becomes 1 × 10 8 cm −2 or less equivalent to the GaN free-standing substrate 22. Therefore, in the SBD 3-1 having the FP structure, the FP structure is used under the condition that the reverse leakage current is reduced and the Schottky electrode such as gold that can realize the low leakage current is used. Electric field relaxation occurs remarkably. As a result, the reverse leakage current is further reduced and the reverse withstand voltage can be increased. The dislocation density can be measured by, for example, counting the number of pits formed by etching in molten KOH and dividing by the unit area.
　またＳＢＤ３－１は、ショットキー電極およびオーミック電極の一方から他方へと電流が流れる、縦型構造を有する。一般にパワーデバイスでは、横型構造に比べて縦型構造はより大きな電流を流すことができるので、縦型構造はパワーデバイスにより適した構造である。ＳＢＤ３－１ではＧａＮ自立基板２２、ＧａＮエピタキシャル層２３が導電性であるため、オーミック電極を裏面側に形成した縦型構造が可能となる。 The SBD 3-1 has a vertical structure in which current flows from one of the Schottky electrode and the ohmic electrode to the other. Generally, in the power device, the vertical structure can pass a larger current than the horizontal structure, and therefore the vertical structure is a structure more suitable for the power device. In the SBD 3-1, since the GaN free-standing substrate 22 and the GaN epitaxial layer 23 are conductive, a vertical structure in which an ohmic electrode is formed on the back side is possible.
　絶縁層２４は、シリコン窒化膜（ＳｉＮx）によって形成することができる。また絶縁層２４中の水素濃度は、３．８×１０22ｃｍ-3未満、より好ましくは２．０×１０22ｃｍ-3未満とすることができる。このように、膜中水素濃度の低いＳｉＮxを、ＦＰ構造を形成する絶縁膜として適用することができる。この場合、水素濃度の高い絶縁層を用いる場合と比べて、ＦＰ構造によるショットキー電極端への電界集中の緩和に基づく逆方向耐電圧上昇の効果が抑制されることはない。つまり、ＳＢＤ３－１では大きな電界緩和効果が得られ、逆方向耐電圧を上昇させることができる。 The insulating layer 24 can be formed of a silicon nitride film (SiN x ). The hydrogen concentration in the insulating layer 24 can be less than 3.8 × 10 22 cm −3 , more preferably less than 2.0 × 10 22 cm −3 . Thus, SiN x having a low hydrogen concentration in the film can be applied as an insulating film for forming the FP structure. In this case, compared with the case where an insulating layer having a high hydrogen concentration is used, the effect of increasing the reverse withstand voltage based on the relaxation of the electric field concentration at the Schottky electrode end by the FP structure is not suppressed. That is, SBD3-1 can provide a large electric field relaxation effect and can increase the reverse withstand voltage.
　図６に、絶縁層２４の厚みを膜厚ｔとして示す。絶縁層２４の膜厚ｔは、１０ｎｍ以上５μｍ以下であることが望ましい。絶縁層２４の膜厚ｔが１０ｎｍ未満であれば、絶縁層２４の耐圧が低く、絶縁層２４が先に破壊されてＦＰ構造の効果は得られない。また、絶縁層２４の厚みが５μｍ超であれば、ＦＰ構造による電界緩和自体が得られない。 FIG. 6 shows the thickness of the insulating layer 24 as the film thickness t. The thickness t of the insulating layer 24 is desirably 10 nm or more and 5 μm or less. If the thickness t of the insulating layer 24 is less than 10 nm, the withstand voltage of the insulating layer 24 is low, and the insulating layer 24 is destroyed first, so that the effect of the FP structure cannot be obtained. Moreover, if the thickness of the insulating layer 24 exceeds 5 μm, the electric field relaxation itself by the FP structure cannot be obtained.
　また、図６に示す寸法Ｌは、ＦＰ長を示す。ＦＰ長とは、ＦＰ電極が絶縁層２４と重なる長さである。本実施の形態の場合、ＦＰ長とは、図６に示すような、ＳＢＤ３－１の、平面形状が円形の電極２５の中心を通る断面において、ＦＰ電極が絶縁層２４と重なっている長さである。つまり、絶縁層２４の開口部の平面形状が円形状であって、電極２５の一部であるショットキー電極の平面形状が円形である場合、ＦＰ長とは、ショットキー電極の半径方向における、ＦＰ電極が絶縁層２４と重なる長さである。 Dimension L shown in FIG. 6 indicates the FP length. The FP length is a length where the FP electrode overlaps the insulating layer 24. In the case of the present embodiment, the FP length is a length in which the FP electrode overlaps the insulating layer 24 in a cross section passing through the center of the electrode 25 having a circular planar shape as shown in FIG. It is. That is, when the planar shape of the opening of the insulating layer 24 is circular and the planar shape of the Schottky electrode that is a part of the electrode 25 is circular, the FP length is the radial direction of the Schottky electrode. The length of the FP electrode overlaps with the insulating layer 24.
　換言すると、ＦＰ長とは、ショットキー電極の平面形状に対する重心と、当該平面形状の外周部上のある一点と、を結ぶような直線の方向において、ＦＰ電極が絶縁層と重なっている長さをいう。このようなＦＰ長は、１μｍ以上１ｍｍ以下であることが望ましい。ＦＰ長が１μｍ未満であれば、制御が困難となり、安定してＦＰ構造の効果が得られない。また、ＦＰ長が１ｍｍ超であれば、ＦＰ構造による電界緩和自体が得られない。 In other words, the FP length is the length in which the FP electrode overlaps the insulating layer in the direction of a straight line connecting the center of gravity of the Schottky electrode with respect to the planar shape and a certain point on the outer periphery of the planar shape. Say. Such an FP length is desirably 1 μm or more and 1 mm or less. If the FP length is less than 1 μm, control becomes difficult, and the effect of the FP structure cannot be obtained stably. Moreover, if the FP length exceeds 1 mm, the electric field relaxation itself by the FP structure cannot be obtained.
　さらに、図６に示すように、絶縁層２４は、電極２５がＧａＮエピタキシャル層２３に接触する部分である開口部に面する、端面２４ａを含む。端面２４ａは、ＧａＮエピタキシャル層２３の表面２３ａに対し、角度θを形成するように傾斜している。電極２５において絶縁層２４に重なる部分であるＦＰ電極は、端面２４ａに接着するように、絶縁層２４に重ねられている。 Furthermore, as shown in FIG. 6, the insulating layer 24 includes an end face 24 a that faces an opening that is a portion where the electrode 25 contacts the GaN epitaxial layer 23. The end face 24a is inclined with respect to the surface 23a of the GaN epitaxial layer 23 so as to form an angle θ. The FP electrode, which is a portion of the electrode 25 that overlaps the insulating layer 24, is overlaid on the insulating layer 24 so as to adhere to the end face 24a.
　端面２４ａが表面２３ａに対し傾斜しているために、ＦＰ構造による電界緩和の効果を増大させることができる。その結果、ＳＢＤ３－１の逆方向耐電圧を一層向上させることができる。このような絶縁層２４の端面２４ａの傾斜は、ウェットエッチングやドライエッチングなどによって形成することができる。端面２４ａは、角度θが０．１°以上６０°以下の範囲であるように形成される。傾斜の角度が０．１°未満であれば、角度の再現性が得にくくなり、また余計に原料が必要となり、製造上問題となる場合があるためである。一方、傾斜の角度が６０°超であれば、電界緩和の効果が小さくなるためである。 Since the end face 24a is inclined with respect to the surface 23a, the effect of electric field relaxation by the FP structure can be increased. As a result, the reverse breakdown voltage of the SBD 3-1 can be further improved. Such an inclination of the end surface 24a of the insulating layer 24 can be formed by wet etching or dry etching. The end face 24a is formed so that the angle θ is in the range of 0.1 ° to 60 °. If the angle of inclination is less than 0.1 °, the angle reproducibility becomes difficult to obtain, and more raw materials are required, which may cause problems in manufacturing. On the other hand, if the inclination angle exceeds 60 °, the effect of electric field relaxation is reduced.
　なお、上記のＧａＮダイオードの構成およびその製造方法は、米国特許出願公開第２０１０／００５９７６１号明細書に開示されており、参照による引用によって、その開示の全体を本明細書に取り入れることができる。 The configuration of the GaN diode and the manufacturing method thereof are disclosed in US Patent Application Publication No. 2010/0059761, and the entire disclosure thereof can be incorporated herein by reference.
　（ダイヤモンドショットキーダイオード）
　図８は、本発明の実施の形態に従うパワーモジュールに適用されうるダイヤモンドショットキーバリアダイオードの１つの例の断面図である。図８に示されるように、ＳＢＤ３－２は、ダイヤモンド基板３０と、第１の金属層３１と、第２の金属層３２とを備える。 (Diamond Schottky diode)
FIG. 8 is a cross-sectional view of one example of a diamond Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention. As shown in FIG. 8, the SBD 3-2 includes a diamond substrate 30, a first metal layer 31, and a second metal layer 32.
　ダイヤモンド基板３０は、バルク単結晶、気相合成法による薄膜多結晶、気相成長法による薄膜単結晶（エピタキシャル膜）のいずれであってもよい。ダイヤモンド基板は、ｎ型またはｐ型のいずれであってもよい。さらに、ダイヤモンド基板は、天然または人工（高圧合成）のバルク単結晶であってもよい。 The diamond substrate 30 may be a bulk single crystal, a thin film polycrystal by a vapor phase synthesis method, or a thin film single crystal (epitaxial film) by a vapor phase growth method. The diamond substrate may be either n-type or p-type. Furthermore, the diamond substrate may be a natural or artificial (high pressure synthesis) bulk single crystal.
　ダイヤモンドの抵抗率は、１×１０5Ω・ｃｍ以下であることが好ましく、より好ましくは１０００Ω・ｃｍ以下、さらに好ましくは、１００Ω・ｃｍ以下である。 The resistivity of diamond is preferably 1 × 10 5 Ω · cm or less, more preferably 1000 Ω · cm or less, and still more preferably 100 Ω · cm or less.
　第１の金属層３１としては、仕事関数が５ｅＶ以下の金属を用いる。「仕事関数（work　function）」とは、フェルミ準位にある電子を真空中に取り出すために必要な最小エネルギーをいう。このような仕事関数としては、例えば、Ｓ．Ｍ．Ｓｚｅ著「Physics　of　Semiconductor　Devices」（第２版）John　Wiley　&　Sons　（１９８１年）第２５１頁に記載されている仕事関数の値を好適に使用することができる。このような、仕事関数が５ｅＶ以下の金属としては、例えば、アルミニウム（Ａｌ）、マグネシウム（Ｍｇ）、亜鉛（Ｚｎ）等が好適に使用可能である。 As the first metal layer 31, a metal having a work function of 5 eV or less is used. “Work function” refers to the minimum energy required to extract electrons in the Fermi level into a vacuum. Examples of such work functions include S.I. M.M. The work function values described in Sze's "Physics of Semiconductor Devices" (2nd edition) John Wiley & Sons (1981), page 251 can be suitably used. As such a metal having a work function of 5 eV or less, for example, aluminum (Al), magnesium (Mg), zinc (Zn), or the like can be suitably used.
　多層構造あるいは形成の容易さの点から、第１の金属層３１の仕事関数は、２．５ｅＶ～４．５ｅＶであることがより好ましい。第１の金属層３１の融点は、７００℃以下であることが好ましい。 From the viewpoint of the multilayer structure or ease of formation, the work function of the first metal layer 31 is more preferably 2.5 eV to 4.5 eV. The melting point of the first metal layer 31 is preferably 700 ° C. or lower.
　第２の金属層３２には、融点が１０００℃以上の高融点金属が用いられる。このような金属としては、例えば、タングステン（Ｗ）、ジルコニウム（Ｚｒ）、タンタル（Ｔａ）、モリブデン（Ｍｏ）、ニオブ（Ｎｂ）等が好適に使用可能である。 For the second metal layer 32, a refractory metal having a melting point of 1000 ° C. or higher is used. As such a metal, for example, tungsten (W), zirconium (Zr), tantalum (Ta), molybdenum (Mo), niobium (Nb) and the like can be suitably used.
　ダイヤモンド基板３０に接している第１の金属層３１の厚さｔ１は、０．５ｎｍ以上であり、好ましくは、５ｎｍ以上である。さらに、第１の金属層３１の厚さｔ１は、１００ｎｍ以下であり、好ましくは、５０ｎｍ以下である。 The thickness t1 of the first metal layer 31 in contact with the diamond substrate 30 is 0.5 nm or more, preferably 5 nm or more. Furthermore, the thickness t1 of the first metal layer 31 is 100 nm or less, and preferably 50 nm or less.
　第２の金属層３２は、第１の金属層３１と接触する。第２の金属層３２の厚さｔ２は、第１の金属層３１の厚さｔ１よりも大きいことが好ましい（ｔ２＞ｔ１）。具体的には、第２の金属層３２の厚みは１０ｎｍ以上であることが好ましく、３０～２００ｎｍであることがより好ましい。第１の金属層の厚さｔ１に対する第２の金属層の厚さｔ２の比（ｔ２／ｔ１）は、４以上であることが好ましく、１０～５０であることがより好ましい。 The second metal layer 32 is in contact with the first metal layer 31. The thickness t2 of the second metal layer 32 is preferably larger than the thickness t1 of the first metal layer 31 (t2> t1). Specifically, the thickness of the second metal layer 32 is preferably 10 nm or more, and more preferably 30 to 200 nm. The ratio (t2 / t1) of the thickness t2 of the second metal layer to the thickness t1 of the first metal layer is preferably 4 or more, and more preferably 10 to 50.
　図９は、本発明の実施の形態に従うパワーモジュールに適用されうるダイヤモンドショットキーバリアダイオードの他の例の断面図である。図９に示されるように、ＳＢＤ３－３は、ダイヤモンド基板３０と、第１のｐ型ダイヤモンド層３５と、第２のｐ型ダイヤモンド層３６と、ショットキー電極３７と、オーミック電極３８とを備える。 FIG. 9 is a cross-sectional view of another example of a diamond Schottky barrier diode that can be applied to the power module according to the embodiment of the present invention. As shown in FIG. 9, the SBD 3-3 includes a diamond substrate 30, a first p-type diamond layer 35, a second p-type diamond layer 36, a Schottky electrode 37, and an ohmic electrode 38. .
　第１のｐ型ダイヤモンド層３５は、ダイヤモンド基板３０の表面に形成されている。第２のｐ型ダイヤモンド層３６は、第１のｐ型ダイヤモンド層３５の上に形成されている。第１のｐ型ダイヤモンド層３５および第２のｐ型ダイヤモンド層３６は、ボロンがドープされたダイヤモンド層である。第１のｐ型ダイヤモンド層３５のボロン濃度は、第２のｐ型ダイヤモンド層３６のボロン濃度よりも大きい。第２のｐ型ダイヤモンド層３６は、フォトリソグラフィおよびエッチングによって、図９に示されるように加工される。 The first p-type diamond layer 35 is formed on the surface of the diamond substrate 30. The second p-type diamond layer 36 is formed on the first p-type diamond layer 35. The first p-type diamond layer 35 and the second p-type diamond layer 36 are diamond layers doped with boron. The boron concentration of the first p-type diamond layer 35 is higher than the boron concentration of the second p-type diamond layer 36. The second p-type diamond layer 36 is processed by photolithography and etching as shown in FIG.
　ショットキー電極３７は、第２のｐ型ダイヤモンド層３６上に形成されている。ショットキー電極３７は、たとえばアルミニウム（Ａｌ）膜およびタングステン（Ｗ）膜をこの順に積層することによって形成される。 The Schottky electrode 37 is formed on the second p-type diamond layer 36. The Schottky electrode 37 is formed, for example, by laminating an aluminum (Al) film and a tungsten (W) film in this order.
　オーミック電極３８は、第１のｐ型ダイヤモンド層３５上に形成されている。オーミック電極３８は、たとえばチタン（Ｔｉ）、モリブデン（Ｍｏ）および金（Ａｕ）をこの順に積層することによって形成される。 The ohmic electrode 38 is formed on the first p-type diamond layer 35. The ohmic electrode 38 is formed, for example, by laminating titanium (Ti), molybdenum (Mo), and gold (Au) in this order.
　なお、上記のダイヤモンドショットキーダイオードの構成および製造方法は米国特許第５７５７０３２号公報に開示されており、参照による引用によって、その開示の全体を本明細書に取り入れることができる。 Note that the configuration and manufacturing method of the above-described diamond Schottky diode is disclosed in US Pat. No. 5,757,032, and the entire disclosure can be incorporated herein by reference.
　本発明の一実施の形態では、半導体スイッチ素子は、トランジスタである。好ましくは、トランジスタは、ＳｉＣトランジスタまたはＧａＮトランジスタである。ＳｉＣトランジスタまたはＧａＮトランジスタは、横型トランジスタであっても縦型トランジスタであってもよいが、より好ましくは、縦型トランジスタである。つまり、好ましくは、半導体スイッチ素子は、半導体スイッチ素子の深さ方向に電流が流れる縦型構造を有する。ＳｉＣトランジスタまたはＧａＮトランジスタをパワーモジュールに用いることによって、Ｓｉトランジスタを用いたパワーモジュールよりも低損失、高速動作、高温環境での安定動作を実現できる。 In one embodiment of the present invention, the semiconductor switch element is a transistor. Preferably, the transistor is a SiC transistor or a GaN transistor. The SiC transistor or the GaN transistor may be a horizontal transistor or a vertical transistor, but is more preferably a vertical transistor. That is, preferably, the semiconductor switch element has a vertical structure in which a current flows in the depth direction of the semiconductor switch element. By using an SiC transistor or a GaN transistor for the power module, it is possible to realize lower loss, higher speed operation, and stable operation in a high temperature environment than a power module using an Si transistor.
　パワーデバイスでは、ＳｉＣトランジスタまたはＧａＮトランジスタを縦型構造とした場合には、横型構造に比べて、より大きな電流を流すことができる。縦型トランジスタを採用することにより、電力変換回路の損失をより一層低減できる。 In the power device, when the SiC transistor or the GaN transistor has a vertical structure, a larger current can flow than in the horizontal structure. By employing a vertical transistor, the loss of the power conversion circuit can be further reduced.
　半導体スイッチ素子１，２は同種のトランジスタにより実現可能である。したがって以下では、半導体スイッチ素子１の構造の例を代表的に説明し、半導体スイッチ素子２の構造については詳細な説明を繰り返さない。 The semiconductor switch elements 1 and 2 can be realized by the same kind of transistors. Therefore, in the following, an example of the structure of the semiconductor switch element 1 will be representatively described, and detailed description of the structure of the semiconductor switch element 2 will not be repeated.
　（ＳｉＣトランジスタ）
　図１０は、本発明の実施の形態に従うパワーモジュールに適用されうるＳｉＣトランジスタの１つの例の断面図である。図１０を参照して、ＳｉＣトランジスタ１－１は、縦型ＤｉＭＯＳＦＥＴ（Double　Implanted　Metal　Oxide　Semiconductor　Field　Effect　Transistor）であって、基板４０と、バッファ層４１と、耐圧保持層４２と、ｐ領域４３と、ｎ＋領域４４と、ｐ＋領域４５と、酸化膜４６と、ソース電極４７ａと、上部ソース電極４７ｂと、ゲート電極４８と、ドレイン電極４９とを備える。 (SiC transistor)
FIG. 10 is a cross-sectional view of one example of an SiC transistor that can be applied to the power module according to the embodiment of the present invention. Referring to FIG. 10, SiC transistor 1-1 is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes substrate 40, buffer layer 41, breakdown voltage holding layer 42, and p region 43. , N + region 44, p + region 45, oxide film 46, source electrode 47a, upper source electrode 47b, gate electrode 48, and drain electrode 49.
　基板４０は、ｎ型のＳｉＣ基板である。バッファ層４１はｎ型のＳｉＣからなり、基板４０の表面に形成されている。バッファ層４１の厚さは、たとえば０．５μｍである。また、バッファ層４１におけるｎ型の導電性不純物の濃度は、たとえば５×１０17ｃｍ-3とすることができる。 The substrate 40 is an n-type SiC substrate. The buffer layer 41 is made of n-type SiC and is formed on the surface of the substrate 40. The thickness of the buffer layer 41 is, for example, 0.5 μm. Further, the concentration of the n-type conductive impurity in the buffer layer 41 can be set to 5 × 10 17 cm −3 , for example.
　耐圧保持層４２は、バッファ層４１上に形成されている。耐圧保持層４２は、ｎ型のＳｉＣからなる。耐圧保持層４２の厚さは、たとえば１０μｍである。耐圧保持層４２におけるｎ型の導電性不純物の濃度として、たとえば５×１０15ｃｍ-3といった値を用いることができる。 The breakdown voltage holding layer 42 is formed on the buffer layer 41. The breakdown voltage holding layer 42 is made of n-type SiC. The thickness of the breakdown voltage holding layer 42 is, for example, 10 μm. As the concentration of the n-type conductive impurity in the breakdown voltage holding layer 42, for example, a value of 5 × 10 15 cm −3 can be used.
　ｐ領域４３は、耐圧保持層４２の表面に、互いに間隔を隔てて形成されており、その導電型はｐ型である。ｎ＋領域４４は、ｐ領域４３の表面層に形成されており、その導電型はｎ型である。ｎ＋領域４４に隣接する位置に、ｐ＋領域４５が形成されている。酸化膜４６は、２つのｎ＋領域４４と、それら２つのｎ＋領域４４の間に露出した、耐圧保持層４２の一部分および２つのｐ領域４３を覆うように形成されている。ゲート電極４８は、酸化膜４６上に形成されている。ソース電極４７ａは、ｎ＋領域４４およびｐ＋領域４５上に形成されている。ソース電極４７ａ上に上部ソース電極４７ｂが形成されている。ドレイン電極４９は基板４０の裏面に形成されている。基板４０の裏面とは、バッファ層４１が形成された表面とは反対側の表面である。 The p regions 43 are formed on the surface of the breakdown voltage holding layer 42 with a space therebetween, and the conductivity type is p-type. The n + region 44 is formed in the surface layer of the p region 43, and its conductivity type is n type. A p + region 45 is formed at a position adjacent to the n + region 44. Oxide film 46, and two n + regions 44 and exposed between the two n + regions 44 are formed so as to cover a portion and two p regions 43 of the breakdown voltage holding layer 42. The gate electrode 48 is formed on the oxide film 46. Source electrode 47 a is formed on n + region 44 and p + region 45. An upper source electrode 47b is formed on the source electrode 47a. The drain electrode 49 is formed on the back surface of the substrate 40. The back surface of the substrate 40 is the surface opposite to the surface on which the buffer layer 41 is formed.
　このように、図１０に示したＳｉＣトランジスタ１－１は、ＳｉＣ基板と、ＳｉＣ基板の表面に形成された半導体層と、ＳｉＣ基板の裏面に形成された電極とを含む。図１０に示した構成によれば、「半導体層」は、バッファ層４１および耐圧保持層４２（ｐ領域４３、ｎ＋領域４４、ｐ＋領域４５を含む）を含む。つまり、好ましくは、半導体スイッチ素子は、炭化珪素トランジスタである。 As described above, SiC transistor 1-1 shown in FIG. 10 includes a SiC substrate, a semiconductor layer formed on the surface of the SiC substrate, and an electrode formed on the back surface of the SiC substrate. According to the configuration shown in FIG. 10, the “semiconductor layer” includes the buffer layer 41 and the breakdown voltage holding layer 42 (including the p region 43, the n + region 44, and the p + region 45). That is, preferably, the semiconductor switch element is a silicon carbide transistor.
　なお、上記のＳｉＣトランジスタの構成は、国際出願番号ＰＣＴ／ＪＰ２０１１／０７９３４８号明細書に開示されており、この文献の開示の全体は、参照による援用によって本明細書に取り入れられる。 The configuration of the SiC transistor is disclosed in International Application No. PCT / JP2011 / 079348, the entire disclosure of which is incorporated herein by reference.
　また、上記のＳｉＣトランジスタの横型の接合型電界効果トランジスタ（ＪＦＥＴ：Junction　Field　Effect　Transistor）の構成は、日本国特許出願公開２００３－６８７６２号公報に開示されており、この文献の開示の全体は、参照による援用によって本明細書に取り入れられる。 Moreover, the structure of the lateral junction field effect transistor (JFET) of the SiC transistor is disclosed in Japanese Patent Application Publication No. 2003-68762, and the entire disclosure of this document is as follows. Incorporated herein by reference.
　（ＧａＮトランジスタ）
　図１１は、本発明の実施の形態に従うパワーモジュールに適用されうるＧａＮトランジスタの１つの例の断面図である。 (GaN transistor)
FIG. 11 is a cross-sectional view of one example of a GaN transistor that can be applied to the power module according to the embodiment of the present invention.
　図１１を参照して、ＧａＮトランジスタ１－２は、ＦＥＴであり、導電性のＧａＮ基板５１と、ｎ－型ＧａＮドリフト層５２と、ｐ型ＧａＮ層５３と、ｎ＋型キャップ層５４とを備える。ｎ－型ＧａＮドリフト層５２と、ｐ型ＧａＮ層５３と、ｎ＋型キャップ層５４とは、ＧａＮ基板５１の表面にエピタキシャル成長によって形成され、ＧａＮ系積層体５５を構成する。 Referring to FIG. 11, GaN transistor 1-2 is an FET, and includes a conductive GaN substrate 51, an n − -type GaN drift layer 52, a p-type GaN layer 53, and an n + -type cap layer 54. Prepare. The n − -type GaN drift layer 52, the p-type GaN layer 53, and the n + -type cap layer 54 are formed on the surface of the GaN substrate 51 by epitaxial growth, and constitute a GaN-based stacked body 55.
　なお、ＧａＮ基板５１の種類に依存して、ＧａＮ基板５１とｎ－型ＧａＮドリフト層５２との間に、ＡｌＧａＮ層またはＧａＮ層からなるバッファ層が挿入されてもよい。また、ｐ型ＧａＮ層５３に代えてｐ型ＡｌＧａＮ層を用いることもできる。 Depending on the type of GaN substrate 51, a buffer layer made of an AlGaN layer or a GaN layer may be inserted between the GaN substrate 51 and the n − -type GaN drift layer 52. Further, a p-type AlGaN layer can be used in place of the p-type GaN layer 53.
　ＧａＮ系積層体５５には、ｎ＋型キャップ層５４およびｐ型ＧａＮ層５３を貫通してｎ－型ＧａＮドリフト層５２に至る開口部６１が形成される。再成長層６２は、開口部６１の壁面およびＧａＮ系積層体５５の表面を被覆するように、エピタキシャル成長によって形成される。再成長層６２は、ｉ(intrinsic)ＧａＮ電子走行層６３およびＡｌＧａＮ電子供給層６４を含む。ｉＧａＮ電子走行層６３とＡｌＧａＮ電子供給層６４との間にＡｌＮ等の中間層が挿入されてもよい。 In the GaN-based stacked body 55, an opening 61 that penetrates the n + -type cap layer 54 and the p-type GaN layer 53 and reaches the n − -type GaN drift layer 52 is formed. The regrowth layer 62 is formed by epitaxial growth so as to cover the wall surface of the opening 61 and the surface of the GaN-based stacked body 55. The regrowth layer 62 includes an i (intrinsic) GaN electron transit layer 63 and an AlGaN electron supply layer 64. An intermediate layer such as AlN may be inserted between the iGaN electron transit layer 63 and the AlGaN electron supply layer 64.
　ゲート電極５６は再成長層６２と重なりあうように位置する。ドレイン電極５８はＧａＮ基板５１の裏面に位置する。ソース電極５７は、ＧａＮ系積層体５５の上方において、再成長層６２にオーミック接触する。図１１に示された構成では、ソース電極５７は、再成長層６２に接触した状態で再成長層６２上に位置する。しかしながらソース電極５７は、ｎ＋型キャップ層５４に接触した状態でｎ＋型キャップ層５４上に位置し、かつ、再成長層６２の端面にオーミック接触してもよい。 The gate electrode 56 is positioned so as to overlap the regrowth layer 62. The drain electrode 58 is located on the back surface of the GaN substrate 51. The source electrode 57 is in ohmic contact with the regrown layer 62 above the GaN-based stacked body 55. In the configuration shown in FIG. 11, the source electrode 57 is located on the regrowth layer 62 in contact with the regrowth layer 62. However, the source electrode 57 may be positioned on the n + -type cap layer 54 in contact with the n + -type cap layer 54 and may be in ohmic contact with the end face of the regrowth layer 62.
　ＧａＮトランジスタ１－２において、電子は、ソース電極５７から電子走行層６３を通り、ｎ－型ＧａＮドリフト層５２を経てドレイン電極５８へと流れる。この電子の経路において、ｐ型ＧａＮ層５３は、ｎ－型ＧａＮドリフト層５２と、ｎ＋型キャップ層５４とに挟まれている。電子は、ｐ型ＧａＮ層５３を流れるわけではないが、ｐ型ＧａＮ層５３は、電子のバンドエネルギーを持ち上げ、かつ耐圧特性を向上するなどのバックゲート効果を発揮する。 In the GaN transistor 1-2, electrons flow from the source electrode 57 through the electron transit layer 63 to the drain electrode 58 through the n − -type GaN drift layer 52. In this electron path, the p-type GaN layer 53 is sandwiched between the n − -type GaN drift layer 52 and the n + -type cap layer 54. Although electrons do not flow through the p-type GaN layer 53, the p-type GaN layer 53 exhibits a back gate effect such as raising the band energy of electrons and improving the breakdown voltage characteristics.
　本実施の形態では、ソース電極５７の下に埋め込まれる形態でｐ型ＧａＮ層５３が配置され、さらに、ｐ型ＧａＮ層５３とソース電極５７とにオーミック接触する導電部５９が配置される。導電部５９は、ｎ＋型キャップ層５４を貫通してｐ型ＧａＮ層５３内に届くとともに、ｐ型ＧａＮ層５３とオーミック接触している。導電部５９によって、ｐ型ＧａＮ層５３とソース電極５７とは共通の電位を有する。ｐ型ＧａＮ層５３はたとえば接地電位に固定される。 In the present embodiment, the p-type GaN layer 53 is disposed so as to be buried under the source electrode 57, and a conductive portion 59 that is in ohmic contact with the p-type GaN layer 53 and the source electrode 57 is disposed. The conductive portion 59 passes through the n + -type cap layer 54 and reaches the p-type GaN layer 53 and is in ohmic contact with the p-type GaN layer 53. Due to the conductive portion 59, the p-type GaN layer 53 and the source electrode 57 have a common potential. The p-type GaN layer 53 is fixed at, for example, the ground potential.
　ｐ型ＧａＮ層５３は、上記したように、次の作用を発揮する：
（１）バンドの正方向へのシフトによるピンチオフ特性の向上；
（２）縦方向耐圧性能の向上；
（３）キンク（kink）現象の防止。 The p-type GaN layer 53 exhibits the following effects as described above:
(1) Improvement of pinch-off characteristics by shifting the band in the positive direction;
(2) Improvement of longitudinal pressure resistance performance;
(3) Prevention of the kink phenomenon.
　上記の（１）および（２）は、上記の導電部５９がなくても、上述のバックゲート効果により、その作用を得ることができる。しかし、ｐ型ＧａＮ層５３にオーミック接触する導電部５９が設けられることで、ドレイン電圧を高くした場合にチャネルからドレイン電極までの間において生成される正孔を外部に引き抜くことができ、（３）の作用を得ることができる。以下、（３）について詳細に説明する。 The above (1) and (2) can obtain the action by the above-mentioned back gate effect even without the conductive part 59. However, by providing the conductive portion 59 in ohmic contact with the p-type GaN layer 53, holes generated between the channel and the drain electrode can be extracted to the outside when the drain voltage is increased. ) Can be obtained. Hereinafter, (3) will be described in detail.
　導電部５９がない場合には、ｐ型ＧａＮ層５３が配置されていても、ドレイン電圧を高めたときにチャネルのドレイン側に高電界領域ができる。この場合、高エネルギーの電子によってアバランシェ破壊が起き、高濃度の正孔が発生する。ＧａＮ系半導体はワイドバンドギャップ半導体であるため、再結合時定数が長い。したがってＧａＮ系積層体５５、とくにｎ－型ＧａＮドリフト層５２に正孔が高濃度に蓄積されてゆく。その結果、ドレイン電流－ドレイン電圧の飽和領域においてドレイン電流の増大などの暴走を招く。ｐ型ＧａＮ層５３に導電部５９を設けることによって、アバランシェ破壊により正孔が多数形成されても、その正孔を、導電部５９を通じて外部に引き抜くことができる。これにより、キンク現象を防止することができる。 If the conductive portion 59 is not provided, even if the p-type GaN layer 53 is disposed, a high electric field region is formed on the drain side of the channel when the drain voltage is increased. In this case, avalanche breakdown occurs due to high-energy electrons, and high-concentration holes are generated. Since the GaN-based semiconductor is a wide band gap semiconductor, the recombination time constant is long. Accordingly, holes are accumulated in high concentration in the GaN-based stacked body 55, particularly the n − -type GaN drift layer 52. As a result, a runaway such as an increase in drain current occurs in the drain current-drain voltage saturation region. By providing the conductive portion 59 in the p-type GaN layer 53, even if a large number of holes are formed by avalanche breakdown, the holes can be extracted outside through the conductive portion 59. Thereby, the kink phenomenon can be prevented.
　導電部５９を設けることにより、ｐ型ＧａＮ層５３は上記（１）～（３）に示す作用を得ることができる。この結果、キンク現象、縦型耐圧等の制約を克服して、自由度を拡大して、開口部に形成される２ＤＥＧ（２次元電子ガス）を縦に通して大電流を操作することが可能となる。 By providing the conductive portion 59, the p-type GaN layer 53 can obtain the actions shown in (1) to (3) above. As a result, it is possible to overcome limitations such as the kink phenomenon and vertical pressure resistance, expand the degree of freedom, and operate a large current vertically through 2DEG (two-dimensional electron gas) formed in the opening. It becomes.
　図１２は、図１１に示すＧａＮトランジスタの平面図である。図１２を参照して、ＧａＮトランジスタ１－２は六角形の形状を有する。したがって、ＧａＮトランジスタ１－２を平面的に稠密に配置することができる。さらに、導電部５９およびソース電極５７は、環状六角形の形状を有する。導電部５９は、ソース電極５７に完全に覆われている。したがって、面積を増加させることなく、ｐ型ＧａＮ層５３をソース電極５７に電気的に接続できる。 FIG. 12 is a plan view of the GaN transistor shown in FIG. Referring to FIG. 12, GaN transistor 1-2 has a hexagonal shape. Therefore, the GaN transistors 1-2 can be densely arranged in a plane. Furthermore, the conductive portion 59 and the source electrode 57 have an annular hexagonal shape. The conductive portion 59 is completely covered with the source electrode 57. Therefore, the p-type GaN layer 53 can be electrically connected to the source electrode 57 without increasing the area.
　ｎ－型ＧａＮドリフト層５２の厚さは１μｍ～２５μｍとすることができる。ｎ－型ＧａＮドリフト層５２のキャリア濃度は、０．２×１０16ｃｍ-3～２０．０×１０16ｃｍ-3とすることができる。ｐ型ＧａＮ層５３の厚さは、０．１μｍ～１０μｍとすることができる。ｐ型ＧａＮ層５３のキャリア濃度は、０．５×１０16ｃｍ-3～５０×１０16ｃｍ-3とすることができる。ｐ型ＧａＮ層５３のバックゲート効果の機能を重視する場合には、キャリア濃度を、上記の値より高くして、たとえば１×１０17ｃｍ-3～１×１０19ｃｍ-3とすることができる。ｎ＋型キャップ層５４の厚さは、０．１μｍ～３μｍとすることができる。ｎ＋型キャップ層５４のキャリア濃度は、１．０×１０17ｃｍ-3～３０．０×１０17ｃｍ-3とすることができる。 The thickness of the n − -type GaN drift layer 52 can be 1 μm to 25 μm. The carrier concentration of the n − -type GaN drift layer 52 can be 0.2 × 10 16 cm −3 to 20.0 × 10 16 cm −3 . The thickness of the p-type GaN layer 53 can be 0.1 μm to 10 μm. The carrier concentration of the p-type GaN layer 53 can be set to 0.5 × 10 16 cm −3 to 50 × 10 16 cm −3 . When importance is attached to the function of the back gate effect of the p-type GaN layer 53, the carrier concentration is set higher than the above value, for example, 1 × 10 17 cm −3 to 1 × 10 19 cm −3. it can. The thickness of the n + -type cap layer 54 can be 0.1 μm to 3 μm. The carrier concentration of the n + -type cap layer 54 can be 1.0 × 10 17 cm −3 to 30.0 × 10 17 cm −3 .
　再成長層６２において、電子走行層６３の厚さは、５ｎｍ～１００ｎｍ程度とすることができる。電子供給層６４の厚さは、１ｎｍ～１００ｎｍ程度とすることができる。電子走行層６３の厚さが５ｎｍより薄いと、２ＤＥＧと電子供給層６４／電子走行層６３との界面が近接しすぎて２ＤＥＧの移動度を低下させる。電子走行層６３の厚さが１００ｎｍを超えると、ｐ型ＧａＮ層５３の効果が薄れ、ピンチオフ特性が劣化する。したがって電子走行層６３の厚さを、１００ｎｍ以下とするのが好ましい。 In the regrowth layer 62, the thickness of the electron transit layer 63 can be about 5 nm to 100 nm. The thickness of the electron supply layer 64 can be about 1 nm to 100 nm. If the thickness of the electron transit layer 63 is less than 5 nm, the interface between the 2DEG and the electron supply layer 64 / the electron transit layer 63 is too close to reduce the mobility of the 2DEG. When the thickness of the electron transit layer 63 exceeds 100 nm, the effect of the p-type GaN layer 53 is reduced and the pinch-off characteristics are deteriorated. Therefore, the thickness of the electron transit layer 63 is preferably 100 nm or less.
　このように、図１１および図１２に示したＳｉＣトランジスタ１－１は、ＧａＮ基板と、ＧａＮ基板の表面に形成された半導体層と、ＧａＮ基板の裏面に形成された電極とを含む。図１１および図１２に示した構成によれば、「半導体層」は、ＧａＮ系積層体５５（ｎ－型ＧａＮドリフト層５２、ｐ型ＧａＮ層５３、ｎ＋型キャップ層５４）である。 Thus, SiC transistor 1-1 shown in FIGS. 11 and 12 includes a GaN substrate, a semiconductor layer formed on the surface of the GaN substrate, and an electrode formed on the back surface of the GaN substrate. According to the configuration shown in FIGS. 11 and 12, the “semiconductor layer” is the GaN-based stacked body 55 (the n − -type GaN drift layer 52, the p-type GaN layer 53, and the n + -type cap layer 54).
　以上の説明したように、好ましくは、半導体スイッチ素子は、窒化ガリウムトランジスタである。窒化ガリウムトランジスタは、第１の主表面と、第１の主表面に対して反対側に位置する第２の主表面とを有する窒化ガリウム基板と、窒化ガリウム基板の第１の主表面に形成された窒化ガリウム層と、窒化ガリウム基板の第２の主表面に形成された電極とを備える。 As described above, preferably, the semiconductor switch element is a gallium nitride transistor. A gallium nitride transistor is formed on a gallium nitride substrate having a first main surface and a second main surface located opposite to the first main surface, and on the first main surface of the gallium nitride substrate. A gallium nitride layer and an electrode formed on the second main surface of the gallium nitride substrate.
　なお、上記のＧａＮトランジスタの構成は、日本国特許出願公開２０１１－８２３９７号公報および国際公開ＷＯ２０１１／０４３１１０パンフレットに開示されており、これらの文献の開示の全体は、参照による援用によって本明細書に取り入れられる。 The configuration of the above GaN transistor is disclosed in Japanese Patent Application Publication No. 2011-82397 and International Publication WO2011 / 043110, and the entire disclosure of these documents is incorporated herein by reference. Incorporated.
　以上説明したように、本実施の形態では、ＧａＮダイオードあるいはダイヤモンドダイオードがパワーモジュールに使用される。すなわち、好ましくは、ダイオードは、窒化ガリウムダイオードである。または、好ましくは、ダイオードは、ダイヤモンドダイオードである。これにより、電力変換回路の損失の低減、動作速度の高速化、高耐圧化、高温での動作安定性などを図ることができる。したがって、電力変換回路の性能をより一層高めることができる。 As described above, in this embodiment, a GaN diode or a diamond diode is used for the power module. That is, preferably, the diode is a gallium nitride diode. Or, preferably, the diode is a diamond diode. As a result, it is possible to reduce the loss of the power conversion circuit, increase the operation speed, increase the withstand voltage, and stabilize the operation at high temperatures. Therefore, the performance of the power conversion circuit can be further improved.
　さらに、本実施の形態では、ＧａＮトランジスタあるいはＳｉＣトランジスタがパワーモジュールに使用される。すなわち、本実施の形態では、（ＳｉＣトランジスタ、ＧａＮショットキーダイオード）、（ＳｉＣトランジスタ、ダイヤモンドショットキーダイオード）、（ＧａＮトランジスタ、ＧａＮショットキーダイオード）、（ＧａＮトランジスタ、ダイヤモンドショットキーダイオード）のいずれかの組み合わせがパワーモジュールに採用される。ＧａＮトランジスタおよびＳｉＣトランジスタのいずれも、Ｓｉトランジスタに比較して、損失の低減、動作速度の高速化、高耐圧化、高温での動作安定性などを図ることができる。したがって、電力変換回路の性能をより一層高めることができる。 Furthermore, in this embodiment, a GaN transistor or a SiC transistor is used for the power module. That is, in this embodiment, any one of (SiC transistor, GaN Schottky diode), (SiC transistor, diamond Schottky diode), (GaN transistor, GaN Schottky diode), (GaN transistor, diamond Schottky diode) The combination is adopted for the power module. Both the GaN transistor and the SiC transistor can reduce loss, increase the operation speed, increase the breakdown voltage, and operate at high temperature, as compared with the Si transistor. Therefore, the performance of the power conversion circuit can be further improved.
　なお、上記実施形態では、半導体スイッチ素子として、ＳｉＣトランジスタおよびＧａＮトランジスタを具体的に示したが、ＳｉＣトランジスタあるいはＧａＮトランジスタに代えてダイヤモンドトランジスタをパワーモジュールに適用してもよい。すなわち、好ましくは、半導体スイッチ素子は、ダイヤモンドトランジスタである。 In the above embodiment, the SiC transistor and the GaN transistor are specifically shown as the semiconductor switch elements. However, a diamond transistor may be applied to the power module instead of the SiC transistor or the GaN transistor. That is, preferably, the semiconductor switch element is a diamond transistor.
　さらに、上記実施形態では、ＳｉＣトランジスタおよびＧａＮトランジスタの構造例を示した。しかしＳｉＣトランジスタおよびＧａＮトランジスタの構造は上記のように限定されるものではない。 Furthermore, in the above embodiment, structural examples of the SiC transistor and the GaN transistor have been shown. However, the structures of the SiC transistor and the GaN transistor are not limited as described above.
　さらに、上記実施形態では、半導体スイッチ素子としてトランジスタを示したが、ＳｉＣ、ＧａＮあるいはダイヤモンドで形成された半導体スイッチ素子であれば、トランジスタに限定されず、本実施の形態に係るパワーモジュールに適用することができる。 Further, in the above embodiment, the transistor is shown as the semiconductor switching element. However, the semiconductor switching element is not limited to the transistor as long as it is a semiconductor switching element formed of SiC, GaN, or diamond, and is applied to the power module according to the present embodiment. be able to.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施の形態の説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
[規則91に基づく訂正 29.03.2012]　
　１，２，１Ａ，２Ａ，１Ｂ，２Ｂ　半導体スイッチ素子、１－１　ＳｉＣトランジスタ、１－２　ＧａＮトランジスタ、３，４，３Ａ，４Ａ，３Ｂ，４Ｂ　ダイオード、３－１，３－２　ショットキーバリアダイオード、５，６，５Ａ，５Ｂ，６，７，７Ａ，７Ｂ　端子、８　直流電源、９　誘導性要素、９Ａ　単相負荷、９Ｂ　三相負荷、１０，１０Ａ～１０Ｃ　ユニット、２２　ＧａＮ自立基板、２２ａ　表面（ＧａＮ自立基板）、２２ｂ　裏面（ＧａＮ自立基板）、２３　エピタキシャル層、２３ａ　表面（ＧａＮエピタキシャル層）、２４　絶縁層、２４ａ　端面（絶縁層）、２５，２６　電極、３０　ダイヤモンド基板、３１　第１の金属層、３２　第２の金属層、３５　第１のｐ型ダイヤモンド層、３６　第２のｐ型ダイヤモンド層、３７　ショットキー電極、３８　オーミック電極、４０　基板（ＳｉＣ）、４１　バッファ層、４２　耐圧保持層、４３　ｐ領域、４４　ｎ＋領域、４５　ｐ＋領域、４６　酸化膜、４７ａ，５７　ソース電極、４７ｂ　上部ソース電極、４８，５６　ゲート電極、４９，５８　ドレイン電極、５１　ＧａＮ基板、５２　ｎ－型ＧａＮドリフト層、５３　ｐ型ＧａＮ層、５４　ｎ＋型キャップ層、５５　ＧａＮ系積層体、５９　導電部、６１　開口部、６２　再成長層、６３　ｉＧａＮ電子走行層、６４　ＡｌＧａＮ電子供給層、１０１～１０３　パワーモジュール。 [Correction 29.03.2012 under Rule 91]
1, 2, 1A, 2A, 1B, 2B Semiconductor switch element, 1-1 SiC transistor, 1-2 GaN transistor, 3,4, 3A, 4A, 3B, 4B diode, 3-1, 3-2 Schottky barrier Diode, 5, 6, 5A, 5B, 6, 7, 7A, 7B terminal, 8 DC power supply, 9 inductive element, 9A single-phase load, 9B three-phase load, 10, 10A-10C unit, 22 GaN free-standing substrate, 22a surface (GaN free-standing substrate), 22b back surface (GaN free-standing substrate), 23 epitaxial layer, 23a surface (GaN epitaxial layer), 24 insulating layer, 24a end surface (insulating layer), 25 and 26 electrodes, 30 diamond substrate, 31st 1 metal layer, 32 second metal layer, 35 first p-type diamond layer, 36 second p-type diamond layer, 37 Schottky electrode, 38 Ohmic electrode, 40 substrate (SiC), 41 buffer layer, 42 breakdown voltage holding layer, 43 p region, 44 n + region, 45 p + region, 46 oxide film, 47a, 57 source electrode, 47b upper source electrode, 48, 56 Gate electrode, 49, 58 Drain electrode, 51 GaN substrate, 52 n − type GaN drift layer, 53 p type GaN layer, 54 n + type cap layer, 55 GaN-based laminate, 59 conductive portion, 61 opening, 62 re Growth layer, 63 iGaN electron transit layer, 64 AlGaN electron supply layer, 101-103 power module.

Claims (3)

  1. 　半導体スイッチ素子（１，２）と、
    　前記半導体スイッチ素子がオン状態である時に逆バイアスされ、前記半導体スイッチ素子がオフ状態である時に導通するように配置されたダイオード（３，４）とを備え、
    　前記ダイオードは、窒化ガリウムダイオードおよびダイヤモンドダイオードのいずれかである、パワーモジュール。     A semiconductor switch element (1, 2);
    A diode (3, 4) arranged to be reverse biased when the semiconductor switch element is in an on state and to conduct when the semiconductor switch element is in an off state;
    The power module, wherein the diode is one of a gallium nitride diode and a diamond diode.
  2. 　前記半導体スイッチ素子（１，２）は、炭化珪素トランジスタ、窒化ガリウムトランジスタ、およびダイヤモンドトランジスタのいずれかである、請求項１に記載のパワーモジュール。 The power module according to claim 1, wherein the semiconductor switch element (1, 2) is any one of a silicon carbide transistor, a gallium nitride transistor, and a diamond transistor.
  3. 　半導体スイッチ素子（１，２）と、
    　前記半導体スイッチ素子（１，２）がオン状態である時に逆バイアスされ、前記半導体スイッチ素子（１，２）がオフ状態である時に導通するように配置されたダイオード（３，４）とを備え、
    　前記ダイオード（３，４）は、窒化ガリウムダイオードおよびダイヤモンドダイオードのいずれかである、電力変換回路。     A semiconductor switch element (1, 2);
    A diode (3, 4) disposed so as to be reverse-biased when the semiconductor switch element (1, 2) is in an on state and to conduct when the semiconductor switch element (1, 2) is in an off state. ,
    The diode (3, 4) is a power conversion circuit which is one of a gallium nitride diode and a diamond diode.
PCT/JP2012/051622 2011-06-14 2012-01-26 Power module and power conversion circuit WO2012172825A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3568908A4 (en) * 2017-01-13 2020-06-03 General Electric Company Rotating switching strategy for power converters

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019097813A1 (en) * 2017-11-16 2019-05-23 パナソニック株式会社 Nitride semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008041685A1 (en) * 2006-10-02 2008-04-10 Hitachi, Ltd. Gate drive circuit
WO2008149523A1 (en) * 2007-05-29 2008-12-11 Panasonic Corporation Power converter
JP2010252568A (en) * 2009-04-17 2010-11-04 Hitachi Ltd Drive circuit of semiconductor element
WO2010150549A1 (en) * 2009-06-26 2010-12-29 株式会社 東芝 Power conversion device
JP2011010404A (en) * 2009-06-24 2011-01-13 Hitachi Ltd Power converter, and electric motor drive device and transportation system employing the same
WO2011052214A1 (en) * 2009-10-30 2011-05-05 パナソニック株式会社 Electrical power converter and induction heating device using same, and electrically driven device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008041685A1 (en) * 2006-10-02 2008-04-10 Hitachi, Ltd. Gate drive circuit
WO2008149523A1 (en) * 2007-05-29 2008-12-11 Panasonic Corporation Power converter
JP2010252568A (en) * 2009-04-17 2010-11-04 Hitachi Ltd Drive circuit of semiconductor element
JP2011010404A (en) * 2009-06-24 2011-01-13 Hitachi Ltd Power converter, and electric motor drive device and transportation system employing the same
WO2010150549A1 (en) * 2009-06-26 2010-12-29 株式会社 東芝 Power conversion device
WO2011052214A1 (en) * 2009-10-30 2011-05-05 パナソニック株式会社 Electrical power converter and induction heating device using same, and electrically driven device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3568908A4 (en) * 2017-01-13 2020-06-03 General Electric Company Rotating switching strategy for power converters

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