WO2012167430A1

WO2012167430A1 - Receiver and methods for providing channel stability

Info

Publication number: WO2012167430A1
Application number: PCT/CN2011/075495
Authority: WO
Inventors: Ligang Zhang; Liang Wu; Jun Rong
Original assignee: Silicon Laboratories, Inc.
Priority date: 2011-06-09
Filing date: 2011-06-09
Publication date: 2012-12-13
Also published as: CN205356311U

Abstract

A receiver includes an analog-to-digital converter (ADC) including an input configurable to digitize a voltage from a potentiometer and including an output for providing an ADC output signal. The receiver further includes a controller coupled to the output of the ADC and adapted to determine a selected channel based on multiple consecutive samples of the ADC output signal.

Description

Receiver and Methods for Providing Channel Stability

FIELD

[0001] The present disclosure is generally related to receiver circuits, and more particularly to receiver circuits and methods for channel stability.

BACKGROUND

[0002] When using an analog-to-digital converter (ADC) to sample a voltage representing a position of an analog tuning wheel or potentiometer, the output of the ADC can be heavily influenced by its working environment. For example, a radio's audio amplifier can induce a large amount of supply ripple, which can be a source of interference that can interfere with the precision of the sampling performed by the ADC. When the supply voltage drops, the precision of the ADC can be adversely affected, in part, because the interference rejection capability of the ADC usually degrades as its supply decreases. Under the influence of interference, ADC samples may not be stable and can sometimes vary beyond a range that is defined for one radio channel. Such variations can produce channel chattering and provide a bad user experience.

SUMMARY

[0003] In an embodiment, a receiver includes an analog-to-digital converter (ADC) including an input configurable to digitize a voltage from a potentiometer and including an output for providing an ADC output signal. The receiver further includes a controller coupled to the output of the ADC and adapted to determine a selected channel based on multiple consecutive samples of the ADC output signal.

[0004] In another embodiment, a method includes sampling a voltage representing a position of a potentiometer using an analog-to-digital converter (ADC) to produce an ADC output signal. The position is mapped to a selected channel. The method further includes capturing multiple samples of the ADC output signal and differentiating between noise in the ADC output signal and a change to the position of the potentiometer in response to capturing the multiple samples.

[0005] In still another embodiment, a receiver includes an input for receiving a signal corresponding to a position of a potentiometer and an analog-to-digital converter (ADC) including an input coupled to the channel tuning input and an output. The ADC is configured to digitize the signal to produce an ADC output signal. The receiver further includes a controller having an input coupled to the output of the ADC and having at least one output. The controller determines a radio frequency in response to the signal. The controller receives multiple samples of the ADC output signal over time and differentiates between noise and a change in the signal from the input based on the multiple samples.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a block diagram of an embodiment of a system including a receiver circuit for providing channel stability.

[0007] FIG. 2 is a partial block diagram and partial logic diagram of an embodiment of a counter circuit that can be used in connection with the receiver circuit of FIG. 1 for providing channel stability.

[0008] FIG. 3 is a diagram of a representative example of a mapping of a potentiometer position to a voltage range that can be used to introduce channel range hysteresis for providing channel stability.

[0009] FIG. 4 is a block diagram of a second embodiment of a system including a receiver circuit configured to provide channel stability.

[0010] FIG. 5 is a flow diagram of an embodiment of a method for providing channel stability by determining a selected channel and/or channel change based on multiple samples of an analog-to-digital output signal.

[0011] FIG. 6 is a flow diagram of an embodiment of a method for providing channel stability by incrementing/decrementing a counter based on a value of an ADC output signal relative to a hysteresis range.

[0012] FIG.7 is a flow diagram of another embodiment of a method for providing channel stability using a counter to determine whether to automatically adjust a volume.

[0013] In the following description, the use of the same reference numerals in different drawings indicates similar or identical items.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS [0014] Embodiments of a receiver include an on-chip analog-to-digital converter (ADC) to digitize a voltage from a potentiometer to determine a tuner channel. In a particular example, the ADC digitizes the voltage from a center tap of the potentiometer. Under adverse working conditions, things like a large audio amplifier output can cause large voltage ripples at the supply, lowering the supply voltage and reducing the power supply rejection ratio (PSRR) of the ADC and other circuitry. Further, direct coupling of the voltage ripple/switching noise on the sensed voltage can reduce sensitivity. Additionally, the ADC output can experience a temporary glitch, representing a false tuning event. A deglitch or an averaging process can be used to avoid such false positives, however, such processes may sacrifice performance in terms of speed, impact the analog tuning radio's feel, and adversely affect the user's experience. Embodiments of receivers and methods are described below that use a multi-decision algorithm and asymmetric averaging to remove such glitches without sacrificing the tuning feel.

[0015] In a particular embodiment, a receiver is disclosed that provides channel stability, even under the influence of interference and power supply ripple. The receiver may be configured to receive digital samples of a voltage representing a position of a tuning dial (such as a potentiometer) and to resolve fluctuations in the digital samples by averaging multiple samples, by introducing channel range hysteresis, by selectively incrementing and decrementing a counter based on a direction of the fluctuation relative to the channel range hysteresis, by automatically adjusting a volume setting, or any combination thereof.

[0016] FIG. 1 is a block diagram of an embodiment of a system 100 including a receiver 101 for providing channel stability. Receiver 101 includes an analog-to- digital converter (ADC) 102 including an input connected to an input terminal 108 and an output connected to a controller 104 for providing an ADC output signal. Receiver 101 further includes a counter circuit 106 including an input connected to the output of ADC 102 and an output connected to controller 104. Input terminal 108 is connected to potentiometer 110.

[0017] In an example, potentiometer 110 is associated with a radio tuning dial, such as a dial for tuning to a particular AM radio station. ADC 102 captures a voltage representing a position of the potentiometer 110 and provides the voltage as an ADC output signal to controller 104. Counter circuit 106 is configured to count a number of samples of the ADC output signal that fall outside of a hysteresis range around a current selected radio station. In an embodiment, counter circuit 106 may be implemented within controller 104 and/or may be implemented as firmware executable by the controller 104. In the illustrated example, counter circuit 106 includes an input connected to controller 104 for receiving threshold settings. Controller 104 generates a tuner control signal in response to the ADC output signal and a count from counter circuit 106.

[0018] In a particular example, the controller 104 averages multiple consecutive samples, such as eight samples, to represent one analog-to-digital converter (ADC) output. In another particular example, the controller 104 introduces channel range hysteresis by mapping a range of voltages to a position of the potentiometer, providing a voltage window introducing a channel range hysteresis such that no movement of the potentiometer position is assumed when fluctuations in the voltage that are within the voltage window. In this instance, controller 104 may program a first voltage threshold and a second voltage threshold within counter circuit 106 to define voltage window, providing the channel range hysteresis. If the ADC output signal has a voltage level that falls outside of the voltage window, then controller 104 can generate a tuner control signal to update the current tuned frequency and a corresponding potentiometer voltage window can be defined within counter circuit 106.

[0019] In still another example, the controller 104 captures a first sample and at least one second sample of the ADC output. The counter circuit 106 is incremented when the first sample and the at least one second sample fall outside of the voltage window for the current potentiometer position in the same direction. The counter circuit 106 is decremented when the first sample falls outside of the voltage window in a first direction and the second sample falls within the voltage window or falls outside of the voltage window in a second direction that is opposite to the first directon. In some instances, the counter circuit 106 increments the count by an increment of one and decrements the count by a weighted decrement of five. When the count of counter circuit 106 exceeds a pre-determined threshold, controller 104 determines that the potentiometer position has changed and generates tuner control signal to tunes to a new channel. [0020] In yet another example, the receiver 101 may experience extremely low frequency interference conditions, which can cause instability due to supply ripple induced by an associated audio amplifier's large current draw due to high volume. In this instance, the controller 104 can configure counter circuit 106 to increment the counter by one if an ADC sample falls outside of the voltage window and decrement the counter by one if two consecutive samples fall within the voltage window or fall outside of the voltage window in a different direction from the previous sample. When the count of counter circuit 106 exceeds a relatively high threshold, controller 104 generates a volume control signal to automatically adjust the volume of the audio output signal by pre-defined increment (such as ldB).

[0021] While the above-examples are provided as separate examples, it should be appreciated that averaging, channel range hysteresis, and various count-based can be implemented separately or in combination, depending on the specific implementation. An example of a counter circuit 106 is described below with respect to FIG. 2.

[0022] FIG. 2 is a partial block diagram and partial logic diagram of an embodiment 200 of a counter circuit 106 that can be used in connection with the receiver 101 of FIG. 1 for providing channel stability. Counter circuit 106 includes a high threshold comparator 202 including an input for receiving the ADC output and an output connected to an input of a counter logic circuit 205. Counter circuit 106 further includes a low threshold comparator 204 including an input for receiving the ADC output and an output connected to a second input of counter logic circuit 205. Counter logic circuit 205 includes an increment logic circuit 206 having first and second inputs for receiving the outputs of the high and low threshold comparators 202 and 204 and includes a decrement logic circuit 208 having first and second inputs for receiving outputs of the high and low threshold comparators 202 and 204. Increment logic circuit 206 includes an output connected to an increment input (INC) of a counter 210. Decrement logic circuit 208 includes an output connected to a decrement input (DEC) of counter 210, which includes an output for providing a counter output signal.

[0023] In an example, controller 104 (in FIG. 1) can configure threshold setting for high and low threshold comparators 202 and 204 of counter circuit 106. In an example, the position of the potentiometer 110 (as determined from a voltage at a center tap of the potentiometer) is mapped to a selected channel. Controller 104 provides associated threshold settings for high and low threshold comparators 202 and 204, defining a channel range hysteresis. Further, counter logic circuit 205 can be configured by controls signals from controller 104 to implement multi-decision logic, such as described above, to increment the counter 210 under some conditions and to decrement the counter 210 by one or more units under other conditions.

[0024] FIG. 3 is a diagram 300 of a representative example of a mapping of a potentiometer position 322, 324, 326, 328, 330, and 332 to a voltage range 302, 304, 306, 308, 310, and so on, that can be used to introduce channel range hysteresis for providing channel stability. Diagram 300 includes channel ranges 312, 314, 316, and 318. As previously discussed, the ADC sample can have uncertainty in the presence of noise and interference. If a position of potentiometer 110 sits at the boundary of two regions defining two adjacent channels (such as position 324 at the boundary of adjacent channels 312 and 314), the ADC output can chatter between the two channels. However, by introducing a channel range hysteresis (such as a voltage range 302 or 304) that extends beyond the channel boundary, the channel range hysteresis can help minimize the impact of small jittering due to noise and interference.

[0025] Referring to FIG. 3, if the initial tuned frequency corresponds to a channel 315, then the channel hysteresis can be set as voltage range 306. As long as the detected potentiometer position (such as positions 326 and 328) is within the voltage range 306, controller 104 detects no movement of the potentiometer 110. If the next sample falls outside of voltage range 306, then controller 104 updates the current tuned frequency based on the change to the position of the potentiometer 110, and the voltage range that provides the channel range hysteresis can be updated accordingly. For example, if the next sample lands in one of the adjacent channels 314 or 316, then the controller 104 can tune to new frequency 314 or 316 with an associated voltage range of 304 or 308, respectively. If the next sample lands in range channel 312 or 318, then the controller 104 can tune to a new frequency with an associated voltage range 302 or 310, respectively.

[0026] In an example, if a first sample falls outside of the voltage range 306 and into voltage range 308 in a first direction, a next sample may fall outside of the voltage range 306 into voltage range 308 or 310 in the same direction, may fall within voltage range 306, or may fall into voltage range 304 or 304 in a second direction that is opposite to the first direction. In the latter instance where adjacent ADC samples fall on opposite sides of the voltage range 306, the wide variability of the ADC output signal may be more indicative of noise than a change in a position of potentiometer 110.

[0027] By providing a voltage range that extends across channel boundaries, controller 104 can selectively adjust the tuner to a new channel frequency when the position of the potentiometer 110 is changed while disregarding jitter or chatter in the ADC output that may be caused by environmental noise and/or supply ripple. Such noise may cause adjacent ADC samples to cross channel boundaries and/or to oscillate between the voltage range and a range associated with an adjacent channel. However, by comparing sequential ADC samples, such oscillations can be readily detected and the high and low thresholds can be adjusted so that jitter/chatter/oscillations do not cause a channel change.

[0028] FIG. 4 is a block diagram of a second embodiment of a system 400 including a receiver 101 configured to provide channel stability. System 400 includes a channel filter 406 configured to communicatively couple to a signal source (such as an antenna) for receiving a radio frequency signal. Channel filter 406 may include off- chip and on-chip components. Channel filter 406 includes an output connected to an input of a low-noise amplifier (LNA) 408, which has a control input connected to a processor 418 (or a micro control unit (MCU)), and an output connected to an input of a mixer 410. Mixer 410 includes an oscillator input connected to an output of a local oscillator 420, which has a control input connected to processor 418. Mixer 410 further includes an output connected to an input of a programmable gain amplifier (PGA) / Filter block 412, which may include PGAs and filters for in-phase and quadrature signal paths (not shown). PGA/Filter block 412 includes at least one control input connected to an output of processor 418 and at least one output connected to a corresponding number of inputs of analog-to-digital converter (ADC) block 414, which can include multiple ADCs. ADC block 414 includes at least one output connected to a corresponding number of inputs of a digital signal processor (DSP) 416, which has an output connected to an input of processor 418. Processor 418 further includes an input connected to an output of ADC 102, which has an input connected to a potentiometer, such as potentiometer 110 in FIG. 1. [0029] Receiver 101 further includes a memory 422 connected to processor 418. Memory 422 stores instructions that, when executed, cause processor 418 to perform various functions. In particular, memory 422 stores channel hysteresis instructions 424 that are executable by processor 418 to configure and/or adjust the voltage range. Memory 422 stores ADC sample averaging instructions 428 that are executable by processor 418 to average a number of ADC output values and to make channel change decisions based on the average of the ADC output values. Further, memory 422 stores the counter 434 and count adjustment logic 436, which can be used to count the number of times that the ADC output falls outside of the voltage range. Memory 422 further includes automatic volume adjustment instructions 430 that, when executed, cause processor 418 to adjust the gain or volume of the output stage, such as when the value of count 434 exceeds a threshold. Memory further includes multi-decision instructions 432 that, when executed, cause processor 418 to selectively adjust the tuned channel based on a count of the ADC output from ADC 102 that is related to the potentiometer input.

[0030] FIG. 5 is a flow diagram of an embodiment of a method 500 for providing channel stability by determining a selected channel and/or channel change based on multiple samples of an analog-to-digital output signal. At 502, a voltage from a center tap of a potentiometer is digitized using an analog-to-digital converter (ADC) to produce an ADC output signal. Advancing to 504, multiple samples of the ADC output signal are captured. In an example, the multiple samples of the ADC output signal may be captured by a counter circuit or by a processor, such as processor 418 executing count adjustment logic instructions 436 to maintain one or more counts 434.

[0031] Continuing to 506, a selected channel is determined based on the multiple samples of the ADC output signal. In an example, processor418 determines a selected channel based on an average of the multiple samples. In another example, processor 418 determines the selected channel based on a count of the number of times that the ADC output signal level falls outside of a voltage range (channel range hysteresis) and based on the direction in which the ADC output signal falls outside of the range.

[0032] In general, by capturing consecutive measurements of the ADC output signal and averaging the two measurements to indicate the channel it should tune to, correlated noise is removed from the tuning decision. Unfortunately, for a noise frequency that is not too much lower than the ADC sampling frequency, the correlated sampling between an input voltage and a reference voltage for the ADC may stop working. Even if the receiver can sample the two voltages at the exact same time, a noise transfer function of the two voltages will not be exactly the same, resulting in a measured ratio that is still impacted by noise sources. The noise traveling paths of the two voltages can also be dramatically different, resulting in totally unpredictable ratios. Additionally, the audio induced ripple can be in many waveform shapes, and simple averaging may produce channel instability. However, by averaging across multiple samples, such as by counting an average of multiple samples (such as eight (8) samples) to represent one ADC output, an average of such outputs can help to filter out the spurs and high frequency interferences.

[0033] While the above-described method uses averaging, it is also possible to employ multi-decision branching techniques to reduce undesired channel change detections in a noisy environment. An example of a multi-decision method of determining when to tune to a new channel is described below with respect to FIG. 6.

[0034] FIG. 6 is a flow diagram of an embodiment of a method 600 for providing channel stability by incrementing/decrementing a counter based on a value of an ADC output signal relative to a hysteresis range. At 602, an ADC sample is received. The ADC sample may be a digitized voltage corresponding to a voltage on a center tap of a potentiometer. Advancing to 604, if the ADC sample not outside of a hysteresis range (a voltage range), no channel change is detected, and the method 600 advances to 608 and the count is reduced by a weighted decrement value (such as five), stopping at zero if the count is less than five and the method 600 returns to 602 to receive another ADC sample. If, at 604, the ADC sample is outside of the hysteresis range, the method 600 proceeds to 606. At 606, if the sample does not fall outside of the hysteresis range in the same direction as the previous sample, the method 600 proceeds to 608 and the count is reduced by a weighted decrement value (such as five), stopping at zero if the count is less than five. The method 600 then returns to 602 to receive another ADC sample. The count adjustments may be performed by a counter circuit including counter logic, by a processor, such as processor 418, or by a combination thereof.

[0035] At 606, if the sample falls outside of the hysteresis range in the same direction as the previous sample, the method 600 advances to 610. At 610, if the count plus one is greater than ten, the processor 418 determines that a new channel is selected. The processor 418 can detect a change in the ADC output signal corresponding to a change in the channel frequency. Continuing to 614, processor generates a control signal to tune to a new channel.

[0036] At 610, if the count plus one is less than or equal to ten, the method 600 advances to 616 and the counter is incremented and the direction of the sample away from the current position is recorded. The method 600 then returns to 602 to receive another ADC sample.

[0037] In an example, the method 600 can be performed iteratively and continuously. The weighted decrement (described in block 608) may vary according to the implementation. In a particular embodiment, the increment may be a unit of one while the decrement may be a unit of five. In block 610, the threshold of ten is one example, but other thresholds may also be used, depending on the implementation. For particularly noisy environments, the count may be increased either by a user or automatically by the processor to provide enhanced channel stability.

[0038] The method of FIG. 6 describes one possible implementation that uses channel range hysteresis (such as high and low voltage thresholds defining a voltage window or range) to enhance channel stability. In particular, introduction of channel range hysteresis can help reduce the impact of small jittering due to noise and interference. In an example, as long as the potentiometer position is within a channel hysteresis range of the currently selected channel, the processor ignores small variations in the ADC output signal that might otherwise represent a changing potentiometer position. However, if the ADC output signal falls outside of the channel hysteresis range, processor detects a channel change and updates the currently tuned frequency and/or potentiometer position range accordingly.

[0039] However, in the presence of supply ripple and/or significant environmental noise, the ADC sample uncertainty can be random and unstable, such that the uncertainty can fall within one hysteresis range or extend beyond the range. This is especially true when the uncertainty is induced by audio amplifier supply ripples. However, by utilizing a multi-decision algorithm, the processor can differentiate noise from a channel change. In a particular example, the processor can assign a weight to each ADC output that falls outside of the channel hysteresis range, and adjust the counter accordingly. By using a counter to count the event together with the weight, processor can differentiate a real move the potentiometer from chattering and jittering due to noise.

[0040] In an example, when the ADC output signal falls outside of the channel hysteresis range, the processor checks to see if the counter result is 0, and, if so, adds 1 for the next sample that goes beyond the hysteresis range and records the direction of the sample away from the current position. If another sample falls outside of the hysteresis range in the same direction, the counter is incremented by one again. If the next sample falls within the hysteresis range or if it falls out of the hysteresis range in the other direction, the processor controls the counter to subtract an increment, which may be weighted. In a particular instance, if the next sample is out of the range in the opposite direction, the processor decrements the counter by an increment of five, but stops if the counter reaches zero. With this configuration, if the counter reaches a threshold, such as 10, the processor determines that the potentiometer has moved its position and tunes to a new channel.

[0041] In some low-frequency conditions, such as that caused by supply ripple induced by the audio amplifier's large current draw, some channel instability may still be present even with the above mentioned multi-decision algorithm. In such instances, it may be desirable to reduce the volume (for example by executing automatic volume adjustment instructions 430), which reduces the supply ripple, enhancing the channel stability. An example of a method of providing a volume adjustment to enhance channel stability is described below with respect to FIG. 7.

[0042] FIG. 7 is a flow diagram of another embodiment of a method 700 for providing channel stability using a counter to determine whether to automatically adjust a volume. At 702, an ADC sample is received. Advancing to 704, if the sample does not fall outside of the hysteresis range, the method 700 proceeds to 706, and if the previous sample is not within the hysteresis range, the method 700 returns to 702 to receive another sample.

[0043] At 706, if the previous sample was within the hysteresis range, the method 700 proceeds to 708, and the counter is decremented. The method 700 then returns to 702 to receive another sample. [0044] Returning to 704, if the sample falls outside of the hysteresis range, the method 700 proceeds to 710 and the counter is incremented. Advancing to 712, if a new channel is determined based on the counter value (blocks 610 and 612 in FIG. 6), the processor controls the receiver to tune to the new channel, and the method 700 continues to 714 and the count is cleared. The method 700 then returns to 702 to receive another ADC sample.

[0045] At 712, if a new channel is not determined, the method 700 advances to 716 and if the counter equals or exceeds a second threshold (such as forty-five (45)), the method 700 continues to 718 and the processor reduces the volume by a predetermined increment (such as ldB). The method 700 then returns to 714 and clears the counter before returning to 702 to receive a next ADC sample. Otherwise, at 716, if the counter is less than the second threshold, the method returns to 702 to receive another ADC sample.

[0046] In digital tuners having integrated digital volume control, the processor can be configured to adjust the volume under such conditions. In an example, if the ADC sample falls outside of the current hysteresis range, the processor increments the counter by one. If consecutive samples fall within the hysteresis range, the counter is decremented by one. When a new frequency is determined and the processor controls the tuner to tune to a new frequency, the counter is cleared. Otherwise, if the counter reaches a count of 45, the processor adjusts the volume by an incremental amount, such as ldB by controlling the digital volume control and the counter is then reset.

[0047] In an example, a method includes sampling a voltage representing a position of a potentiometer using an analog-to-digital converter (ADC) to produce an ADC output signal, the position mapped to a selected channel. The method further includes capturing multiple samples of the ADC output signal and differentiating between noise in the ADC output signal and a change to the position of the potentiometer in response to capturing the multiple samples. In a particular example, differentiating between noise in the ADC output signal and the change to the position allows the controller of a receiver circuit to provide enhanced channel stability even when the ADC output signal is time- varying due to power supply ripple or other noise.

[0048] In one embodiment, differentiating between the noise and the change includes averaging a pre-determined number of the multiple samples to produce an average sample representing a single ADC output, determining whether the average sample falls within a frequency range around the selected channel, and detecting a new position of the potentiometer when the average sample falls outside of the frequency range. In another embodiment, differentiating between the noise and the change includes selecting a first threshold voltage that is greater than the voltage representing the position of the potentiometer, selecting a second threshold voltage that is less than the voltage representing the position of the potentiometer, and comparing the multiple samples to the first and second threshold voltages to determine when one of the multiple samples falls outside of a voltage range defined by the first and second threshold voltages.

[0049] In a particular aspect, the method can include incrementing a counter when a first sample of the multiple samples falls outside of the voltage range in a first direction, incrementing the counter when a second sample of the multiple samples falls outside of the voltage range in the first direction, and decrementing the counter when the second sample of the multiple samples falls within the voltage range or falls outside of the voltage range in a second direction that is opposite to the first direction. In one instance, decrementing the counter includes decreasing a count of the counter by a decrement of five. In another instance, the decrement can be one, two, or some other value. In a particular embodiment, the decrement is weighted. For example, if the sample of the ADC output signal falls outside of the voltage range, not into a voltage range corresponding to the adjacent channel but into some other channel, the increment or decrement can be weighted accordingly to either increase the count by an increment of at least one or decrease the count by a decrement of at least one.

[0050] In conjunction with the systems, receiver circuits, and methods described above, a controller is configurable to receive an ADC output signal corresponding to a position of a potentiometer and to differentiate between noise and the position change to selectively control a channel selection of a receiver circuit. In a particular example, the volume may be adjusted to reduce noise due to power supply ripple caused by the audio amplifier at the output. In a particular example, a receiver includes an analog- to-digital converter (ADC) including an input configurable to digitize a voltage at a center tap of a potentiometer and including an output for providing an ADC output signal. The receiver further includes a controller coupled to the output of the ADC and adapted to determine a selected channel based on multiple consecutive samples of the ADC output signal.

[0051] Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. A receiver comprises:

an analog-to-digital converter (ADC) including an input configurable to digitize a voltage from a potentiometer and including an output for providing an ADC output signal; and

a controller coupled to the output of the ADC and adapted to determine a selected channel based on multiple consecutive samples of the ADC output signal.

2. The receiver of claim 1 , wherein:

the controller averages a number of the multiple consecutive samples to represent an

ADC output sample; and

the controller selectively adjusts the selected channel when the ADC output sample falls outside of a range associated with the selected channel.

3. The receiver of claim I, wherein:

the ADC output signal corresponds to a position of the potentiometer; and

the position is mapped to one of a plurality of channels.

4. The receiver of claim 3, wherein the controller selects a voltage range corresponding to the ADC output signal to provide a channel range hysteresis for resolving uncertainty in the position of the potentiometer caused by fluctuations in the ADC output signal.

5. The receiver of claim 4, wherein the channel range hysteresis comprises:

a first threshold voltage;

a second threshold voltage; and

wherein the first and second threshold voltages define a voltage range.

6. The receiver of claim 5, further comprising a counter including an input coupled to the output of the ADC and an output coupled to the controller, wherein the counter: increments a count when the ADC output signal falls outside of the voltage range; and decrements the count when the ADC output signal falls within the range.

7. The receiver of claim 6, wherein the controller selectively adjusts a tuned frequency in response to the count exceeding a threshold.

8. The receiver of claim 5, further comprising a counter including an input coupled to the output of the ADC and an output coupled to the controller, wherein the counter: increments the count when the ADC output signal falls outside of the voltage range in a direction that corresponds to that of a previous sample of the multiple consecutive samples.

9. The receiver of claim 8, wherein the counter decrements the count when the ADC output signal falls outside of the voltage range and a direction opposite to that of a previous sample of the multiple consecutive samples.

10. A method comprising:

sampling a voltage representing a position of a potentiometer using an analog-to-digital converter (ADC) to produce an ADC output signal, the position mapped to a selected channel;

capturing multiple samples of the ADC output signal; and

differentiating between noise in the ADC output signal and a change to the position of the potentiometer in response to capturing the multiple samples.

11. The method of claim 10, wherein differentiating between the noise and the change comprises:

averaging a pre- determined number of the multiple samples to produce an average sample representing an ADC output;

determining whether the average sample falls within a frequency range around the selected channel; and detecting a new position of the potentiometer when the average sample falls outside of the frequency range.

12. The method of claim 10, wherein differentiating between the noise and the change comprises:

selecting a first threshold voltage that is greater than the voltage representing the position of the potentiometer;

selecting a second threshold voltage that is less than the voltage representing the position of the potentiometer; and

comparing the multiple samples to the first and second threshold voltages to determine when one of the multiple samples falls outside of a voltage range defined by the first and second threshold voltages.

13. The method of claim 12, further comprising:

incrementing a counter when a first sample of the multiple samples falls outside of the voltage range in a first direction;

incrementing the counter when a second sample of the multiple samples falls outside of the voltage range in the first direction; and

decrementing the counter when the second sample of the multiple samples falls within the voltage range or falls outside of the voltage range in a second direction that is opposite to the first direction.

14. The method of claim 13, wherein decrementing the counter comprises decreasing a count of the counter by an increment of five.

15. A receiver comprising:

an input for receiving a signal corresponding to a position of a potentiometer;

an analog-to-digital converter (ADC) including an input coupled to the channel tuning input and an output, the ADC configured to digitize the signal to produce an ADC output signal; and

a controller including an input coupled to the output of the ADC and including at least one output, the controller to determine a radio frequency in response to the signal, the controller to receive multiple samples of the ADC output signal over time and to differentiate between noise and a change in the signal from the input based on the multiple samples.

16. The receiver of claim 15, wherein the controller is configured to:

average a number of the multiple samples to produce an average value,

compare the average value to a threshold to detect the change in the signal; and generate a tuner control signal when the average value exceeds the threshold.

17. The receiver of claim 15, wherein the controller compares each of the multiple samples to a first threshold and a second threshold defining a channel range.

18. The receiver of claim 17, wherein the controller generates a tuner control signal to adjust the radio frequency when a sample of the multiple samples falls outside of the channel range.

19. The receiver of claim 17, further comprising a counter configured to increment a count when a first sample of the multiple samples falls outside of the channel range in a first direction, to increment the count again when a next sample of the multiple samples falls outside of the channel range in the first direction, and to decrement the count when the next sample of the multiple samples falls within the channel range or falls outside of the channel range in a second direction opposite to the first direction.

20. The receiver of claim 19, wherein the controller is configured to generate a tuner control signal to alter a selected channel when the count exceeds a first threshold and to generate a volume control signal when the count exceeds a second threshold.