WO2012163050A1

WO2012163050A1 - Method and device for reducing power consumption of chip

Info

Publication number: WO2012163050A1
Application number: PCT/CN2011/082151
Authority: WO
Inventors: 朱元好
Original assignee: 华为技术有限公司
Priority date: 2011-11-14
Filing date: 2011-11-14
Publication date: 2012-12-06
Also published as: CN102511188B; CN102511188A

Abstract

The present invention relates to the field of communications. Provided in embodiments of the present invention is a method for reducing the power consumption of a chip. The method comprises: receiving within a first unit time a configuration parameter of a logic module that the chip needs to process within a second unit time, the configuration parameter comprising at least the count of data blocks comprised in the logic module and the length of the data blocks, while the second unit time is the unit time subsequent to the first unit time; determining, on the basis of the configuration parameter of the logic module corresponding to a processor unit comprised by the chip, a voltage required within the second unit time by the processor unit; supplying within the second unit time the voltage required by the processor unit to the processor unit. A device comprising: a receiver module, a determination module, and a supply module. The present invention prevents power consumption wastage and performance loss for the chip.

Description

Method and device for reducing power consumption of chip

The present invention relates to the field of communications, and in particular, to a method and device for reducing power consumption of a chip. Background technique

In the field of communication, the performance of the chip affects the quality of the general message; the performance of the chip is affected by its own temperature. The temperature of the chip itself is determined by the ambient temperature on the one hand and the power consumption of the chip itself on the other hand. The power consumption of the chip reduces the temperature of the chip to achieve the purpose of improving the performance of the chip.

At present, DVFS (Dynamic Voltage and Frequency Scaling) technology provides a method for reducing the power consumption of the chip, specifically: predicting the next unit time of the current unit time according to the load of the chip in the current unit book time. The required performance of the chip, and calculate the voltage required by the chip in the next unit time, and inform the power management module to adjust the voltage supplied to the chip in the next unit time, thus reducing the power of the chip by dynamically adjusting the voltage supplied to the chip. Consumption.

In the process of implementing the present invention, the inventors have found that the prior art has at least the following problems:

According to the load of the chip in the current unit time, there is a large inaccuracy in the performance required by the chip in the next unit time. If the predicted performance is greater than the actual required performance of the chip, the power consumption of the chip is wasted; The predicted performance is less than the actual performance required by the chip, which can result in a loss of performance of the chip. Summary of the invention

In order to avoid waste of power consumption and loss of performance of the chip, embodiments of the present invention provide a method and device for reducing power consumption of a chip. The technical solution provided by the embodiment of the present invention is as follows:

A method of reducing power consumption of a chip, the method comprising:

Receiving, in the first unit time, a configuration parameter of a logic module that is required to be processed by the chip in the second unit time, where the configuration parameter includes at least a number of data blocks included in the logic module and a length of the data block, The second unit time is a unit time after the first unit time;

Determining, according to configuration parameters of the logic module corresponding to the processing unit included in the chip, a voltage required by the processing unit in the second unit time;

The voltage required by the processing unit is supplied to the processing unit at the second unit time. An apparatus for reducing power consumption of a chip, where the apparatus includes: a receiving module, configured to receive, in a first unit time, a configuration parameter of a logic module that is required to be processed by a chip in a second unit time, where the configuration parameter includes at least the a number of data blocks included in the logic module and a length of the data block, where the second unit time is a unit time after the first unit time;

a determining module, configured to determine, according to configuration parameters of the logic module corresponding to the processing unit included in the chip, a voltage required by the processing unit in the second unit time;

And a supply module, configured to supply a voltage required by the processing unit to the processing unit in the second unit time. In the embodiment of the present invention, the configuration parameter of the logic module required to be processed by the chip in the second unit time is received in the first unit time, and the configuration parameter of the logic module corresponding to the processing unit included in the chip can be accurately determined. The voltage required by the processing unit in two unit time is supplied to the processing unit for the voltage required by the processing unit in the second unit time. In this way, waste of power consumption of the chip and loss of performance can be avoided. DRAWINGS

1 is a flowchart of a method for reducing power consumption of a chip according to Embodiment 1 of the present invention;

2 is a flow chart of a method for reducing power consumption of a chip according to Embodiment 2 of the present invention;

3 is a schematic structural diagram of a second protocol processing layer according to Embodiment 2 of the present invention;

4 is a schematic diagram of a device for reducing power consumption of a chip according to Embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of a second device for reducing power consumption of a chip according to Embodiment 3 of the present invention; FIG.

6 is a schematic diagram of a third device for reducing power consumption of a chip according to Embodiment 3 of the present invention;

7 is a schematic diagram of a fourth device for reducing power consumption of a chip according to Embodiment 3 of the present invention;

FIG. 8 is a schematic diagram of a fifth device for reducing power consumption of a chip according to Embodiment 3 of the present invention. detailed description

In order to make the objects, the technical solutions and the advantages of the present invention more apparent, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Example 1

As shown in FIG. 1 , an embodiment of the present invention provides a method for reducing power consumption of a chip, including:

Step 101: Receive, in a first unit time, a configuration parameter of a logic module that is processed by a chip in a second unit time, where the configuration parameter includes at least a number of data blocks included in the logic module and a length of the data block, Two unit time is Unit time after the first unit time;

Step 102: Determine, according to a configuration parameter of a logic module corresponding to the processing unit included in the chip, a voltage required by the processing unit in a second unit time;

Step 103: Supply the processing unit with the voltage required by the processing unit at the second unit time.

The above step 102 may include:

(1): acquiring, according to a configuration parameter of the logic module corresponding to the processing unit, a frequency required by the processing unit in a second unit time;

(2): Acquire the voltage required for the processing unit in the second unit time according to the frequency required by the processing unit in the second unit time.

Further, the above (1) may include:

(1-1): calculating, according to configuration parameters of the logic module corresponding to the processing unit, a processing amount of the logic module corresponding to the processing unit;

(1-2): Calculate the frequency required by the processing unit in the second unit time according to the processing amount of the logic module corresponding to the processing unit and the delay indicator of the processing unit.

Further, the above (2) may include:

(2-1): determining a frequency range corresponding to the processing unit according to a frequency required by the processing unit in the second unit time;

(2-2): According to the frequency range corresponding to the processing unit, the voltage required for the processing unit in the second unit time is obtained from the correspondence relationship between the stored frequency range and the voltage.

Further, after (1) above, the method may further include:

In the second unit time, the frequency of the processing unit is adjusted to the frequency required by the processing unit.

In the embodiment of the present invention, the configuration parameter of the logic module required to be processed by the chip in the second unit time is received in the first unit time, and the configuration parameter of the logic module corresponding to the processing unit included in the chip can be accurately determined. The voltage required by the processing unit in two unit time is supplied to the processing unit for the voltage required by the processing unit in the second unit time. In this way, waste of power consumption of the chip and loss of performance can be avoided. Example 2

Embodiments of the present invention provide a method for reducing power consumption of a chip. In this embodiment, the first protocol layer sends the program in the first protocol layer to the second protocol layer, and the chip in the second protocol layer receives the program and processes the program, and the chip in the second protocol layer The method provided in this embodiment can be used to reduce the power consumption of the device to improve its performance. See Figure 2, the method includes:

Step 201: Receive, in a first unit time, a configuration parameter of a logic module that is processed by a chip in a second unit time, and the configuration parameter includes at least a number of data blocks included in the logic module and a length of the data block, and second The unit time is the unit time after the first unit time;

Wherein, any program in the first protocol layer is assumed to be a first program, and the entire first program may be divided into one or more logic modules according to functions of each program segment in the first program, and the logic module includes one or more a data block; any other program in the first protocol layer, assuming a second program, the structure of the second program is the same as the first program, that is, the number and type of the logic modules included in the second program are respectively the first program The number of logical modules included is the same as the type, but the number of data blocks and the length of the data block included in the logical module of the same type in the first program and the second program are not necessarily the same.

Wherein, any one of the chips in the second protocol layer includes one or more processing units, and one or more logic modules in the processing unit corresponding to the chip included in the chip in the second protocol layer may be configured in advance, and the second protocol layer A processing unit included in any of the chips is used to process data blocks included in its corresponding logic module.

The first protocol layer sends the data block included in the logic module to be processed in the first unit time to the second protocol layer in the first unit time, and the chip in the second protocol layer receives the logic module sent by the first protocol layer. Included data block, the data block included in the logic module is mapped into a processing unit corresponding to the logic module, and the data block included in the logic module is processed by the processing unit; and the first protocol layer is still in the first unit time Transmitting, by the second protocol layer, the configuration parameter of the logic module to be processed in the second unit time, the chip in the second protocol layer receiving the configuration parameter of the logic module, and preparing resources according to the configuration parameter of the logic module, the resource is used by the resource Processing the data block included in the logic module sent by the first protocol layer in the second unit time.

It is assumed that the first protocol layer may be a data link layer, the second protocol layer may be a physical layer, and the chips in the second protocol layer perform baseband processing on a program in the first protocol layer; see FIG. 3, in the first protocol layer The first program is divided into logic modules including CRC (Cyclic Redundancy Check), segmentation, FEC (Forward Error Correction), rate matching, scrambling and modulation; The layer includes a first chip and a second chip, and the processing unit in the first chip includes a Home Access Center (HAC), a first processing core, and a second processing core, and the processing unit in the second chip includes a third The processing core and the fourth processing core may be configured in advance that the first processing core corresponds to the logic module included in the first program as a CRC and a segment, the HAC corresponding to the first program includes a logic module, and the second processing core corresponds to the first program. The logic module is rate matching, the third processing core corresponds to the logic module included in the first program is scrambling, and the fourth processing core corresponds to the logic module included in the first program is modulation, that is, A processing core is configured to process the CRC and the segmentation two logic modules included in the first program, the HAC is configured to process the logic module included in the first program to be FEC, and the second processing core is configured to process the logic module included in the first program as rate matching a third processing core for processing a logic module included in the first program The block is scrambled, and the fourth processing core is used to process the logic module included in the first program as modulation.

Assume that the first protocol layer requires that the logic module processed by the chip of the second protocol layer in the second unit time includes CRC, segmentation, FEC, rate matching, scrambling and modulation, then the first protocol layer is in the first unit time. Transmitting the configuration parameters of the logic module CRC, the segmentation configuration parameters, the FEC configuration parameters, the rate matching configuration parameters, the scrambled configuration parameters, and the modulated configuration parameters of the logic module to be processed in the second unit time to the second protocol layer chip.

It should be noted that: the configuration parameter of the CRC includes at least the number of data blocks included in the CRC, the length of the data block, and the number of CRC bits; the configuration parameter of the segment includes at least the number of data blocks and the data block included in the segment. The length of the FEC configuration parameter includes at least the number of data blocks included in the FEC, the length of the data block, and the FEC encoding mode; the configuration parameters of the rate matching include at least the number of data blocks included in the speed matching and the length of the data block; The disturbed configuration parameter includes at least the number of data blocks included in the scrambling and the length of the data block; and, the modulated configuration parameters include at least the number of data blocks included in the modulation and the length of the data block.

In the communication field, one unit time may be one or more TTIs (Transmission Time Intervals). The first unit time may be the current unit time, and the second unit time may be the first unit time, the second unit time, or the third unit time after the first unit time.

Step 202: Calculate, according to a configuration parameter of the logic module, a processing quantity of the logic module according to any logic module that needs to be processed in the second unit time;

Specifically, the processing amount of the logic module is calculated according to the number of data blocks included in the logic module and the length of the data block; for any other logic module, the calculation method of the logic module is calculated according to the same calculation method as the logic module. Processing volume.

The number of data blocks included in the logic module and the length of the data block may be multiplied to obtain a processing amount of the logic module.

The logic module CRC needs to calculate the processing amount of the logic module CRC according to the number of data blocks included in the logic module CRC, the length of the data block, and the number of CRC bits. For the logic module FEC, The processing amount of the logic module FEC is calculated according to the number of data blocks included in the logic module FEC, the length of the data block, and the FEC encoding mode.

For example, according to the configuration parameter of the CRC, the processing amount of the CRC is calculated as Cl, the processing amount C2 of the segment is calculated according to the configuration parameter of the segment, and the processing amount C3 of the FEC is calculated according to the configuration parameter of the FEC, and the configuration parameter according to the rate matching is configured. The processing amount of the rate matching is calculated as C4, the processing amount of the scrambling is calculated as C5 according to the scrambled configuration parameter, and the processing amount of the modulation is calculated as C6 according to the modulated configuration parameter.

Step 203: Calculate, according to the delay indicator of the processing unit and the processing amount of the logic module corresponding to the processing unit, the frequency required by the processing unit in the second unit time, for any processing unit included in the chip; Specifically, the delay indicator corresponding to the processing unit is obtained, and the processing unit is calculated in the second unit time according to the delay indicator of the processing unit and the processing amount of the logic module corresponding to the processing unit according to the following formula (1). Required frequency; c

…… (1 );

T where, in equation (1), F is the frequency required by the processing unit in the second unit time, C is the processing amount of the logic module corresponding to the processing unit, and T is the delay indicator of the processing unit.

Wherein, for the chip of the second protocol layer, each processing unit in the chip may be set in advance to correspond to a delay indicator; after the data is input to the processing unit, the processing unit is after the time delay indicator corresponding to the processing unit Output the processing result of this data.

In this embodiment, the delay indicator corresponding to the first processing core may be set to be T1, the delay indicator corresponding to the HAC is Τ2, the delay indicator corresponding to the second processing core is Τ3, and the delay corresponding to the third processing core is The delay indicator corresponding to the indicator Τ4 and the fourth processing core is Τ5, wherein after the data is input to the first processing core, after the T1 time, the first processing core outputs the result of processing the data, and the delay index of the HAC is Τ2 The meaning of the delay indicator Τ3 of the second processing core, the delay indicator Τ4 of the third processing core, and the delay indicator Τ5 of the fourth processing core are similar, and will not be explained one by one.

For example, the delay indicator T1 of the first processing core is obtained, according to the processing quantity C1 of the logic module CRC corresponding to the first processing core, the processing quantity C2 of the segment, and the delay indicator T1 of the first processing core, and according to the following formula (1-1) calculating the frequency F1 required for the first processing core in the second unit time;

_{F 1} = ^ ...... ( 1-1 )

T1 obtains the delay indicator T2 corresponding to the HAC, according to the processing amount C3 of the logic module FEC corresponding to the HAC and the delay indicator Τ2 of the HAC, and calculates the required HAC in the second unit time according to the following formula (1-2) Frequency F2;

C3

F2 -—······· ( 1-2)

Τ2 Obtain a delay indicator corresponding to the second processing core Τ3, according to the processing amount of the logic module corresponding to the second processing core

C4 and the second processing core delay indicator Τ3, and calculate the frequency F3 required for the second processing core in the second unit time according to the following formula (1-3);

C4

F3 -—······· ( 1-3 )

Τ3 obtaining the delay indicator Τ4 corresponding to the third processing core, according to the processing amount C5 of the logical module scrambling corresponding to the third processing core and the delay indicator Τ4 of the third processing core, and calculating according to the following formula (1-4) The frequency F4 required for the third processing core in the second unit time; F4 -—······· (1-4)

T4 obtains a delay indicator Τ5 corresponding to the fourth processing core, and calculates a processing amount C6 modulated by the logic module corresponding to the fourth processing core and a delay indicator Τ5 of the fourth processing core, and is calculated according to the following formula (1-5) The frequency F5 required for processing the core in the second unit time;

F5 ^ ...... (1-5).

T5 Step 204: Obtain a voltage required by the processing unit in a second unit time according to a frequency required by the processing unit in the second unit time;

Specifically, the frequency range corresponding to the processing unit is determined according to the frequency required by the processing unit in the second unit time, and the corresponding frequency range of the processing unit is obtained according to the corresponding relationship between the stored frequency range and the voltage. The voltage required by the processing unit in the second unit time.

In this case, the correspondence between the frequency range and the voltage can be set in advance. For example, the correspondence between the frequency range and the voltage as shown in Table 1 can be set in advance.

Table 1

For example, the frequency range corresponding to the first processing core is determined to be 301Mh-400Mh according to the frequency F1 required by the first processing core in the second unit time, and the frequency range shown in Table 1 is determined according to the determined frequency range 301Mh-400Mh. In the corresponding relationship with the voltage, the voltage required to acquire the first processing core in the second unit time is 0.9V; and the frequency range corresponding to the HAC is determined to be 0-300Mh according to the frequency F2 required by the HAC in the second unit time, According to the determined frequency range 0-300Mh, from the corresponding relationship between the frequency range and the voltage as shown in Table 1, the voltage required to obtain the HAC in the second unit time is 0.8V; according to the second processing in the second unit time The frequency F3 required by the core determines that the frequency range corresponding to the second processing core is 0Mh-300Mh, and obtains the second unit according to the determined frequency range 0Mh-300Mh from the corresponding relationship between the frequency range and the voltage as shown in Table 1. The voltage required for the second processing core is 0.8V; the frequency range corresponding to the third processing core is determined to be 401Mh-500Mh according to the frequency F4 required for the third processing core in the second unit time, according to the determined frequency range. 401Mh-500M h from the correspondence between the frequency range and the voltage as shown in Table 1, obtaining the voltage required for the third processing core in the second unit time is IV; and, according to the fourth processing core required in the second unit time Frequency F5 determines the fourth The frequency range corresponding to the processing core is 301Mh-400Mh, and the voltage required for the fourth processing core in the second unit time is obtained from the corresponding relationship between the frequency range and the voltage as shown in Table 1 according to the determined frequency range 301Mh-400Mh. It is 0.9V.

In this embodiment, the first protocol layer sends the configuration parameter of the logic module to be processed in the second unit time to the second protocol layer in the first unit time, so that the second unit layer needs to be processed according to the second unit time. The configuration parameter of the logic module can accurately calculate the processing amount of the logic module to be processed in the second unit time, so that the frequency required by the processing unit corresponding to each logic module in the second unit time can be accurately calculated. And according to the frequency required by the processing unit in the second unit time, the voltage required by the processing unit in the second unit time is accurately obtained, so that loss of chip performance and waste of power consumption can be avoided.

Step 205: Supply the processing unit with the voltage required by the processing unit in the second unit time.

Specifically, the voltage required by the processing unit in the second unit time may be notified to the power management module, so that the power management module supplies the processing unit with the voltage required by the processing unit in the second unit time, thus reducing the second The power consumption of the chip within the protocol layer.

Further, the frequency of the processing unit can also be adjusted to the frequency required by the processing unit in the second unit time.

Wherein, for any other processing unit included in the chip, the steps of the above steps 203-205 are performed to obtain the voltage required by the processing unit in the second unit time, and the processing unit is supplied to the processing unit in the second unit time. The voltage required.

The first protocol layer sends the data block included in the logic module to be processed to the second protocol layer in the second unit time, and the second protocol layer maps the data block included in the logic module to the processing unit corresponding to the logic module. Then, the processing unit processes the data blocks included in the logic module mapped to itself.

For example, according to the voltage required for the first processing core in the second unit time is 0.9V, a voltage of 0.9V is supplied to the first processing core in the second unit time, according to the voltage required for the HAC in the second unit time. 0.8V, supplying 0.8V voltage to the HAC in the second unit time, supplying 0.8V voltage to the second processing core according to the voltage required for the second processing core in the second unit time is 0.8V According to the voltage required for the third processing core in the second unit time is IV, the voltage of the IV is supplied to the third processing core in the second unit time, and the voltage required for the fourth processing core in the second unit time is 0.9V, a voltage of 0.9V is supplied to the fourth processing core in the second unit time.

Wherein, in the second unit time, the first protocol layer sends the data block included in the logic module CRC, the data block included in the segment, the data block included in the FEC, the data block included in the rate matching, the data block included in the scrambling, and the modulation The included data block is sent to the second protocol layer; the second protocol layer maps the data block included in the CRC and the data block included in the segment to the first processing core, maps the data block included in the FEC to the HAC, and matches the rate to the included data. Block mapping to the second processing core, including scrambling The data block is mapped to the third processing core, and the data block included in the modulation is mapped to the fourth processing core; then the first processing core performs baseband processing on the data block included in the CRC and the data block included in the segment, and the data included in the FEC by the HAC The block performs baseband processing, the second processing check performs baseband processing on the data block included in the rate matching, the third processing core performs baseband processing on the data block included in the scrambling, and the fourth processing check performs baseband processing on the data block included in the modulation.

The method in the second protocol layer includes a control processing core (CTR Core, Control Core), and the main body of the method in this embodiment may be the control processing core. In addition, the method provided in this embodiment may also be applied. LTE (Long Term Evolution) network, CDMA (Code Division Multiple Access) network, WCDMA (Wideband Code Division Multiple Access) network, WiMAX (Worldwide Interoperability for Microwave Access, Global Microwave Interconnect) networks and/or GSM (Global System of Mobile communication) networks include upstream and downstream processing.

In the embodiment of the present invention, the configuration parameters of the logic module that are processed by the processing unit included in the chip in the second unit time are received in the first unit time, and the second unit time is accurately calculated according to the configuration parameter of each logic module. The first protocol layer sends the processing amount of each logic module to be processed, and accurately calculates the processing unit in the second unit time according to the processing amount of the logic module corresponding to the processing unit and the delay indicator of the processing unit The required frequency, and accurately obtaining the voltage required by the processing unit in the second unit time according to the frequency required by the processing unit in the second unit time, thus avoiding loss of chip performance and work Waste of consumption. Example 3

As shown in FIG. 4, an embodiment of the present invention provides a device for reducing power consumption of a chip, including:

The receiving module 301 is configured to receive, in the first unit time, a configuration parameter of a logic module that is processed by the chip in the second unit time, where the configuration parameter includes at least a number of data blocks included in the logic module and a length of the data block. The second unit time is the unit time after the first unit time;

The determining module 302 is configured to determine, according to configuration parameters of the logic module corresponding to the processing unit included in the chip, a voltage required by the processing unit in the second unit time;

The supply module 303 is configured to supply the processing unit with a voltage required by the processing unit at a second unit time.

The first unit time may be the current unit time, and the second unit time may be the first unit time, the second unit time or the third unit time after the first unit time. In addition, one unit time can be one or more TTI (Transmission Time Interval).

The receiving module 301 can receive, in the first unit time, the configuration parameter of the logic module that the chip of the second protocol layer sent by the first protocol layer needs to process in the second unit time; the program in the first protocol layer includes One or more logic a module, the chip in the second protocol layer includes one or more processing units, and the processing unit included in the chip corresponds to a logic module included in the program in the first protocol layer; in the second unit time, the first protocol layer is sent in The logic module that is processed by the chip of the second protocol layer in the second unit time includes a data block, and the processing unit included in the chip processes the data block included in the corresponding logic module.

Wherein, referring to FIG. 5, the determining module 302 can include:

The first obtaining unit 3021 is configured to acquire, according to a configuration parameter of the logic module corresponding to the processing unit, a frequency required by the processing unit in the second unit time;

The second obtaining unit 3022 is configured to obtain a voltage required by the processing unit in the second unit time according to a frequency required by the processing unit in the second unit time.

The first obtaining unit may specifically include:

a first calculating sub-unit a, configured to calculate a processing amount of the logic module corresponding to the processing unit according to a configuration parameter of the logic module corresponding to the processing unit;

The second calculating subunit b is configured to calculate a frequency required by the processing unit in the second unit time according to the processing amount of the logic module corresponding to the processing unit and the delay indicator of the processing unit.

The first calculating sub-unit a may multiply the number of data blocks included in the logic module by the length of the data block to obtain the processing amount of the logic module.

The second calculating sub-unit b can calculate the required processing unit in the second unit time according to the processing quantity C of the logic module corresponding to the processing unit and the delay index T of the processing unit according to the following formula (2) Frequency

…… (2).

T, see Figure 7, the second acquisition unit includes:

Determining a sub-unit c, configured to determine a frequency range corresponding to the processing unit according to a frequency required by the processing unit in a second unit time;

The obtaining sub-unit d is configured to obtain, according to the frequency range corresponding to the processing unit, the voltage required by the processing unit in the second unit time from the corresponding relationship between the stored frequency range and the voltage.

In this embodiment, the supply module 303 can notify the power management module of the voltage required by the processing unit in the second unit time, so that the power management module supplies the processing unit to the processing unit in the second unit time. The voltage required.

Further, referring to FIG. 8, the device may further include:

The adjusting module 304 is configured to adjust the frequency of the processing unit to a frequency required by the processing unit in the second unit time. The device provided in this embodiment may be a chip for baseband processing in a communication device such as a base station or a base station control device, or a communication device such as a base station and a base station control device including a chip for baseband processing.

In the embodiment of the present invention, the configuration parameter of the logic module required to be processed by the chip in the second unit time is received in the first unit time, and the configuration parameter of the logic module corresponding to the processing unit included in the chip can be accurately determined. The voltage required by the processing unit in two unit time is supplied to the processing unit for the voltage required by the processing unit in the second unit time. In this way, waste of power consumption of the chip and loss of performance can be avoided. It should be noted that: the device for reducing the power consumption of the chip provided by the foregoing embodiment is only illustrated by the division of the foregoing functional modules when reducing the power consumption of the chip. In actual applications, the foregoing functions may be allocated according to requirements. It is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the foregoing embodiment provides a method for reducing the power consumption of the chip and the method for reducing the power consumption of the chip. The specific implementation process is described in detail in the method embodiment, and details are not described herein again. It can be understood in the art that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium. The storage medium to which it is obtained may be a read only memory, a magnetic disk or an optical disk or the like. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

Claim

A method for reducing power consumption of a chip, the method comprising:

The voltage required by the processing unit is supplied to the processing unit at the second unit time.

The method according to claim 1, wherein determining the voltage required by the processing unit in the second unit time according to a configuration parameter of a logic module corresponding to the processing unit included in the chip comprises:

Acquiring, according to configuration parameters of the logic module corresponding to the processing unit, a frequency required by the processing unit in the second unit time;

The voltage required by the processing unit during the second unit time is obtained based on the frequency required by the processing unit during the second unit time.

The method according to claim 2, wherein determining the frequency required by the processing unit in the second unit time according to the configuration parameter of the logic module corresponding to the processing unit included in the chip comprises:

Calculating a processing quantity of the logic module corresponding to the processing unit according to a configuration parameter of the logic module corresponding to the processing unit;

Calculating a frequency required by the processing unit in the second unit time according to a processing amount of the logic module corresponding to the processing unit and a delay indicator of the processing unit.

The method according to claim 2 or 3, wherein, according to the frequency required by the processing unit in the second unit time, obtaining the processing unit required in the second unit time The voltage, including:

Determining, according to a frequency required by the processing unit in the second unit time, a frequency range corresponding to the processing unit;

And obtaining, according to a frequency range corresponding to the processing unit, a voltage required by the processing unit in the second unit time from a corresponding relationship between the stored frequency range and the voltage.

The method according to claim 3, wherein after the calculating the frequency required by the processing unit in the second unit time, the method further includes:

A device for reducing power consumption of a chip, the device comprising: a receiving module, configured to receive, in a first unit time, a configuration parameter of a logic module required to be processed by a chip in a second unit time, The configuration parameter includes at least a number of data blocks included in the logic module and a length of the data block, where the second unit time is a unit time after the first unit time;

And a supply module, configured to supply a voltage required by the processing unit to the processing unit in the second unit time.

The device of claim 6, wherein the determining module comprises:

a first acquiring unit, configured to acquire, according to a configuration parameter of the logic module corresponding to the processing unit, a frequency required by the processing unit in the second unit time;

And a second acquiring unit, configured to acquire, according to a frequency required by the processing unit in the second unit time, a voltage required by the processing unit in the second unit time.

The device of claim 7, wherein the first obtaining unit comprises:

a first calculation subunit, configured to calculate, according to configuration parameters of the logic module corresponding to the processing unit, a processing amount of the logic module corresponding to the processing unit;

And a second calculating subunit, configured to calculate, according to a processing amount of the logic module corresponding to the processing unit and a delay indicator of the processing unit, a frequency required by the processing unit in the second unit time.

The device according to claim 7 or 8, wherein the second obtaining unit comprises:

Determining a subunit, configured to determine a frequency range corresponding to the processing unit according to a frequency required by the processing unit in the second unit time;

And a obtaining sub-unit, configured to acquire, according to a frequency range corresponding to the processing unit, a voltage required by the processing unit in the second unit time from a correspondence between a stored frequency range and a voltage.

The device of claim 8, wherein the device further comprises:

And an adjustment module, configured to adjust a frequency of the processing unit to a frequency required by the processing unit in the second unit time.