WO2012157801A1 - Semiconductor waveform generator - Google Patents

Semiconductor waveform generator Download PDF

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Publication number
WO2012157801A1
WO2012157801A1 PCT/KR2011/003738 KR2011003738W WO2012157801A1 WO 2012157801 A1 WO2012157801 A1 WO 2012157801A1 KR 2011003738 W KR2011003738 W KR 2011003738W WO 2012157801 A1 WO2012157801 A1 WO 2012157801A1
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Prior art keywords
charge
discharge
output
control unit
sawtooth
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PCT/KR2011/003738
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French (fr)
Korean (ko)
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장기석
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(주)태진기술
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Publication of WO2012157801A1 publication Critical patent/WO2012157801A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/10—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements vacuum tubes only
    • H03K4/12—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements vacuum tubes only in which a sawtooth voltage is produced across a capacitor

Definitions

  • the present invention is a semiconductor waveform generator that can be applied as a component to various circuits using a DC-DC converter and a pulse width modulation method, and more particularly, generates a reference voltage for determining amplitude and uses a current mirror to generate a sawtooth wave generating capacitor.
  • the invention relates to a semiconductor waveform generator that allows charge and discharge control to produce accurate sawtooth waves.
  • a DC-DC converter or a pulse width modulation circuit requires a semiconductor waveform generator to process an input signal.
  • a charge and discharge circuit is used to turn off a resistor, a capacitor, and the like.
  • -It can't be integrated by external mounting with chip, or it can be composed of complex circuit through oscillator, differential circuit, integrating circuit, etc., and a separate bias circuit is needed to determine the amplitude of sawtooth wave.
  • a separate clock generator for switching on blanking for no load high efficiency operation is required.
  • the bias current flows through the charge / discharge circuit even in the sawtooth descender, which has a disadvantage in that the amount of bias current for driving is large.
  • the present invention provides a semiconductor waveform generator that generates a reference voltage for determining amplitude and controls the charging and discharging of a sawtooth generating capacitor using a current mirror to generate an accurate sawtooth wave.
  • a reference signal generator for generating a reference voltage by receiving VDD, dividing the reference voltage to generate an upper limit value VFB and a lower limit value VTHL of the sawtooth wave;
  • a charge / discharge control unit which controls the charge / discharge of the sawtooth generating capacitor to generate the sawtooth wave
  • the upper and lower limits of the sawtooth wave are controlled through the latch by controlling the latch set S and the reset R by comparing the sawtooth wave output signal of the charge / discharge control unit with the upper limit value VFB and the lower limit value VTHL, respectively. It is characterized in that it comprises a sawtooth amplitude control unit for generating and outputting a square wave signal whose amplitude according to the control is controlled and fed back to the charge and discharge enable signal of the charge and discharge control unit.
  • the reference signal generator is the reference signal generator
  • a first operational amplifier for receiving the reference voltage VREF of the regulator 11 to the (+) input terminal and receiving the feedback saw upper limit value VFB to the (-) input terminal to compare and amplify the difference;
  • the sawtooth wave upper limit value VFB and the sawtooth wave are applied by an input voltage through a PMOS transistor whose gate is controlled by the output of the first operational amplifier, and divided by a plurality of resistors R1, R2, and R3 connected in series. Characterized in that the upper and lower limit generating unit for generating a lower limit (VHTL).
  • the amplitude control unit (A) The amplitude control unit,
  • a second operational amplifier configured to compare the sawtooth wave upper limit value (VFB) of the reference signal generator to a (+) input terminal and to receive the output (CT) of the sawtooth generating capacitor to a ( ⁇ ) input terminal;
  • a third operational amplifier for comparing the sawtooth wave lower limit value (VHTL) of the reference signal generator to a negative input terminal and receiving an output CT of the sawtooth generating capacitor to a positive input terminal for comparison;
  • a latch configured to receive an output of the second operational amplifier to a set bar terminal (/ S) and an output of the third operational amplifier to a reset bar terminal (/ R) to perform a latch inversion output (/ Q);
  • a square wave output unit configured to output a pulse signal through an NMOS transistor NM receiving an inverted output of the latch at a gate thereof;
  • the charge and discharge control unit controls the charge and discharge control unit
  • a drain and a gate are commonly connected to the PMOS transistors PM1 and PM2 that receive the reference voltage VREF of the reference signal generator from the gate, and the PMOS transistors PM1 and PM2 form a current mirror.
  • a reference current generator comprising morph transistors NM1 and NM2 to receive the reference voltage VREF as a bias voltage to generate a reference current to copy the reference current by a current mirror;
  • PMOS for receiving a charge enable signal ENP and an NMOS transistor NM3 having a common drain and gate connected to a PMOS transistor PM3 connected to the PMOS transistor PM2 of the reference current generator.
  • a drain is connected to the PMOS transistor PM5 that receives the output of the transistor PM7 to the gate and the drain in common, and the PMOS transistor PM5 is connected to the NMOS3 NM3 to form a current mirror.
  • It consists of NMOS transistor NM4 and PMOS transistor PM6 connected to the PMOS transistor PM5 by a common gate to form a current mirror, and radiates the reference current of the reference current generator as a charge bias using a current mirror. Is output through the PMOS transistor PM6 at the charging voltage of the sawtooth generating capacitor according to the charge enable signal ENP.
  • a charging control unit ;
  • An NMOS transistor NM5 having a drain and a gate connected to a PMOS transistor PM4 connected to the PMOS transistor PM2 of the reference current generator unit in common, and a sawtooth generating capacitor connected to an output of the charge control unit are discharged.
  • An MOS transistor NM7 receiving the enable signal ENN from the gate and a drain connected to the NMOS transistor NM7 and connected to the NMOS transistor NM5 through a common gate to form a current mirror.
  • a discharge control unit configured to copy the reference current generated by the reference current generating unit as a discharge bias by a current mirror and control discharge of the sawtooth generating capacitor according to the discharge enable signal. do.
  • the present invention generates a sawtooth upper limit value and a lower limit value by generating a reference voltage by itself, and controls to charge and discharge the sawtooth capacitor by a charge / discharge control unit for charge / discharge control biased by the reference current using a current mirror.
  • a charge / discharge control unit for charge / discharge control biased by the reference current using a current mirror.
  • FIG. 1 is a block diagram of a semiconductor waveform generator according to the present invention.
  • FIG. 2 is a detailed circuit diagram of a charge / discharge control unit of the semiconductor waveform generator according to the present invention.
  • FIG. 3 is a timing diagram of a semiconductor waveform generator according to the present invention.
  • PM, PM1-PM7 PMOS transistor NM, NM1-NM7: NMOS transistor
  • FIG. 1 is a configuration diagram of a semiconductor waveform generator according to the present invention, as shown therein,
  • a reference signal generator 10 which receives VDD to generate a reference voltage VREF, divides the reference voltage VREF, and generates an upper limit value VFB and a lower limit value VTHL of the sawtooth wave;
  • Charge and discharge enable signal (ENP) ENN fed back by receiving the reference voltage VREF generated by the reference signal generator 10 as a bias to generate a reference current, and copying the reference current using a current mirror.
  • a charge / discharge control unit 30 which controls the charge / discharge of the sawtooth wave generating capacitor 40 to generate the sawtooth wave;
  • the sawtooth output signal of the charge / discharge control unit 30 and the upper limit value VFB and the lower limit value VTHL of the reference signal generator 10 are compared, respectively, to control the latch set S and the reset R to latch. It is characterized by consisting of a sawtooth amplitude control unit 30 for generating and outputting a square wave signal whose amplitude is controlled according to the upper and lower limit of the sawtooth wave through the charge and discharge enable signal of the charge and discharge control unit 30 through It is done.
  • the reference signal generator 10 is the reference signal generator
  • a regulator 11 for generating a reference voltage VREF from an input voltage VDD;
  • a first operational amplifier (OP1) for receiving a reference voltage (VREF) of the regulator (11) to the (+) input terminal and receiving a feedback saw upper limit value (VFB) to the (-) input terminal to compare and amplify the difference;
  • the sawtooth wave upper limit value VFB is divided by a plurality of resistors R1, R2, and R3 connected in series by receiving an input voltage through a PMOS transistor whose gate is controlled by the output of the first operational amplifier OP1. And an upper and lower limit value generation unit 12 for generating a sawtooth wave lower limit value VHTL.
  • the amplitude control unit 30 The amplitude control unit 30,
  • Second operational amplifier OP2 for comparing the sawtooth wave upper limit value VFB of the reference signal generator 10 to the (+) input terminal and receiving the output CT of the sawtooth wave generating capacitor 40 to the ( ⁇ ) input terminal.
  • Third operational amplifier OP3 for comparing the lower sawtooth limit value VHTL of the reference signal generator 12 to the (+) input terminal and receiving the output CT of the sawtooth generating capacitor 40 to the negative input terminal.
  • the output of the second operational amplifier OP2 is input to the set bar terminal / S, and the output of the third operational amplifier OP3 is input to the reset bar terminal / R, respectively.
  • a square wave output unit 32 for outputting a pulse signal through an NMOS transistor NM receiving an inverted output / Q of the latch 31 to a gate;
  • the inverted output / Q of the latch 31 is inverted and buffered through the first inverter INV 1 to feed back to the charge enable signal ENP of the charge / discharge controller 20, and the first inverter INV.
  • a charge / discharge enable controller 33 which inverts the output of 1) through the second inverter INV 2 and feeds back the discharge enable signal ENN of the charge / discharge controller 20.
  • the charge / discharge control unit 20 may include:
  • a drain and a gate are commonly connected to the PMOS transistors PM1 and PM2 that receive the reference voltage VREF of the reference signal generator 10 to the gate, and the PMOS transistors PM1 and PM2 are connected to each other.
  • a reference current generator 21 which is composed of NMOS transistors NM1 and NM2 forming a mirror and receives the reference voltage VREF as a bias voltage to generate a reference current to copy the reference current by a current mirror;
  • An NMOS transistor NM3 having a drain and a gate commonly connected to the PMOS transistor PM3 connected to the PMOS transistor PM2 of the reference current generator 21 and the charge enable signal ENP to the gate.
  • a drain is connected to the PMOS transistor PM5 and the PMOS transistor PM5 that receive the output of the applied PMOS transistor PM7 to the gate and the drain in common, and is connected to the NMOS transistor NM3 as a common gate.
  • It is composed of an NMOS transistor NM4 constituting a current mirror and a PMOS transistor PM6 connected to a common gate with the PMOS transistor PM5 to charge a reference current of the reference current generator 21 using a current mirror. Charging by copying as a bias and outputting the charged voltage of the sawtooth generating capacitor 40 through the PMOS transistor PM6 according to the charge enable signal ENP. Fisherman 22 and;
  • An NMOS transistor NM5 having a drain and a gate commonly connected to a PMOS transistor PM4 connected to a PMOS transistor PM2 of the reference current generator 21 as a common gate, and an output of the charge controller 22 are connected.
  • An NMOS transistor NM7 connected to the sawtooth generating capacitor 40 and receiving a discharge enable signal ENN, and a drain connected to the NMOS transistor NM7, are common to the NMOS transistor NM5.
  • NMOS transistor NM6 connected to a gate to form a current mirror.
  • the reference current generated by the reference current generator 21 is copied as a discharge bias by a current mirror to generate the sawtooth wave generating capacitor according to the discharge enable signal. Characterized in that the discharge control unit 23 for controlling the discharge of the (40).
  • the current mirror configured in the embodiment of the drawings is not limited to this, and the current mirror may be configured using a current mirror having any configuration such as, for example, a Wilson current mirror, a Weidler current mirror, or a cascode current mirror. .
  • the input voltage VDD is input to the regulator 11 to generate a constant reference voltage VREF, and the first operational amplifier OP1 compares and amplifies the sawtooth wave upper limit value VFB fed back to the reference voltage VREF.
  • the PMOS transistor PM is controlled by the output of the first operational amplifier OP1, and a plurality of resistors R1-R3 are connected in series to the output terminal of the PMOS transistor PM, so that the sawtooth wave upper limit value VFB and the sawtooth wave. Generate a lower limit (VTHL).
  • the sawtooth wave upper limit value VFB fed back from the reference voltage VREF generated by the regulator 11 is compared in the first operational amplifier OP1 to control the PMOS transistor PM to generate a stable sawtooth wave upper limit value and a lower limit value.
  • the charge / discharge control unit 20 controls the charging and discharging of the sawtooth generating capacitor 40 to generate the sawtooth signal CT, and the sawtooth signal CT is a second operational amplifier OP2 and a third operational amplifier, respectively.
  • the latch 31 is controlled in comparison with the sawtooth wave upper limit value VFB and the sawtooth wave lower limit value VTHL.
  • FIG. 3 is a timing diagram of a sawtooth wave generating circuit according to the present invention.
  • the second operation amplifier OP2 when the sawtooth wave signal CT is lower than the lower limit value VTHL, the second operation amplifier OP2 outputs a low signal and the third operation amplifier OP3 outputs a high signal, and the set bar of the latch 31 is provided.
  • the (/ S) signal is in a high state
  • the reset bar (/ R) signal is in a low state
  • the inverting output (/ Q) of the latch is in a low state.
  • the PMOS transistor PM7 since the high signal inverted by the first inverter INV 1 is applied as the charge enable signal ENP, the PMOS transistor PM7 is turned off and the low signal output from the second inverter INV 2. Is applied to the NMOS transistor NM7 with the discharge enable signal ENN, and the signal is turned off. Accordingly, the PMOS transistors PM5 and PM6 maintain the turn-on state to open the charging loop, and the discharge loop is blocked by the NMOS transistor NM7 being turned off, so that the sawtooth capacitor 40 proceeds with the charging mode.
  • the output of the third operational amplifier OP3 is inverted from a high to a low signal so that the reset bar (/ R) signal of the latch 31 becomes high.
  • the set bar (/ S) signal of the latch 31 is not changed, the inverted output (/ Q) of the latch 31 maintains the low signal which is the output of the charging mode.
  • the output of the second operational amplifier OP2 changes from a high signal to a low signal, thus setting bar (/ S) of the latch 31.
  • the signal toggles from high to low.
  • the latch 31 is toggled from low to high while the output is toggled.
  • the charge enable signal ENP which is the output of the first inverter INV 1
  • the PMOS transistors PM5 and PM6 are turned off while charging loops. Is blocked, and the NMOS transistor NM7, which is applied to the gate with the high signal of the second inverter INV 2 as the discharge enable signal ENN, is turned on to open the discharge loop and discharged through the discharge control unit 23. This is done.
  • the sawtooth signal CT immediately falls below the upper limit value VFB and the output of the second operational amplifier OP2 is also changed to a high signal, thereby keeping the set bar (/ S) signal of the latch 31 high again. Since there is no change in the reset signal of the latch 31, the output maintains the current state to maintain the discharge mode.
  • the output of the third operational amplifier OP3 becomes high and the reset bar signal of the latch 31 (/ R).
  • the toggle signal CT generates a sawtooth wave signal between the upper limit value VFB and the lower limit value VTHL.
  • the charge / discharge control unit 20 includes the reference voltage VREF generated by the reference voltage generator 10 and the PMOS transistors PM1 and PM2 of the reference current generator 21, and the charge control unit ( It is operated by being input to the gate of the PMOS transistor PM3 of the 22 and the PMOS transistor PM4 of the discharge control unit 23, and is operated by the reference current generator 21, the charge control unit 22, and the reference current generator 21. ) And the discharge control unit 23 are biased by the reference currents radiated by the current mirrors, so that they are operated at the same reference current, thereby achieving accurate and stable charge and discharge control operations.

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Abstract

The present invention relates to a semiconductor waveform generator, comprising: a reference signal generation unit for generating a reference voltage (VREF), and generating an upper threshold value (VFB) and a lower threshold value (VTHL) of a sawtooth wave by dividing the reference voltage (VREF); a charge / discharge control unit for generating a reference current by receiving the reference voltage (VREF) which is generated by the reference signal generation unit and inputted through a bias, and for controlling the charging / discharging of a sawtooth wave generation capacitor to generate the sawtooth wave, based on charge / discharge enabling signals (ENP) (ENN), which are feed backed by copying the reference voltage using a current mirror; and a sawtooth wave amplitude control unit for comparing a sawtooth output signal from the charge / discharge control unit with each of the upper threshold value (VFB) and the lower threshold value (VTHL) from the reference signal generation unit, controlling a resetting (R) and a setting (S) of a latch, thereby generating and outputting via the latch a square wave having an amplitude which is controlled according to the controlling of the upper and lower thresholds of the sawtooth wave, and feeding back the square wave as the charge / discharge enabling signals of the charge / discharge control unit.

Description

반도체 파형 발생기Semiconductor waveform generator
본 발명은 DC-DC 컨버터 및 펄스폭 변조방식을 이용하는 각종 회로에 구성요소로 응용이 가능한 반도체 파형 발생기로서, 더욱 상세하게는 진폭을 결정하는 기준전압을 생성하고 전류미러를 이용하여 톱니파 발생 캐패시터의 충전과 디스차지를 제어하게 하여 정확한 톱니파를 생성하도록 한 반도체 파형 발생기에 관한 것이다.The present invention is a semiconductor waveform generator that can be applied as a component to various circuits using a DC-DC converter and a pulse width modulation method, and more particularly, generates a reference voltage for determining amplitude and uses a current mirror to generate a sawtooth wave generating capacitor. The invention relates to a semiconductor waveform generator that allows charge and discharge control to produce accurate sawtooth waves.
반도체 집적회로에서 DC-DC 컨버터나 펄스폭 변조방식 회로에서는 입력신호를 처리하기 위해서는 반도체 파형 발생기가 필요한데, 종래의 기술은 충방전 회로를 이용하여 저항, 캐패시터(Capacitor) 등을 오프-칩(Off-Chip)으로 외부에 장착하여 집적화 되지 못하거나, 발진기(Oscillator), 미분 회로, 적분 회로 등을 통해 복잡한 회로로 구성이 되며, 공히 톱니파의 진폭 결정을 위해 별도의 바이어스 회로를 필요로 하며, DC-DC 컨버터(converter)에 활용될 경우 무부하 고효율 동작을 위한 스위치 온 블랭킹(Switch On Blanking)을 위한 클럭발생기(Clock Generator)를 별도로 필요로 하는 단점이 있었다.In a semiconductor integrated circuit, a DC-DC converter or a pulse width modulation circuit requires a semiconductor waveform generator to process an input signal. In the conventional technology, a charge and discharge circuit is used to turn off a resistor, a capacitor, and the like. -It can't be integrated by external mounting with chip, or it can be composed of complex circuit through oscillator, differential circuit, integrating circuit, etc., and a separate bias circuit is needed to determine the amplitude of sawtooth wave. When used in a DC converter, there is a disadvantage in that a separate clock generator for switching on blanking for no load high efficiency operation is required.
또한 톱니파의 하강기에도 충방전 회로로 바이어스 전류가 흐르게 되어 구동을 위한 바이어스 전류량이 크다는 단점이 있었다.In addition, the bias current flows through the charge / discharge circuit even in the sawtooth descender, which has a disadvantage in that the amount of bias current for driving is large.
본 발명은 진폭을 결정하는 기준전압을 생성하고 전류미러를 이용하여 톱니파 발생 캐패시터의 충전과 디스차지를 제어하게 하여 정확한 톱니파를 생성하도록 한 반도체 파형 발생기를 제공하기 위한 것이다.SUMMARY OF THE INVENTION The present invention provides a semiconductor waveform generator that generates a reference voltage for determining amplitude and controls the charging and discharging of a sawtooth generating capacitor using a current mirror to generate an accurate sawtooth wave.
본 발명에 의한 반도체 파형 발생기는,The semiconductor waveform generator according to the present invention,
VDD를 입력받아 기준전압을 발생시키고, 기준전압을 분압하여 톱니파의 상한값(VFB)과 하한값(VTHL)을 발생시키는 기준신호 발생부와;A reference signal generator for generating a reference voltage by receiving VDD, dividing the reference voltage to generate an upper limit value VFB and a lower limit value VTHL of the sawtooth wave;
상기 기준신호 발생부에서 생성된 기준전압(VREF)을 바이어스로 입력받아 기준전류를 생성하고, 기준전류를 전류 미러를 이용하여 복사하여 피드백되는 충방전 인에이블신호(ENP)(ENN)에 의거하여 톱니파 발생 캐패시터의 충방전을 제어하여 톱니파를 발생시키는 충방전제어부와;Based on the reference voltage VREF generated by the reference signal generator as a bias to generate a reference current, and based on the charge / discharge enable signal ENP ENN fed back by copying the reference current using a current mirror. A charge / discharge control unit which controls the charge / discharge of the sawtooth generating capacitor to generate the sawtooth wave;
상기 충방전 제어부의 톱니파 출력신호와 상기 기준신호 발생부의 상한값(VFB)과 하한값(VTHL)을 각각 비교하여 래치의 세트(S) 및 리세트(R)를 제어하여 래치를 통해 톱니파의 상한 및 하한 제어에 따른 진폭이 제어된 구형파 신호를 발생시켜 출력함과 아울러 상기 충방전제어부의 충전 및 방전 인에이블신호로 피드백시키는 톱니파 진폭제어부로 구성됨을 특징으로 한다.The upper and lower limits of the sawtooth wave are controlled through the latch by controlling the latch set S and the reset R by comparing the sawtooth wave output signal of the charge / discharge control unit with the upper limit value VFB and the lower limit value VTHL, respectively. It is characterized in that it comprises a sawtooth amplitude control unit for generating and outputting a square wave signal whose amplitude according to the control is controlled and fed back to the charge and discharge enable signal of the charge and discharge control unit.
상기 기준신호 발생부는, The reference signal generator,
입력전압(VDD)으로부터 기준전압(VREF)을 생성하는 레귤레이터와;A regulator for generating a reference voltage VREF from an input voltage VDD;
상기 레귤레이터(11)의 기준전압(VREF)을 (+)입력단에, 피드백되는 톱니파 상한값(VFB)을 (-)입력단에 입력받아 차이를 비교증폭하는 제1연산증폭기와;A first operational amplifier for receiving the reference voltage VREF of the regulator 11 to the (+) input terminal and receiving the feedback saw upper limit value VFB to the (-) input terminal to compare and amplify the difference;
상기 제1연산증폭기의 출력에 의해 게이트가 제어되는 피모스트랜지스터(PM)를 통해 입력전압을 인가받아 직렬 연결된 복수의 저항(R1, R2, R3)에 의해 분압하여 톱니파 상한값(VFB)과, 톱니파 하한값(VHTL)을 생성하는 상하한값 생성부로 구성됨을 특징으로 한다.The sawtooth wave upper limit value VFB and the sawtooth wave are applied by an input voltage through a PMOS transistor whose gate is controlled by the output of the first operational amplifier, and divided by a plurality of resistors R1, R2, and R3 connected in series. Characterized in that the upper and lower limit generating unit for generating a lower limit (VHTL).
상기 진폭제어부는,The amplitude control unit,
상기 기준신호 발생부의 톱니파 상한값(VFB)을 (+)입력단에, 상기 톱니파 발생 캐패시터의 출력(CT)을 (-)입력단에 입력받아 비교하는 제2연산증폭기와;A second operational amplifier configured to compare the sawtooth wave upper limit value (VFB) of the reference signal generator to a (+) input terminal and to receive the output (CT) of the sawtooth generating capacitor to a (−) input terminal;
상기 기준신호 발생부의 톱니파 하한값(VHTL)을 (-)입력단에, 상기 톱니파 발생 캐패시터의 출력(CT)을 (+)입력단에 입력받아 비교하는 제3연산증폭기와;A third operational amplifier for comparing the sawtooth wave lower limit value (VHTL) of the reference signal generator to a negative input terminal and receiving an output CT of the sawtooth generating capacitor to a positive input terminal for comparison;
상기 제2연산증폭기의 출력을 세트바 단자(/S)에, 상기 제3연산증폭기의 출력을 리세트바 단자(/R)에 각각 입력받아 래치 반전출력(/Q)을 하는 래치와;A latch configured to receive an output of the second operational amplifier to a set bar terminal (/ S) and an output of the third operational amplifier to a reset bar terminal (/ R) to perform a latch inversion output (/ Q);
상기 래치의 반전출력(/Q)을 게이트에 입력받는 앤모스 트랜지스터(NM)를 통해서 펄스신호를 출력하는 구형파 출력부와;A square wave output unit configured to output a pulse signal through an NMOS transistor NM receiving an inverted output of the latch at a gate thereof;
상기 래치의 반전출력(/Q)을 제1인버터를 통해 반전 버퍼링하여 상기 충방전 제어부의 충전 인에이블신호(ENP)로 피드백시키고, 상기 제1인버터의 출력을 제2인버터를 통해 반전시켜 상기 충방전 제어부의 방전 인에이블신호(ENN)로 피드백시키는 충방전 인에이블 제어부로 구성됨을 특징으로 한다.Inverting and buffering the inverted output (/ Q) of the latch through a first inverter to feed back to the charge enable signal (ENP) of the charge and discharge controller, and inverts the output of the first inverter through a second inverter to charge Characterized in that the charge and discharge enable control unit for feeding back to the discharge enable signal (ENN) of the discharge control unit.
상기 충방전제어부는,The charge and discharge control unit,
상기 기준신호 발생부의 기준전압(VREF)을 게이트에 입력받는 피모스트랜지스터(PM1)(PM2)와, 상기 피모스트랜지스터(PM1)(PM2)에 각각 드레인과 게이트가 공통 연결되어 전류미러를 이루는 앤모스트랜지스터(NM1, NM2)로 이루어져 상기 기준전압(VREF)을 바이어스 전압으로 입력받아 기준전류를 발생하여 전류미러에 의해 기준전류를 복사하는 기준전류 발생부와;A drain and a gate are commonly connected to the PMOS transistors PM1 and PM2 that receive the reference voltage VREF of the reference signal generator from the gate, and the PMOS transistors PM1 and PM2 form a current mirror. A reference current generator comprising morph transistors NM1 and NM2 to receive the reference voltage VREF as a bias voltage to generate a reference current to copy the reference current by a current mirror;
상기 기준전류 발생부의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM3)에 드레인과 게이트가 공통연결된 앤모스트랜지스터(NM3), 충전인에이블신호(ENP)를 게이트에 인가받는 피모스트랜지스터(PM7)의 출력을 게이트와 드레인에 공통 입력받는 피모스트랜지스터(PM5), 상기 피모스트랜지스터(PM5)에 드레인이 연결되고 상기 앤모스트랜지스터(NM3)와 공통 게이트로 연결되어 전류미러를 이루는 앤모스트랜지스터(NM4) 및 상기 피모스트랜지스터(PM5)와 공통게이트로 연결되어 전류미러를 이루는 피모스트랜지스터(PM6)로 이루어져, 상기 기준전류 발생부의 기준전류를 전류미러를 이용하여 충전 바이어스로서 복사하여 상기 충전 인에이블신호(ENP)에 따라 상기 톱니파 발생 캐패시터의 충전 전압으로 상기 피모스트랜지스터(PM6)를 통해 출력하는 충전제어부와;PMOS for receiving a charge enable signal ENP and an NMOS transistor NM3 having a common drain and gate connected to a PMOS transistor PM3 connected to the PMOS transistor PM2 of the reference current generator. A drain is connected to the PMOS transistor PM5 that receives the output of the transistor PM7 to the gate and the drain in common, and the PMOS transistor PM5 is connected to the NMOS3 NM3 to form a current mirror. It consists of NMOS transistor NM4 and PMOS transistor PM6 connected to the PMOS transistor PM5 by a common gate to form a current mirror, and radiates the reference current of the reference current generator as a charge bias using a current mirror. Is output through the PMOS transistor PM6 at the charging voltage of the sawtooth generating capacitor according to the charge enable signal ENP. A charging control unit;
상기 기준전류 발생부의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM4)에 드레인과 게이트가 공통 연결된 앤모스트랜지스터(NM5), 상기 충전제어부의 출력이 연결된 톱니파 발생 캐패시터에 연결되고 방전인에이블신호(ENN)를 게이트에 인가받는 앤모스트랜지스터(NM7)와, 상기 앤모스 트랜지스터(NM7)에 드레인이 연결되고 상기 앤모스트랜지스터(NM5)와 공통 게이트로 연결되어 전류미러를 이루는 앤모스 트랜지스터(NM6)로 이루어져, 상기 기준전류 발생부에서 발생된 기준전류를 전류미러에 의해 방전 바이어스로서 복사하여 상기 방전인에이블 신호에 따라 상기 톱니파 발생 캐패시터의 방전 제어를 하는 방전 제어부로 구성됨을 특징으로 한다.An NMOS transistor NM5 having a drain and a gate connected to a PMOS transistor PM4 connected to the PMOS transistor PM2 of the reference current generator unit in common, and a sawtooth generating capacitor connected to an output of the charge control unit are discharged. An MOS transistor NM7 receiving the enable signal ENN from the gate and a drain connected to the NMOS transistor NM7 and connected to the NMOS transistor NM5 through a common gate to form a current mirror. And a discharge control unit configured to copy the reference current generated by the reference current generating unit as a discharge bias by a current mirror and control discharge of the sawtooth generating capacitor according to the discharge enable signal. do.
본 발명은 자체적으로 기준전압을 발생시켜 톱니파 상한값과 하한값을 생성하고, 전류미러를 이용하여 기준전류에 의해 바이어스되는 충방전제어를 하는 충방전 제어부에 의해 톱니파 캐패시터를 충전 및 방전시키도록 제어하되, 톱니파 신호와 상한값 및 하한값을 비교하여 래치를 이용해 충방전 인에이블신호를 생성하여 피드백시키도록 함으로써, 안정화된 진폭제어는 물론 전류 미러에 의해 충방전 바이어스제어를 하기 때문에 정밀한 톱니파를 생성할 수 있는 효과가 있다.The present invention generates a sawtooth upper limit value and a lower limit value by generating a reference voltage by itself, and controls to charge and discharge the sawtooth capacitor by a charge / discharge control unit for charge / discharge control biased by the reference current using a current mirror. By comparing the sawtooth signal with the upper limit value and the lower limit value, and generating and feeding back the charge / discharge enable signal using the latch, the effect of generating the sawtooth wave precisely because the charge and discharge bias control is performed by the current mirror as well as the stabilized amplitude control. There is.
도 1은 본 발명에 의한 반도체 파형 발생기의 구성도.1 is a block diagram of a semiconductor waveform generator according to the present invention.
도 2는 본 발명에 의한 반도체 파형 발생기의 충방전 제어부의 상세 회로도.2 is a detailed circuit diagram of a charge / discharge control unit of the semiconductor waveform generator according to the present invention.
도 3은 본 발명에 의한 반도체 파형 발생기의 타이밍도. 3 is a timing diagram of a semiconductor waveform generator according to the present invention;
*도면부호의 설명* Explanation of Drawings
10 : 기준전압 발생부 11 : 레귤레이터10: reference voltage generator 11: regulator
12 : 상하한값 발생부 20 : 충방전 제어부12: upper and lower limit value generation unit 20: charge and discharge control unit
21 : 기준전류 발생부 22 : 충전 제어부21: reference current generator 22: charge control unit
23 : 방전 제어부 30 : 진폭 제어부23: discharge control 30: amplitude control
31 : 래치 32 : 구형파 출력부31: latch 32: square wave output
33 : 충방전 인에이블 제어부 40 : 톱니파 발생 캐패시터33: charge and discharge enable control unit 40: sawtooth wave generation capacitor
OP1-OP3 : 제1-제3연산증폭기OP1-OP3: 1st-3rd Operational Amplifier
PM, PM1 - PM7 : 피모스트랜지스터 NM, NM1 - NM7 : 앤모스트랜지스터 PM, PM1-PM7: PMOS transistor NM, NM1-NM7: NMOS transistor
이하, 본 발명의 실시 예를 첨부된 도면을 참조해서 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 의한 반도체 파형 발생기의 구성도로서 이에 도시된 바와 같이,1 is a configuration diagram of a semiconductor waveform generator according to the present invention, as shown therein,
VDD를 입력받아 기준전압(VREF)을 발생시키고, 기준전압(VREF)을 분압하여 톱니파의 상한값(VFB)과 하한값(VTHL)을 발생시키는 기준신호 발생부(10)와;A reference signal generator 10 which receives VDD to generate a reference voltage VREF, divides the reference voltage VREF, and generates an upper limit value VFB and a lower limit value VTHL of the sawtooth wave;
상기 기준신호 발생부(10)에서 생성된 기준전압(VREF)을 바이어스로 입력받아 기준전류를 생성하고, 기준전류를 전류 미러를 이용하여 복사하여 피드백되는 충방전 인에이블신호(ENP)(ENN)에 의거하여 톱니파 발생 캐패시터(40)의 충방전을 제어하여 톱니파를 발생시키는 충방전제어부(30)와;Charge and discharge enable signal (ENP) ENN fed back by receiving the reference voltage VREF generated by the reference signal generator 10 as a bias to generate a reference current, and copying the reference current using a current mirror. A charge / discharge control unit 30 which controls the charge / discharge of the sawtooth wave generating capacitor 40 to generate the sawtooth wave;
상기 충방전 제어부(30)의 톱니파 출력신호와 상기 기준신호 발생부(10)의 상한값(VFB)과 하한값(VTHL)을 각각 비교하여 래치의 세트(S) 및 리세트(R)를 제어하여 래치를 통해 톱니파의 상한 및 하한 제어에 따른 진폭이 제어된 구형파 신호를 발생시켜 출력함과 아울러 상기 충방전제어부(30)의 충전 및 방전 인에이블신호로 피드백시키는 톱니파 진폭제어부(30)로 구성됨을 특징으로 한다.The sawtooth output signal of the charge / discharge control unit 30 and the upper limit value VFB and the lower limit value VTHL of the reference signal generator 10 are compared, respectively, to control the latch set S and the reset R to latch. It is characterized by consisting of a sawtooth amplitude control unit 30 for generating and outputting a square wave signal whose amplitude is controlled according to the upper and lower limit of the sawtooth wave through the charge and discharge enable signal of the charge and discharge control unit 30 through It is done.
상기 기준신호 발생부(10)는, The reference signal generator 10,
입력전압(VDD)으로부터 기준전압(VREF)을 생성하는 레귤레이터(11)와;A regulator 11 for generating a reference voltage VREF from an input voltage VDD;
상기 레귤레이터(11)의 기준전압(VREF)을 (+)입력단에, 피드백되는 톱니파 상한값(VFB)을 (-)입력단에 입력받아 차이를 비교증폭하는 제1연산증폭기(OP1)와;A first operational amplifier (OP1) for receiving a reference voltage (VREF) of the regulator (11) to the (+) input terminal and receiving a feedback saw upper limit value (VFB) to the (-) input terminal to compare and amplify the difference;
상기 제1연산증폭기(OP1)의 출력에 의해 게이트가 제어되는 피모스트랜지스터(PM)를 통해 입력전압을 인가받아 직렬 연결된 복수의 저항(R1, R2, R3)에 의해 분압하여 톱니파 상한값(VFB)과, 톱니파 하한값(VHTL)을 생성하는 상하한값 생성부(12)로 구성됨을 특징으로 한다.The sawtooth wave upper limit value VFB is divided by a plurality of resistors R1, R2, and R3 connected in series by receiving an input voltage through a PMOS transistor whose gate is controlled by the output of the first operational amplifier OP1. And an upper and lower limit value generation unit 12 for generating a sawtooth wave lower limit value VHTL.
상기 진폭제어부(30)는,The amplitude control unit 30,
상기 기준신호 발생부(10)의 톱니파 상한값(VFB)을 (+)입력단에, 상기 톱니파 발생 캐패시터(40)의 출력(CT)을 (-)입력단에 입력받아 비교하는 제2연산증폭기(OP2)와;Second operational amplifier OP2 for comparing the sawtooth wave upper limit value VFB of the reference signal generator 10 to the (+) input terminal and receiving the output CT of the sawtooth wave generating capacitor 40 to the (−) input terminal. Wow;
상기 기준신호 발생부(12)의 톱니파 하한값(VHTL)을 (+)입력단에, 상기 톱니파 발생 캐패시터(40)의 출력(CT)을 (-)입력단에 입력받아 비교하는 제3연산증폭기(OP3)와;Third operational amplifier OP3 for comparing the lower sawtooth limit value VHTL of the reference signal generator 12 to the (+) input terminal and receiving the output CT of the sawtooth generating capacitor 40 to the negative input terminal. Wow;
상기 제2연산증폭기(OP2)의 출력을 세트바 단자(/S)에, 상기 제3연산증폭기(OP3)의 출력을 리세트바 단자(/R)에 각각 입력받아 반전출력(/Q)을 하는 래치(31)와;The output of the second operational amplifier OP2 is input to the set bar terminal / S, and the output of the third operational amplifier OP3 is input to the reset bar terminal / R, respectively. A latch 31;
상기 래치(31)의 반전출력(/Q)을 게이트에 입력받는 앤모스 트랜지스터(NM)를 통해서 펄스신호를 출력하는 구형파 출력부(32)와;A square wave output unit 32 for outputting a pulse signal through an NMOS transistor NM receiving an inverted output / Q of the latch 31 to a gate;
상기 래치(31)의 반전출력(/Q)을 제1인버터(INV 1)를 통해 반전 버퍼링하여 상기 충방전 제어부(20)의 충전 인에이블신호(ENP)로 피드백시키고, 상기 제1인버터(INV 1)의 출력을 제2인버터(INV 2)를 통해 반전시켜 상기 충방전 제어부(20)의 방전 인에이블신호(ENN)로 피드백시키는 충방전 인에이블 제어부(33)로 구성됨을 특징으로 한다.The inverted output / Q of the latch 31 is inverted and buffered through the first inverter INV 1 to feed back to the charge enable signal ENP of the charge / discharge controller 20, and the first inverter INV. And a charge / discharge enable controller 33 which inverts the output of 1) through the second inverter INV 2 and feeds back the discharge enable signal ENN of the charge / discharge controller 20.
도 2는 본 발명에 의한 반도체 파형 발생기의 충방전 제어부의 상세 회로도로서, 이에 도시된 바와 같이, 상기 충방전제어부(20)는,2 is a detailed circuit diagram of the charge / discharge control unit of the semiconductor waveform generator according to the present invention. As shown therein, the charge / discharge control unit 20 may include:
상기 기준신호 발생부(10)의 기준전압(VREF)을 게이트에 입력받는 피모스트랜지스터(PM1)(PM2)와, 상기 피모스트랜지스터(PM1)(PM2)에 각각 드레인과 게이트가 공통연결되어 전류미러를 이루는 앤모스트랜지스터(NM1, NM2)로 이루어져 상기 기준전압(VREF)을 바이어스 전압으로 입력받아 기준전류를 발생하여 전류미러에 의해 기준전류를 복사하는 기준전류 발생부(21)와;A drain and a gate are commonly connected to the PMOS transistors PM1 and PM2 that receive the reference voltage VREF of the reference signal generator 10 to the gate, and the PMOS transistors PM1 and PM2 are connected to each other. A reference current generator 21 which is composed of NMOS transistors NM1 and NM2 forming a mirror and receives the reference voltage VREF as a bias voltage to generate a reference current to copy the reference current by a current mirror;
상기 기준전류 발생부(21)의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM3)에 드레인과 게이트가 공통연결된 앤모스트랜지스터(NM3), 충전인에이블신호(ENP)를 게이트에 인가받는 피모스트랜지스터(PM7)의 출력을 게이트와 드레인에 공통 입력받는 피모스트랜지스터(PM5), 상기 피모스트랜지스터(PM5)에 드레인이 연결되고 상기 앤모스트랜지스터(NM3)와 공통게이트로 연결되어 전류미러를 이루는 앤모스트랜지스터(NM4) 및 상기 피모스트랜지스터(PM5)와 공통게이트로 연결된 피모스트랜지스터(PM6)로 이루어져, 상기 기준전류 발생부(21)의 기준전류를 전류미러를 이용하여 충전 바이어스로서 복사하여 상기 충전 인에이블신호(ENP)에 따라 상기 톱니파 발생 캐패시터(40)의 충전 전압으로 상기 피모스트랜지스터(PM6)를 통해 출력하는 충전제어부(22)와;An NMOS transistor NM3 having a drain and a gate commonly connected to the PMOS transistor PM3 connected to the PMOS transistor PM2 of the reference current generator 21 and the charge enable signal ENP to the gate. A drain is connected to the PMOS transistor PM5 and the PMOS transistor PM5 that receive the output of the applied PMOS transistor PM7 to the gate and the drain in common, and is connected to the NMOS transistor NM3 as a common gate. It is composed of an NMOS transistor NM4 constituting a current mirror and a PMOS transistor PM6 connected to a common gate with the PMOS transistor PM5 to charge a reference current of the reference current generator 21 using a current mirror. Charging by copying as a bias and outputting the charged voltage of the sawtooth generating capacitor 40 through the PMOS transistor PM6 according to the charge enable signal ENP. Fisherman 22 and;
상기 기준전류 발생부(21)의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM4)에 드레인과 게이트가 공통연결된 앤모스트랜지스터(NM5), 상기 충전제어부(22)의 출력이 연결된 톱니파 발생 캐패시터(40)에 연결되고 방전인에이블신호(ENN)를 게이트에 인가받는 앤모스트랜지스터(NM7)와, 상기 앤모스 트랜지스터(NM7)에 드레인이 연결되고 상기 앤모스트랜지스터(NM5)와 공통 게이트로 연결되어 전류미러를 이루는 앤모스 트랜지스터(NM6)로 이루어져 상기 기준전류 발생부(21)에서 발생된 기준전류를 전류미러에 의해 방전 바이어스로서 복사하여 상기 방전인에이블 신호에 따라 상기 톱니파 발생 캐패시터(40)의 방전 제어를 하는 방전 제어부(23)로 구성됨을 특징으로 한다.An NMOS transistor NM5 having a drain and a gate commonly connected to a PMOS transistor PM4 connected to a PMOS transistor PM2 of the reference current generator 21 as a common gate, and an output of the charge controller 22 are connected. An NMOS transistor NM7 connected to the sawtooth generating capacitor 40 and receiving a discharge enable signal ENN, and a drain connected to the NMOS transistor NM7, are common to the NMOS transistor NM5. NMOS transistor NM6 connected to a gate to form a current mirror. The reference current generated by the reference current generator 21 is copied as a discharge bias by a current mirror to generate the sawtooth wave generating capacitor according to the discharge enable signal. Characterized in that the discharge control unit 23 for controlling the discharge of the (40).
여기서, 도면의 실시예로 구성된 전류 미러는 이에 한정되지 아니하고, 전류 미러는, 예를들어 윌슨 전류미러, 위들러 전류미러, 캐스코드 전류미러 등 어떤한 구성의 전류미러를 사용해서 구성할 수도 있다.Here, the current mirror configured in the embodiment of the drawings is not limited to this, and the current mirror may be configured using a current mirror having any configuration such as, for example, a Wilson current mirror, a Weidler current mirror, or a cascode current mirror. .
이와 같이 구성된 본 발명에 의한 반도체 파형 발생기는,The semiconductor waveform generator according to the present invention configured as described above,
입력전압(VDD)을 레귤레이터(11)에 입력받아 일정한 기준전압(VREF)을 발생하고, 제1연산증폭기(OP1)는 상기 기준전압(VREF)과 피드백되는 톱니파 상한값(VFB)를 비교 증폭하며, 제1연산증폭기(OP1)의 출력을에 의해 피모스 트랜지스터(PM)가 제어되고, 피모스트랜지스터(PM)의 출력단에 복수의 저항(R1-R3)이 직렬 연결되어 톱니파 상한값(VFB)과 톱니파 하한값(VTHL)을 발생한다. 따라서 레귤레이터(11)에서 발생된 기준전압(VREF)과 피드백되는 톱니파 상한값(VFB)이 제1연산증폭기(OP1)에서 비교되어 피모스트랜지스터(PM)를 제어함으로서 안정된 톱니파 상한값 및 하한값을 발생시킬 수 있다.The input voltage VDD is input to the regulator 11 to generate a constant reference voltage VREF, and the first operational amplifier OP1 compares and amplifies the sawtooth wave upper limit value VFB fed back to the reference voltage VREF. The PMOS transistor PM is controlled by the output of the first operational amplifier OP1, and a plurality of resistors R1-R3 are connected in series to the output terminal of the PMOS transistor PM, so that the sawtooth wave upper limit value VFB and the sawtooth wave. Generate a lower limit (VTHL). Accordingly, the sawtooth wave upper limit value VFB fed back from the reference voltage VREF generated by the regulator 11 is compared in the first operational amplifier OP1 to control the PMOS transistor PM to generate a stable sawtooth wave upper limit value and a lower limit value. have.
그리고 충방전 제어부(20)에서 톱니파 발생 캐패시터(40)의 충전과 방전을 제어하여 톱니파 신호(CT)를 발생하고, 톱니파 신호(CT)는, 각각 제2연산증폭기(OP2)와 제3연산증폭기(OP3)에서 톱니파 상한값(VFB), 톱니파 하한값(VTHL)과 비교되어 래치(31)를 제어하게 된다.The charge / discharge control unit 20 controls the charging and discharging of the sawtooth generating capacitor 40 to generate the sawtooth signal CT, and the sawtooth signal CT is a second operational amplifier OP2 and a third operational amplifier, respectively. At OP3, the latch 31 is controlled in comparison with the sawtooth wave upper limit value VFB and the sawtooth wave lower limit value VTHL.
도 3은 본 발명에 의한 톱니파 발생회로의 타이밍도이다.3 is a timing diagram of a sawtooth wave generating circuit according to the present invention.
먼저, 상기 톱니파 신호(CT)가 하한값(VTHL)보다 낮은 경우, 제2연산증폭기(OP2)는 로우신호를, 제3연산증폭기(OP3)는 하이신호를 출력하고, 래치(31)의 세트바(/S) 신호는 하이 상태가, 리세트바(/R) 신호는 로우 상태가 되며, 래치의 반전출력(/Q)은 로우 상태가 된다.First, when the sawtooth wave signal CT is lower than the lower limit value VTHL, the second operation amplifier OP2 outputs a low signal and the third operation amplifier OP3 outputs a high signal, and the set bar of the latch 31 is provided. The (/ S) signal is in a high state, the reset bar (/ R) signal is in a low state, and the inverting output (/ Q) of the latch is in a low state.
이에 따라 제1인버터(INV 1)에서 반전된 하이신호가 충전인에이블신호(ENP)로 인가되므로, 피모스트랜지스터(PM7)은 오프 상태가 되고, 제2인버터(INV 2)에서 출력되는 로우신호가 방전인에이블신호(ENN)로 앤모스트랜지스터(NM7)에 인가되어 오프상태가 된다. 따라서 피모스트랜지스터(PM5, PM6)는 턴온 상태를 유지하여 충전루프를 열어주게되며, 방전루프는 앤모스트랜지스터(NM7)가 오프되어 차단되므로 톱니파 캐패시터(40)에는 충전모드가 진행된다.Accordingly, since the high signal inverted by the first inverter INV 1 is applied as the charge enable signal ENP, the PMOS transistor PM7 is turned off and the low signal output from the second inverter INV 2. Is applied to the NMOS transistor NM7 with the discharge enable signal ENN, and the signal is turned off. Accordingly, the PMOS transistors PM5 and PM6 maintain the turn-on state to open the charging loop, and the discharge loop is blocked by the NMOS transistor NM7 being turned off, so that the sawtooth capacitor 40 proceeds with the charging mode.
이후, 톱니파 신호(CT)가 하한값(VTHL)을 넘는 경우, 제3연산증폭기(OP3)의 출력이 하이에서 로우 신호로 반전되어 래치(31)의 리세트바(/R) 신호를 하이 상태로 만든다. 그렇지만 래치(31)의 세트바(/S) 신호가 변하지 않고 있으므로, 래치(31)의 반전출력(/Q)은 충전모드의 출력인 로우신호를 유지하게 된다.Subsequently, when the sawtooth wave signal CT exceeds the lower limit value VTHL, the output of the third operational amplifier OP3 is inverted from a high to a low signal so that the reset bar (/ R) signal of the latch 31 becomes high. Make. However, since the set bar (/ S) signal of the latch 31 is not changed, the inverted output (/ Q) of the latch 31 maintains the low signal which is the output of the charging mode.
충전모드가 진행되어 상기 톱니파 신호(CT)가 상한값(VFB)를 넘으면, 제2연산증폭기(OP2)의 출력이 하이신호에서 로우신호로 변하고, 이에 따라 래치(31)의 세트바(/S)신호가 하이상태에서 로우 상태로 토글된다. 따라서, 래치(31)는 출력이 토글되면서 반전출력(/Q)이 로우에서 하이 상태로 토글된다.When the sawtooth signal CT exceeds the upper limit value VFB when the charging mode is performed, the output of the second operational amplifier OP2 changes from a high signal to a low signal, thus setting bar (/ S) of the latch 31. The signal toggles from high to low. Thus, the latch 31 is toggled from low to high while the output is toggled.
이에 따라 제1인버터(INV 1)의 출력인 충전인에이블 신호(ENP)는 로우신호가 되면서 피모스트랜지스터(PM7)을 턴온시키므로, 피모스트랜지스터(PM5, PM6)는 턴오프 상태가 되면서 충전 루프는 차단되고, 제2인버터(INV 2)의 하이신호를 방전인에이블신호(ENN)로 게이트에 인가받는 앤모스트랜지스터(NM7)는 턴온되면서 방전루프를 열어주게 되어 방전제어부(23)를 통해 방전이 이루어진다.Accordingly, since the charge enable signal ENP, which is the output of the first inverter INV 1, becomes a low signal and turns on the PMOS transistor PM7, the PMOS transistors PM5 and PM6 are turned off while charging loops. Is blocked, and the NMOS transistor NM7, which is applied to the gate with the high signal of the second inverter INV 2 as the discharge enable signal ENN, is turned on to open the discharge loop and discharged through the discharge control unit 23. This is done.
따라서 톱니파 신호(CT)는 상한값(VFB) 이하로 즉시 떨어지면서 제2연산증폭기(OP2)의 출력도 하이신호로 바뀌어 래치(31)의 세트바(/S)신호를 다시 하이상태로 유지시키지만, 래치(31)의 리세트신호의 변화가 없으므로 출력은 현상태를 유지하여 방전모드를 유지시킨다.Therefore, the sawtooth signal CT immediately falls below the upper limit value VFB and the output of the second operational amplifier OP2 is also changed to a high signal, thereby keeping the set bar (/ S) signal of the latch 31 high again. Since there is no change in the reset signal of the latch 31, the output maintains the current state to maintain the discharge mode.
상기와 같은 방전모드가 진행되어 상기 톱니파 신호(CT)가 상기 하한값(VTHL) 이하가 되면, 제3연산증폭기(OP3)의 출력이 하이 상태가 되면서 래치(31)의 리세트바신호(/R)가 로우상태로 변하면서 래치(31)의 출력이 토글된다. 즉, 래치(31)의 반전출력(/Q)이 하이 상태로 로우 상태로 변하면서 충전인에이블 신호(ENP)는 하이신호로, 방전인에이블신호(ENN)는 로우신호가 되어 다시 충전모드를 진행한다. 이때 제3연산증폭기(OP3)의 출력이 로우에서 하이로 즉시 변하여 리세트바(/R)신호가 토글되더라도 세트신호의 변화가 없기 때문에 래치(31)의 출력은 충전모드신호로 유지된다.When the sawtooth signal CT falls below the lower limit value VTHL when the discharge mode is performed as described above, the output of the third operational amplifier OP3 becomes high and the reset bar signal of the latch 31 (/ R). ) Changes to a low state and the output of the latch 31 is toggled. That is, when the inverted output (/ Q) of the latch 31 changes from the high state to the low state, the charge enable signal ENP becomes a high signal and the discharge enable signal ENN becomes a low signal to resume the charging mode. Proceed. At this time, even if the output of the third operational amplifier OP3 immediately changes from low to high and the reset bar (/ R) signal is toggled, the output of the latch 31 is maintained as the charging mode signal because there is no change in the set signal.
이와 같은 과정을 반복하여 도 3에 도시된 바와 같이 토글신호(CT)는 상한값(VFB)과 하한값(VTHL) 사이에서 톱니파 신호를 발생하게 되는 것이다.By repeating this process, as shown in FIG. 3, the toggle signal CT generates a sawtooth wave signal between the upper limit value VFB and the lower limit value VTHL.
본 발명에 의한 충방전제어부(20)는, 기준전압 발생부(10)에서 발생된 기준전압(VREF)을 기준전류 발생부(21)의 피모스트랜지스터(PM1)(PM2)와, 충전제어부(22)의 피모스트랜지스터(PM3), 방전 제어부(23)의 피모스트랜지스터(PM4)의 게이트에 입력받아 동작되고, 기준전류발생부(21)와 충전제어부(22), 기준전류 발생부(21)와 방전제어부(23)가 각각 전류미러에 의해 복사되는 기준전류에 의해 바이어스가 걸리도록 함으로써, 동일한 기준전류에서 동작되므로 정확하고 안정된 충방전 제어동작이 이루어진다.The charge / discharge control unit 20 according to the present invention includes the reference voltage VREF generated by the reference voltage generator 10 and the PMOS transistors PM1 and PM2 of the reference current generator 21, and the charge control unit ( It is operated by being input to the gate of the PMOS transistor PM3 of the 22 and the PMOS transistor PM4 of the discharge control unit 23, and is operated by the reference current generator 21, the charge control unit 22, and the reference current generator 21. ) And the discharge control unit 23 are biased by the reference currents radiated by the current mirrors, so that they are operated at the same reference current, thereby achieving accurate and stable charge and discharge control operations.

Claims (4)

  1. 반도체 파형 발생기에 있어서,In semiconductor waveform generator,
    VDD를 입력받아 기준전압(VREF)을 발생시키고, 기준전압(VREF)을 분압하여 톱니파의 상한값(VFB)과 하한값(VTHL)을 발생시키는 기준신호 발생부(10)와;A reference signal generator 10 which receives VDD to generate a reference voltage VREF, divides the reference voltage VREF, and generates an upper limit value VFB and a lower limit value VTHL of the sawtooth wave;
    상기 기준신호 발생부(10)에서 생성된 기준전압(VREF)을 바이어스로 입력받아 기준전류를 생성하고, 기준전류를 전류 미러를 이용하여 복사하여 피드백되는 충방전 인에이블신호(ENP)(ENN)에 의거하여 톱니파 발생 캐패시터(40)의 충방전을 제어하여 톱니파를 발생시키는 충방전제어부(30)와;Charge and discharge enable signal (ENP) ENN fed back by receiving the reference voltage VREF generated by the reference signal generator 10 as a bias to generate a reference current and copying the reference current using a current mirror. A charge / discharge control unit 30 for controlling the charge / discharge of the sawtooth wave generating capacitor 40 to generate the sawtooth wave;
    상기 충방전 제어부(30)의 톱니파 출력신호와 상기 기준신호 발생부(10)의 상한값(VFB)과 하한값(VTHL)을 각각 비교하여 래치의 세트(S) 및 리세트(R)를 제어하여 래치를 통해 톱니파의 상한 및 하한 제어에 따른 진폭이 제어된 구형파 신호를 발생시켜 출력함과 아울러 상기 충방전제어부(30)의 충전 및 방전 인에이블신호로 피드백시키는 톱니파 진폭제어부(30)로 구성된 것을 특징으로 하는 반도체 파형 발생기.The sawtooth output signal of the charge / discharge control unit 30 and the upper limit value VFB and the lower limit value VTHL of the reference signal generator 10 are compared, respectively, to control the latch set S and the reset R to latch. It is characterized by consisting of a sawtooth wave amplitude control unit 30 for generating and outputting a square wave signal whose amplitude is controlled according to the upper and lower limits of the sawtooth wave through the charge and discharge enable signal of the charge and discharge control unit 30 through Semiconductor waveform generator.
  2. 제 1 항에 있어서, 상기 기준신호 발생부(10)는, The method of claim 1, wherein the reference signal generator 10,
    입력전압(VDD)으로부터 기준전압(VREF)을 생성하는 레귤레이터(11)와;A regulator 11 for generating a reference voltage VREF from an input voltage VDD;
    상기 레귤레이터(11)의 기준전압(VREF)을 (+)입력단에, 피드백되는 톱니파 상한값(VFB)을 (-)입력단에 입력받아 차이를 비교증폭하는 제1연산증폭기(OP1)와;A first operational amplifier (OP1) for receiving a reference voltage (VREF) of the regulator (11) to the (+) input terminal and receiving a feedback saw upper limit value (VFB) to the (-) input terminal to compare and amplify the difference;
    상기 제1연산증폭기(OP1)의 출력에 의해 게이트가 제어되는 피모스트랜지스터(PM)를 통해 입력전압을 인가받아 직렬 연결된 복수의 저항(R1, R2, R3)에 의해 분압하여 톱니파 상한값(VFB)과, 톱니파 하한값(VHTL)을 생성하는 상하한값 생성부(12)로 구성된 것을 특징으로 하는 반도체 파형 발생기.The sawtooth wave upper limit value VFB is divided by a plurality of resistors R1, R2, and R3 connected in series by receiving an input voltage through a PMOS transistor whose gate is controlled by the output of the first operational amplifier OP1. And an upper and lower limit generator (12) for generating a sawtooth wave lower limit (VHTL).
  3. 제 1 항에 있어서, 상기 진폭제어부(30)는,The method of claim 1, wherein the amplitude control unit 30,
    상기 기준신호 발생부(10)의 톱니파 상한값(VFB)을 (+)입력단에, 상기 톱니파 발생 캐패시터(40)의 출력(CT)을 (-)입력단에 입력받아 비교하는 제2연산증폭기(OP2)와;Second operational amplifier OP2 for comparing the sawtooth wave upper limit value VFB of the reference signal generator 10 to the (+) input terminal and receiving the output CT of the sawtooth wave generating capacitor 40 to the (−) input terminal. Wow;
    상기 기준신호 발생부(12)의 톱니파 하한값(VHTL)을 (+)입력단에, 상기 톱니파 발생 캐패시터(40)의 출력(CT)을 (-)입력단에 입력받아 비교하는 제3연산증폭기(OP3)와;Third operational amplifier OP3 for comparing the lower sawtooth limit value VHTL of the reference signal generator 12 to the (+) input terminal and receiving the output CT of the sawtooth generating capacitor 40 to the negative input terminal. Wow;
    상기 제2연산증폭기(OP2)의 출력을 세트바 단자(/S)에, 상기 제3연산증폭기(OP3)의 출력을 리세트바 단자(/R)에 각각 입력받아 반전출력(/Q)을 하는 래치(31)와;The output of the second operational amplifier OP2 is input to the set bar terminal / S, and the output of the third operational amplifier OP3 is input to the reset bar terminal / R, respectively. A latch 31;
    상기 래치(31)의 반전출력(/Q)을 게이트에 입력받는 앤모스 트랜지스터(NM)를 통해서 펄스신호를 출력하는 구형파 출력부(32)와;A square wave output unit 32 for outputting a pulse signal through an NMOS transistor NM receiving an inverted output / Q of the latch 31 to a gate;
    상기 래치(31)의 반전출력(/Q)을 제1인버터(INV 1)를 통해 반전 버퍼링하여 상기 충방전 제어부(20)의 충전 인에이블신호(ENP)로 피드백시키고, 상기 제1인버터(INV 1)의 출력을 제2인버터(INV 2)를 통해 반전시켜 상기 충방전 제어부(20)의 방전 인에이블신호(ENN)로 피드백시키는 충방전 인에이블 제어부(33)로 구성된 것을 특징으로 하는 반도체 파형 발생기.The inverted output / Q of the latch 31 is inverted and buffered through the first inverter INV 1 to feed back to the charge enable signal ENP of the charge / discharge controller 20, and the first inverter INV. A semiconductor waveform comprising a charge and discharge enable control unit 33 which inverts the output of 1) through the second inverter INV 2 and feeds it back to the discharge enable signal ENN of the charge and discharge control unit 20. generator.
  4. 제 1 항에 있어서, 상기 충방전제어부(20)는,The method of claim 1, wherein the charge and discharge control unit 20,
    상기 기준신호 발생부(10)의 기준전압(VREF)을 게이트에 입력받는 피모스트랜지스터(PM1)(PM2)와, 상기 피모스트랜지스터(PM1)(PM2)에 각각 드레인과 게이트가 공통연결되어 전류미러를 이루는 앤모스트랜지스터(NM1, NM2)로 이루어져 상기 기준전압(VREF)을 바이어스 전압으로 입력받아 기준전류를 발생하여 전류미러에 의해 기준전류를 복사하는 기준전류 발생부(21)와;A drain and a gate are commonly connected to the PMOS transistors PM1 and PM2 that receive the reference voltage VREF of the reference signal generator 10 to the gate, and the PMOS transistors PM1 and PM2 are connected to each other. A reference current generator 21 which is composed of NMOS transistors NM1 and NM2 forming a mirror and receives the reference voltage VREF as a bias voltage to generate a reference current to copy the reference current by a current mirror;
    상기 기준전류 발생부(21)의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM3)에 드레인과 게이트가 공통연결된 앤모스트랜지스터(NM3), 충전인에이블신호(ENP)를 게이트에 인가받는 피모스트랜지스터(PM7)의 출력을 게이트와 드레인에 공통 입력받는 피모스트랜지스터(PM5), 상기 피모스트랜지스터(PM5)에 드레인이 연결되고 상기 앤모스트랜지스터(NM3)와 공통게이트로 연결되어 전류미러를 이루는 앤모스트랜지스터(NM4) 및 상기 피모스트랜지스터(PM5)와 공통게이트로 연결된 피모스트랜지스터(PM6)로 이루어져, 상기 기준전류 발생부(21)의 기준전류를 전류미러를 이용하여 충전 바이어스로서 복사하여 상기 충전 인에이블신호(ENP)에 따라 상기 톱니파 발생 캐패시터(40)의 충전 전압으로 상기 피모스트랜지스터(PM6)를 통해 출력하는 충전제어부(22)와;An NMOS transistor NM3 having a drain and a gate commonly connected to the PMOS transistor PM3 connected to the PMOS transistor PM2 of the reference current generator 21 and the charge enable signal ENP to the gate. A drain is connected to the PMOS transistor PM5 and the PMOS transistor PM5 that receive the output of the applied PMOS transistor PM7 to the gate and the drain in common, and is connected to the NMOS transistor NM3 as a common gate. It is composed of an NMOS transistor NM4 constituting a current mirror and a PMOS transistor PM6 connected to a common gate with the PMOS transistor PM5 to charge a reference current of the reference current generator 21 using a current mirror. Charging by copying as a bias and outputting the charged voltage of the sawtooth generating capacitor 40 through the PMOS transistor PM6 according to the charge enable signal ENP. Fisherman 22 and;
    상기 기준전류 발생부(21)의 피모스트랜지스터(PM2)와 공통 게이트로 연결된 피모스트랜지스터(PM4)에 드레인과 게이트가 공통연결된 앤모스트랜지스터(NM5), 상기 충전제어부(22)의 출력이 연결된 톱니파 발생 캐패시터(40)에 연결되고 방전인에이블신호(ENN)를 게이트에 인가받는 앤모스트랜지스터(NM7)와, 상기 앤모스 트랜지스터(NM7)에 드레인이 연결되고 상기 앤모스트랜지스터(NM5)와 공통 게이트로 연결되어 전류미러를 이루는 앤모스 트랜지스터(NM6)로 이루어져 상기 기준전류 발생부(21)에서 발생된 기준전류를 전류미러에 의해 방전 바이어스로서 복사하여 상기 방전인에이블 신호에 따라 상기 톱니파 발생 캐패시터(40)의 방전 제어를 하는 방전 제어부(23)로 구성된 것을 특징으로 하는 반도체 파형 발생기.An NMOS transistor NM5 having a drain and a gate commonly connected to a PMOS transistor PM4 connected to a PMOS transistor PM2 of the reference current generator 21 as a common gate, and an output of the charge controller 22 are connected. An NMOS transistor NM7 connected to the sawtooth generating capacitor 40 and receiving a discharge enable signal ENN, and a drain connected to the NMOS transistor NM7, are common to the NMOS transistor NM5. The saw current wave generating capacitor is formed of an NMOS transistor NM6 connected to a gate to form a current mirror, and the reference current generated by the reference current generator 21 is copied as a discharge bias by a current mirror. A semiconductor waveform generator, characterized by comprising a discharge control unit 23 for controlling discharge of 40.
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