WO2012156946A1 - Circuit intégré radiofréquence - Google Patents

Circuit intégré radiofréquence Download PDF

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Publication number
WO2012156946A1
WO2012156946A1 PCT/IB2012/052499 IB2012052499W WO2012156946A1 WO 2012156946 A1 WO2012156946 A1 WO 2012156946A1 IB 2012052499 W IB2012052499 W IB 2012052499W WO 2012156946 A1 WO2012156946 A1 WO 2012156946A1
Authority
WO
WIPO (PCT)
Prior art keywords
configurable
topology
low noise
noise amplifier
impedance matching
Prior art date
Application number
PCT/IB2012/052499
Other languages
English (en)
Inventor
Jari Johannes Heikkinen
Jonne Juhani Riekki
Jouni Kristian Kaukovuori
Original Assignee
Renesas Mobile Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB1108444.9A external-priority patent/GB2481487B/en
Priority claimed from US13/111,423 external-priority patent/US8378748B2/en
Priority claimed from US13/224,430 external-priority patent/US8427239B2/en
Priority claimed from GB1115183.4A external-priority patent/GB2486515B/en
Priority claimed from GB1117606.2A external-priority patent/GB2490976A/en
Priority claimed from US13/271,630 external-priority patent/US8514021B2/en
Application filed by Renesas Mobile Corporation filed Critical Renesas Mobile Corporation
Priority to CN201280034977.4A priority Critical patent/CN103843248A/zh
Priority to EP12727440.5A priority patent/EP2710728A1/fr
Publication of WO2012156946A1 publication Critical patent/WO2012156946A1/fr

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Definitions

  • This application relates to Radio Frequency Integrated Circuits (RFICs). In particular, but not exclusively, this application relates to configurable RFICs.
  • RFICs Radio Frequency Integrated Circuits
  • Radio-frequency (RF) platforms are high-volume products, which include several integrated circuits (ICs) for audio, power management, radio transceiver, etc.
  • ICs can offer the best economical figures for mass-production products, since the mask costs are fixed which leads to decreasing unit costs as the number of fabricated ICs increases.
  • the over-the-air (OTA) performance defines the capabilities of the RF platform.
  • OTA performance is an important selling factor and can be a crucial selection criterion for a potential customer, as well as the unit cost.
  • OTA performance is a function of antenna performance and capabilities of RFIC and baseband ICs.
  • the size of the antenna scales inversely to the RF frequency, i.e. antennas become larger when the wavelength increases.
  • the size of the antennas is limited due to a small form-factor product thus leading to sub- optimal antenna performance. Therefore, the platform performance can be degraded at frequencies below lGHz leading to decreased uplink/downlink performance.
  • State-of-the-art RFICs are designed to operate at several different bands, for example Global System for Mobile Communications (GSM) 850, 900, 1800, and/or 1900, Wideband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA) and/or Long Term Evolution (LTE) Bands 1, 2, 3, etc.
  • GSM Global System for Mobile Communications
  • WCDMA Wideband Code Division Multiple Access
  • HSPA High Speed Packet Access
  • LTE Long Term Evolution
  • RF filter or duplex filter in the case of links utilising Frequency Division Duplexing (FDD)
  • FDD Frequency Division Duplexing
  • WCDMA and LTE Bands 2 and 3 have a narrow duplex frequency gap, (the frequency difference between the highest transmission frequency and the lowest receiver frequency) resulting in a higher IL. Since the receiver sensitivity in the abovementioned bands is comparatively worse, the range of the wireless link is shorter. As a result, the network design becomes more challenging and more expensive, for example more base stations are needed.
  • a good reference sensitivity level is a relevant figure -of-merit.
  • the IL before the Low Noise Amplifier (LNA) stage of an RF receiver is expected to increase due to inter-band carrier aggregation (CA) as more complex front-end module (FEM) designs are required.
  • CA inter-band carrier aggregation
  • FEM front-end module
  • some of the existing bands will be extended to cover even wider bandwidths and probably with narrower duplex distances (e.g. Band 2 + G- block, Uplink: 1910-1915MHz, Downlink: 1990-1995MHz).
  • additional losses are expected due to diplexer and switch losses, and additional filtering required due to challenging duplex and co-existence scenarios.
  • cost-optimisation including in relation to filter modules and materials.
  • the LNA is usually the first amplifying stage in an RF receiver. According to Friis' equation, the LNA sets the minimum noise figure of the receiver. A low LNA noise figure is a crucial parameter determining the reference sensitivity level of the whole transceiver or RF platform. The LNA is also a crucial part for determining the input impedance of the RFIC. Sufficient input matching performance is required because the performance of the RF filter preceding the LNA will degrade if the input of the LNA is not properly matched to a certain input impedance. Since the RF filters preceding the LNA typically have a fixed frequency range, the RFIC inputs will be matched to specific frequencies as well.
  • RFIC performance is a crucial factor in determining the radio platform performance.
  • the LNA which defines the minimum possible noise figure, which in part defines the reference sensitivity level.
  • the sensitivity performance and input matching configurability of RFICs are fixed and this leads to sub-optimal platform design, since there are several levels of customer (for example network operators, Original Equipment Manufacturers (OEMS), etc.) and different mobile device products each of which may have different requirements for the same chipset. Since the cost of individual ICs scales down when the number of units increases, it is not economically wise to design separately optimised ICs for different customers and/or products.
  • a configurable radio- frequency integrated circuit comprising one or more configurable low noise amplifier circuits, each of the one or more configurable low noise amplifier circuits being configurable between:
  • the respective low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, the one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from the internal input impedance matching topology.
  • the respective low noise amplifier circuit does not comprise at least one of the one or more internal input impedance matching components.
  • the respective low noise amplifier circuit does not comprise any of the one or more internal input impedance matching components.
  • the different topology comprises a partly externally matched or a fully externally matched topology where one or more external components, i.e. components external to the configurable RFIC, are required for input impedance matching.
  • external matching components are placed externally to the RFIC on a Printed Wiring Board (PWB) or suchlike
  • the configurable RFIC can be configured according to the desire of the customer. Cost-efficiency and high quality and reliability can be provided by configuring one or more LNAs in the RFIC in the internal input impedance matching topology. Improved sensitivity can be provided by configuring one or more LNAs in the RFIC in the different topology where external input impedance matching components are required. Embodiments therefore provide a capability to trade-off cost against performance with a single RFIC design. This leads to a more optimal engineering and marketing solution since a variety of products with different requirements can be covered using the same RFIC.
  • At least one of the one or more configurable low noise amplifier circuits comprises a switching arrangement, the at least one configurable low noise amplifier circuit being configurable between one of the internal input impedance matching topology and the different topology via the respective switching arrangement.
  • the circuit can be configured in the internal input impedance matching topology or different topology according to the desired performance of the circuit.
  • the internal input impedance matching topology comprises a resistive feedback low noise amplifier topology and the different topology comprises an inductively degenerated low noise amplifier topology. In some embodiments, the internal input impedance matching topology comprises a common-gate low noise amplifier topology and the different topology comprises an inductively degenerated low noise amplifier gate topology.
  • the different topology comprises an inductively degenerated low noise amplifier topology and the internal input impedance matching topology comprises an impedance matching stage coupled to an input of the configurable low noise amplifier circuit, the output of the impedance matching stage providing an input bias voltage for the impedance matching stage, and a feedback stage coupled to an output of the impedance matching stage and a voltage source, the feedback stage providing a compensated operating voltage for the impedance matching stage.
  • the RFIC can support several different combinations of LNA topologies providing either impedance matching capabilities internally or requiring external matching components.
  • the configurable RFIC comprises an interface arranged to connect at least one of the one or more configurable low noise amplifier circuits to a radio -frequency (RF) front end module.
  • the interface comprises at least a first input connection arranged to connect at least a first one of the one or more configurable low noise amplifier circuits to a first RF band output of the RF front end module.
  • the interface comprises at least a second input connection arranged to connect at least a second one of the one or more configurable low noise amplifier circuits to a second RF band output of the RF front end module, wherein the second RF band is different from the first RF band.
  • the configurable RFIC is capable of coupling multiple RF band inputs to multiple configurable LNAs, for example in a carrier aggregation environment.
  • the configurable RFIC comprises a further interface arranged to connect at least one of the one or more configurable low noise amplifier circuits to a further RF front end module.
  • the RF front end module comprises a main antenna RF front end module and the further RF front end module interface comprises a diversity antenna RF front end module.
  • HSDPA High Speed Downlink Packet Access
  • LTE Long Term Evolution
  • the further interface comprises at least a third input connection arranged to connect at least a third one of the one or more configurable low noise amplifier circuits to a third RF band output of the further RF front end module, wherein the first RF band comprises the third RF band, and at least a fourth input connection arranged to connect at least a fourth one of the one or more configurable low noise amplifier circuits to a fourth RF band output of the further RF front end module, wherein the third RF band is different from the fourth RF band.
  • the first RF band comprises the third RF band and the second RF band comprises the fourth RF band.
  • a method of configuring a configurable RFIC comprising one or more configurable low noise amplifier circuits, the method comprising applying one of: a first set of one or more control signals to at least one of the one or more circuits to configure the at least one circuit in an internal input impedance matching topology in which the respective low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, the one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; or
  • an RF module comprising one or more RF front end modules coupled to one or more configurable RFICs according to the first embodiments.
  • a chipset comprising one or more configurable RFICs according to the first embodiments.
  • a device comprising one or more configurable RFICs according to the first embodiments.
  • the device may for example comprise a mobile/cellular telephone.
  • a configurable radio -frequency integrated circuit comprising one or more configurable low noise amplifier circuits, each of the one or more configurable low noise amplifier circuits being configurable between:
  • the respective low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, the one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a fully externally matched topology in which the respective low noise amplifier circuit does not comprise any of the one or more internal input impedance matching components.
  • Figure 1 illustrates an exemplary receiver comprising an RF module and an antenna according to the prior art.
  • Figure 2 illustrates an RF chipset on a PWB for a receiver according to the prior art.
  • Figure 3 illustrates an RF chipset on a PWB for a receiver according to the prior art.
  • Figure 4 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 6 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 7 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 8 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 9 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 10 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • Figure 11 is a circuit diagram of an inductively degenerated LNA according to embodiments.
  • Figure 12 is a circuit diagram of a common-gate LNA according to embodiments.
  • Figure 13 is a circuit diagram of a configurable LNA according to embodiments.
  • Figure 14 is a circuit diagram of a resistive feedback LNA according to embodiments.
  • Figure 15 is a circuit diagram of a configurable LNA according to embodiments.
  • Figure 16 is a block diagram of a signal reusing low noise amplifier according to embodiments.
  • Figure 17 illustrates a common-mode feedback amplifier according to embodiments.
  • Figure 18 is a circuit diagram of a signal reusing low noise amplifier according to embodiments.
  • Figure 19 is a circuit diagram of a configurable low noise amplifier according to embodiments.
  • Figure 20 is a circuit diagram of a configurable low noise amplifier configured in an inductively degenerated topology according to embodiments. Detailed Description
  • Receivers typically include one or more radio frequency (RF) filters located between the antenna and the LNA(s) that form the first amplifying stage of the receiver.
  • Figure 1 illustrates an exemplary receiver comprising an RF module 100 and antenna 130.
  • RF module 100 comprises an RF Front End Module 132 which in turn includes one or more (up to a total of n) RF filters 1 10 - 1 12 that filter radio frequency signals gathered by antenna 130.
  • RF module 100 also comprises an RFIC 134 which in turn comprises one or more (up to a total of m) LNAs 120 - 122 that amplify the filtered signals generated by the RF filters 110 - 1 12.
  • FIG. 3 illustrates an RF chipset on a PWB for a receiver.
  • the receiver includes a HB antenna and a LB antenna connected to a main RF FEM.
  • the receiver also includes a diversity (DIV) antenna connected to a DIV FEM.
  • the RF FEMs connect to one or more PAs and an RFIC.
  • the RFIC comprises a TX comprising one or more amplifiers and a RX comprising one or more LB LNAs, one or more HB LNAs and one or more DIV LNAs.
  • the DIV antenna is an additional antenna which is included to improve the reception quality and reliability of the RF receiver link, for example as used in HSDPA and LTE environments.
  • RFICs support several different frequency bands. Since the RF filters between the antenna and RFIC typically are optimised for a fixed and narrow frequency range, the RFIC inputs are matched to specific frequencies. Therefore, RFICs contain several inputs dedicated to different frequency areas. In addition, in High Speed Downlink Packet Access (HSDPA) and LTE, for example, there is a need for a diversity (DIV) receiver. Therefore, the number of RF inputs supported within RFICs increases further, particularly when there is a need for a DIV receiver.
  • HSDPA High Speed Downlink Packet Access
  • LTE Long Term Evolution
  • DIV diversity
  • the LNA is usually the first block in an RFIC receiver.
  • the input matching can be passive and/or active consisting of internal on-chip components or input matching can be achieved with external components placed on a PWB.
  • on-chip components have a poorer quality factor than external components.
  • external components should be avoided where possible since the size of the application board and cost should be minimized.
  • the external component count tends to be higher in multi-band and multi-mode transceivers covering several frequency bands.
  • the need for a diversity receiver in cellular HSDPA and LTE for example, can increase the number of external matching components required on an application board.
  • the matching network consisting of external components usually gives some passive voltage gain prior to LNA thus decreasing the noise contribution of the LNA input transistors, and therefore, decreases the overall noise figure of the receiver.
  • LNA topologies containing external matching components can achieve better noise figure compared to LNAs with internal matching.
  • the selectivity of the LNA can be improved with passive matching components. For example, the effect of the transmitter (TX) in Frequency Division Duplexing (FDD) systems can be suppressed.
  • FDD Frequency Division Duplexing
  • desensitization in multi-radio environment can be mitigated.
  • Embodiments described herein relate to RFICs that have the capability to be adaptively modified thus avoiding non-optimal and inflexible design.
  • Such configurable RFICs provide performance-optimized and cost-effective RF platforms serving different kinds of needs.
  • Embodiments comprise a configurable RFIC comprising one or more configurable low noise amplifier circuits.
  • Each of the one or more configurable low noise amplifier circuits is configurable between an internal input impedance matching topology and a different topology.
  • a low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input.
  • the one or more internal input impedance matching components are located internally to the respective low noise amplifier circuit.
  • a respective low noise amplifier circuit does not comprise any of the one or more internal input impedance matching components.
  • the low noise amplifier circuit does not have the input impedance matching capability of the internal input impedance matching topology, so one or more components located externally to the low noise amplifier circuit are required for input impedance matching.
  • the different topology is referred to as an external input impedance matching topology, i.e. a topology which requires one or more external components for input impedance matching.
  • an LNA In the external input impedance matching topology, an LNA has a better noise figure thus leading to better reference sensitivity level on the platform level. However, the cost is higher due to the requirement for external matching components which leads to an increase in PWB area.
  • an input connection of an RFIC interface from an RF band output of a FEM to a configurable LNA configured to the internal input impedance matching topology is depicted as an empty triangle.
  • An input connection of an RFIC interface from an RF band output of a FEM to a configurable LNA configured to the external input impedance matching topology, i.e. which utilises external impedance matching is depicted as a shaded (or 'filled') triangle.
  • an LNA is configured to the internal input impedance matching topology then its input connection (or 'port' or 'pin') in the RFIC interface can be connected directly to the appropriate RF band output of the FEM.
  • an LNA is configured to the external input impedance matching topology then its input connection in the RFIC interface will be connected to the appropriate RF band output of the FEM via one or more external matching components.
  • Figure 4 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 4 depict an ultra low-cost scenario with a single receiver (RX) branch from a main FEM to a configurable RFIC.
  • the configurable RFIC comprises an interface which is arranged to connect one or more configurable LNAs to the main FEM.
  • the interface comprises several input connections each of which connect an input of a configurable LNA to an RF band output of the main FEM.
  • no external impedance matching components are utilised and all LNAs within the RFIC are configured to the internal input impedance matching topology where input matching is realised internally to each LNA circuit.
  • Figure 5 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 5 depict a low-cost scenario with a main RX branch from a main FEM to a configurable RFIC and also a DIV RX branch from a DIV FEM to the same configurable RFIC.
  • the configurable RFIC of embodiments of Figure 5 comprises a first interface which is arranged to connect one or more configurable LNAs to the main FEM.
  • the first interface comprises several input connections each of which connect the input of a configurable LNA to an RF band output of the main FEM.
  • the configurable RFIC also comprises a second interface which is arranged to connect one or more configurable LNAs to the DIV FEM.
  • the second interface comprises several input connections each of which connect the input of a configurable LNA to an RF band output of the DIV FEM.
  • no external impedance matching components are utilised and all LNAs within the RFIC are configured to the internal input impedance matching topology where input matching is realised internally to each LNA circuit.
  • the configurable RFICs of embodiments of Figures 6 to 10 described below also comprise first and second interfaces which are arranged to connect the inputs of one or more configurable LNAs to the outputs of RF bands of the main and DIV FEMs respectively.
  • Figure 6 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 6 depict a scenario where a European network operator wishes to boost the sensitivity of RF Band 1.
  • the configurable LNA which is connected to the Band 1 RF output of the main FEM is configured to the external input impedance matching topology where the noise performance, and therefore, sensitivity of the main RX is improved using external input impedance matching components. Additionally, the leakage of the TX of the main receiver branch can be suppressed with such external matching.
  • the RF (duplex) filter In the diversity branch, however, there is no TX connected to the RF (duplex) filter. Since the main and div receivers operate at the same frequency, but the antennas are physically different and separate from each other, there is a finite isolation, for example 10 to 15 dB, between the two antennas. This means that the effect of the TX is less in the DIV branch than in the main branch since TX leakage is suppressed by the amount of antenna isolation. This means that external matching components are not mandatory in the DIV branch.
  • the configurable LNA which is connected to the Band 1 RF output of the DIV FEM is therefore configured to the internal input impedance matching topology where internal impedance matching components are used to keep component count and cost as low as possible.
  • a configurable LNA connected to the RF Band 1 output of the main FEM is configured to an external input impedance matching topology
  • a configurable LNA connected to the RF Band 1 output of the DIV FEM is configured to an internal input impedance matching topology.
  • Figure 7 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 7 depict a scenario where a US network operator wants to compensate the insertion losses due to the FEM at RF Band 2.
  • the configurable LNA which is connected to the Band 2 RF output of the main FEM is configured to the external input impedance matching topology where external matching components are required.
  • the configurable LNA which is connected to the Band 2 RF output of the DIV FEM is also configured to the external input impedance matching topology where external matching components are required. This means that on the PWB, one or more external matching components will be connected in-between the Band 2 RF output of the main FEM and the input of the appropriate configurable LNA in the RFIC's main interface. Similarly, one or more external matching components will be connected in-between the Band 2 RF output of the DIV FEM and the input of the appropriate configurable LNA in the RFIC's DIV interface.
  • RF Band 2 will extend to also cover G-block (Uplink frequencies: 1910- 1915MHz, Downlink frequencies: 1990- 1995MHz), thus forming even more challenging filtering scenario for duplexers.
  • G-block Uplink frequencies: 1910- 1915MHz, Downlink frequencies: 1990- 1995MHz
  • Figure 8 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 8 depict a scenario where a network operator utilising RF Band 20 (791 MHz - 821 MHz) wants to improve the sensitivity level.
  • the third harmonic of the RX band (2373-2463 MHz) partially overlaps with 2.4-GHz industrial, scientific and medical (ISM) band. Therefore, to mitigate the down-conversion from the third harmonic and to minimize the desensitization of the wanted channel, Interference-to-Signal-Ratio (ISR) performance can be improved with better selectivity provided by external input impedance matching components.
  • ISR Interference-to-Signal-Ratio
  • the configurable LNA which is connected to the Band 20 RF output of the main FEM is configured to the external input impedance matching topology where external matching components are required.
  • the configurable LNA which is connected to the Band 20 RF output of the DIV FEM is also configured to the external input impedance matching topology where external matching components are required. This means that on the PWB, one or more external matching components will be connected in-between the Band 20 RF output of the main FEM and the input of the appropriate configurable LNA in the RFIC's main interface. Similarly, one or more external matching components will be connected in-between the Band 20 RF output of the DIV FEM and the input of the appropriate configurable LNA in the RFIC's DIV interface.
  • Figure 9 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 9 depict a Carrier Aggregation (CA) scenario where additional loss due to complex FEM and filtering setup is partially compensated for with external matching components.
  • CA Carrier Aggregation
  • Both the main FEM and DIV FEM function using both RF band 3 and RF band 7 with the configurable RFIC processing signals from both RF band 3 and RF band 7 from each of the main FEM and DIV FEM accordingly.
  • the configurable LNA which is connected to the Band 3 RF output of the main FEM is configured to the external input impedance matching topology where external matching components are required.
  • the configurable LNA which is connected to the Band 7 RF output of the main FEM is also configured to the external input impedance matching topology where external matching components are required.
  • the configurable LNA which is connected to the Band 3 RF output of the DIV FEM is configured to the external input impedance matching topology where external matching components are required.
  • the configurable LNA which is connected to the Band 7 RF output of the DIV FEM is also configured to the external input impedance matching topology where external matching components are required
  • one or more external matching components will be connected in-between the Band 3 RF output of the main FEM and the input of the appropriate configurable LNA in the RFIC's main interface. Further, one or more external matching components will be connected in-between the Band 7 RF output of the main FEM and the input of the appropriate configurable LNA in the RFIC's main interface.
  • one or more external matching components will be connected in-between the Band 3 RF output of the DIV FEM and the input of the appropriate configurable LNA in the RFIC's DIV interface and one or more external matching components will be connected in-between the Band 7 RF output of the DIV FEM and the input of the appropriate configurable LNA in the RFIC's DIV interface.
  • Figure 10 illustrates an RF chipset on a PWB for a receiver comprising a configurable RFIC according to embodiments.
  • the embodiments of Figure 10 depict the most expensive and high-performance scenario where all LNAs within the RFIC are configured to the external input impedance matching topology where input matching is realised using external input matching components.
  • All configurable LNAs which are connected to outputs of the main FEM, such as RF Band outputs, are configured to the external input impedance matching topology where external matching components are required.
  • all configurable LNA which are connected to various outputs of the DIV FEM, such as RF Band outputs are configured to the external input impedance matching topology where external matching components are required.
  • one or more external matching components will be connected in-between RF band outputs of the main FEM and the inputs of the appropriate configurable LNAs in the RFIC's main interface.
  • one or more external matching components will be connected in-between RF band outputs of the DIV FEM and the inputs of the appropriate configurable LNAs in the RFIC's DIV interface.
  • a configurable RFIC according to embodiments can be adaptively configured according to the desire of the customer. Sensitivity can be improved if required at the cost of using external matching components and increasing PWB area. Improved selectivity can be achieved to suppress TX leakage or other radio systems (e.g. 2.4- GHz or 5 -GHz connectivity radios). Since the configurable LNAs within the RFIC can be matched without external input impedance matching components, the configurable RFIC embodiments provide a cost-efficient solution with high quality and reliability. Thus, embodiments provide a capability to trade-off between price and performance.
  • each of the one or more configurable low noise amplifier circuits comprises a switching arrangement.
  • Each of the circuits is configurable between one of an internal input impedance matching topology and a different topology via the respective switching arrangement.
  • the different topology may comprise a topology where one or more external components are required for input impedance matching.
  • the switching arrangement may comprise one or more topology switching means which may for example comprise switching transistors and/or bias voltage switching means. Switching arrangements for switching between a number of pairs of different internal input impedance matching and external input impedance matching topologies are described below in relation to Figures 11 to 20.
  • the internal input impedance matching topology comprises a common-gate low noise amplifier topology and the different topology comprises an inductively degenerated low noise amplifier topology.
  • Example configurable LNAs for such embodiments are described below in relation to Figures 11 to 13.
  • the internal input impedance matching topology comprises a resistive feedback low noise amplifier topology and the different topology comprises an inductively degenerated low noise amplifier topology.
  • Example configurable LNAs for such embodiments are described below in relation to Figures 11, 14 and 15.
  • the different topology comprises an inductively degenerated low noise amplifier topology and the internal input impedance matching topology comprises an impedance matching stage coupled to an input of the configurable low noise amplifier circuit, the output of the impedance matching stage providing an input bias voltage for the impedance matching stage, and a feedback stage coupled to an output of the impedance matching stage and a voltage source, the feedback stage providing a compensated operating voltage for the impedance matching stage.
  • the latter topology here is referred to below as a signal reusing topology.
  • Example configurable LNAs for such embodiments are described below in relation to Figures 11 and 16 to 20.
  • each of the one or more configurable low noise amplifier circuits comprises a common output terminal at which an output signal of the respective configurable low noise amplifier circuit is provided when configured in either the internal input impedance matching topology or the different topology.
  • the output of the circuit when configured in the first topology is produced at output terminal 260 and the output of the circuit when configured in the second topology is also produced at output terminal 260.
  • Such re -use of a single output terminal for both topologies provides a lower cost solution both for the configurable LNA itself and other components connecting to it than a solution requiring multiple output terminals.
  • a single, common, pair of output terminals can be employed for the case of a differential amplifier, rather than multiple pairs of output terminals for different configurations.
  • Such common output terminal features are especially beneficial in configurable RFIC embodiments described herein wherein multiple configurable LNAs are present.
  • LNA topology is the inductively degenerated LNA topology, a detailed analysis of which has been given in, for example, in D. K. Shaeffer and T. H. Lee, "A 1.5-V, 1.5 -GHz CMOS low noise amplifier,” IEEE J. of Solid-State Circuits, vol. 32, no. 5, May 1997, pp. 745-759.
  • each of transistors M2_p, M2_m, M3_p, M3_m is an enhancement mode n-channel metal-oxide-semiconductor field- effect transistor (MOSFET) (also referred to as 'NMOS').
  • MOSFET metal-oxide-semiconductor field- effect transistor
  • the differential amplifier amplifies the difference between the two input signals inp, inm applied to its input terminals 220 and 222, where the signal applied to input terminal 222 is a signal having the same magnitude as the signal applied to input terminal 220 but being 180 degrees out of phase with that signal (i.e. the signals have opposite phase).
  • the differential amplifier can be capable of rejecting signal components common to both its input signals whilst amplifying the difference between the two signals.
  • the degree to which the differential amplifier rejects signal components common to both its input signals whilst amplifying the difference between the two signals can be measured by the Common-Mode Rejection Ratio (CMRR) metric.
  • CMRR Common-Mode Rejection Ratio
  • the gate terminal of input transistor M2_p on the plus side of the amplifier is connected to a bias voltage source vbias ldeg via a first bias resistor Rblp.
  • the gate terminal of input transistor M2_p is also connected to an external matching component Lextp via a decoupling capacitor acclp.
  • Input terminal 220 is connected to external matching component Lextp.
  • External matching component Lextp is located on a separate circuit or device to the circuit containing the LNA of Figure 11 , i.e. matching component Lextp is 'off-chip' (denoted by dashed surrounding box in Figure 11). In this case, matching component Lextp is an inductor.
  • the gate terminals of input transistors M2_p and M2_m thus each form an input terminal of their respective input transistor.
  • the source and drain terminals of input transistors M2_p and M2_m therefore form output terminals of the input transistors.
  • the source terminal of each of the two input transistors M2_p and M2_m is connected to a different respective terminal of an inductor Ldeg.
  • Inductor Ldeg is a centre -tap differential inductor device with mutual coupling. Inductor Ldeg provides inductive degeneration of the source terminals of the two gain transistors M2_p and M2_m.
  • the centre -tap terminal of inductor Ldeg is connected to ground.
  • the drain terminal of gain transistor M2_p on the plus side of the differential amplifier is connected to the source terminal of cascode transistor M3_p.
  • the drain terminal of gain transistor M2_m on the minus side of the differential amplifier is connected to the source terminal of cascode transistor M3_m.
  • the gate terminals of cascode transistors M3_p and M3_m are both connected to the circuit voltage supply Vdd (a DC voltage). Note that a gate terminal DC voltage can be set to a level other than Vdd, such that the drain voltages of gain transistors M2_p,m can be set to a desired level in order to increase the available voltage swing at the drain terminals of cascode transistors M3_p,m.
  • the drain terminals of cascode transistors M3_p and M3_m are connected to output terminals 260 and 262 respectively, where 260 is the output terminal of the plus side of the differential amplifier at which output signal outp is produced, and 262 is the output terminal of the minus side of the differential amplifier at which output signal outm is produced.
  • the noise performance of the LNA topology depicted in Figure 11 is typically dominated by the noise performance of input transistors M2_p and M2_m.
  • the noise performance can be improved by optimizing the input matching network (for example including gain transistors M2_p and M2_m and external matching components Lextp and Lextm).
  • the input matching network preceding the input transistors provides passive voltage gain which can be measured as a ratio of the voltage swing observed at the gate to source terminal junction of the corresponding input transistor, e.g. M2_p, and the voltage swing at the LNA input.
  • a high value for this ratio is beneficial in reducing the drain current noise of input transistor M2_p, but it increases the induced gate current noise of the input transistor.
  • the inductively degenerated LNA requires several off-chip external matching components Lextp and Lextm, and thus tends to be relatively expensive.
  • a second known LNA topology is the common-gate LNA, a detailed analysis of which has been given in a journal publication entitled "A 4.5-mW 900-MHz CMOS Receiver for Wireless Paging," by Hooman Darabi and Asad A. Abidi published in IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August 2000.
  • the LNA of Figure 12 is a differential amplifier, where transistors Ml_p and M3_p form the positive or 'plus' side of the differential amplifier, and transistors Ml m and M3_m form the negative or 'minus' side of the differential amplifier.
  • the common-gate LNA of Figure 12 includes a common-gate LNA stage (labelled cg core in Figure 12) which includes input transistors Ml_p,m which are provided with appropriate bias voltages from voltage source vbias cg via bias resistors Rb2p,m.
  • the common-gate LNA stage also includes cascode transistors M3_p,m and inductors 250p,m.
  • the common-gate LNA stage of Figure 12 also contains a capacitor cf p,m between the gate of each input transistor and their output source terminals.
  • Lextp and Lextm are provided in the common-gate LNA of Figure 12.
  • Input transistors Ml p and Ml m are thus directly connected to the input terminals 220, 222 respectively, via decoupling capacitors acc2p and acc2m.
  • the common-gate LNA of Figure 12 is capable of matching the impedance connected to input terminals 220 and 222 internally within the LNA.
  • a common-gate LNA such as that depicted in Figure 12 has a capability for internal input impedance matching because the impedance at the source of an input transistor is inversely proportional to the transconductance g m .
  • the single- ended termination impedance is 50 ⁇ , and therefore a transconductance of approximately 20 mS is required.
  • a large impedance towards the signal ground is required in order to steer the signal into the source terminal of the input transistors which can be achieved with a current source connected to the respective source nodes.
  • a current source topology is not typically utilised due to associated poor noise performance and stacking of several transistors can lead to technology restrictions.
  • the noise parameter ⁇ can be much greater than unity, and a can be much less than unity.
  • an achievable noise figure tends to be around 3dB or greater. This means that the noise figure is somewhat higher for a common-gate LNA compared to an inductively degenerated common-source LNA.
  • a common-gate LNA can provide wideband matching without external matching components.
  • a common-gate LNA offers good linearity.
  • good input matching is also achieved in common-mode which results in good common-mode linearity as well.
  • a common-gate LNA has poorer noise performance and, depending on the application, it can require special attention in relation to interface design.
  • Embodiments relate to an LNA circuit that can be configured between one of a first topology in which the low noise amplifier circuit comprises a degeneration inductance stage such that the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit comprises a common-gate low noise amplifier stage such that the low noise amplifier circuit operates as a common-gate low noise amplifier.
  • first topology external matching components are used in conjunction with the LNA for input impedance matching purposes.
  • input impedance matching is carried out using components internal to the LNA topology; no external matching components are required in the second topology.
  • Input impedance matching may for example involve matching to the output impedance of an RF filter connected to one or more inputs of the LNA.
  • FIG. 13 An exemplary configurable LNA circuit according to the invention is illustrated in Figure 13. As with the LNAs of Figures 11 and 12, the exemplary LNA of Figure 13 is a differential amplifier, where transistors Ml_p, M2_p and M3_p form the positive or 'plus' side of the differential amplifier, and transistors Ml m, M2_m and M3_m form the negative or 'minus' side of the differential amplifier.
  • the exemplary configurable LNA circuit of Figure 13 contains a common-gate LNA stage (labelled cg_core) as per the common-gate LNA stage of the circuit of Figure 12.
  • the topology of the configurable LNA of Figure 13 necessarily contains some similar features to both the inductively degenerated LNA of Figure 1 1 and the common-gate LNA of Figure 12; however, there are several important differences which include the following:
  • the configurable LNA of Figure 13 contains a switching arrangement for configuring the LNA between one of the first topology and the second topology.
  • the switching arrangement contains a topology switching means, in this case switching transistors SWlp,m connected between an output of the degeneration inductance stage and an input of the configurable LNA.
  • the source terminals of SWlp,m are connected to the source terminals of the input transistors Ml_p,m of the common-gate LNA stage and the drain terminals of SWlp,m are connected to decoupling capacitors acc2p,m.
  • the source terminals of switching transistors SWlp,m are also connected to the source terminals of the input transistors M2_p,m of the inductively degenerated LNA stage.
  • the gate terminals of switching transistors SWlp,m are connected to a configuration control signal terminal, for example as labelled xLdeg in Figure 13.
  • the configurable LNA of Figure 13 instead of including both degeneration inductors in each side of the differential amplifier as per the inductively degenerated LNA of Figure 1 1 and also inductors at the source of the input transistors Ml_p, m in both sides of the differential amplifier as per the common-gate LNA stage of Figure 12, the configurable LNA of Figure 13 only comprises inductors 250p,m. Further, the inductor (Ldeg) in Figure 11 comprises a single centre -tapped inductor, whilst in Figures 12 and 13 there are two separate inductors 250p,m. These inductors are shared between the first and second topologies and usefully employed when the configurable LNA is configured in either topology. Such component re -use helps reduce costs and die area.
  • switching transistors SWlp,m can be switched between an open state, whereby the configurable LNA of Figure 13 is configured in the first topology, and a closed state, whereby the configurable LNA of Figure 13 is configured in the second topology.
  • the configurable LNA can be configured according to the desired use case. Sensitivity can be improved in the first, inductively degenerated configuration if required but at the cost of a requirement for external matching components. However, since in the second, common-gate configuration the configurable LNA can be matched without external input impedance matching components, a cost-efficient solution is provided. The second, common-gate configuration also provides better linearity than the first, inductively degenerated configuration. Thus, embodiments provide the possibility to trade-off between price and performance.
  • a switching transistor When in an open state, a switching transistor provides a high resistance between its drain and source terminals which effectively disconnects (or Open- circuits') the drain and source terminals.
  • a switching transistor may be placed in the open state by applying an appropriate control signal to the respective configuration control signal terminal such that the voltage between the gate terminal and the source terminal (i.e. the voltage V gs ) of the switching transistor is less (or approximately less) than the threshold voltage (i.e. the voltage V t ) of the switching transistor, i.e. a switching transistor may thus be described as being in cutoff mode.
  • a configuration control signal for configuring a switching transistor into an open state may for example comprise a digital '0' signal (such as a signal comprising a first voltage level).
  • a switching transistor When in a closed state, a switching transistor provides a low resistance between its drain and source terminals which effectively connects (or 'short-circuits') the drain and source terminals.
  • a switching transistor can be placed in the closed state by applying a configuration control signal to its control signal terminal such that the voltage between the gate terminal and the source terminal (i.e. the voltage V gs ) of the switching transistors is greater than the threshold voltage (i.e. the voltage V t ) of the switching transistor, i.e. a switching transistor may thus be described as being in triode mode.
  • a configuration control signal for configuring a switching transistor into a closed state may for example comprise a digital ' 1 ' (such as a signal comprising a second voltage level)
  • switching transistors SWlp,m are configured to an open state.
  • the switching arrangement also comprises a second bias voltage switching means adapted to set the bias voltage vbias cg to either a relatively high or a relatively low bias voltage.
  • the configurable low noise amplifier circuit is configurable in the first topology by using the second bias voltage switching means to set the bias voltage vbias_cg to a relatively low bias voltage. Applying a relatively low bias voltage to the input transistors Ml_p,m of the common-gate LNA stage biases the Ml_p,m transistors in an open state.
  • a relatively low bias voltage may for example comprise a zero bias voltage.
  • inductors 250p,m therefore provide inductive degeneration of the source terminals of input transistors M2_p, as in the inductively degenerated LNA o f Figure 11.
  • the configurable LNA thus operates as an inductively degenerated LNA when switching transistors SWlp,m are switched to an open state, i.e. when the configurable LNA is configured in the first topology.
  • the configurable LNA does not provide internal input impedance matching, for example matching to the output impedance of a preceding RF filter connected to input terminals 220 and 222.
  • the input impedance of the configurable LNA of Figure 13 can be matched, for example to a preceding RF filter, by connecting appropriate external impedance matching components.
  • the external matching components may for example comprise external matching components Lextp and Lextm, which are connected in-between decoupling capacitors acclp,m and input terminals 220 and 222 respectively.
  • the first topology of the configurable LNA of Figure 13 thus provides at least some of the benefits of the inductively degenerated LNA of Figure 11, including relatively low noise figure, but requires the use of external matching components in order to provide input impedance matching.
  • switching transistors SWlp,m are configured to a closed state.
  • the configurable low noise amplifier circuit is configurable in the second topology by using the first bias voltage switching means to set the bias voltage vbias_ldeg to a relatively low bias voltage. Applying a relatively low bias voltage to the input transistors M2_p,m of the inductively degenerated LNA stage biases the M2_p,m transistors to an open state.
  • the configurable low noise amplifier circuit is configurable in the second topology by using the second bias voltage switching means to set the bias voltage vbias_cg to a relatively high bias voltage. Applying a relatively high bias voltage to the input transistors Ml_p,m of the common-gate LNA stage biases the Ml_p,m transistors in a closed state.
  • the source terminals of input transistors Ml_p,m of the common-gate LNA stage are connected via inductors 250p,m, which are connected to ground.
  • Inductors 250p,m connected to the source terminals of input transistors Ml_p,m source are high impedance at the operating frequency and work as the DC-current path to ground for the second topology.
  • Inductors 250p,m remain in-circuit in both the first topology and the second topology such that embodiments use the area of an expensive (in terms of area) integrated inductor for two different purposes.
  • the same integrated inductor is used as a degeneration inductor in the inductively degenerated topology and as a DC feed inductor in the common-gate LNA topology.
  • the use of a single inductor in both topologies avoids one expensive on-chip component being required for one topology and another expensive on-chip component being required for the other topology.
  • the configurable LNA of Figure 13 thus provides an LNA that can be configured according to the desired use case or design requirements.
  • the LNA can be configured in the first topology if a more sensitive LNA with a better noise figure is required, at the cost of a need for external matching components, e.g. Lextp and Lextm, in order to provide impedance matching for the inputs of the configurable LNA.
  • the LNA can be configured in the second topology in order to provide a more cost effective solution with better linearity.
  • a further known LNA topology is the resistive feedback (or 'shunt-resistor') LNA, a detailed analysis of which has been given in C.-F. Liao and S.-I. Liu, "A broadband noise-cancelling CMOS LNA for 3.1-10.6-GHz UWB receivers," IEEE Journal of Solid-State Circuits, vol. 42, no. 2, Feb. 2007, pp. 329-339.
  • the LNA of Figure 14 is a differential amplifier, where transistors 200 and 210 form the positive or 'plus' side of the differential amplifier, and transistors 202 and 212 form the negative or 'minus' side of the differential amplifier.
  • no inductor Ldeg which provides inductive degeneration of the source terminals of the input transistors M2_p,m in the inductively degenerated LNA of Figure 11 , is present in the resistive feedback LNA of Figure 14. Instead, the source terminals of input transistors 200 and 202 of the resistive feedback LNA of Figure 14 are connected directly to ground.
  • the resistive feedback LNA of Figure 14 is capable of matching the impedance connected to input terminals 220 and 222 internally within the LNA.
  • Embodiments relate to an LNA circuit that can be configured between one of a first topology in which the low noise amplifier circuit comprises a degeneration inductance such that the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit comprises a feedback resistance such that the low noise amplifier circuit operates as a resistive feedback low noise amplifier.
  • first topology external matching components are used in conjunction with the LNA for input impedance matching purposes.
  • input impedance matching is carried out using components internal to the LNA topology; no external matching components are required in the second topology.
  • Input impedance matching may for example involve matching to the output impedance of an RF filter connected to one or more inputs of the LNA.
  • FIG. 15 An exemplary configurable LNA circuit according to the invention is illustrated in Figure 15. As with the LNAs of Figures 1 1 and 14, the exemplary LNA of Figure 15 is a differential amplifier, where transistors 200 and 210 form the positive or 'plus' side of the differential amplifier, and transistors 202 and 212 form the negative or 'minus' side of the differential amplifier.
  • the topology of the configurable LNA of Figure 15 necessarily contains some similar features to both the inductively degenerated low noise amplifier of Figure 11 and the resistive feedback LNA of Figure 14; however, there are several important differences which include the following:
  • the configurable LNA of Figure 15 contains a switching arrangement for configuring the LNA between one of the first topology and the second topology.
  • the switching arrangement contains a number of topology switching means.
  • the configurable LNA of Figure 15 includes feedback resistor 300 on the plus side of the differential amplifier.
  • feedback resistor 300 is connected to a topology switching means, in this case switching transistor 400, that is in turn connected to input terminal 220.
  • One of the drain terminal and source terminal of switching transistor 400 is connected to feedback resistor 300, whilst the other terminal is coupled to input terminal 220.
  • the gate terminal of switching transistor 400 is connected to a configuration control signal terminal 421. Topology switching means 400 is thus connected between the gate of input transistor 200 (via decoupling capacitor 240) and feedback resistor 300.
  • the configurable LNA of Figure 15 includes feedback resistor 302 on the minus side of the differential amplifier.
  • feedback resistor 302 is connected to a topology switching means, in this case switching transistor 402, that is in turn connected to input terminal 222.
  • One of the drain terminal and source terminal of switching transistor 402 is connected to feedback resistor 302, whilst the other terminal is coupled to input terminal 222.
  • the gate terminal of switching transistor 402 is connected to a configuration control signal terminal 423. Topology switching means 402 is thus connected between the gate of input transistor 202 (via the decoupling capacitor 242) and feedback resistor 302.
  • an inductor 250 is present in the configurable LNA of Figure 15.
  • a topology switching means in this case a switching transistor 410, is connected between the source terminals of input transistors 200 and 202.
  • One of the drain terminal and source terminal of switching transistor 410 is connected to the source terminal of input transistor 200, whilst the other terminal is connected to the source terminal of input transistor 202.
  • the gate terminal of switching transistor 410 is connected to a configuration control signal terminal 425.
  • decoupling capacitors 430 and 432 provide DC decoupling from the supply voltage in order to increase switching performance of switching transistors 400 and 402 respectively.
  • switching transistors 400, 402 and 410 can be switched between an open state, whereby the configurable LNA of Figure 15 is configured in the first topology, and a closed state, whereby the configurable LNA of Figure 15 is configured in the second topology.
  • switching transistors 400, 402 and 410 are configured to an open state.
  • switching transistors 400 and 402 are configured to an open state.
  • feedback resistors 300 and 302 are effectively disconnected from the input signals applied to input terminals 220 and 222, respectively.
  • inductor 250 By configuring switching transistor 410 to an open state, the source terminals of input transistors 200 and 202 are effectively connected only via inductor 250, whose centre -tap is connected to ground. Inductor 250 therefore provides inductive degeneration of the source terminals of input transistors 200 and 202, as in the inductively degenerated LNA of Figure 11.
  • the configurable LNA thus operates as an inductively degenerated LNA when switching transistors 400, 402 and 410 are switched to an open state, i.e. when the configurable LNA is configured in the first topology.
  • the configurable LNA when configured in the first topology, does not provide internal input impedance matching, for example matching to the output impedance of a preceding RF filter connected to input terminals 220 and 222.
  • the input impedance of the configurable LNA of Figure 15 should be matched, for example to a preceding RF filter, by connecting external impedance matching components, for example external matching components 230 and 232 as depicted in the inductively degenerated LNA of Figure 11 , in-between decoupling capacitors 240, 242 and input terminals 220 and 222 respectively.
  • the first topology of the configurable LNA of Figure 15 thus provides the benefits of the inductively degenerated LNA of Figure 11 , i.e. relatively low noise figure, but requires the use of external matching components in order to provide input impedance matching.
  • switching transistors 400, 402 and 410 are configured to a closed state.
  • switching transistors 400 and 402 By configuring switching transistors 400 and 402 to a closed state, feedback resistors 300 and 302 are effectively connected to the input terminals 220 and 222, respectively.
  • a feedback loop is present between output terminals 260 and 262 and input terminals 220 and 222, respectively (and thus the input terminals of input transistors 200 and 202, respectively, via decoupling capacitors 240 and 242).
  • the configurable LNA thus operates as a resistive feedback LNA when switching transistors 400, 402 and 410 are configured to a closed state, i.e. when the configurable LNA is configured in the second topology.
  • the configurable LNA when configured in the second topology, provides internal input impedance matching, for example matching to the output impedance of a preceding RF filter connected to input terminals 220 and 222.
  • external matching components for example external matching components
  • Lextp and Lextm as depicted in the inductively degenerated LNA of Figure 11 are not required when the configurable LNA is configured in the second configuration state.
  • switching transistor 410 When the configurable LNA of Figure 15 is configured in the second topology, switching transistor 410 is configured to a closed state; this provides additional benefits, as will now be described.
  • switching transistor 410 By configuring switching transistor 410 to a closed state, the source terminals of the input transistors 200 and 202 are effectively connected (i.e. short-circuited).
  • the connection formed by switching transistor 410 between the source terminals of input transistors 200 and 202 is in parallel to inductor 250 which connects the source terminals of the input transistors 200 and 202.
  • inductor 250 is a differential inductor device with mutual coupling.
  • the mutual coupling of the differential inductor device causes the inductor to operate differently for common- mode signals applied to the differential amplifier, compared to differential-mode signals applied to the differential amplifier.
  • Common-mode signals applied to the differential amplifier are signal components that have the same magnitude and same phase in the respective input signals applied to input terminals 220 and 222.
  • differential-mode signals are signal components that have the same magnitude and opposite phase in the respective input signals applied to input terminals 220 and 222.
  • inductor 250 remains active, providing an inductance equivalent to:
  • the inductance provided by inductor 250 (as per equation (1) above) in relation to common-mode signals forms an impedance that serves to attenuate interference and other noise from the ground voltage supply.
  • the power supply noise rejection performance for example as demonstrated by a higher Power Supply Rejection Ratio (PSRR) metric, of the configurable LNA when configured in the second topology is thus improved.
  • the degeneration inductance provided by inductor 250 is thus adapted to provide a power supply noise rejection impedance when the configurable LNA is configured in the second topology.
  • the inductance provided by inductor 250 in relation to common-mode signals forms a degeneration inductor for the source terminals of input transistors 200 and 202.
  • a degeneration inductor serves to improve the common-mode rejection performance, for example as demonstrated by a higher CMRR metric, of the configurable LNA when configured in the second topology.
  • the degeneration inductance provided by inductor 250 is thus adapted to provide a common-mode signal rejection impedance in relation to signal components common to input signals applied to input terminals 220 and 222 when the configurable LNA is configured in the second topology.
  • the configurable LNA enables such improvements in CMRR in a resistive feedback LNA topology by 'borrowing' the inductor Ldeg from the inductively degenerated LNA of Figure 11.
  • the 'borrowing' of the inductor Ldeg also ensures that an expensive (in terms of chip area) on-chip component from the first topology of the configurable LNA is used in both configurations of the configurable LNA.
  • the LNA can be configured in the first topology if a more sensitive LNA with a better noise figure is required, at the cost of a need for one or more external matching components, e.g. Lextp and Lextm, in order to provide impedance matching for the inputs of the configurable LNA.
  • external matching components e.g. Lextp and Lextm
  • the signal reusing LNA has wideband matching for differential as well as for common mode signals. Therefore, the good differential linearity is also retained for common mode signals.
  • a further gain stage parallel to the input impedance matching stage increases the LNA gain.
  • the amplified signal at the output of the input impedance matching stage is reused in order to decrease the noise contribution of the following transistors.
  • the signal reusing LNA can be biased without the need for large-value AC-coupling capacitors at the LNA input. Due to the lack of passive voltage gain prior to the signal reusing LNA input stage, the noise figure is higher compared to an inductively degenerated LNA. Furthermore, there are additional noise sources in addition to the gain transistors. However, since the signal reusing LNA does not require external components nor an additional on-chip source inductor for input impedance matching, the overall cost is much lower compared to an inductively degenerated LNA.
  • the signal reusing topology provides a cost-efficient solution.
  • Certain exemplary embodiments of this disclosure achieve high gain and therefore reduce the noise contribution of processing stages following an LNA. This can be seen when applying Friis' equation: the noise factors for subsequent components are divided by the power gain of a preceding LNA.
  • Certain exemplary embodiments of differential LNA provide good input impedance matching over a wide bandwidth for differential as well as for common-mode signals, which in turn results in good common-mode linearity.
  • An LNA according to some embodiments has compensation for temperature, process, corner, and ageing effects and offers no restrictions when choosing an interface to mixer and analogue baseband components.
  • the LNA removes the need for direct current (DC)-coupling capacitors for input transistor devices, which leads to a smaller die area being used when compared to prior art LNAs.
  • DC direct current
  • Figure 16 shows a schematic illustration of one or more stages in one of the sides of a differential amplifier of a signal reusing LNA according to embodiments. Certain features of the differential amplifier are omitted, such as a coupling to a further side of the differential amplifier and ground, to better demonstrate the conceptual aspects of the embodiments.
  • the stages shown in Figure 16 have a signal inp applied at input terminal 220.
  • the input terminal is coupled to an impedance matching stage 410.
  • the impedance matching stage 410 acts to match an input impedance seen at the input terminal 220.
  • one or more components of the impedance matching stage 410 may have a combined impedance that matches any impedance of receiver processing stages upstream of the LNA such as a front-end module, RF filter, duplex filter, etc.
  • the input terminal 220 is further electrically coupled to a gain stage 420, i.e. the impedance matching stage 410 and the gain stage 420 are both coupled in parallel to the input terminal 220. Having a gain stage 420 in parallel with the impedance matching stage 410 increases the gain of the LNA. As approximately illustrated by the relative size of the stages in Figure 16, the gain of the gain stage 420 is greater than any gain provided by the impedance matching stage 410. Gain stage 420 is coupled to the output terminal 260 at which output signal outp is produced.
  • the output of the impedance matching stage 410 (node A) is coupled to a feedback stage 430.
  • the output of the impedance matching stage 410 also contributes to the output outp of the system, in the present example, via a second gain, signal processing or signal reuse stage 440.
  • the impedance matching stage 410 may be coupled to the output terminal 260 without signal reuse stage 440, for example via other components that maintain a high impedance at node A, such that the LNA still provides adequate impedance matching.
  • the outputs of the signal reuse stage 440 and the gain stage 420 are combined to produce output signal outp. This may be achieved by coupling the outputs of both stages at node B so that two output current signals are constructively combined.
  • both the gain stage 420 and the signal reuse stage share the same DC current path thus optimising the current consumption of the LNA.
  • the impedance matching stage 410 By coupling the output of the impedance matching stage 410 to the output terminal 260, e.g. via signal reuse stage 440, it may be said that the result of the impedance matching stage 410 is "reused", i.e. is subsequently used to produce the output of the amplifier, in the present example via a further gain stage.
  • the impedance matching functionality of the impedance matching stage 410 could be provided without electrically coupling the impedance matching stage 410 to the output terminal 260, e.g. without any coupling between node A and node B.
  • the reuse of a signal that has been processed, and in some cases amplified, by the impedance matching stage 410 decreases noise contributions, i.e.
  • the impedance matching stage 410 uses feedback stage 430.
  • the feedback stage 430 comprises a feedback amplifier, however other functionally similar feedback arrangements with or without gain may be used in other implementations.
  • the output of the impedance matching stage 410 which may comprise a current and voltage at point A, is coupled to an inverting input 434 of the feedback amplifier.
  • the non-inverting input 432 of the amplifier is coupled to a voltage source 435, which provides a configurable voltage bias, vbias.
  • the voltage bias vbias may be an internally or externally created bias voltage (from the perspective of an integrated LNA). It may be generated using a resistor and a constant current for example. It may also use a proportional to absolute temperature (PTAT) current or voltage reference to accommodate changes in temperature.
  • the output 436 of the feedback stage 430 is coupled to a voltage bias 415 for the impedance matching stage 410, i.e. a voltage that is used to set an operating point for the impedance matching stage 410.
  • the feedback provided by feedback stage 430 in use and over time, sets the (DC) voltage at node A to the applied voltage bias vbias. For example, this may be achieved in steady state operation.
  • the voltage at node A defines an input bias voltage for the impedance matching stage 410 and the gain stage 420 (see description of Figure 18 below).
  • This has the advantage of avoiding the use of any AC-coupling capacitors and bias resistors to bias the input voltages of stages 410 and 420, thus reducing the cost and size of an integrated LNA.
  • the feedback stage 430 compensates for temperature and corner variations in one or more transistor devices that make up the LNA, such as transistors that implement the impedance matching stage 410. By changing the voltage bias 415 of at least the impedance matching stage 410 the LNA can compensate for comer effects and ageing. This is important in mass-produced circuits (i.e.
  • the feedback stage 430 also improves productivity by enabling configuration of the LNA to optimise performance, e.g. by compensating for at least one of corner, temperature, and ageing variations that can reduce performance.
  • an input bias voltage for the impedance matching state 410 and the gain stage 420 can be provided without large value alternating current (AC) coupling capacitors or bias resistors at the input to the LNA being required.
  • AC coupling capacitors are typically of a large size, this further avoids the need for a large die area.
  • the lack of bias resistors results in a better noise factor performance in blocking conditions.
  • FIG 17 shows an implementation of feedback stage 430 that is, for example, suitable for use in the LNA of Figure 18 described below.
  • This implementation uses a feedback amplifier XI to provide common-mode feedback functionality.
  • the non- inverting input 432 of amplifier XI is coupled to a voltage source, for example source 435 in Figure 16, which provides the configurable voltage bias, vbias.
  • the output 436 of the feedback stage 430 is coupled to a voltage bias 415 for a PMOS (P-channel metal-oxide-semiconductor field-effect transistor, PMOS being shorthand for P- MOSFET) transistor that implements impedance matching stage 410.
  • PMOS P-channel metal-oxide-semiconductor field-effect transistor
  • the PMOS voltage bias pmos vbias and the common-mode feedback input cm fb may be coupled to the equivalent point in Figure 18, as described below.
  • the common-mode feedback circuit XI compensates for temperature and corner variations in one or more transistor devices that make up the LNA, such as NMOS transistors. By changing the PMOS voltage bias pmos vbias, a NMOS/PMOS ratio can be kept constant across different temperature, ageing and process effects. As described above, this offers a more robust solution.
  • the LNA circuit of Figure 18 has two sides, 605 and 610, which together form a differential amplifier. Differential side 605 is arranged to process input signal inp provided at terminal 220 whereas differential side 610 is arranged to process input signal inm provided at terminal 222. Differential side 605 produces an output signal outp at output terminal 260 and differential side 610 produces an output signal outm at output terminal 262.
  • the topology of Figure 18 is symmetrical, i.e. the configuration of the first differential amplifier side 605 is replicated in the second differential amplifier side 610.
  • the first differential amplifier side 605 may relate to a non-inverting, "plus” or positive side and the second differential amplifier side 610 may relate to an inverting, "minus” or negative side of an LNA (or vice versa).
  • the functionality of the first differential amplifier side may alternatively be implemented without the second differential amplifier side to provide a single-ended amplifier.
  • an impedance matching stage such as stage 410 in Figure 16, is implemented by transistors Ml_p and M3_p and feedback resistor Rf .
  • transistor Ml_p is an NMOS transistor and transistor M3_p is a PMOS transistor.
  • Transistors Ml_p and M3_p form a feedback portion of the LNA.
  • the gate terminal of transistor Ml_p is coupled to input terminal 220.
  • the source terminal of transistor Ml_p is coupled to ground.
  • the drain terminal of transistor Ml p is coupled to the drain terminal of transistor M3_p via node A.
  • the source terminal of transistor M3_p is coupled to voltage supply vdd.
  • the gate terminal of transistor M3_p is coupled to input terminal 220 via AC coupling capacitor accl_p and is also coupled to pmos vbias, a PMOS voltage bias provided by feedback amplifier XI, via a resistor Rpv.
  • AC coupling capacitor accl_p enables an AC signal to pass through from input terminal 220 to the gate of transistor M3_p but blocks any DC component so as to isolate the DC voltage bias seen at the gate of transistor M3_p from that seen at the gate of transistor Ml_p. This enables the DC voltage bias seen at the gate of the transistor M3_p to be set by pmos vbias.
  • applying the PMOS voltage bias pmos vbias to the gate of PMOS transistor M3_p implements the application of a voltage bias to impedance matching stage 410 as described above with regard to Figure 16.
  • Resistor Rpv acts to separate the two differential amplifier sides 605 and 610 (i.e. p and m). Without this resistor in each differential amplifier side, the PMOS gates of each differential amplifier side would short-circuit via the gate connections of M3_p and M3_m.
  • pmos vbias is coupled to the output pmos vbias of amplifier XI as shown in Figure 17.
  • the same pmos vbias is also applied to the other differential side, i.e. both pmos vbias nodes are coupled to the pmos vbias output of feedback amplifier XI .
  • the AC coupling capacitor accl_p need only have a small capacitance, for example less than lpF. This minimises the parasitic capacitance at critical nodes within the circuit and minimises the cost and die area required by circuit capacitors.
  • the transconductances of devices Ml_p and M3_p with feedback resistor Rfb match the input impedance of the LNA shown in Figure 18 to a desired source impedance.
  • this input impedance may be 100 ohms differential, 50 ohms single -ended.
  • Node A may be considered to be the output of an impedance matching stage implemented by transistors Ml_p and M3_p and feedback resistor Rfb.
  • Node A is also coupled to the common-mode feedback input cm fb of amplifier XI as shown in Figure 17 via resistor Rem. Any voltage signal at node A is sensed using resistor Rem without interfering with any AC signal present at node A.
  • a voltage bias vbias is applied to amplifier XI .
  • Feedback amplifier XI which implements common-mode feedback stage 430, acts to modify the PMOS voltage bias signal pmos vbias that biases PMOS transistor M3_p (e.g. sets the operating point for the transistor by setting the voltage at the gate of the transistor) such that, in use, the voltage at node cm fb equals the voltage bias vbias.
  • the input bias voltages for the impedance matching stage 410 and the gain stage 420 are, in this example, based on vbias.
  • a gain stage is implemented by gain transistor M2_p in differential amplifier side 605 and gain transistor M2_m in differential amplifier side 610.
  • these transistors are NMOS transistors.
  • the gate terminal of gain transistor M2_p is coupled to the input terminal 220.
  • the gate terminal is subject to a (DC) voltage bias as set by the voltage at point A and feedback resistor Rfb, i.e. the same voltage bias set for transistor Ml_p.
  • the source terminal of gain transistor M2_p is coupled to ground.
  • the drain terminal of gain transistor M2_p is coupled to node B.
  • a signal reuse stage is implemented by transistor M4_p.
  • the source terminal of transistor M4_p is also coupled to node B.
  • a gate terminal of transistor M4_p is coupled to voltage supply vdd via resistor Rm4.
  • the voltage bias for transistor M4_p could be replaced with an alternate bias voltage, for example a proportion of vdd such as 0.75* vdd.
  • the gate voltage bias, vdd in this case is selected such that transistor M4_p operates as a linear amplifier.
  • the gate terminal of transistor M4_p is further coupled to node A via AC coupling capacitor acc2_p. Again, capacitor acc2_p need only be small, e.g.
  • the impedance matching stage further amplifies the input signal inp, i.e. acts as a constant transconductance (gm) amplifier, to produce an amplified (AC) signal at node A.
  • This amplified signal is "reused" in the first gain stage.
  • the amplified signal at node A is applied to the gate terminal of transistor M4_p, which further amplifies the signal to produce a further amplified signal at node B with high current and low noise characteristics.
  • node A need not be coupled to a further portion of differential side 605, i.e. the impedance matching function could be achieved without the coupling of node A and the gate terminal of transistor M4_p.
  • certain embodiments use (“reuse” when considering a first use as part of the impedance matching function) the signal at node A to provide better LNA performance.
  • another form of coupling other than a buffer or amplifying transistor may be used such that the signal at A is reused at B.
  • transistor M5_p is an NMOS transistor.
  • a source terminal of transistor M5_p is electrically coupled to node B.
  • a drain terminal of transistor M5_p is electrically coupled to node C.
  • a gate terminal of transistor M5_p is coupled to voltage source vdd (as well as a gate terminal of transistor M5_m, which forms part of the second differential side 610).
  • the gate bias voltage of transistor M5_m should follow the gate bias voltage of transistor M4_m.
  • Node C is at least coupled to output terminal 260 and a tuneable LC resonator 270, 280.
  • the tuneable LC resonator implements a configurable load that is at least electrically coupled to both drain terminals of transistors M5_p,m.
  • the tuneable LC resonator comprises a variable capacitor in parallel with a centre -tap differential inductor; the centre -tap differential inductor is electrically coupled to the voltage supply vdd.
  • a gate terminal DC voltage for transistors M5_p,m can be set to a level other than vdd, such that the drain voltage of gain transistor M2_p can be set to a desired level in order to increase the available voltage swing at the drain terminal of transistor M5_p. If the gate terminal DC voltage for transistors M5_p,m is to be changed, it is recommended to also change the gate terminal DC voltage for transistor M4_p accordingly, so as to maintain sufficient performance characteristics.
  • a current steering cascode X2 may be provided between the drain terminal of each of transistors M5_p,m and the tuneable LC resonator / each output.
  • Node B thus outputs from the gain stage a high signal current with low noise to the cascode or buffer stage, which is then fed as a current through the M5_p cascode transistor, which is in turn followed by the tuneable LC resonator 270, 280.
  • At least resistors Rem, Rpv, and Rm4 have large values, i.e. values with an order of magnitude around 10 kOhms.
  • the exact values of the resistors, and the capacitors, described herein may be selected using standard design practices, based on implementation specifications.
  • the current consumption of the LNA can be reduced.
  • Certain embodiments described herein provide an advantage of achieving good noise performance, i.e. having a low noise factor, without external matching components. Certain embodiments also have a low current consumption, for example when compared with known resistive feedback LNAs.
  • Embodiments can comprise a fully integrated differential amplifier on a single chip. By suitably biasing gain and impedance matching stages, in particular transistors implementing those stages, at least one of accurate gain, linearity, noise, and input impedance matching may be achieved despite at least one of differing manufacturing processes, temperature effects, variations in supply voltage and aging conditions. Certain embodiments enable the transconductances of MOSFET devices to be accurately set to mitigate the aforementioned variations.
  • this is achieved by biasing transistors Ml and M2 using resistive feedback and a DC bias point set with a constant transconductance circuit and a common-mode feedback stage.
  • the use of at least the resistive feedback further avoids the need to use additional DC-biasing resistors to bias voltages seen by transistors Ml and M2.
  • Embodiments described herein minimise the number of biasing resistors and AC-coupling capacitors, such that costs and die area, i.e. the area taken up by an integrated chip on a substrate, are minimised. This makes certain embodiments attractive for implementations requiring a number of LNAs for different frequency bands.
  • Certain LNA embodiments presented herein provide common-mode matching and good common-mode linearity. They further provide wideband input impedance matching, i.e. impedance matching across a wide range of RF signal frequencies. This wideband matching occurs without the need for specific frequency calibration.
  • the topology of Figure 18 is capable of matching frequencies in the range 0 to 3GHz. This is due to there being an absence of frequency selecting components in the topology and the lack of any inductors as a source load, as for example is found with an inductively degenerated LNA. This results in better attenuation against far away signal blockers such as transmitters, wireless networks and BluetoothTM signals, as for example compared to known resistive feedback LNAs.
  • Wideband matching further avoids degradation of duplex filter performance, which may occur if the impedance matching does not occur over the frequency range processed by the duplex filter. It also avoids desensitising of a receiver front end and intermodulation products.
  • no inductor Ldeg which provides inductive degeneration of the source terminals of gain transistors M2_p,m in the inductively degenerated LNA of Figure 11 , is present in the signal reusing LNA of Figure 18. Instead, the source terminals of input transistors M2_p,m of the gain stage of the signal reusing LNA of Figure 18 are connected directly to ground.
  • the signal reusing LNA of Figure 18 is capable of matching the impedance connected to input 220 and 222 internally within the LNA.
  • Lextp and Lextm present in the signal reusing LNA of Figure 18 that provide a passive voltage gain prior to transistors Ml_p,m, M2_p,m, as described above for the inductively degenerated LNA of Figure 1 1 , so the noise effects of gain transistors M2_p, m are not mitigated.
  • additional noise sources in the signal reusing LNA of Figure 18 between the output terminals 260 and 262 and input terminals 220 and 222 of the LNA.
  • the noise performance of the signal reusing LNA of Figure 18 is worse compared to the inductively degenerated LNA of Figure 11.
  • the signal reusing LNA of Figure 18 does not require external matching components Lextp and Lextm, nor inductor Ldeg for inductive degeneration, the overall cost of the signal reusing LNA of Figure 18 is lower compared to that of the inductively degenerated LNA of Figure 11.
  • Some embodiments relate to an LNA circuit that can be configured between one of a first topology in which the low noise amplifier circuit comprises a degeneration inductance such that the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology, referred to herein as a signal reusing topology.
  • In the first topology one or more external input impedance matching components are used in conjunction with the LNA for input impedance matching purposes.
  • input impedance matching is carried out using components internal to the LNA topology; no external matching components are required in the second topology.
  • Input impedance matching may for example involve matching to the output impedance of an RF filter connected to one or more inputs of the LNA.
  • the topology of the configurable LNA of Figure 19 necessarily contains some similar features to both the inductively degenerated low noise amplifier of Figure 11 and the signal reusing LNA of Figure 18; however, there are several important differences which include the following:
  • the configurable LNA of Figure 19 contains a switching arrangement for configuring the LNA between one of the first inductively degenerated topology and the second, signal reusing topology.
  • the switching arrangement comprises a number of topology switching means.
  • the configurable LNA of Figure 19 includes input impedance stage 410, feedback stage 430 and signal reusing stage 440.
  • input impedance matching stage 410 is connected to a topology switching means, in this case switching transistor SW2p, that is in turn coupled to input terminal 220.
  • switching transistor SW2p is connected to feedback resistor Rf and AC coupling capacitor accl_p, whilst the source terminal is connected to input terminal 220.
  • the gate terminal of switching transistor SW2p is connected to a configuration control signal terminal xLdeg2.
  • Topology switching means SW2p is thus connected between the gate of transistor Ml_p and feedback resistor Rf and AC coupling capacitor accl_p.
  • the minus side of the differential amplifier is similarly connected with a topology switching means SW2m connected to the gate of transistor Ml m.
  • a topology switching means in this case a switching transistor SW3p, is connected between the first bias resistor Rbp and the bias voltage source vbias.
  • the drain terminal of switching transistor SW3p is connected to Rbp, whilst the source terminal is connected to vbias.
  • a topology switching means in this case a switching transistor SW3m, is connected between the second bias resistor Rbm and the bias voltage source vbias.
  • switching transistors SW1 , SW2p,m can be switched to an open state and SW3p,m can be switched to a closed state, whereby the configurable LNA of Figure 19 is configured in the first, inductively degenerated topology.
  • switching transistors SW1, SW2p,m can be switched to a closed state and SW3p,m can be switched to an open state, whereby the configurable LNA of Figure 19 is configured in the second, signal reusing topology.
  • the configurable low noise amplifier can be configured between the first and second topologies by using a switching arrangement.
  • the switching arrangement comprises a number of topology switching means, which in embodiments comprise switching transistors.
  • the configurable low noise amplifier circuit is configurable in the first topology by coupling the output of feedback amplifier XI of feedback stage 430 on both the plus and minus sides of the differential amplifier to the positive supply voltage vdd in order to open the M3_p,m transistors.
  • the common mode feedback amplifier XI on both the plus and minus sides of the differential amplifier is disabled by connecting its enable input to an appropriate control signal.
  • the configurable low noise amplifier circuit is configurable in the first topology by opening the signal reusing M4_p,m transistors. This can be achieved by applying an appropriate control signal to the gates of the M4_p,m transistors, for example a relatively low control signal compared to when the configurable low noise amplifier circuit is configured in the second topology.
  • Transistors Ml_p,m, M3_p,m and M4_p,m are opened and therefore not affecting the circuit operation (such components being shown in grey instead of black in Figure 20).
  • the common mode feedback of feedback amplifier XI is disabled and the bias resistors Rpv and Rem connected to XI in addition to resistor Rf have no effect on the operation of the configurable low noise amplifier. Since in this configuration the input impedance matching stage (denoted XMATCH in Figures 19 and 20) is disabled, input impedance matching is achieved using external matching components Lextp and Lextm.
  • inductor Ldeg By configuring switching transistor SW1 to an open state, the source terminals of input transistors M2_p,m are effectively connected only via inductor Ldeg, whose centre -tap is connected to ground. Inductor Ldeg therefore provides inductive degeneration of the source terminals of input transistors M2p,m, as in the inductively degenerated LNA of Figure 11.
  • the configurable LNA when configured in the first topology, does not provide internal input impedance matching, for example matching to the output impedance of a preceding RF filter connected to input terminals 220 and 222.
  • the input impedance of the configurable LNA of Figure 20 should be matched, for example to a preceding RF filter, by connecting external impedance matching components, for example external matching components Lextp and Lextm as depicted in the inductively degenerated LNA of Figure 11.
  • switching transistors SW1 and SW2p,m are configured to a closed state and switching transistors SW3p,m are configured to an open state.
  • input impedance matching stage 410 and feedback stage 430 (collectively denoted XMATCH in Figure 19) and signal coupling stage 440 are connected such that the circuit operation is identical to that of the signal reusing LNA depicted in Figure 18.
  • Input impedance matching is achieved (via XMATCH) without use of any external matching components such as Lextp and Lextm.
  • the configurable low noise amplifier circuit is configurable in the second topology by decoupling the output of feedback amplifier XI of feedback stage 430 on both the plus and minus sides of the differential amplifier from the positive supply voltage vdd such that the M3_p,m transistors are closed. Further, the common mode feedback amplifier XI on both the plus and minus sides of the differential amplifier is enabled by application of an appropriate control signal to its enable input.
  • the configurable low noise amplifier circuit is configurable in the second topology by closing the signal reusing M4_p,m transistors. This can be achieved by applying an appropriate control signal to the gates of the M4_p,m transistors, for example a relatively high control signal compared to when the configurable low noise amplifier circuit is configured in the first topology.
  • the configurable LNA When configured in the second topology, the configurable LNA provides internal input impedance matching, for example matching to the output impedance of a preceding RF filter connected to input terminals 220 and 222.
  • external matching components for example external matching components Lextp and Lexpm as depicted in the inductively degenerated LNA of Figure 11 , are not required.
  • switching transistor SW1 is configured to a closed state; this provides additional benefits, as will now be described.
  • inductor Ldeg is a differential inductor device with mutual coupling. The mutual coupling of the differential inductor device causes the inductor to operate differently for common- mode signals applied to the differential amplifier, compared to differential-mode signals applied to the differential amplifier.
  • connection formed by switching transistor SW1 between the source terminals of input transistors M2_p,m forms a virtual ground for the differential signal.
  • the configurable LNA enables an improvement in the PSRR in a signal reusing LNA topology by 'borrowing' the inductor Ldeg from the inductively degenerated LNA topology.
  • the 'borrowing' of inductor Ldeg also ensures that an expensive (in terms of chip area) on-chip component from the first topology of the configurable LNA can be used in both configurations of the configurable LNA.
  • the configurable LNA enables an improvement in the CMRR in a signal reusing LNA topology by 'borrowing' the inductor Ldeg from the inductively degenerated LNA of Figure 11.
  • the 'borrowing' of the inductor Ldeg also ensures that an expensive (in terms of chip area) on-chip component from the first topology of the configurable LNA can be used in both configurations of the configurable LNA.
  • the LNA can be configured in the first topology if a more sensitive LNA with a better noise figure is required, at the cost of a need for external matching components, e.g. Lextp and Lextm, in order to provide impedance matching for the inputs of the configurable LNA.
  • the LNA can be configured in the second topology in order to provide a more cost effective solution.
  • the configurable RFIC of embodiments may be configured by its manufacturer, or by a third party installing one or more configurable RFICs, for example in a device or module thereof; this may involve a method of configuring a configurable RFIC comprising one or more configurable low noise amplifier circuits.
  • the configuring method may comprise applying one of a first set of one or more control signals to at least one of the one or more circuits to configure the at least one circuit in an internal input impedance matching topology in which the respective low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, the one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit, or a second set of one or more control signals to at least one of the one or more circuits to configure the at least one circuit in a different topology in which the respective low noise amplifier circuit does not comprise the one or more internal input impedance matching components.
  • a set of control signals may for example be applied to one or more switching transistors and/or bias voltage switching means.
  • the configurable RFIC of embodiments can be incorporated in a number of different devices.
  • a device could comprise a user equipment such as a mobile station, personal digital assistant or cellular telephony device etc.; the configurable RFIC may for example be included in a receiver of such a user equipment.
  • a device could comprise a modem device to be attached to a user equipment, for example a Universal Serial Bus (USB) modem.
  • a device could comprise a communication module such as a Machine -to-Machine (M2M) module which can be inserted into another device such as a laptop computer or other device with communication capability (for example a vending machine).
  • M2M Machine -to-Machine
  • Such a device could comprise a chipset which may include radio and baseband parts.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

Les modes de réalisation de la présente invention concernent des circuits intégrés radiofréquence (RFIC) configurables. Dans un mode de réalisation, un circuit intégré radiofréquence comprend un ou plusieurs circuits amplificateurs faible bruit configurables, chacune desdits circuits amplificateurs faible bruit configurables étant configurable entre : une topologie d'adaptation de l'impédance d'entrée interne, dans laquelle le circuit amplificateur faible bruit concerné comprend un ou plusieurs éléments d'adaptation de l'impédance d'entrée interne conçus pour adapter l'impédance d'entrée de l'amplificateur faible concerné par rapport à une entrée donnée, ledit ou lesdits éléments d'adaptation de l'impédance d'entrée interne étant placés à l'intérieur du circuit amplificateur faible bruit concerné; et une topologie différente de ladite topologie d'adaptation de l'impédance d'entrée.
PCT/IB2012/052499 2011-05-19 2012-05-18 Circuit intégré radiofréquence WO2012156946A1 (fr)

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CN201280034977.4A CN103843248A (zh) 2011-05-19 2012-05-18 射频集成电路
EP12727440.5A EP2710728A1 (fr) 2011-05-19 2012-05-18 Circuit intégré radiofréquence

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GB1108444.9A GB2481487B (en) 2011-05-19 2011-05-19 Amplifier
GB1108444.9 2011-05-19
US13/111,423 2011-05-19
US13/111,423 US8378748B2 (en) 2011-05-19 2011-05-19 Amplifier
US13/224,430 US8427239B2 (en) 2011-09-02 2011-09-02 Apparatus and method for low noise amplification
US13/224,430 2011-09-02
GB1115183.4 2011-09-02
GB1115183.4A GB2486515B (en) 2011-09-02 2011-09-02 Apparatus and method for low noise amplification
US13/271,630 2011-10-12
GB1117606.2 2011-10-12
GB1117606.2A GB2490976A (en) 2011-05-19 2011-10-12 LNAs adaptable between inductively degenerated and internal impedance matching configurations
US13/271,630 US8514021B2 (en) 2011-05-19 2011-10-12 Radio frequency integrated circuit
US13/308,772 US8319555B1 (en) 2011-05-19 2011-12-01 Amplifier
US13/308,772 2011-12-01

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CN108111131A (zh) * 2017-12-29 2018-06-01 广州慧智微电子有限公司 一种反馈电路及放大器
WO2019132821A1 (fr) * 2017-12-30 2019-07-04 Istanbul Sehir Universitesi Amplificateur à entrées multiples pour supporter de multiples bandes

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