WO2012155301A1

WO2012155301A1 - Method for implementing basic input and output system (bios) of loongson cpu mainboard and interrupt method thereof

Info

Publication number: WO2012155301A1
Application number: PCT/CN2011/000876
Authority: WO
Inventors: 邵宗有; 刘新春; 杨晓君; 尹宁宁; 郑臣明; 李永成; 李丰旺
Original assignee: 曙光信息产业股份有限公司
Priority date: 2010-11-04
Filing date: 2011-05-20
Publication date: 2012-11-22

Abstract

A method for implementing Basic Input and Output System (BIOS) of Loongson CPU mainboard and the interrupt method thereof are provided. The methods include: mapping and translating the address of the Loongson CPU and a north bridge chip, mapping and translating the address of a Direct Memory Access (DMA) device, configuring the address space of a Peripheral Command Indicator (PCI), debugging after combining the coreboot with the pmon as a new BIOS, and debugging the kernel interrupt system. With the method presented, it can solve the problem of the address mapping and translating between the Loongson CPU and the AMD bridge chip in a BIOS level, the problem of addressing the DMA device in the pmon, the reading and writing problem of PCI configuration space of a Loongson blade, the transplanting and debugging problem from the coreboot to pmon. The interrupt processing mode of the external device of the Loongsoon mainboard guarantees the regular works of the external device of the Loongsoon mainboard.

Description

Bi-core cpu main board Bias implementation method and interrupt method thereof

The present invention relates to the implementation of motherboard bios and interrupts, and more particularly to a Loongson CPU motherboard bios and an implementation of interrupts. Background technique

The Godson-3 series CPUs include 4 core 3A, 8 core 3B, 16 core 3C CPUs, and other series of CPUs developed in the future.

The Godson-3 CPU is a general-purpose multi-core CPU. It adopts the MIPS architecture and can fully realize the functions of Intel and AMD X86 architecture CPUs. It also has unique advantages in terms of energy saving and security, although it is better than X86 CPU in terms of performance. It's still a little behind, but it can completely replace the X86 CPU in most areas.

Although the Loongson 3A and 3B CPUs have been available, they have not solved the key problem of "use", that is, they have not found the North and South bridge chipsets and peripherals that work with the Loongson CPU, just like a person has a brain, but cannot Finding the body and limbs that match the brain is still a CPU that can't be practical but conceptual.

In order to solve the practical problems of the Loongson CPU, the possibility of "Godson 3 CPU + SIS chipsets" and "Godson 3 CPU + nVIDIA chipsets" was discussed, and the motherboard samples were developed, but it was not successful.

At present, the "Godson 3 CPU + AMD North Bridge RS780E + AMD South Bridge SB710" solution has been adopted, and it has achieved success and finally realized productization. As shown in Figure 1.

However, after the motherboard is formed, how to make the motherboard run requires software support, including BIOS, kernel and other support.

PM0N is an open source software that combines some functions of BIOS and boot loader. It supports MIPS, ARM, PowerPC and other architectures, and is mostly used in embedded systems. Coreboot is a free and open source software project that is designed to replace the traditional bios on existing computers, primarily supporting the x86 platform.

On the kernel side, Godson's interrupt system is completely different from the X86. Godson's interrupt system uses an exception handling table instead of the X86 IDT table (interrupt descriptor table), using the device's interrupt controller to control interrupts without supporting APIC; and AMD bridges support the X86 platform. Therefore, how to cooperate with Loongson CPU in the kernel is a problem. Summary of the invention In order to obtain a bios and l imjx kernel that can be run on the Loongson motherboard, and solve the problems of address mapping, PCI configuration space read and write, and interrupt allocation, the present invention provides a Loongson CPU motherboard bios and an interrupt system implementation method.

A Loongson CPU motherboard bios and an interrupt implementation method are as follows:

Address mapping conversion between Loongson CPU and Northbridge chip;

Mapping the DMA device address;

Configuring the PCI address space;

After coreboot and pmon are merged into new bios, debugging; and,

Debug the kernel interrupt system.

Preferably, the address mapping conversion process first maps the Loongson CPU physical address space to the HT bus address space, and then maps the HT bus address space to the PCI address space.

Further preferably, the mapping of the Loongson CPU physical address space to the HT bus address space is implemented by a first-level crossbar.

Further preferably, only the 48-bit address space is mapped when the Loongson CPU physical address space is mapped.

Further preferably, the mapping of the HT bus address space to the PCI address space is implemented by HT to PCI bridge.

Preferably, the DMA device address mapping conversion is implemented by modifying a register initial value associated with DMA addressing in the Northbridge chip.

Still preferably, the registers are capable of 8-bit, 16-bit and 32-bit read and write operations.

Preferably, the bios combines the debugging part of the PM0N CPU, the memory and the serial port with the initialization part of the coreboot north-south bridge controller and device.

Preferably, after the bios are debugged, after the south bridge is initialized, all device controllers that may affect debugging are turned off before the PCI scan.

Preferably, the kernel interrupt system responds to and controls an interrupt request of an external device of the north and south bridge by cascading the interrupt controller of the Loongson CPU with the 8259A controller.

Preferably, the interrupt system uses an exception handling table to classify the interrupts.

Preferably, the interrupt is handled by an interrupt controller.

Further preferably, the interrupt system uses a South Bridge 8259A controller in conjunction with an interrupt controller of the Loongson 3A CPU to implement an external device interrupt response.

Further preferably, the Godson 3A motherboard allocates the interrupt number of the south bridge device by configuring the interrupt pin, the interrupt line and the trigger mode of the south bridge device. Through the method provided by the invention, the address mapping conversion problem between the CPU core Loongson CPU and the AMD bridge chip is solved, the DMA device addressing problem in the PM0N, the Loongson blade PCI configuration space read and write problem, and the migration and debugging from coreboot to pmon The problem. Moreover, the interrupt processing method of the external device of the Loongson motherboard ensures the normal operation of the external device on the Loongson motherboard. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is the company's Loongson motherboard CB50-A

Figure 2 shows the address range of the AMD bridge device.

Figure 3 is the physical address structure of the Loongson blade layered

Figure 4 is the Godson 3A physical address map

Figure 5 is a PCI compatible configuration mode

Figure 6 shows the address format under the MIPS architecture.

Figure 7 is the running chart of Loongson bios

Figure 8 is a schematic diagram of the CPU interrupt structure

Figure 9 Godson 3A motherboard external interrupt response process Specific implementation:

First, the conversion of Godson CPU and North Bridge address mapping

In the x86 platform, the system's addresses are divided into physical addresses, bus addresses, and virtual addresses. In Linux, the 4GB (virtual) memory of a process is divided into user space and kernel space. The user space is 0~3GB (ie PAGE_OFFSET, which is equal to OxCOOOOOOO in 0X86), and 1G in lj is kernel space. Programmers can only use virtual addresses. Each process in the system has its own private user space (0 to 3G), which is invisible to other processes in the system. The address when the CPU issues the fetch request is the virtual address of the current context, and the MMU finds the physical address of the virtual address from the page table, and completes the fetching.

Moreover, the x86 platform uses a technology called Memory Map (MMIO), which is part of the PCI specification. 10 device ports are mapped to memory space. After mapping, the CPU accesses port 10 as if it were accessing memory. Figure 2 shows the MEM mapping address for several devices in the AMD bridge in coreboot, and 'h' for hexadecimal.

The Godson CPU is a CPU of the MIPS architecture, which is different from the address allocation and addressing mode of the x86 CPU. Godson 3A uses 48-bit physical address space, 47-44 bits distinguish 16 nodes, 44~0 is the internal address of each node; Godson blade server is a CC-NUMA architecture consisting of two nodes, the whole system The address space can be divided into four levels, that is, the physical address interval, the address space of the first-level crossbar route in the node, and the address of the HT. Space, PCI address space. The next level is a subinterval of the previous level, as shown in Figure 3.

The system must have a node with node-id 0, which is responsible for system startup. The node-id of another node of the Godson blade server is set to 01 by the hardware jumper, so the physical address space range of the entire system is [0x0000 0000 — 0000 ~ 0x2000—0000—0000], where [0x0000 0000— 0000 ~ 0x1000—0000—0000] is the physical address range of node 0, and [0xl000_0000_0000 ~0x2000_0000_0000] is the physical address range of node 01.

The devices connected to the North and South Bridge chips are PCI devices. The PCI system has 4GB of memory space and 64K of 10 space. The CPU needs to access the configuration space, memory space, and 10 space of the PCI device. After a series of conversion processes, that is, 48-bit CPU address space, 40-bit HT address space PCI. Address space. As shown in Figure 4.

1. Conversion of CPU physical address space to HT address space

Godson 3A maps the CPU physical address space [OxOeOO- 0000-0000~0χ1000_0000_0000] to the HT 40-bit address space [0x00-0000-0000 ~ 0χ100_0000_0000]. This mapping is through the address routing window of the primary crossbar or the first-level crossbar. The default settings are implemented. Because HT has only 40 bits of address space, it does not consider extra bits.

2. Conversion from HT address space to PCI address space

The mapping of the HT 40-bit address space to the PCI address space is implemented via the HT to PCI bridge, which is hardware-guaranteed and requires no software configuration. After mapping, the starting MEM address of the PCI device is 0x10000000, and the starting address of 10 is 0x18000000. This address is used as a PCI MEM BASE or 10 BASEc in the PMON program. For each PCI device, PMON establishes a pci-device structure. The information of each PCI device is recorded in this structure, including the type of the device, the mem size, and the pointer of the next device, which form a linked list. During the PCI device scanning process, PMON searches the resource request information of all devices recursively according to the linked list, and forms a pci-win structure to form a memory and 10 resource request linked list. In the PCI device resource allocation process, the allocation of memory and 10 is performed according to the following formula:

PCI device MEM address = MEM address of the previous device + MEM request size of the PCI device

PCI device 10 address = MEM address of the previous device + 10 request size of the PCI device

The initial value of the MEM address of the first device is equal to 0x10000000, and the 10 address is 0x18000000. In the PMON program, the MEM, 10 size of the device is obtained by reading the configuration space of the PCI device, thereby allocating the MEM, 10 address of the PCI device.

Second, Godson 3A motherboard device DMA operation configuration:

The process of accessing memory by DMA in the Loongson CPU is as follows: 1. The address that the PCI device sends out to access the memory passes through the North Bridge chip and is routed from the North Bridge to the HT1 controller.

2. The HT1 controller routes the address to the first level based on its internal address window register.

3, the first level crossbar according to its internal address window register to the address to the secondary cache, and then to the second level crossbar;

4. The secondary crossbar routes the address to the memory controller according to its internal address window configuration.

The north and south bridge chips are connected to many devices that need to perform DMA operations, such as network card devices, which need to perform DMA operations when receiving and sending data messages. Because of the difference between the X86 architecture and the MIPS architecture in the physical address of the memory, it is necessary to modify the setting of the DMA operation register of the North Bridge in the BIOS. Otherwise, the DMA operation cannot be performed correctly. The invention makes the following modifications to the related registers of the north bridge in PMON: The value of nbconfig 0x90 is changed from 0x40000000 to ΟχίΌΟΟΟΟΟΟ, thereby ensuring the correct DMA operation address of the north and south bridge devices, and ensuring the normal operation of the device DMA.

Third, Godson blade PCI configuration space and 10 space read and write:

In the Godson blade BIOS, the initialization code of the north and south bridge devices mainly draws on the x86 architecture BIOS coreboot ₀ in coreboot, the north and south bridge chip initialization code is completely implemented according to the working principle of the X86 CPU. The Godson 3 processor is a MIPS architecture CPU. The address space and PCI configuration space read and write access are completely different from the X86 architecture. This requires us to rewrite the north and south bridge chip initialization code, mainly for the north and south bridge device PCI. Modification of the read and write functions of the configuration space.

X86 Architecture The BIOS used by the CPU basically uses the PCI compatible configuration method to read and write the PCI configuration space registers.

The PC1 compatible configuration method uses two 32-bit 10 ports, which are configuration address port 0xCF8 and configuration data port 0XCFC. Configure the address port data format as shown in Figure 5.

When you want to read the PCI configuration space register contents of the device, you need to write the bus number, device number, function number, register position and other information of the device to the configuration address port, and then read the configuration data port to get the PCI configuration space related register. content.

When writing the contents of the PC1 configuration space register of the device, you need to write the bus number, device number, function number, register position and other information of the device to the configuration address port, and then write the data to the configuration data port to write the relevant content. Go to the PCI configuration space related registers.

The PCI and PCI-E buses can use this method to read and write the PCI configuration space registers inside the device on the bus. Using this method, the PCI configuration space registers can be directly read and written by 8-bit, 16-bit, and 32-bit.

In the MIPS architecture, the HT bus configuration method is used to read and write the PCI configuration space register. The HT bus configuration method means that the HT bus can use the PCI compatible configuration method to read and write the PCI configuration space register inside the device on the bus, or use its own unique configuration method to perform the PCI configuration space register inside the device on the bus. Read and write operations.

In the MIPS architecture, the address format of type 0 and type 1 is shown in Figure 6. The 40-bit to 63-bit address needs to be determined according to the CPU and HT bus. Currently, the address we use is 0x90000E. On the Godson 3A motherboard, we define type 0 address HT_MAP_TYPE0—CONF_ADDR is OxbaOOOOOO, type 1 address HT M AP T YPE 1 CONF ADDR is 0xbb000000.

When you want to read the PCI configuration space register contents of the device, you need to add the bus number, device number, function number, register position and other information of the device to the first address to get the last read and write access address. The formula is as follows:

Addr |= (dev « 11 | func « 8 | reg)

Where addr = HT MAP TYPEO CONF ADDR or

HT MAP TYPE 1 CONF ADDR; reg is the PCI register number to be operated.

When a read access is made to the last obtained address, the contents of the PCI configuration space related register are obtained; when the relevant data is written to the last obtained address, the relevant content can be written to the PCI configuration space related register.

For the 10 operation, under the X86 architecture, there is a 10-address space with an interval of OxO-Oxffff, which can be accessed using the in and out instructions. In the MIPS architecture, there is no direct corresponding 10 address space, and there is no direct access to the 10 address space for instructions such as in, out. However, some devices such as serial port, real-time clock, interrupt controller, IDE, etc. need to read and write the 10 address space they use during normal operation. In this way, under the MIPS architecture, the corresponding read and write operations must also be implemented in order for these devices to work properly. To understand this, use OxFDFCOOOOOO in the HT address window as the 10 address space. The base address after mapping this area is Oxb8000000. The formula for such a 10 address is:

Addr BONITO—PCIIO— BASE— VA + addr

Where BONITO PCUO— BASE— VA = 0xb8000000

Therefore, in order to achieve seamless migration from coreboot to pmon, you need to modify and add the PCI configuration space read and write functions and 10 space read and write functions. The changed and added function interface includes PCI configuration space register 8-bit, 16-bit, 32-bit read operation function; PCI configuration space register 8-bit, 16-bit, 32-bit write operation function; PCI configuration space type 0, type 1 read/write Method; Debug information output function; Memory register 8-bit, 16-bit, 32-bit read and write function; 10 register 8-bit, 16-bit, 32-bit read and write function; Initial configuration parameter setting function; Device search function; Device positioning function Etc. Other changes that need to be included include 10 address macro definitions, etc. 4. Pmon debugging method for Godson 3A motherboard

In the early stage of the Loongson 3A motherboard debugging, there is no guarantee that the code for initializing the north and south bridges in pmon is correct, all The device works fine. In order to ensure the power-on debugging progress of the Loongson blade motherboard and reduce the complexity of the debugging work, we choose a simple and simple method, that is, to shield the complex and unused devices in the north-south bridge before scanning the PCI device of the pmon code. , and the subsequent necessary equipment debugging.

Figure 7 shows the PMON code initialization flow chart:

As seen from the flow chart, PMON mainly performs debugging of CPU, memory and serial port in the assembly part. After entering the C language part, the initialization of the north and south bridge controllers and devices is started. In the initialization process of the north-south bridge, the controllers of each device are first enabled and initialized, so that the devices under the controller that have been enabled are enumerated during the PCI scanning process, and the controllers that are not enabled are Do not enumerate and allocate resources. Therefore, the simplification of debugging is to turn off the controllers of these more complex devices in the north and south bridges before the PCI scan, after the initialization of the north and south bridges, so that during the PCI scan, the program considers that the controllers of these devices are not enabled. There are no devices under the controller, so they will not be initialized, which greatly reduces the interference and reduces the complexity of debugging.

Five, Godson 3A motherboard Linux kernel interrupt allocation:

The x86 architecture interrupt system has 256 interrupt numbers. When an interrupt occurs, the CPU uses the interrupt number to index the interrupt descriptor table (IDT) with the IDTR register as the base address. Each entry of the IDT points to the corresponding interrupt handler. .

In the interrupt processing system of the Godson 3 CPU, there are only special exceptions and general exceptions. Special exceptions include cold start, TLB refill, xTLB refill, and cache error. There are 32 general exceptions. The general exception No. 0 is the interrupt associated with the external device. Figure 8 shows the four-level cascade of the Godson 3A motherboard. Interrupt structure diagram. The first three levels belong to the interrupt cascade inside the CPU.

The first level is the interrupt controller of each core of the CPU. There are 4 cores inside the CPU. The Cause and Status registers of each core form an interrupt controller. After the CPU executes an instruction, it will check if the corresponding bit of the Cause register is set. The second stage consists of an interrupt controller with 32 interrupt lines. The 32 interrupt lines can be routed to the CPU's 4 cores by configuring the CPU's internal interrupt routing registers. The third stage consists of an HT interrupt controller, an LPC interrupt controller, and an inter-core interrupt controller. The HT interrupt controller is used to accept interrupts from 10 devices. The fourth stage is related to the AMD chipset. It is connected to the South Bridge's 8259A controller, and all peripheral interrupts on the bridge are sent to the 8259A controller before being sent to the HT interrupt controller.

Therefore, the key to configuring an external device interrupt is the cooperation of the peripheral and the South Bridge 8259A controller. According to the characteristics of AMD South Bridge 8259A, it can be divided into three steps:

1) The int _e rrupt_pm of the configured device is connected to the first interrupt line of the 8259A controller. Some of the connections are hardware settings and some require software configuration. There are 12 8259A interrupt lines on the AMD bridge. -

2) Configure the interrupt line, which is the interrupt number. 3) Configure the trigger mode of the interrupt, level trigger or edge trigger.

After configuring these three items, the North and South Bridge devices can be interrupted normally. Figure 9 describes the process of responding to the interrupt of the external device.

When a hardware device triggers an interrupt, the CPU hardware sets the Exc code field and IP bit of the cause register accordingly. The program in the general exception handling in the kernel except - vec3 - generic will query the Exc code field of the cause register to determine which of the 32 general exceptions. The external device interrupt belongs to number 0, then the kernel enters the interrupt handler's entry address handle_init and calls the interrupt dispatch function plat_irq_dispatch. Plat_irq_dispatch will judge whether the interrupt source or interrupt controller has an interrupt according to [IP7~IP0] of the CPU CAUSE register. The external device interrupt belongs to the HT1 interrupt controller, and the HT1 interrupt controller is cascaded with the South Bridge 8259A control. Device. This function will call the 8259A interrupt allocation process, which is the three steps described above. After the interrupt number is distributed through these three steps, the kernel will directly call the do_IRQ() function to execute the corresponding driver. The entire interrupt call process is complete.

In addition, as can be seen from Figure 8, all 10 device interrupts on the AMD bridge are transmitted to the CPU through the HT1 interrupt route, and since the APIC function is not implemented in the Godson 3A CPU, the interrupt of 10 devices can only be sent to the master. The CPU has 4 cores, and the secondary CPU cannot handle 10 interrupts. Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present invention and are not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that: Modifications or equivalents of the present invention are intended to be included within the scope of the appended claims.

Claims

Rights request

1. A Loongson CPU motherboard bios and an interrupt implementation method are characterized by the following steps: The address mapping of the Loongson CPU and the Northbridge chip is performed;

Mapping the DMA device address;

Configuring the PCI address space;

After coreboot and pmon are merged into new bios, debugging; and,

Debug the kernel interrupt system.

The method according to claim 1, wherein the address mapping conversion process first maps the Loongson CPU physical address space to the HT bus address space, and then maps the HT bus address space to the PCI address space.

3. The method according to claim 2, wherein: mapping the Loongson CPU physical address space to the HT bus address space is implemented by a first-level crossbar.

4. The method according to claim 3, wherein: the Loongson CPU physical address space mapping only maps a 48-bit address space.

5. The method of claim 2, wherein: mapping the HT bus address space to the PCI address space is implemented by using an HT to PCI bridge.

6. The method of claim 1 wherein: said DMA device address mapping conversion is accomplished by modifying an initial value of a register associated with DMA addressing within the Northbridge chip.

7. The method of claim 6 wherein: said register is capable of 8-bit, 16-bit and 32-bit read and write operations.

8. The method of claim 1, wherein: the bios fuses the debug portion of the CPU, memory, and serial ports of the PM0N with the initialization portion of the northboot bridge controller and device of the coreboot.

9. The method according to claim 1, wherein: after the bios is debugged, after the south bridge is initialized, all device controllers that may affect debugging are turned off before the PCI scan.

10. The method of claim 1, wherein: the kernel interrupt system responds to and controls an interrupt request of an external device of the north-south bridge by cascading an interrupt controller of the Loongson CPU with the 8259A controller.

11. The method of claim 1 wherein: said interrupt system employs an exception handling table to classify the interrupts.

12. The method of claim 1 wherein: the interrupt is processed by an interrupt controller.

13. The method according to claim 10, wherein: the interrupt system uses a South Bridge 8259A controller in conjunction with an interrupt controller of the Loongson 3A CPU to implement an external device interrupt response.

14. The method of claim 10, wherein: the Loongson 3A motherboard allocates an interrupt number of the south bridge device by configuring an interrupt pin, an interrupt line, and a trigger mode of the south bridge device.