WO2012155301A1 - Method for implementing basic input and output system (bios) of loongson cpu mainboard and interrupt method thereof - Google Patents
Method for implementing basic input and output system (bios) of loongson cpu mainboard and interrupt method thereof Download PDFInfo
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- WO2012155301A1 WO2012155301A1 PCT/CN2011/000876 CN2011000876W WO2012155301A1 WO 2012155301 A1 WO2012155301 A1 WO 2012155301A1 CN 2011000876 W CN2011000876 W CN 2011000876W WO 2012155301 A1 WO2012155301 A1 WO 2012155301A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
Definitions
- the present invention relates to the implementation of motherboard bios and interrupts, and more particularly to a Loongson CPU motherboard bios and an implementation of interrupts. Background technique
- the Godson-3 series CPUs include 4 core 3A, 8 core 3B, 16 core 3C CPUs, and other series of CPUs developed in the future.
- the Godson-3 CPU is a general-purpose multi-core CPU. It adopts the MIPS architecture and can fully realize the functions of Intel and AMD X86 architecture CPUs. It also has unique advantages in terms of energy saving and security, although it is better than X86 CPU in terms of performance. It's still a little behind, but it can completely replace the X86 CPU in most areas.
- Loongson 3A and 3B CPUs have been available, they have not solved the key problem of "use", that is, they have not found the North and South bridge chipsets and peripherals that work with the Loongson CPU, just like a person has a brain, but cannot Finding the body and limbs that match the brain is still a CPU that can't be practical but conceptual.
- PM0N is an open source software that combines some functions of BIOS and boot loader. It supports MIPS, ARM, PowerPC and other architectures, and is mostly used in embedded systems. Coreboot is a free and open source software project that is designed to replace the traditional bios on existing computers, primarily supporting the x86 platform.
- Godson's interrupt system is completely different from the X86.
- Godson's interrupt system uses an exception handling table instead of the X86 IDT table (interrupt descriptor table), using the device's interrupt controller to control interrupts without supporting APIC; and AMD bridges support the X86 platform. Therefore, how to cooperate with Loongson CPU in the kernel is a problem. Summary of the invention In order to obtain a bios and l imjx kernel that can be run on the Loongson motherboard, and solve the problems of address mapping, PCI configuration space read and write, and interrupt allocation, the present invention provides a Loongson CPU motherboard bios and an interrupt system implementation method.
- a Loongson CPU motherboard bios and an interrupt implementation method are as follows:
- the address mapping conversion process first maps the Loongson CPU physical address space to the HT bus address space, and then maps the HT bus address space to the PCI address space.
- mapping of the Loongson CPU physical address space to the HT bus address space is implemented by a first-level crossbar.
- mapping of the HT bus address space to the PCI address space is implemented by HT to PCI bridge.
- the DMA device address mapping conversion is implemented by modifying a register initial value associated with DMA addressing in the Northbridge chip.
- the registers are capable of 8-bit, 16-bit and 32-bit read and write operations.
- the bios combines the debugging part of the PM0N CPU, the memory and the serial port with the initialization part of the coreboot north-south bridge controller and device.
- the kernel interrupt system responds to and controls an interrupt request of an external device of the north and south bridge by cascading the interrupt controller of the Loongson CPU with the 8259A controller.
- the interrupt system uses an exception handling table to classify the interrupts.
- the interrupt is handled by an interrupt controller.
- the interrupt system uses a South Bridge 8259A controller in conjunction with an interrupt controller of the Loongson 3A CPU to implement an external device interrupt response.
- the Godson 3A motherboard allocates the interrupt number of the south bridge device by configuring the interrupt pin, the interrupt line and the trigger mode of the south bridge device.
- the address mapping conversion problem between the CPU core Loongson CPU and the AMD bridge chip is solved, the DMA device addressing problem in the PM0N, the Loongson blade PCI configuration space read and write problem, and the migration and debugging from coreboot to pmon The problem.
- the interrupt processing method of the external device of the Loongson motherboard ensures the normal operation of the external device on the Loongson motherboard.
- BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is the company's Loongson motherboard CB50-A
- Figure 2 shows the address range of the AMD bridge device.
- Figure 3 is the physical address structure of the Loongson blade layered
- Figure 4 is the Godson 3A physical address map
- Figure 5 is a PCI compatible configuration mode
- Figure 6 shows the address format under the MIPS architecture.
- Figure 7 is the running chart of Loongson bios
- FIG. 8 is a schematic diagram of the CPU interrupt structure
- the system's addresses are divided into physical addresses, bus addresses, and virtual addresses.
- the 4GB (virtual) memory of a process is divided into user space and kernel space.
- the user space is 0 ⁇ 3GB (ie PAGE_OFFSET, which is equal to OxCOOOOOOO in 0X86), and 1G in lj is kernel space.
- Programmers can only use virtual addresses.
- Each process in the system has its own private user space (0 to 3G), which is invisible to other processes in the system.
- the address when the CPU issues the fetch request is the virtual address of the current context, and the MMU finds the physical address of the virtual address from the page table, and completes the fetching.
- MMIO Memory Map
- 10 device ports are mapped to memory space. After mapping, the CPU accesses port 10 as if it were accessing memory.
- Figure 2 shows the MEM mapping address for several devices in the AMD bridge in coreboot, and 'h' for hexadecimal.
- the Godson CPU is a CPU of the MIPS architecture, which is different from the address allocation and addressing mode of the x86 CPU.
- Godson 3A uses 48-bit physical address space, 47-44 bits distinguish 16 nodes, 44 ⁇ 0 is the internal address of each node;
- Godson blade server is a CC-NUMA architecture consisting of two nodes, the whole system
- the address space can be divided into four levels, that is, the physical address interval, the address space of the first-level crossbar route in the node, and the address of the HT. Space, PCI address space.
- the next level is a subinterval of the previous level, as shown in Figure 3.
- the system must have a node with node-id 0, which is responsible for system startup.
- the node-id of another node of the Godson blade server is set to 01 by the hardware jumper, so the physical address space range of the entire system is [0x0000 0000 — 0000 ⁇ 0x2000—0000—0000], where [0x0000 0000— 0000 ⁇ 0x1000—0000—0000] is the physical address range of node 0, and [0xl000_0000_0000 ⁇ 0x2000_0000_0000] is the physical address range of node 01.
- the devices connected to the North and South Bridge chips are PCI devices.
- the PCI system has 4GB of memory space and 64K of 10 space.
- the CPU needs to access the configuration space, memory space, and 10 space of the PCI device. After a series of conversion processes, that is, 48-bit CPU address space, 40-bit HT address space PCI. Address space. As shown in Figure 4.
- Godson 3A maps the CPU physical address space [OxOeOO- 0000-0000 ⁇ 0 ⁇ 1000_0000_0000] to the HT 40-bit address space [0x00-0000-0000 ⁇ 0 ⁇ 100_0000_0000]. This mapping is through the address routing window of the primary crossbar or the first-level crossbar. The default settings are implemented. Because HT has only 40 bits of address space, it does not consider extra bits.
- mapping of the HT 40-bit address space to the PCI address space is implemented via the HT to PCI bridge, which is hardware-guaranteed and requires no software configuration.
- the starting MEM address of the PCI device is 0x10000000, and the starting address of 10 is 0x18000000. This address is used as a PCI MEM BASE or 10 BASEc in the PMON program.
- PMON establishes a pci-device structure.
- the information of each PCI device is recorded in this structure, including the type of the device, the mem size, and the pointer of the next device, which form a linked list.
- PMON searches the resource request information of all devices recursively according to the linked list, and forms a pci-win structure to form a memory and 10 resource request linked list.
- the allocation of memory and 10 is performed according to the following formula:
- PCI device MEM address MEM address of the previous device + MEM request size of the PCI device
- PCI device 10 address MEM address of the previous device + 10 request size of the PCI device
- the initial value of the MEM address of the first device is equal to 0x10000000, and the 10 address is 0x18000000.
- the MEM, 10 size of the device is obtained by reading the configuration space of the PCI device, thereby allocating the MEM, 10 address of the PCI device.
- the process of accessing memory by DMA in the Loongson CPU is as follows: 1.
- the address that the PCI device sends out to access the memory passes through the North Bridge chip and is routed from the North Bridge to the HT1 controller.
- the HT1 controller routes the address to the first level based on its internal address window register.
- the first level crossbar according to its internal address window register to the address to the secondary cache, and then to the second level crossbar;
- the secondary crossbar routes the address to the memory controller according to its internal address window configuration.
- the north and south bridge chips are connected to many devices that need to perform DMA operations, such as network card devices, which need to perform DMA operations when receiving and sending data messages. Because of the difference between the X86 architecture and the MIPS architecture in the physical address of the memory, it is necessary to modify the setting of the DMA operation register of the North Bridge in the BIOS. Otherwise, the DMA operation cannot be performed correctly.
- the invention makes the following modifications to the related registers of the north bridge in PMON: The value of nbconfig 0x90 is changed from 0x40000000 to ⁇ , thereby ensuring the correct DMA operation address of the north and south bridge devices, and ensuring the normal operation of the device DMA.
- the initialization code of the north and south bridge devices mainly draws on the x86 architecture BIOS coreboot 0 in coreboot, the north and south bridge chip initialization code is completely implemented according to the working principle of the X86 CPU.
- the Godson 3 processor is a MIPS architecture CPU.
- the address space and PCI configuration space read and write access are completely different from the X86 architecture. This requires us to rewrite the north and south bridge chip initialization code, mainly for the north and south bridge device PCI. Modification of the read and write functions of the configuration space.
- BIOS used by the CPU basically uses the PCI compatible configuration method to read and write the PCI configuration space registers.
- the PC1 compatible configuration method uses two 32-bit 10 ports, which are configuration address port 0xCF8 and configuration data port 0XCFC. Configure the address port data format as shown in Figure 5.
- the PCI and PCI-E buses can use this method to read and write the PCI configuration space registers inside the device on the bus.
- the PCI configuration space registers can be directly read and written by 8-bit, 16-bit, and 32-bit.
- the HT bus configuration method is used to read and write the PCI configuration space register.
- the HT bus configuration method means that the HT bus can use the PCI compatible configuration method to read and write the PCI configuration space register inside the device on the bus, or use its own unique configuration method to perform the PCI configuration space register inside the device on the bus. Read and write operations.
- the address format of type 0 and type 1 is shown in Figure 6.
- the 40-bit to 63-bit address needs to be determined according to the CPU and HT bus.
- the address we use is 0x90000E.
- type 0 address HT_MAP_TYPE0—CONF_ADDR is OxbaOOOOOO
- type 1 address HT M AP T YPE 1 CONF ADDR is 0xbb000000.
- reg is the PCI register number to be operated.
- the changed and added function interface includes PCI configuration space register 8-bit, 16-bit, 32-bit read operation function; PCI configuration space register 8-bit, 16-bit, 32-bit write operation function; PCI configuration space type 0, type 1 read/write Method; Debug information output function; Memory register 8-bit, 16-bit, 32-bit read and write function; 10 register 8-bit, 16-bit, 32-bit read and write function; Initial configuration parameter setting function; Device search function; Device positioning function Etc. Other changes that need to be included include 10 address macro definitions, etc. 4. Pmon debugging method for Godson 3A motherboard
- FIG. 7 shows the PMON code initialization flow chart
- PMON mainly performs debugging of CPU, memory and serial port in the assembly part.
- the initialization of the north and south bridge controllers and devices is started.
- the controllers of each device are first enabled and initialized, so that the devices under the controller that have been enabled are enumerated during the PCI scanning process, and the controllers that are not enabled are Do not enumerate and allocate resources. Therefore, the simplification of debugging is to turn off the controllers of these more complex devices in the north and south bridges before the PCI scan, after the initialization of the north and south bridges, so that during the PCI scan, the program considers that the controllers of these devices are not enabled. There are no devices under the controller, so they will not be initialized, which greatly reduces the interference and reduces the complexity of debugging.
- the x86 architecture interrupt system has 256 interrupt numbers.
- the CPU uses the interrupt number to index the interrupt descriptor table (IDT) with the IDTR register as the base address.
- IDT interrupt descriptor table
- the first level is the interrupt controller of each core of the CPU. There are 4 cores inside the CPU.
- the Cause and Status registers of each core form an interrupt controller. After the CPU executes an instruction, it will check if the corresponding bit of the Cause register is set.
- the second stage consists of an interrupt controller with 32 interrupt lines. The 32 interrupt lines can be routed to the CPU's 4 cores by configuring the CPU's internal interrupt routing registers.
- the third stage consists of an HT interrupt controller, an LPC interrupt controller, and an inter-core interrupt controller. The HT interrupt controller is used to accept interrupts from 10 devices.
- the fourth stage is related to the AMD chipset. It is connected to the South Bridge's 8259A controller, and all peripheral interrupts on the bridge are sent to the 8259A controller before being sent to the HT interrupt controller.
- the key to configuring an external device interrupt is the cooperation of the peripheral and the South Bridge 8259A controller. According to the characteristics of AMD South Bridge 8259A, it can be divided into three steps:
- the int e rrupt_pm of the configured device is connected to the first interrupt line of the 8259A controller. Some of the connections are hardware settings and some require software configuration. There are 12 8259A interrupt lines on the AMD bridge. -
- Figure 9 describes the process of responding to the interrupt of the external device.
- the CPU hardware When a hardware device triggers an interrupt, the CPU hardware sets the Exc code field and IP bit of the cause register accordingly.
- the program in the general exception handling in the kernel except - vec3 - generic will query the Exc code field of the cause register to determine which of the 32 general exceptions.
- the external device interrupt belongs to number 0, then the kernel enters the interrupt handler's entry address handle_init and calls the interrupt dispatch function plat_irq_dispatch. Plat_irq_dispatch will judge whether the interrupt source or interrupt controller has an interrupt according to [IP7 ⁇ IP0] of the CPU CAUSE register.
- the external device interrupt belongs to the HT1 interrupt controller, and the HT1 interrupt controller is cascaded with the South Bridge 8259A control. Device. This function will call the 8259A interrupt allocation process, which is the three steps described above. After the interrupt number is distributed through these three steps, the kernel will directly call the do_IRQ() function to execute the corresponding driver. The entire interrupt call process is complete.
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Abstract
A method for implementing Basic Input and Output System (BIOS) of Loongson CPU mainboard and the interrupt method thereof are provided. The methods include: mapping and translating the address of the Loongson CPU and a north bridge chip, mapping and translating the address of a Direct Memory Access (DMA) device, configuring the address space of a Peripheral Command Indicator (PCI), debugging after combining the coreboot with the pmon as a new BIOS, and debugging the kernel interrupt system. With the method presented, it can solve the problem of the address mapping and translating between the Loongson CPU and the AMD bridge chip in a BIOS level, the problem of addressing the DMA device in the pmon, the reading and writing problem of PCI configuration space of a Loongson blade, the transplanting and debugging problem from the coreboot to pmon. The interrupt processing mode of the external device of the Loongsoon mainboard guarantees the regular works of the external device of the Loongsoon mainboard.
Description
一种龙芯 cpu主板 Bias实现方法及其中断方法 技术领域 Bi-core cpu main board Bias implementation method and interrupt method thereof
本发明涉及主板 bios及中断的实现, 具体地说, 提供了一种龙芯 CPU主板 bios以 及中断的实现方法。 背景技术 The present invention relates to the implementation of motherboard bios and interrupts, and more particularly to a Loongson CPU motherboard bios and an implementation of interrupts. Background technique
龙芯 3号系列 CPU包括 4核心 3A, 8核心 3B, 16核心 3C的 CPU, 以及后续开发 的其他系列的 CPU。 The Godson-3 series CPUs include 4 core 3A, 8 core 3B, 16 core 3C CPUs, and other series of CPUs developed in the future.
龙芯 3号 CPU是一款通用的多核的 CPU, 采用 MIPS架构, 完全可以实现 Intel 和 AMD X86架构 CPU的功能, 而且在节能、 安^:等方面有独特的优势, 尽管在性能方面 比 X86 CPU还稍微落后一些, 但在绝大部分领域可以完全代替 X86 CPU。 The Godson-3 CPU is a general-purpose multi-core CPU. It adopts the MIPS architecture and can fully realize the functions of Intel and AMD X86 architecture CPUs. It also has unique advantages in terms of energy saving and security, although it is better than X86 CPU in terms of performance. It's still a little behind, but it can completely replace the X86 CPU in most areas.
尽管龙芯 3A和 3B CPU已经面世, 但一直没有解决 "用" 的关键问题, 即一直没 有找到与龙芯 CPU配套且能正常工作的南北桥 chipsets和外围设备,就像一个人有了大 脑, 但无法找到配合大脑的躯体和四肢, 仍是一个不能实用只是概念意义的 CPU。 Although the Loongson 3A and 3B CPUs have been available, they have not solved the key problem of "use", that is, they have not found the North and South bridge chipsets and peripherals that work with the Loongson CPU, just like a person has a brain, but cannot Finding the body and limbs that match the brain is still a CPU that can't be practical but conceptual.
为解决龙芯 CPU的实用问题, 曾经探讨了 "龙芯 3 CPU+SIS公司 chipsets" , "龙 芯 3 CPU+nVIDIA公司 chipsets" 的可能性, 并研发了主板样品, 但最终没有成功。 In order to solve the practical problems of the Loongson CPU, the possibility of "Godson 3 CPU + SIS chipsets" and "Godson 3 CPU + nVIDIA chipsets" was discussed, and the motherboard samples were developed, but it was not successful.
目前采用 "龙芯 3 CPU + AMD公司北桥 RS780E + AMD公司南桥 SB710"方案, 取得了成功, 并最终实现了产品化。 如图 1所示。 At present, the "Godson 3 CPU + AMD North Bridge RS780E + AMD South Bridge SB710" solution has been adopted, and it has achieved success and finally realized productization. As shown in Figure 1.
但是在主板成型之后,如何能够使主板运行,就需要软件方面的支持,这包括 BIOS、 内核等的支持。 However, after the motherboard is formed, how to make the motherboard run requires software support, including BIOS, kernel and other support.
PM0N是一个兼有 BIOS和 boot loader部分功能的开放源码软件,支持 MIPS、 ARM、 PowerPC等架构, 多用于嵌入式系统。 Coreboot是一个自由开源软件项目, 它的目的是 替代现有计算机上面传统的 bios, 主要支持 x86平台。 PM0N is an open source software that combines some functions of BIOS and boot loader. It supports MIPS, ARM, PowerPC and other architectures, and is mostly used in embedded systems. Coreboot is a free and open source software project that is designed to replace the traditional bios on existing computers, primarily supporting the x86 platform.
在内核方面,龙芯的中断系统与 X86完全不一样。龙芯的中断系统采用异常处理表 而不是 X86 的 IDT 表 (中断描述符表), 采用设备的中断控制器来控制中断而不支持 APIC; 而 AMD桥片支持的都是 X86平台。 因此在内核方面如何与龙芯 CPU进行配合 是个问题。 发明内容
为了得到一种在龙芯主板上可以运行的 bios以及 l imjx内核, 解决地址映射、 PCI 配置空间读写以及中断分配等问题, 本发明提供了一种龙芯 CPU主板 bios及中断系统 的实现方法。 On the kernel side, Godson's interrupt system is completely different from the X86. Godson's interrupt system uses an exception handling table instead of the X86 IDT table (interrupt descriptor table), using the device's interrupt controller to control interrupts without supporting APIC; and AMD bridges support the X86 platform. Therefore, how to cooperate with Loongson CPU in the kernel is a problem. Summary of the invention In order to obtain a bios and l imjx kernel that can be run on the Loongson motherboard, and solve the problems of address mapping, PCI configuration space read and write, and interrupt allocation, the present invention provides a Loongson CPU motherboard bios and an interrupt system implementation method.
一种龙芯 CPU主板 bios以及中断的实现方法, 步骤如下: A Loongson CPU motherboard bios and an interrupt implementation method are as follows:
将龙芯 CPU与北桥芯片进行地址映射转换; Address mapping conversion between Loongson CPU and Northbridge chip;
将 DMA设备地址进行映射转换; Mapping the DMA device address;
对 PCI地址空间进行配置; 以及 Configuring the PCI address space;
将 coreboot与 pmon融合成新 bios后, 调试; 以及, After coreboot and pmon are merged into new bios, debugging; and,
调试内核中断系统。 Debug the kernel interrupt system.
优选的, 所述地址映射转换过程为先将龙芯 CPU物理地址空间映射到 HT总线地址空 间, 再将 HT总线地址空间映射到 PCI地址空间。 Preferably, the address mapping conversion process first maps the Loongson CPU physical address space to the HT bus address space, and then maps the HT bus address space to the PCI address space.
再优选的,所述龙芯 CPU物理地址空间映射到 HT总线地址空间是通过一级 crossbar 实现的。 Further preferably, the mapping of the Loongson CPU physical address space to the HT bus address space is implemented by a first-level crossbar.
再优选的, 所述龙芯 CPU物理地址空间映射时只映射 48位地址空间。 Further preferably, only the 48-bit address space is mapped when the Loongson CPU physical address space is mapped.
再优选的, 所述 HT总线地址空间映射到 PCI地址空间是通过 HT to PCI bri dge实 现。 Further preferably, the mapping of the HT bus address space to the PCI address space is implemented by HT to PCI bridge.
优选的, 所述 DMA设备地址映射转换是通过修改北桥芯片内与 DMA寻址相关的寄存 器初值实现。 Preferably, the DMA device address mapping conversion is implemented by modifying a register initial value associated with DMA addressing in the Northbridge chip.
再优选的, 所述寄存器可以进行 8位, 16位和 32位读写操作。 Still preferably, the registers are capable of 8-bit, 16-bit and 32-bit read and write operations.
优选的, 所述 bios是将 PM0N的 CPU、 内存和串口的调试部分与 coreboot的南北桥 控制器和设备的初始化部分融合。 Preferably, the bios combines the debugging part of the PM0N CPU, the memory and the serial port with the initialization part of the coreboot north-south bridge controller and device.
优选的, 所述 bios调试时在初始化南桥后, PCI扫描前, 关闭掉所有可能影响调试 的设备控制器。 Preferably, after the bios are debugged, after the south bridge is initialized, all device controllers that may affect debugging are turned off before the PCI scan.
优选的, 所述内核中断系统是通过将龙芯 CPU的中断控制器与 8259A控制器级联, 来响应和控制南北桥外部设备的中断请求。 Preferably, the kernel interrupt system responds to and controls an interrupt request of an external device of the north and south bridge by cascading the interrupt controller of the Loongson CPU with the 8259A controller.
优选的, 所述中断系统采用异常处理表来对中断分类。 Preferably, the interrupt system uses an exception handling table to classify the interrupts.
优选的, 采用中断控制器处理中断。 Preferably, the interrupt is handled by an interrupt controller.
再优选的,所述中断系统采用南桥 8259A控制器与龙芯 3A CPU的中断控制器相配合, 来实现外部设备中断的响应。 Further preferably, the interrupt system uses a South Bridge 8259A controller in conjunction with an interrupt controller of the Loongson 3A CPU to implement an external device interrupt response.
再优选的, 龙芯 3A主板通过配置南桥设备的中断阵脚、 中断线路和触发方式, 来分 配南桥设备的中断号。
通过本发明提供的方法,解决了在 BIOS层龙芯 CPU和 AMD桥片之间的地址映射转换 问题, PM0N中 DMA设备寻址问题, 龙芯刀片 PCI配置空间读写问题以及从 coreboot到 pmon移植和调试的问题。而且龙芯主板外部设备的中断处理方式,保证了龙芯主板上外 部设备正常工作。 附图说明- 图 1是曙光公司的龙芯主板 CB50-A Further preferably, the Godson 3A motherboard allocates the interrupt number of the south bridge device by configuring the interrupt pin, the interrupt line and the trigger mode of the south bridge device. Through the method provided by the invention, the address mapping conversion problem between the CPU core Loongson CPU and the AMD bridge chip is solved, the DMA device addressing problem in the PM0N, the Loongson blade PCI configuration space read and write problem, and the migration and debugging from coreboot to pmon The problem. Moreover, the interrupt processing method of the external device of the Loongson motherboard ensures the normal operation of the external device on the Loongson motherboard. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is the company's Loongson motherboard CB50-A
图 2是 AMD桥片设备的地址范围 Figure 2 shows the address range of the AMD bridge device.
图 3是龙芯刀片分层的物理地址结构 Figure 3 is the physical address structure of the Loongson blade layered
图 4是龙芯 3A物理地址映射图 Figure 4 is the Godson 3A physical address map
图 5是 PCI兼容配置模式 Figure 5 is a PCI compatible configuration mode
图 6是 MIPS架构下地址格式 Figure 6 shows the address format under the MIPS architecture.
图 7是龙芯 bios运行流程图 Figure 7 is the running chart of Loongson bios
图 8是 CPU中断结构示意图 Figure 8 is a schematic diagram of the CPU interrupt structure
图 9 龙芯 3A主板外部中断响应过程 具体实施方式: Figure 9 Godson 3A motherboard external interrupt response process Specific implementation:
一、 龙芯 CPU与北桥地址映射的转换 First, the conversion of Godson CPU and North Bridge address mapping
在 x86平台中, 系统的地址分为物理地址、 总线地址和虚拟地址。 Linux中, 进程的 4GB (虚拟)内存分为用户空间、内核空间。用户空间分布为 0〜3GB (即 PAGE— OFFSET, 在 0X86中它等于 OxCOOOOOOO) , 乘 lj下的 1G为内核空间。 程序员只能使用虚拟地址。 系统中每个进程有各自的私有用户空间(0〜3G), 这个空间对系统中的其他进程是不可 见的。 CPU发出取指令请求时的地址是当前上下文的虚拟地址, MMU再从页表中找到 这个虚拟地址的物理地址, 完成取指。 In the x86 platform, the system's addresses are divided into physical addresses, bus addresses, and virtual addresses. In Linux, the 4GB (virtual) memory of a process is divided into user space and kernel space. The user space is 0~3GB (ie PAGE_OFFSET, which is equal to OxCOOOOOOO in 0X86), and 1G in lj is kernel space. Programmers can only use virtual addresses. Each process in the system has its own private user space (0 to 3G), which is invisible to other processes in the system. The address when the CPU issues the fetch request is the virtual address of the current context, and the MMU finds the physical address of the virtual address from the page table, and completes the fetching.
而且 x86平台使用了名为内存映射 (MMIO) 的技术, 该技术是 PCI规范的一部分, 10设备端口被映射到内存空间, 映射后, CPU访问 10端口就如同访问内存一样。 图 2 是 coreboot中 AMD桥片的几个设备的 MEM映射地址, 'h' 表示十六进制。 Moreover, the x86 platform uses a technology called Memory Map (MMIO), which is part of the PCI specification. 10 device ports are mapped to memory space. After mapping, the CPU accesses port 10 as if it were accessing memory. Figure 2 shows the MEM mapping address for several devices in the AMD bridge in coreboot, and 'h' for hexadecimal.
龙芯 CPU是 MIPS架构的 CPU, 与 x86 CPU的地址分配和寻址方式有所不同。龙芯 3A采用 48位的物理地址空间, 47〜44 位区分标示 16个节点, 44~0 为每个节点的内部 地址; 龙芯刀片服务器是由两个节点组成的 CC-NUMA的架构,整个系统的地址空间可 分为 4个层次, 即物理地址区间、 节点内一二级 crossbar路由的地址空间、 HT的地址
空间、 PCI的地址空间。 下一层次是上一层的一个子区间, 见图 3所示。 The Godson CPU is a CPU of the MIPS architecture, which is different from the address allocation and addressing mode of the x86 CPU. Godson 3A uses 48-bit physical address space, 47-44 bits distinguish 16 nodes, 44~0 is the internal address of each node; Godson blade server is a CC-NUMA architecture consisting of two nodes, the whole system The address space can be divided into four levels, that is, the physical address interval, the address space of the first-level crossbar route in the node, and the address of the HT. Space, PCI address space. The next level is a subinterval of the previous level, as shown in Figure 3.
. 系统中必须有一个 node— id为 0的主节点, 负责系统的启动,龙芯刀片服务器另一个 节点的 node— id 由硬件跳线设置为 01, 因此整个系统的物理地址空间范围为 [0x0000 0000— 0000 ~ 0x2000—0000—0000],其中 [0x0000 0000— 0000 ~ 0x1000—0000—0000] 为节点 0的物理地址范围, [0xl000_0000_0000 ~0x2000_0000_0000]为节点 01的物理地 址范围。 The system must have a node with node-id 0, which is responsible for system startup. The node-id of another node of the Godson blade server is set to 01 by the hardware jumper, so the physical address space range of the entire system is [0x0000 0000 — 0000 ~ 0x2000—0000—0000], where [0x0000 0000— 0000 ~ 0x1000—0000—0000] is the physical address range of node 0, and [0xl000_0000_0000 ~0x2000_0000_0000] is the physical address range of node 01.
在南北桥芯片上连接的设备都是 PCI设备。 PCI系统有 4GB的 memory空间和 64K 的 10空间, CPU要访问 PCI设备的配置空间、 memory空间、 和 10空间需要经过一系 列的转换过程即 48位的 CPU地址空间 40 位的 HT地址空间 PCI的地址空间。 如图 4所示。 The devices connected to the North and South Bridge chips are PCI devices. The PCI system has 4GB of memory space and 64K of 10 space. The CPU needs to access the configuration space, memory space, and 10 space of the PCI device. After a series of conversion processes, that is, 48-bit CPU address space, 40-bit HT address space PCI. Address space. As shown in Figure 4.
1. CPU的物理地址空间到 HT地址空间的转换 1. Conversion of CPU physical address space to HT address space
龙芯 3A把 CPU物理地址空间 [OxOeOO— 0000— 0000〜 0χ1000_0000_0000]映射到 HT的 40位地址空间 [0x00—0000—0000 ~ 0χ100_0000_0000],这种映射是通过一级 crossbar的地 址路由窗口或者一级 crossbar的默认设置实现的。因为 HT只有 40位的地址空间对多余 的位不予考虑。 Godson 3A maps the CPU physical address space [OxOeOO- 0000-0000~0χ1000_0000_0000] to the HT 40-bit address space [0x00-0000-0000 ~ 0χ100_0000_0000]. This mapping is through the address routing window of the primary crossbar or the first-level crossbar. The default settings are implemented. Because HT has only 40 bits of address space, it does not consider extra bits.
2. HT地址空间到 PCI地址空间的转换 2. Conversion from HT address space to PCI address space
HT 40位地址空间的到 PCI地址空间的映射是通过 HT to PCI bridge实现的, 这是硬 件保证的不需要软件做任何配置。映射后 PCI设备的起始 MEM地址为 0x10000000, 10 起始地址为 0x18000000。 这个地址在 PMON程序中作为 PCI的 MEM BASE或者 10 BASEc 而对于每个 PCI设备, PMON通过建立了一个 pci— device的结构体。 在这个结 构体中记录了每个 PCI设备的信息, 包括该设备的类型, mem大小, 以及 next device 的指针等, 组成了一个链表。在 PCI设备扫描过程中, PMON就会根据该链表递归的搜 寻所有设备的资源请求信息, 并形成 pci— win结构, 组成 memory和 10资源请求链表。 在 PCI设备资源分配过程中就会按照下面公式, 进行 memory和 10的分配: The mapping of the HT 40-bit address space to the PCI address space is implemented via the HT to PCI bridge, which is hardware-guaranteed and requires no software configuration. After mapping, the starting MEM address of the PCI device is 0x10000000, and the starting address of 10 is 0x18000000. This address is used as a PCI MEM BASE or 10 BASEc in the PMON program. For each PCI device, PMON establishes a pci-device structure. The information of each PCI device is recorded in this structure, including the type of the device, the mem size, and the pointer of the next device, which form a linked list. During the PCI device scanning process, PMON searches the resource request information of all devices recursively according to the linked list, and forms a pci-win structure to form a memory and 10 resource request linked list. In the PCI device resource allocation process, the allocation of memory and 10 is performed according to the following formula:
PCI设备 MEM地址 =上一个设备的 MEM地址 +该 PCI设备的 MEM请求大小 PCI device MEM address = MEM address of the previous device + MEM request size of the PCI device
PCI设备 10地址 =上一个设备的 MEM地址 +该 PCI设备的 10请求大小 PCI device 10 address = MEM address of the previous device + 10 request size of the PCI device
其中第一个设备的 MEM地址的初始值等于 0x10000000, 10地址为 0x18000000。在 PMON程序中, 通过读取 PCI设备的配置空间来获取设备的 MEM、 10大小, 从而分配 PCI设备的 MEM、 10地址。 The initial value of the MEM address of the first device is equal to 0x10000000, and the 10 address is 0x18000000. In the PMON program, the MEM, 10 size of the device is obtained by reading the configuration space of the PCI device, thereby allocating the MEM, 10 address of the PCI device.
二、 龙芯 3A主板上的设备 DMA操作配置: Second, Godson 3A motherboard device DMA operation configuration:
在龙芯 CPU中设备以 DMA的方式访问内存的过程如下:
1、 PCI设备发出访存的地址经过北桥芯片, 由北桥路由到 HT1控制器;The process of accessing memory by DMA in the Loongson CPU is as follows: 1. The address that the PCI device sends out to access the memory passes through the North Bridge chip and is routed from the North Bridge to the HT1 controller.
2、 HT1控制器根据其内部地址窗口寄存器将地址路由到一级 crossbar 2. The HT1 controller routes the address to the first level based on its internal address window register.
3、 一级 crossbar根据其内部的地址窗口寄存器将地址路由到二级 cache, 然后到二 级 crossbar; 3, the first level crossbar according to its internal address window register to the address to the secondary cache, and then to the second level crossbar;
4、 二级 crossbar根据其内部的地址窗口配置将地址路由到内存控制器。 4. The secondary crossbar routes the address to the memory controller according to its internal address window configuration.
南北桥芯片处连接了很多需要进行 DMA操作的设备, 比如网卡设备, 它在接收、 发送数据报文时, 需要进行 DMA操作。 因为 X86架构与 MIPS架构在内存物理地址上 的差异, 就需要在 BIOS中对北桥的相关 DMA操作寄存器的设置做相应的修改, 否则 会导致 DMA操作无法正确进行。本发明在 PMON中针对北桥的相关寄存器做了如下修 改: 将 nbconfig 0x90的值由 0x40000000改成 ΟχίΌΟΟΟΟΟΟ, 从而保证了南北桥设备的 DMA操作地址正确, 保证了设备 DMA的正常工作。 The north and south bridge chips are connected to many devices that need to perform DMA operations, such as network card devices, which need to perform DMA operations when receiving and sending data messages. Because of the difference between the X86 architecture and the MIPS architecture in the physical address of the memory, it is necessary to modify the setting of the DMA operation register of the North Bridge in the BIOS. Otherwise, the DMA operation cannot be performed correctly. The invention makes the following modifications to the related registers of the north bridge in PMON: The value of nbconfig 0x90 is changed from 0x40000000 to ΟχίΌΟΟΟΟΟΟ, thereby ensuring the correct DMA operation address of the north and south bridge devices, and ensuring the normal operation of the device DMA.
三、 龙芯刀片 PCI配置空间和 10空间读写: Third, Godson blade PCI configuration space and 10 space read and write:
在龙芯刀片 BIOS中对南北桥设备的初始化代码主要借鉴 x86架构的 BIOS coreboot 0 在 coreboot中, 南北桥芯片初始化代码是完全按照 X86 CPU的工作原理实现的。 而龙 芯 3处理器是 MIPS架构的 CPU, 在地址空间、 PCI配置空间读写访问等方面与 X86架 构完全不同, 这就需要我们对南北桥芯片初始化代码进行重新改写, 主要是针对南北桥 设备 PCI配置空间的读写函数等的修改。 In the Godson blade BIOS, the initialization code of the north and south bridge devices mainly draws on the x86 architecture BIOS coreboot 0 in coreboot, the north and south bridge chip initialization code is completely implemented according to the working principle of the X86 CPU. The Godson 3 processor is a MIPS architecture CPU. The address space and PCI configuration space read and write access are completely different from the X86 architecture. This requires us to rewrite the north and south bridge chip initialization code, mainly for the north and south bridge device PCI. Modification of the read and write functions of the configuration space.
X86架构 CPU使用的 BIOS程序基本上都是使用了 PCI兼容配置方法读写 PCI配置 空间寄存器。 X86 Architecture The BIOS used by the CPU basically uses the PCI compatible configuration method to read and write the PCI configuration space registers.
PC1兼容配置方法使用了两个 32位的 10端口, 分别为配置地址端口 0xCF8和配置 数据端口 0XCFC。 配置地址端口数据格式如图 5所示。 The PC1 compatible configuration method uses two 32-bit 10 ports, which are configuration address port 0xCF8 and configuration data port 0XCFC. Configure the address port data format as shown in Figure 5.
当要读设备的 PCI配置空间寄存器内容时, 需要将设备的总线号、 设备号、 功能号、 寄存器位置等信息写到配置地址端口, 然后读配置数据端口, 即可得到 PCI配置空间相 关寄存器的内容。 When you want to read the PCI configuration space register contents of the device, you need to write the bus number, device number, function number, register position and other information of the device to the configuration address port, and then read the configuration data port to get the PCI configuration space related register. content.
当要写设备的 PC1配置空间寄存器内容时, 需要将设备的总线号、 设备号、 功能号、 寄存器位置等信息写到配置地址端口, 然后将数据写到配置数据端口, 即可将相关内容 写到 PCI配置空间相关寄存器。 When writing the contents of the PC1 configuration space register of the device, you need to write the bus number, device number, function number, register position and other information of the device to the configuration address port, and then write the data to the configuration data port to write the relevant content. Go to the PCI configuration space related registers.
PCI、 PCI-E总线可以使用此方法对总线上的设备内部的 PCI配置空间寄存器进行读 写操作。 使用此方法, 可以对 PCI配置空间寄存器直接进行 8位、 16位、 32位的读写 操作。 The PCI and PCI-E buses can use this method to read and write the PCI configuration space registers inside the device on the bus. Using this method, the PCI configuration space registers can be directly read and written by 8-bit, 16-bit, and 32-bit.
而在 MIPS架构下采用的是 HT总线配置方法读写 PCI配置空间寄存器。
HT总线配置方法指 HT总线即可以使用 PCI兼容配置方法对总线上的设备内部的 PCI配置空间寄存器进行读写操作, 也可以使用自己特有的配置方法对总线上的设备内 部的 PCI配置空间寄存器进行读写操作。 In the MIPS architecture, the HT bus configuration method is used to read and write the PCI configuration space register. The HT bus configuration method means that the HT bus can use the PCI compatible configuration method to read and write the PCI configuration space register inside the device on the bus, or use its own unique configuration method to perform the PCI configuration space register inside the device on the bus. Read and write operations.
在 MIPS架构下, 类型 0、 类型 1的地址格式如图 6所示, 其中 40位到 63位地址需 要根据 CPU和 HT总线确定, 目前我们使用的地址为 0x90000E。 在龙芯 3A主板上, 我们定义类型 0 地址 HT—MAP_TYPE0— CONF_ADDR 为 OxbaOOOOOO, 类型 1 地址 HT M AP T YPE 1 CONF ADDR为 0xbb000000。 In the MIPS architecture, the address format of type 0 and type 1 is shown in Figure 6. The 40-bit to 63-bit address needs to be determined according to the CPU and HT bus. Currently, the address we use is 0x90000E. On the Godson 3A motherboard, we define type 0 address HT_MAP_TYPE0—CONF_ADDR is OxbaOOOOOO, type 1 address HT M AP T YPE 1 CONF ADDR is 0xbb000000.
当要读设备的 PCI配置空间寄存器内容时, 需要将设备的总线号、 设备号、 功能号、 寄存器位置等信息与首地址相加, 得到最后的读写访问地址。 公式如下: When you want to read the PCI configuration space register contents of the device, you need to add the bus number, device number, function number, register position and other information of the device to the first address to get the last read and write access address. The formula is as follows:
addr |= (dev « 11 | func « 8 | reg) Addr |= (dev « 11 | func « 8 | reg)
其中 addr = HT MAP TYPEO CONF ADDR或者 Where addr = HT MAP TYPEO CONF ADDR or
HT MAP TYPE 1 CONF ADDR; reg为需要操作的 PCI寄存器号。 HT MAP TYPE 1 CONF ADDR; reg is the PCI register number to be operated.
当对最后得到的地址进行读访问时, 即可得到 PCI配置空间相关寄存器的内容; 当 将相关数据写到最后得到的地址时, 即可将相关内容写到 PCI配置空间相关寄存器。 When a read access is made to the last obtained address, the contents of the PCI configuration space related register are obtained; when the relevant data is written to the last obtained address, the relevant content can be written to the PCI configuration space related register.
对于 10操作, 在 X86架构下, 存在区间为 OxO-Oxffff的 10地址空间, 可以使用 in、 out指令进行访问。 而在 MIPS架构中, 并没有直接对应的 10地址空间, 也没有直接对 应于 in、 out这样的指令对 10地址空间进行访问。 但有些如串口、 实时时钟、 中断控制 器、 IDE等设备在正常工作时, 都需要对它们使用的 10地址空间进行相应的读写操作。 这样, 在 MIPS架构下, 也要实现对应的读写操作, 才能使这些设备正常工作。 为了解 决此问题, 将 HT地址窗口中的 OxFDFCOOOOOO做为 10地址空间。 这段区域映射后的 基地址为 Oxb8000000。 这样 10地址的公式为: For the 10 operation, under the X86 architecture, there is a 10-address space with an interval of OxO-Oxffff, which can be accessed using the in and out instructions. In the MIPS architecture, there is no direct corresponding 10 address space, and there is no direct access to the 10 address space for instructions such as in, out. However, some devices such as serial port, real-time clock, interrupt controller, IDE, etc. need to read and write the 10 address space they use during normal operation. In this way, under the MIPS architecture, the corresponding read and write operations must also be implemented in order for these devices to work properly. To understand this, use OxFDFCOOOOOO in the HT address window as the 10 address space. The base address after mapping this area is Oxb8000000. The formula for such a 10 address is:
addr BONITO—PCIIO— BASE— VA + addr Addr BONITO—PCIIO— BASE— VA + addr
其中 BONITO PCUO— BASE— VA = 0xb8000000 Where BONITO PCUO— BASE— VA = 0xb8000000
因此, 为了实现从 coreboot到 pmon的无缝移植就需要对 PCI配置空间的读写函数 和 10空间的读写函数进行修改和添加。 更改、 添加的函数接口包括 PCI配置空间寄存 器 8位、 16位、 32位读操作函数; PCI配置空间寄存器 8位、 16位、 32位写操作函数; PCI配置空间类型 0、 类型 1读 /写方法; 调试信息输出函数; Memory寄存器 8位、 16 位、 32位读、 写函数; 10寄存器 8位、 16位、 32位读、 写函数; 初始化配置参数设置 函数; 设备查找函数; 设备定位函数等; 其他需要更改的还包括 10地址宏定义等; 四、 龙芯 3A主板的 pmon调试方法 Therefore, in order to achieve seamless migration from coreboot to pmon, you need to modify and add the PCI configuration space read and write functions and 10 space read and write functions. The changed and added function interface includes PCI configuration space register 8-bit, 16-bit, 32-bit read operation function; PCI configuration space register 8-bit, 16-bit, 32-bit write operation function; PCI configuration space type 0, type 1 read/write Method; Debug information output function; Memory register 8-bit, 16-bit, 32-bit read and write function; 10 register 8-bit, 16-bit, 32-bit read and write function; Initial configuration parameter setting function; Device search function; Device positioning function Etc. Other changes that need to be included include 10 address macro definitions, etc. 4. Pmon debugging method for Godson 3A motherboard
在龙芯 3A主板调试初期, 并不能保证 pmon中对南北桥初始化的代码都正确, 所有
设备都能正常工作。 为了保证龙芯刀片主板上电调试进度和减轻调试工作的复杂度, 我 们选择一种化繁为简的方法, 即先在 pmon代码的 PCI设备扫描之前, 屏蔽南北桥中复 杂的、 不使用的设备, 而进行后续必要设备的调试。 In the early stage of the Loongson 3A motherboard debugging, there is no guarantee that the code for initializing the north and south bridges in pmon is correct, all The device works fine. In order to ensure the power-on debugging progress of the Loongson blade motherboard and reduce the complexity of the debugging work, we choose a simple and simple method, that is, to shield the complex and unused devices in the north-south bridge before scanning the PCI device of the pmon code. , and the subsequent necessary equipment debugging.
图 7为 PMON代码初始化流程图: Figure 7 shows the PMON code initialization flow chart:
从流程图中看出, PMON在汇编部分主要进行 CPU、 内存与串口等的调试, 进入 C 语言部分后, 开始南北桥控制器与设备的初始化。 其中南北桥初始化过程中首先会对各 个设备的控制器进行使能与初始化,这样在 PCI扫描过程中会枚举出己被使能的控制器 下的设备, 而未被使能的控制器就不进行枚举和分配资源。 因此调试的简化做法是在初 始化南北桥之后, PCI扫描之前,关掉南北桥中这些较复杂的设备的控制器,使得在 PCI 扫描的时候, 程序认为这些设备的控制器都未被使能, 控制器下面没有设备, 这样就不 会对这些设备进行初始化, 大大减少了干扰, 降低了调试的复杂度。 As seen from the flow chart, PMON mainly performs debugging of CPU, memory and serial port in the assembly part. After entering the C language part, the initialization of the north and south bridge controllers and devices is started. In the initialization process of the north-south bridge, the controllers of each device are first enabled and initialized, so that the devices under the controller that have been enabled are enumerated during the PCI scanning process, and the controllers that are not enabled are Do not enumerate and allocate resources. Therefore, the simplification of debugging is to turn off the controllers of these more complex devices in the north and south bridges before the PCI scan, after the initialization of the north and south bridges, so that during the PCI scan, the program considers that the controllers of these devices are not enabled. There are no devices under the controller, so they will not be initialized, which greatly reduces the interference and reduces the complexity of debugging.
五、 龙芯 3A主板中 Linux内核的中断分配: Five, Godson 3A motherboard Linux kernel interrupt allocation:
x86架构的中断系统有 256个中断号, 当中断发生时, CPU用中断号索引以 IDTR 寄存器的值为基地址的中断描述符表(IDT), IDT的每个表项指向相应的中断处理程序。 The x86 architecture interrupt system has 256 interrupt numbers. When an interrupt occurs, the CPU uses the interrupt number to index the interrupt descriptor table (IDT) with the IDTR register as the base address. Each entry of the IDT points to the corresponding interrupt handler. .
而在龙芯 3号 CPU的中断处理系统中, 只存在特例异常和通用异常。 特例异常包括 冷启动、 TLB重填、 xTLB重填、 cache错误; 通用异常共 32个, 第 0号通用异常就是 与外部设备相关的中断, 图 8中表示的就是龙芯 3A主板的四级级联的中断结构图。 其 中前三级属于 CPU内部的中断级联。 In the interrupt processing system of the Godson 3 CPU, there are only special exceptions and general exceptions. Special exceptions include cold start, TLB refill, xTLB refill, and cache error. There are 32 general exceptions. The general exception No. 0 is the interrupt associated with the external device. Figure 8 shows the four-level cascade of the Godson 3A motherboard. Interrupt structure diagram. The first three levels belong to the interrupt cascade inside the CPU.
第一级是 CPU每个核的中断控制器, CPU内部有 4个核,每个核的 Cause 和 Status 寄存器分别组成一个中断控制器。 CPU执行完一条指令后都会检査 Cause寄存器相应的 位有没有被置位。第二级由一个具有 32根中断线的中断控制器组成, 32根中断线可以 通过配置 CPU内部的中断路由寄存器, 将中断分别路由到 CPU的 4个核上。 第三级由 HT 中断控制器、 LPC中断控制器、 核间中断控制器组成。 其中 HT中断控制器用于接 受 10设备的中断。 第四级与 AMD芯片组有关, 它连接在南桥的 8259A控制器上, 而 桥片上的所有外设中断都是先送往 8259A控制器, 然后再送往 HT中断控制器的。 The first level is the interrupt controller of each core of the CPU. There are 4 cores inside the CPU. The Cause and Status registers of each core form an interrupt controller. After the CPU executes an instruction, it will check if the corresponding bit of the Cause register is set. The second stage consists of an interrupt controller with 32 interrupt lines. The 32 interrupt lines can be routed to the CPU's 4 cores by configuring the CPU's internal interrupt routing registers. The third stage consists of an HT interrupt controller, an LPC interrupt controller, and an inter-core interrupt controller. The HT interrupt controller is used to accept interrupts from 10 devices. The fourth stage is related to the AMD chipset. It is connected to the South Bridge's 8259A controller, and all peripheral interrupts on the bridge are sent to the 8259A controller before being sent to the HT interrupt controller.
因此,配置外部设备中断的关键在于外设和南桥 8259A控制器的配合。根据 AMD 南 桥 8259A的特点, 可以分为三个步骤: Therefore, the key to configuring an external device interrupt is the cooperation of the peripheral and the South Bridge 8259A controller. According to the characteristics of AMD South Bridge 8259A, it can be divided into three steps:
1) 配置好设备的 interrupt_pm是连接在 8259A控制器的第几根中断线上, 这种连 接有些是硬件设置好的, 有些是需要软件配置的。 在 AMD桥片的 8259A中断线有 12 根。 -1) The int e rrupt_pm of the configured device is connected to the first interrupt line of the 8259A controller. Some of the connections are hardware settings and some require software configuration. There are 12 8259A interrupt lines on the AMD bridge. -
2) 配置 interrupt line, 也就是中断号。
3) 配置中断的触发方式, 电平触发还是边沿触发。 2) Configure the interrupt line, which is the interrupt number. 3) Configure the trigger mode of the interrupt, level trigger or edge trigger.
配置好这三项后, 南北桥设备就可以正常响应中断了, 图 9描述了外部设备响应中 断的过程。 After configuring these three items, the North and South Bridge devices can be interrupted normally. Figure 9 describes the process of responding to the interrupt of the external device.
当某个硬件设备触发了中断, CPU硬件会相应的设置 cause寄存器的 Exc code域及 IP位。 内核中通用异常处理中的程序 except— vec3— generic就会查询 cause寄存器的 Exc code域来确定是 32种通用异常中的哪一种。 外部设备中断属于 0号, 那么内核进入中 断处理程序的入口地址 handle— init 并调用中断分发函数 plat_irq_dispatch。 plat_irq_dispatch 将根据 CPU CAUSE 寄存器的 [IP7~IP0]判断是那个中断源或者中断 控制器发生了中断, 外部设备中断是属于 HT1 中断控制器, 而与 HT1 中断控制器级联 的就是南桥的 8259A控制器。 这样函数就会调用 8259A的中断分配过程, 也就是上面 描述的三个步骤。通过这三个步骤将中断号分发完后,内核就会直接调用 do_IRQ()函数, 执行对应的驱动程序。 整个中断调用过程也就完成了。 When a hardware device triggers an interrupt, the CPU hardware sets the Exc code field and IP bit of the cause register accordingly. The program in the general exception handling in the kernel except - vec3 - generic will query the Exc code field of the cause register to determine which of the 32 general exceptions. The external device interrupt belongs to number 0, then the kernel enters the interrupt handler's entry address handle_init and calls the interrupt dispatch function plat_irq_dispatch. Plat_irq_dispatch will judge whether the interrupt source or interrupt controller has an interrupt according to [IP7~IP0] of the CPU CAUSE register. The external device interrupt belongs to the HT1 interrupt controller, and the HT1 interrupt controller is cascaded with the South Bridge 8259A control. Device. This function will call the 8259A interrupt allocation process, which is the three steps described above. After the interrupt number is distributed through these three steps, the kernel will directly call the do_IRQ() function to execute the corresponding driver. The entire interrupt call process is complete.
另外, 从图 8中可以看出, AMD桥片上的所有 10设备中断是通过 HT1中断路由传 到 CPU的, 而且由于龙芯 3A CPU内没有实现 APIC的功能, 因此 10设备的中断只能 发送到主 CPU的 4个核, 次 CPU不能处理 10中断。 最后应当说明的是: 以上实施例仅用以说明本实用新型的技术方案而非对其限制, 尽管参照上述实施例对本实用新型进行了详细的说明, 所属领域的普通技术人员应当理 解: 依然可以对本实用新型的具体实施方式进行修改或者等同替换, 而未脱离本实用新 型精神和范围的任何修改或者等同替换, 其均应涵盖在本实用新型的权利要求范围当 中。
In addition, as can be seen from Figure 8, all 10 device interrupts on the AMD bridge are transmitted to the CPU through the HT1 interrupt route, and since the APIC function is not implemented in the Godson 3A CPU, the interrupt of 10 devices can only be sent to the master. The CPU has 4 cores, and the secondary CPU cannot handle 10 interrupts. Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present invention and are not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that: Modifications or equivalents of the present invention are intended to be included within the scope of the appended claims.
Claims
1、 一种龙芯 CPU主板 bios以及中断的实现方法, 其特征在于: 步骤如下: 将龙芯 CPU与北桥芯片进行地址映射转换; 1. A Loongson CPU motherboard bios and an interrupt implementation method are characterized by the following steps: The address mapping of the Loongson CPU and the Northbridge chip is performed;
将 DMA设备地址进行映射转换; Mapping the DMA device address;
对 PCI地址空间进行配置; 以及 Configuring the PCI address space;
将 coreboot与 pmon融合成新 bios后, 调试; 以及, After coreboot and pmon are merged into new bios, debugging; and,
调试内核中断系统。 Debug the kernel interrupt system.
2、如权利要求 1所述的方法,其特征在于:所述地址映射转换过程为先将龙芯 CPU 物理地址空间映射到 HT总线地址空间, 再将 HT总线地址空间映射到 PCI地址空间。 The method according to claim 1, wherein the address mapping conversion process first maps the Loongson CPU physical address space to the HT bus address space, and then maps the HT bus address space to the PCI address space.
3、 如权利要求 2所述的方法, 其特征在于: 所述龙芯 CPU物理地址空间映射到 HT总线地址空间是通过一级 crossbar实现的。 3. The method according to claim 2, wherein: mapping the Loongson CPU physical address space to the HT bus address space is implemented by a first-level crossbar.
4、 如权利要求 3所述的方法, 其特征在于: 所述龙芯 CPU物理地址空间映射时只 映射 48位地址空间。 4. The method according to claim 3, wherein: the Loongson CPU physical address space mapping only maps a 48-bit address space.
5、 如权利要求 2所述的方法, 其特征在于: 所述 HT总线地址空间映射到 PCI地 址空间是通过 HT to PCI bridge实现。 5. The method of claim 2, wherein: mapping the HT bus address space to the PCI address space is implemented by using an HT to PCI bridge.
6、 如权利要求 1 所述的方法, 其特征在于: 所述 DMA设备地址映射转换是通过 修改北桥芯片内与 DMA寻址相关的寄存器初值实现。 6. The method of claim 1 wherein: said DMA device address mapping conversion is accomplished by modifying an initial value of a register associated with DMA addressing within the Northbridge chip.
7、 如权利要求 6所述的方法, 其特征在于: 所述寄存器可以进行 8位, 16位和 32 位读写操作。 7. The method of claim 6 wherein: said register is capable of 8-bit, 16-bit and 32-bit read and write operations.
8、 如权利要求 1所述的方法, 其特征在于: 所述 bios是将 PM0N的 CPU、 内存和串 口的调试部分与 coreboot的南北桥控制器和设备的初始化部分融合。 8. The method of claim 1, wherein: the bios fuses the debug portion of the CPU, memory, and serial ports of the PM0N with the initialization portion of the northboot bridge controller and device of the coreboot.
9、如权利要求 1所述的方法, 其特征在于: 所述 bios调试时在初始化南桥后, PCI 扫描前, 关闭掉所有可能影响调试的设备控制器。 9. The method according to claim 1, wherein: after the bios is debugged, after the south bridge is initialized, all device controllers that may affect debugging are turned off before the PCI scan.
10、 如权利要求 1所述的方法, 其特征在于: 所述内核中断系统是通过将龙芯 CPU 的中断控制器与 8259A控制器级联, 来响应和控制南北桥外部设备的中断请求。 10. The method of claim 1, wherein: the kernel interrupt system responds to and controls an interrupt request of an external device of the north-south bridge by cascading an interrupt controller of the Loongson CPU with the 8259A controller.
11、 如权利要求 1所述的方法, 其特征在于: 所述中断系统采用异常处理表来对中 断分类。 11. The method of claim 1 wherein: said interrupt system employs an exception handling table to classify the interrupts.
12、 如权利要求 1所述的方法, 其特征在于: 采用中断控制器处理中断。 12. The method of claim 1 wherein: the interrupt is processed by an interrupt controller.
13、 如权利要求 10所述的方法, 其特征在于: 所述中断系统采用南桥 8259A控制 器与龙芯 3A CPU的中断控制器相配合, 来实现外部设备中断的响应。 13. The method according to claim 10, wherein: the interrupt system uses a South Bridge 8259A controller in conjunction with an interrupt controller of the Loongson 3A CPU to implement an external device interrupt response.
14、 如权利要求 10所述的方法, 其特征在于: 龙芯 3A主板通过配置南桥设备的中 断阵脚、 中断线路和触发方式, 来分配南桥设备的中断号。 14. The method of claim 10, wherein: the Loongson 3A motherboard allocates an interrupt number of the south bridge device by configuring an interrupt pin, an interrupt line, and a trigger mode of the south bridge device.
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CN2010105364701A CN102023878A (en) | 2010-11-04 | 2010-11-04 | Method for realizing Infiniband network on Loongson blade server |
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CN201010536470.1 | 2010-11-04 | ||
CN201010536636XA CN102023880A (en) | 2010-11-04 | 2010-11-04 | Basic input/output system (BIOS) for godson blade |
CN201110126477.0A CN102184122B (en) | 2011-05-16 | 2011-05-16 | Interrupt realizing method for Loongson central processing unit (CPU) mainboard |
CN201110126477.0 | 2011-05-16 |
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