WO2012133964A1

WO2012133964A1 - Apparatus and method for generating digital value

Info

Publication number: WO2012133964A1
Application number: PCT/KR2011/002219
Authority: WO
Inventors: 김태욱; 김동규; 최병덕
Original assignee: 한양대학교 산학협력단
Priority date: 2011-03-31
Filing date: 2011-03-31
Publication date: 2012-10-04

Abstract

An apparatus and a method for generating a physically unclonable function (PUF) value are disclosed. An apparatus for generating a digital value comprises: a digital value generation unit for generating a random digital value by using a process variation of a semiconductor; and a digital value freezing unit, which is connected to the digital value generation unit and is fixed in either a first state or a second state in accordance with the generated digital value, for freezing the digital value, thereby freezing the digital value that is generated when the digital value generation unit is initially driven.

Description

Digital value generator and method

Related to the field of digital security, and more specifically, security of electronic devices, embedded system security, system on chip (SoC) security, smart card security, universal subscriber identity module (USIM) security, etc. An apparatus and method for generating an identification key for use in digital signatures and the like are required for encryption and decryption.

With the recent development of technologies such as electronic tags, the necessity of inserting a unique ID (hereinafter referred to as an identification key) on a chip produced in large quantities has increased. Accordingly, there is a need for an apparatus and method for generating random digital values (such as identification keys or unique IDs).

However, in order to use the identification key as a unique ID of a device or chip, the randomness and the once generated identification are completely random when the digital bits constituting the generated identification key are '1' and '0'. The key must be guaranteed with a high level of time-invariance that does not change over time.

However, the digital value generated from the apparatus for generating the conventional digital value satisfies randomness, but it is difficult to satisfy reliability, that is, time invariant due to noise, differential aging, and the like.

Therefore, there is an urgent need for an apparatus and method for generating a non-replicable digital value that is resistant to noise and resistant to environmental changes such as external temperature.

Apparatus and method for generating a PUF that is physically non-replicable using process deviations in the manufacturing process of a semiconductor chip, thereby generating a simple digital structure with random structure and freezing the generated value to ensure time invariance To provide.

The present invention provides a digital value generating device and method capable of generating reliable random digital values that are robust against noise and environmental changes and guarantee time invariance.

The digital value generator is connected to the digital value generator and a digital value generator that generates a random digital value using a process deviation of a semiconductor, and either one of a first state and a second state corresponding to the generated digital value. The digital value may be frozen by including a digital value freezing unit which is fixed to a state and freezes the digital value.

According to one side, the digital value generator may include a physically unclonable function (PUF) that is not physically replicable.

According to another aspect, the digital value generator is connected to the output terminal of the first inverter and the input terminal of the second inverter to the first node and the input terminal of the first inverter and the output terminal of the second inverter to the second node. In connection, when the first node and the second node are shorted, the digital value may be generated using a logical level of at least one of the first node and the second node.

According to another aspect, the digital value generator includes a differential amplifier for amplifying a potential difference between two input nodes, and generates the digital value by using a logical level of an output node when the two input nodes are shorted. Can be.

According to another aspect, the digital value generator includes an SR latch (Set-Reset latch) having two input nodes and two output nodes, and if the two input nodes are short-circuited the logical level of the output node The digital value may be generated by using the same.

According to another aspect, the digital value freezing unit may be a fuse that freezes the digital value by not breaking or not receiving an overcurrent corresponding to the digital value generated during the initial driving of the digital value generating unit.

According to another aspect, the first state may be a state where the fuse is blown, and the second state may be a state where the fuse is not blown.

According to another aspect, the digital value freezing unit may be a nonvolatile memory device that stores the digital value generated during the initial driving of the digital value generating unit.

According to another aspect, the nonvolatile memory device may be any one of an electrically erasable programmable read-only memory (EEPROM) and a flash memory.

According to another aspect, the first state may be a state in which a digital value '0' is stored in the nonvolatile memory device, and the second state may be a state in which a digital value '1' is stored in the nonvolatile memory device.

According to another aspect, the digital value freezing unit may be located inside the digital value generating unit.

In the digital value generating method, a digital value generating device generates a digital value using a semiconductor process deviation, wherein the digital value generating unit of the device is connected to the generating unit and to generate the random digital value. The digital value freezing unit of the device may include freezing the generated random digital value.

According to another aspect, the digital value generator may include a physically unclonable function (PUF) that is not physically replicable.

According to another aspect, the generating of the digital value may include connecting the output terminal of the first inverter and the input terminal of the second inverter to the first node and the input terminal of the first inverter and the output terminal of the second inverter. The method may include connecting to a second node and generating the digital value by using a logical level of at least one of the first node and the second node when the first node and the second node are shorted.

According to another aspect, the step of generating the digital value is based on a differential amplifier that amplifies the potential difference between two input nodes, using the logical level of the output node when the two input nodes are shorted. It may be a step of generating.

According to another aspect, the step of generating the digital value is based on an SR latch (Set-Reset latch) having two input nodes and two output nodes, when the two input nodes are shorted. The digital value may be generated using a logical level.

According to another aspect, the step of freezing the digital value by flowing an overcurrent to the fuse in response to the digital value generated during the initial driving of the circuit, the fuse is blown to freeze the digital value It may be a step.

According to another aspect, the freezing of the digital value may be a step of storing the digital value generated during initial driving of the circuit in a nonvolatile memory device.

According to another aspect, the nonvolatile memory device may be any one of an electrically erasable programmable read-only memory (EEPROM) and a flash ROM.

As the structure of the circuit for generating the digital value by using the process deviation of the manufacturing process of the semiconductor chip is simple and the time invariant is satisfied, the reliability of the digital value is increased.

In addition, even if different circuits are created under the same design, the same identification key is not generated, thereby physically replicating the circuits, thereby ensuring high security.

1 is a block diagram showing a digital value generating device according to an embodiment of the present invention.

2 is a circuit diagram illustrating a configuration of a digital value generating device according to an embodiment of the present invention.

3 is a timing diagram when voltage is applied to the digital value generating device according to one embodiment of the present invention.

4 through 9 are circuit diagrams for describing a configuration of a digital value generating device according to various embodiments of the present disclosure.

10 is a flowchart illustrating a digital value generating method according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a digital value generating device according to an embodiment of the present invention. The digital value generating device according to an embodiment of the present invention includes a digital value generating unit 110 and a digital value freezing unit 120.

The digital value generator 110 generates a random digital value based on the voltage vvd applied to the digital value generator 110.

Process deviations in semiconductor processes occur for a variety of reasons. For example, when manufacturing a transistor, parameters such as an effective gate length, an index of doping concentration, an index of oxide thickness, or a threshold voltage may be a cause of the process deviation. Since the process deviation is due to natural phenomena, the process deviation can be made small but not completely eliminated.

Therefore, in general, a semiconductor manufacturing process having a small process deviation is recognized to be excellent, and various techniques are attempted to reduce process variation in the technical field of the semiconductor process. However, the digital value generator 110 according to the present invention generates digital values that are randomly determined and are not changed once determined, using the process deviation of the semiconductor process.

The digital value freezing unit 120 is connected to the digital value generating unit 110 and is fixed to one of a first state and a second state corresponding to the digital value generated by the digital value generating unit 110. Freeze the digital value.

Although the digital value generated by the digital value generator 110 is guaranteed randomness by the process deviation, the digital value may change with time due to noise, differential aging, or the like. Accordingly, the digital value freezing unit 120 freezes the digital value so that the digital value does not change even when noise, environmental changes, etc. are generated so that a digital value that is guaranteed to be invariant in time is generated.

Hereinafter, the configuration of a digital value generating device in one embodiment of the present invention will be described in more detail with reference to FIG. 2.

Referring to FIG. 2, as described above, the digital value generator 210 generates a digital value that is not physically duplicated and may include, for example, a physically unclonable function (PUF).

2 illustrates, as an example, that the digital value generator 210 includes a PUF circuit including an SR latch (Set-Reset latch). In addition, an exemplary embodiment in which the digital value freezing unit 220 includes a first fuse and a second fuse is illustrated.

When the voltage vdd is applied to the SR latch included in the digital value generator 210 during the initial driving of the digital value generator, a random digital value is generated by the process deviation of the SR latch. At this time, the overcurrent flows to the digital value freezing unit 220 by the generated random digital value.

Accordingly, the fuse included in the digital value freezing unit 220 which has received the overcurrent is blown, and thus the digital value output through the digital value freezing unit 220 may be permanently frozen. That is, after the freezing, the configuration of the circuit is permanently changed according to whether the fuse is blown. Therefore, the digital value does not change after the circuit is changed by the initial driving. This process may be referred to as freezing. have.

Since the blown fuse is not connected again, this embodiment solves the problem of not guaranteeing time invariability, which is a problem when generating a digital value in a PUF circuit using a conventional process deviation.

3 is a timing diagram illustrating a digital value output as a voltage is applied to a digital value generating device according to an embodiment of the present invention with reference to FIG. 3.

3 illustrates an example in which the second fuse is blown as the overcurrent flows through the second fuse.

2 and 3, when the digital value generating device performs initial driving and a voltage is applied to the digital value generating unit 210, as the second fuse of the digital value freezing unit 220 is blown. The first output value is always generated at zero, and the second output value is always generated at one.

Accordingly, the digital value freezing unit 220 generates a random digital value generated by the digital value generating unit 210 according to the state of the fuse, that is, the first state in which the fuse is blown and the second state in which the fuse is not blown. The value can be frozen.

4 through 9 are circuit diagrams for describing a configuration of a digital value generating device according to various embodiments of the present disclosure. Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 4, the digital value generator is implemented to include a differential amplifier for amplifying a potential difference between two input nodes as shown in FIG. 4A, so that the digital value generator outputs when the two input nodes are shorted. Logical levels of nodes can be used to generate digital values.

The digital value freezing unit 400 may be implemented to include two fuses. In this case, the fuse may be connected between the digital value generating unit and the ground as shown in FIG. 2, but FIGS. 4B to 4D. It may be connected in the digital value generator as shown.

In this case, the fuse of the digital value determination unit may be connected to a position corresponding to each of the input nodes, as shown in Figure 4b may be connected between the input terminal and the output terminal, as shown in Figure 4c It may be connected in parallel between and the output terminal, it may be connected in parallel between the input terminal and the output terminal as shown in Figure 4d.

According to the configuration of the illustrated fuses, the overcurrent flows selectively to either fuse by a digital value generated during the first operation, so that the superiority of the output value is fixed from the first and subsequent operations.

For example, in the circuit of FIG. 4 (b), when OUT first outputs a voltage higher than OUTb (negative signal of OUT), the comparator compares it to a digital value and converts it into a digital value through a logic circuit and an overcurrent load circuit. Cut off by over-current flowing only to the right fuse.

Then, the output voltage of OUT is always vdd from the subsequent operation, and OUTb (the negative signal of OUT) always has an output voltage lower than vdd, so that the right and the right of the output voltage are fixed, and the digital value converted therefrom is also fixed.

Next, referring to FIG. 5, the digital value generator may include a dual inverter as shown in FIG. 5A.

In this case, an output terminal of the first inverter and an input terminal of the second inverter are connected to a first node, and an input terminal of the first inverter and an output terminal of the second inverter are connected to a second node, so that the first node and When the second node is shorted, the digital value may be generated using a logical level of at least one of the first node and the second node.

At this time, the fuse of the digital value freezing unit may also be connected between the digital value generating unit and the ground as in FIG. 5B, but may be connected between the power supply and the output terminal as in FIG. 5C, and the output terminal as in FIG. 5D. It may be connected in parallel between the and ground, and may be connected in parallel between the power supply and the output terminal as shown in FIG.

Next, referring to FIG. 6, the digital value generator includes an SR latch having two input nodes and two output nodes as shown in FIG. 6A, so that when the two input nodes are shorted, The digital value may be generated using a logical level.

In this case, the fuse of the digital value freezing unit may be connected between the digital value generating unit and the ground as shown in FIGS. 6B to 6D.

On the other hand, as shown in Figure 7, the digital value freezing unit of the present invention EEPROM (Electrically Erasable Programmable Read-Only Memory), the flash memory for storing the digital value generated during the initial driving of the digital value generation unit It may be implemented as a nonvolatile memory device.

In the following embodiment, a configuration using a nonvolatile memory device as the digital value freezing unit is described. However, the digital value freezing unit is not limited to the one including the nonvolatile memory device, but all floating gates. It can be configured utilizing an element.

Even when the digital value freezing unit is implemented to include a nonvolatile memory device, similarly to the case where the digital value freezing unit is implemented to include a fuse as described above, a state in which charge generated by a power applied to the digital value generating unit is charged, that is, The digital value generated according to the first state in which the digital value '0' is stored in the nonvolatile memory device and the second state in which the digital value '1' is stored in the nonvolatile memory device may be frozen.

In this case, as shown in FIG. 7A, the digital value generator includes a differential amplifier for amplifying a potential difference between input nodes, and connects the digital value freezing unit 700 to a position corresponding to the position where the fuse is connected. The generated digital value may be frozen by using the state in which the digital value is stored in the nonvolatile memory device.

Specifically, when the circuit operates, the ON voltage is applied to the gate of the flash memory device. In the initial operation, the floating gate of the flash memory device is charged with negative charge according to the superiority of the output voltage.

For example, the circuit of FIG. 7B charges the flash memory device on the right when the OUT voltage is high and the floating gate of the flash memory device on the left when the OUTb voltage is high. If the voltage at OUT is high and the floating gate of the right flash memory device is negatively charged, the output voltage of OUT is vdd because the right flash memory device does not turn on even if the ON voltage is input to the gate of the flash memory device in a subsequent operation. The OUTb output voltage is lower than that, so the voltage superiority of the initial operation is fixed as it is.

In this case, as in FIG. 7B, the nonvolatile memory device may be connected between an input terminal and an output terminal, and may be connected in parallel between a power supply and an output terminal as shown in FIG. 7C, and as shown in FIG. 7D. It can also be connected in parallel between the input and output terminals.

Next, referring to FIG. 8, the digital value generator may include a dual inverter as illustrated in FIG. 8A, and the digital value freezer may include a nonvolatile memory device.

In this case, the nonvolatile memory device of the digital value freezing unit may be connected between the digital value generating unit and ground as shown in FIG. 8B, but may be connected between a power supply and an output terminal as shown in FIG. 8C, and Likewise, it can be connected in parallel between the output terminal and ground, or can be connected in parallel between the power supply and the output terminal as shown in FIG. 8E.

Next, referring to FIG. 9, the digital value generator includes an SR latch having two input nodes and two output nodes as shown in FIG. 9A, and the digital value generator includes a nonvolatile memory device. Can be.

Even in this case, the nonvolatile memory device of the digital value freezing unit may be connected in various forms between the digital value generating unit and the ground as shown in FIGS. 9B to 9D.

Due to such a configuration, the digital value generator according to the present invention does not generate the same identification key even if different circuits are created under the same design, so that physical replication of the circuit is not possible. Thus, randomness and time invariance of the identification key are satisfied. By using multiple identical devices such as dual inverters, differential amplifiers, SR latches, EEPROMs, and flash memories to generate identification keys, physically copying is impossible, ensuring high security.

Hereinafter, a method of generating a digital value using a digital value generating device according to an embodiment of the present invention will be described with reference to FIG. 10.

First, when a voltage is applied to the digital value generator in the initial operation of the digital value generator (S1010), a random digital value is generated from the PUF included in the digital value generator due to the process deviation of the PUF (S1020).

Then, the digital value freezing unit of the digital value generating device causes the fuse included in the digital value freezing unit to be blown by using the current caused by the voltage, or the digital value freezing unit of the digital value freezing unit includes a digital value in the nonvolatile memory device included in the digital value freezing unit. By storing the digital value generated in the digital value generating device is permanently frozen (S1030).

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

Claims

A digital value generator for generating a random digital value using the process deviation of the semiconductor; And

A digital value freezing unit connected to the digital value generating unit and fixed to either one of a first state and a second state corresponding to the generated digital value to freeze the digital value;

Digital value generating device comprising a.
The method of claim 1,

The digital value generator

A digital value generating device comprising a physically unclonable function (PUF).
The method of claim 2,

The digital value generator

The output terminal of the first inverter and the input terminal of the second inverter are connected to a first node, and the input terminal of the first inverter and the output terminal of the second inverter are connected to a second node, so that the first node and the first node are connected. And generating the digital value by using a logical level of at least one of the first node and the second node when two nodes are shorted.
The method of claim 2,

The digital value generator

And a differential amplifier for amplifying the potential difference between two input nodes, wherein said digital value is generated using a logical level of an output node when said two input nodes are shorted.
The method of claim 2,

The digital value generator

A digital value comprising a set-reset latch having two input nodes and two output nodes, wherein the digital value is generated using a logical level of the output node when the two input nodes are shorted; Generating device.
The method of claim 1,

The digital value freezing unit

And a fuse that freezes the digital value by not breaking or not receiving an overcurrent corresponding to the digital value generated during initial driving of the digital value generator.
The method of claim 6,

The first state is

The fuse is blown;

The second state is

And the fuse is not blown.
The method of claim 1,

The digital value freezing unit

And a non-volatile memory device for storing the digital value generated during initial driving of the digital value generator.
The method of claim 8,

The nonvolatile memory device

A digital value generator, which is either EEPROM (Electrically Erasable Programmable Read-Only Memory) or Flash Memory.
The method of claim 8,

The first state is

The digital value '0' is stored in the nonvolatile memory device.

The second state is

And a digital value '1' is stored in the nonvolatile memory device.
The method of claim 1,

The digital value freezing unit

And a digital value generator located inside the digital value generator.
In the method of the digital value generating device to generate a digital value using the semiconductor process deviation,

Generating, by the digital value generator of the device, the random digital value; And

Freezing the generated random digital value by the digital value freezing unit of the device connected to the generation unit;

Digital value generation method comprising a.
The method of claim 12,

The digital value generator

A digital value generation method comprising a physically unclonable function (PUF).
The method of claim 13,

Generating the digital value

By connecting the output terminal of the first inverter and the input terminal of the second inverter to the first node and the input terminal of the first inverter and the output terminal of the second inverter to the second node, the first node and the first node Generating the digital value using a logical level of at least one of the first node and the second node when two nodes are shorted.
The method of claim 13,

Generating the digital value

And based on a differential amplifier amplifying the potential difference between two input nodes, generating the digital value using a logical level of an output node when the two input nodes are shorted.
The method of claim 13,

Generating the digital value

Based on an SR latch (Set-Reset latch) having two input nodes and two output nodes, the digital value that generates the digital value using the logical level of the output node when the two input nodes are shorted. How to generate a value.
The method of claim 12,

Freezing the digital value is

And freezing the digital value by causing the fuse to blow by flowing an overcurrent to the fuse in response to the digital value generated during initial driving of the circuit.
The method of claim 12,

Freezing the digital value is

And storing the digital value generated during the initial driving of the circuit in a nonvolatile memory device.
The method of claim 18,

The nonvolatile memory device

A method of generating digital values, either EEPROM (Electrically Erasable Programmable Read-Only Memory) or Flash ROM.