WO2012127177A1

WO2012127177A1 - Configuration memory cell

Info

Publication number: WO2012127177A1
Application number: PCT/GB2011/050543
Authority: WO
Inventors: Anthony Stansfield
Original assignee: Panasonic Corporation
Priority date: 2011-03-18
Filing date: 2011-03-18
Publication date: 2012-09-27

Abstract

A configuration memory for a programmable logic device (PLD) is described comprising a plurality of memory cells for a configuration memory of a programmable logic device (PLD) each memory cell comprising a storage element and first input means and second input means each being independently operable to provide access to the storage element. The second input means of at least one of the plurality of memory cells is arranged to receive control signals from a test interface for providing test signals to the PLD.

Description

CONFIGURATION MEMORY CELL

The present invention relates to storage elements for programmable logic devices (PLDs) and in particular, but not exclusively, to a memory cell for a PLD configuration memory.

Programmable logic devices (PLDs) typically comprise a number of configurable logic units the functionality of which is typically configured by data stored in associated configuration memories. The configuration memory of a reconfigurable array can make up a significant portion of the array. It is therefore desirable to use small circuit elements to keep the die area required for the configuration memory small.

In addition, it is desirable for the configuration memory to be compatible with conventional automatic test pattern generation (ATPG) tools. Compatibility with ATPG tools allows automatic generation of patterns of test data which are loaded by the ATPG tool into a configuration memory scan chain. This makes it easier to integrate the testing of the configuration memory with test patterns for the remainder of the chip where the array is a component in an application specific integrated circuit (ASIC) or system on chip device (SoC).

However, there is a conflict between the requirement for small circuit area and compatibility with conventional ATPG tools. An array that uses registers for the configuration memory is easy to generate test patterns for with an ATPG tool but each register is large compared to a simple latch (e.g. SRAM) cell.

An array having a configuration memory implemented using latches is significantly smaller than one using registers as a latch cell is typically half the size of register cell. However, latches are more difficult to use in an ATPG workflow.

There is therefore a need for an improved memory cell for configuration memories that addresses at least some of the above problems.

In a first aspect there is provided a configuration memory for a programmable logic device comprising a plurality of memory cells each memory cell comprising a storage element, an output and first input means and second input means each being independently operable to provide access to the storage element, wherein the second input means of at least one of the plurality of memory cells is arranged to receive control signals from a test interface for providing test signals to the programmable logic device.

Preferably the configuration memory further comprises a test interface arranged to control at least the second input means of the at least one of the memory cells.

Preferably at least one storage element comprises a latch comprising a pair of cross coupled inverters.

Further preferably the first and second input means comprise an enable input wherein said access is provided upon receipt of a predetermined signal level at the enable input.

In some embodiments the first or the second input means of at least one of the plurality of memory cells comprises a pair of access transistors having differential inputs connected across the pair of cross-coupled inverters. Preferably the first or the second input means of at least one of the plurality of memory cells comprises a transmission gate or pass-gate comprising a complimentary N-channel and P-channel transistor pair.

In some embodiments the second input means of at least one of the plurality of memory cells is operable to provide an output signal when the second input is un-driven and arranged to provide access to the storage element such that the memory cell acts as a bus keeper circuit.

In some embodiments the second input means of at least one of the plurality of memory cells is operable to provide an output signal when the second input is un-driven and the memory cell is configured such that both the first and second input means provide access to the storage element such that the memory cell acts as a weak driver circuit.

In further embodiments the storage element comprises a register having a master and slave latch circuit and preferably the second input means is provided to the slave latch. Further preferably, the first input means is enabled by a clock signal and the second input means is enabled by an independent enable input. Preferably the first input means comprises a first pair of access transistors having differential inputs connected across the master latch and a second pair of access transistors having differential inputs connected across the slave latch wherein the first and second pair of access transistors are arranged to receive complimentary signals from a clock. Preferably the second input means comprises a transmission or pass gate comprising a complimentary NMOS and PMOS transistor pair.

In a second aspect there is provided a memory cell for a configuration memory of a programmable logic device comprising a storage element, an output; and first input means and second input means each being independently operable to provide access to the storage element; wherein the second input means is arranged to receive control signals from a test interface for providing test signals to the programmable logic device. In embodiments the storage element comprises a latch comprising a pair of cross-coupled inverters.

Preferably the first and second input means comprise an enable input wherein said access is provided upon receipt of a predetermined signal level at the enable input.17 and preferably at least the first or second input means comprises a pair of access transistors having differential inputs connected across the pair of cross-coupled inverters. Further preferably the at least the first or second input means comprises a transmission gate or pass-gate comprising a complimentary N-channel and P-channel transistor pair.

In embodiments the memory cell is arranged such that the second input means is operable to provide an output signal when the second input means is un-driven and arranged to provide access to the storage element such that the memory cell acts as a bus keeper circuit.

In embodiments the memory cell is arranged so that the second input means is operable to provide an output signal when the second input means is un-driven and the memory cell is configured such that both the first and second input means provide access to the storage element such that the memory cell acts as a weak driver circuit.

In other embodiments the storage element comprises a register having a master and slave latch circuit. Preferably the second input means is provided to the slave latch.

In embodiments the first input means is enabled by a clock signal and the second input means is enabled by an independent enable input. Preferably, the first input means comprises a first pair of access transistors having differential inputs connected across the master latch and a second pair of access transistors having differential inputs connected across the slave latch wherein the first and second pair of access transistors are arranged to receive complimentary signals from a clock.

In embodiments the second input means comprises a transmission or pass gate comprising a complimentary NMOS and PMOS transistor pair.

In a further aspect there is provided configurable multiplexer circuit comprising a decoder, a plurality of buffered tri-state outputs and a memory cell according to the second aspect wherein the memory cell is configurable to operate as a bus-keeper circuit or a weak driver circuit.

In a further aspect there is provided a method of utilising a memory cell for a configuration memory of a programmable logic device comprising a storage element; an output; and first input means and second input means each being independently operable to provide access to the storage element said method comprising configuring any of the first or second input means to receive configuration signals from a configuration or test interface for providing test or configuration signals to the programmable logic device.

In a further aspect there is provided a method of utilising a memory cell for a configuration memory of a programmable logic device comprising a storage element; an output; and first input means and second input means each being independently operable to provide access to the storage element said method comprising arranging the second input means so that it is un-driven and arranging the second input means to provide access to the storage element; wherein the memory cell provides a weak driving signal to the second input means such that the memory cell acts as a bus keeper circuit.

In a further aspect there is provided a method of utilising a memory cell for a configuration memory of a programmable logic device comprising a storage element; an output; and first input means and second input means each being independently operable to provide access to the storage element said method comprising arranging the second input means to be un-driven providing a driving signal to the first input means, and configuring the first and second input means such that they both provide access to the storage element so that the memory cell allows the signal driving the first input to propagate to the second input means. Preferably the method comprises connecting the second input to an internal node of a logic circuit and preferably the logic circuit comprises a multiplexer.

Embodiments of the present invention will now be described with reference to the accompanying drawings in which:

Figure 1 shows a simplified schematic of a programmable logic device (PLD) architecture;

Figure 2 shows a simplified schematic of a tile in the programmable logic device of Figure 1 ;

Figure 3 is a circuit diagram of a conventional latch;

Figure 4 is a circuit diagram of a conventional register;

Figure 5 is a schematic showing a conventional latch-based configuration memory utilising latches and registers of Figures 3 and 4;

Figure 6a is a schematic showing a pair of 4-input multiplexers, each with two configuration bits to select one of the four inputs whereby the two configuration bits are connected to the same configuration inputs;

Figure 6b is a schematic showing a pair of 4-input multiplexers, each with two configuration bits to select one of the four inputs whereby the two configuration bits of each multiplexer are connected to separate configuration inputs but configuration bits of the two multiplexer share a common configuration input;

Figure 7 shows a memory cell in an embodiment of the present invention comprising a latch with two inputs;

Figure 8 shows a timing diagram of the inputs and outputs of the memory cell of Figure 7 during a write operation.

Figure 9 shows a schematic of a pair of 4-bit multiplexers each with two configuration bits where the configuration bits comprise the memory cell of Figure 7;

Figure 10 shows a circuit diagram of a 4-bit multiplexer implemented with tri-state buffers and a decoder whereby the decoder is provided with inputs from two latch cells; β

Figure 1 1a shows an alternative implementation of the memory cell of Figure 7 utilising pass-gate inputs;

Figure 1 1 b shows an alternative implementation of the memory cell of Figure 1 1a with one input inverted;

Figure 11c shows a further alternative implementation of the memory cell of Figure 7 with one differential and one single ended input;

Figure 12 shows a further embodiment of the present invention wherein the memory cell comprises a register having a second input to a slave latch of the register;

Figure 13 shows a memory cell according to an embodiment of the present invention when arranged to receive signals from a configuration and test interface.

Figure 14 shows a further embodiment of the present invention where the memory cell is arranged for use as a bus keeper or weak driver so the second input is un-driven and is connected as an input to a logic circuit.

Figure 15 shows a further embodiment in which the signal for the second input is provided by a configuration interface independently from the signal for the first input.

Figure 1 illustrates simplified programmable logic device (PLD) architecture 1000 of the present invention. The PLD 1000 includes an array of tiles 1001 a - 1001 p, programmable input/output (I/O) blocks 1002a - 1002d. Some of the tiles 1001a - 1001 p and I/O blocks 1002a - 1002d are connected by a number of connecting lines (not shown in figure 1). Clock signals are distributed by, for example, clock trees such as a balanced tree (e.g. the H clock tree).

Figure 2 shows simplified illustration of a tile 1001 , which is one of the tiles 1001a - 1001 p. The tiles 1001 a - 1001 p have similar structure. In other words, the tile 1001 is a repeating unit of the PLD 1000. The tile 1001 includes a logic block 201 , a number of interconnecting lines 202 and configuration memory block 205. The logic block 201 includes logic circuits and at least one D-type flip- flop (D-FF) for holding data. The D-FF can be a part of a scan chain and the D- FF can be tested by conventional scan test. The interconnecting lines are interconnected by programmable interconnect points 203 (PIPs, shown as small dots in figure 2). PIPs are often coupled into groups (e.g. group 204) that implement multiplexer circuits selecting one of several interconnecting lines to provide a signal to a destination interconnecting line or the logic block 201. The PIPs 203 are controlled by control signals based on the configuration data stored in the configuration memory block 205. The configuration memory block 205 comprises a plurality of latch circuits.

A standard latch-based configuration memory suitable for ATPG workflow will be described together with the conventional latch and register elements used therein. Figure 3 shows a conventional latch cell 30 having access transistors 31 and 32 driven by complimentary inputs in' and 'not_in' respectively. Buffered outputs 'not_out' and Out' provide access to the bit value stored by the cell. An enable signal provided to gates of the access transistors 31 and 32 permit the cell to be loaded with data.

Figure 4 shows a conventional register cell 40 comprising two latches 41 and 42 arranged in a master/slave configuration where the enable signal of the access transistor pair 43 and 44 of the slave latch 42 is the compliment of a clock signal provided to access transistor pair 45 and 46 of the master latch 41. This arrangement permits clocking of the storage element such that the register 40 is loaded with data upon completion of the rising and falling edge of a clock pulse provided to the access transistor pair 45 and 46. The buffered outputs Out' and 'not_out' of the slave latch 42 provide the data value stored in the register 40.

Figure 5 shows a conventional latch-based configuration memory 50 suitable for use with a programmable logic device (PLD). It has two main sections comprising a small bank of registers 31 and a larger batch of latches 52. The registers 51 are loaded with data to be stored in the configuration memory 50 while the latches provide the actual configuration storage.

The configuration memory 50 is loaded by performing a sequential process whereby in a first step data is loaded into the registers 51 by pulsing the clock while holding all the word line signals of the latches 52 low. This ensures that all the latches 52 are holding their state while the new data in loaded into the registers 51. In a second step data is copied into a group of latches by raising or lowering one of 'wordlineO' to 'wordline3'. In order to load the complete memory, the sequence is repeated for each separate wordline.

There are a number of problems that arise when trying to test the latch based configuration memory using standard ATPG tools. In particular, the long sequence of operations required to load the array of figure 5 is too complex for standard ATPG tools. The normal approach to testing latches is to force them all to be transparent. In other words, the enable signal (usually serviced by the word line) is forced high so that the latch input propagates directly to the output of each latch. However, this is problematic with the memory of figure 5 where multiple latches share the same input. As they share the same input then they will also share the same output when forced to be transparent during test. This significantly restricts the number of possible states of the configuration memory that are visible to the ATPG tool.

For example, an array with N wordlines and M inputs would contain N bits and have a total of 2 ^M possible states. If all latches are made transparent (i.e. all wordlines are forced high), there are only M independent inputs. Therefore, there will be only 2^M states that are configurable during test. The inventors have recognised that this large reduction in the number of possible states results in a significant reduction in the achievable test coverage of the device.

Figures 6a and 6b show two examples of scenarios where this reduction in testability can arise.

Figure 6a shows a pair of 4-input multiplexers 61 and 62, each with two configuration bits (e.g. latches) 63, 64 and 65, 66 for selecting one of the 4 inputs 00, 01 , 10, 11. For each multiplexer 61 and 62, the two configuration bits

63, 64 and 65, 66 are connected to the same input. Further the output of the first multiplexer 61 is connected to the '01 ' input of the second multiplexer 62.

Therefore, although the two multiplexers 61 and 62 can be set independently, during test each multiplexer can select only the 00 or the 1 1 state. This means that it is not possible to select a valid path through the two multiplexers - e.g. from any of the inputs A, B, C, D to the output E (i.e. input 01 of the second multiplexer 62). A further scenario is shown in Figure 6b with the same pair of 4-input multiplexers, but with different connections to the configuration bits 63, 64 and 65, 66. Here, the configuration bits for a single multiplexer have different inputs; however, there is sharing of data between the multiplexers. The first and second configuration bits 63, 64 of the first multiplexer 61 have common inputs with the first and second configuration bits 65, 66 of the second multiplexer 62. Accordingly, the first multiplexer 61 can select any of its inputs, however, the second multiplexer 62 is forced to select the same input because of the common configuration inputs to the configuration bits. This means that only the B to E path through the multiplexers 61 and 62 can be addressed.

Figures 6a and 6b show examples where the coupling of configuration bits between connected blocks can result in some paths through the blocks being un-selectable. Although, changing the coupling can change which paths are or are not selectable, there is no guarantee that there exists a choice of coupling that allows all paths between blocks to be selectable. Therefore, it is desirable to find a way of improving the number of paths that are selectable during test.

First Embodiment

Figure 7 shows an embodiment of the invention comprising a modified latch 70 that improves test coverage for a configuration memory. As will be described below this latch permits the high test coverage associated with register based implementations while retaining most of the small die area benefit of latch based memory.

As shown in figure 7, the latch 70 has two differential inputs 71 and 72 having individual enable lines (enable 1 and enable2) respectively. Each input comprises a pair of complementary access transistors 71 -1 , 71 -2 and 72-1 , 72-2 having differential inputs in1/not_in1 and in2/not_in2 respectively and gates connected to independent enable inputs enablel and enable2. The first and second inputs 71 and 72 are connected to a common input node of the cross- coupled inverter circuit 73 of the latch 70 and permit access for the purpose of reading or writing data to the latch 70 only when their corresponding enable inputs are high.

Operation of the latch 70 of figure 7 will now be described with reference to the timing diagram shown in figure 8. In this example, the latch is storing a high value. Input in 1 is high (and notjnl low) while in2 is also high (and not_in2 low). Enable 1 and enable 2 are low so the latch 70 is holds the high value which can be read at the output Note that, the operation of the latch 70 is non-synchronous in this embodiment and the state will change on the falling or rising edges of the relevant inputs. At time 801 there is a falling edge on inl and a corresponding rising edge on notjnl . However, as both of the enable signals remain low there is no change to the state held by the latch and therefore no change at the output. At time 802, there is a rising edge on enable 1 at which point the output changes to the low state in accordance with inl being low and not Jn 1 being high. At time 803, enablel goes low and the output remains low. At time 804, inl is set high (and notjnl set low), however, there is no output change as enablel remains low. Subsequently at 805 there is a rising edge on enable2 and so the values of in2 and not__in2 become relevant. As in2 is high (and notJn2 low) the output goes high (regardless of the value of inl and notjnl). Enable 2 subsequently remains high and at time 806 in2 goes low on a falling edge (and notJn2 goes high). The output switches low because enable2 remains high. This example demonstrates how the enable signals to determine which input controls the value stored by the latch 70 but of course other sequences of input signals are possible.

Figure 9 provides an illustration of how the latch 70 shown in figure 7 can be used to improve test coverage. In this simple example (which is based on the scenario of Figure 6(b)), the configuration bits 91 and 92 for the second multiplexer comprise latches according to figure 7 each having two inputs inl and in2. In this embodiment each latch is configured so that their second input is connected to the inverse of the first input (i.e. in2=notJn1 , and notJn2 = inl).

If the two configuration bits are arranged to have the same 'enable2' input then there are now two possible combinations of inputs that can cause the second multiplexer to propagate the output of the first: i) enable1 =high, and inputs = 01

ii) enable2=high, and inputs = 10

These two combinations mean that both the B to E and the C to E paths through the pair of multiplexers are now selectable.

By adding alternative input(s) to the latch cell, we expand the number of states that are available to the ATPG tool when generating test patterns. This is likely to result in increased test coverage.

Furthermore, we only have to choose the connection pattern for the first input for efficient configuration. The connection pattern for the second input can be chosen simply in order to increase test coverage. In fact, an iterative process can be used, where the second connections are made specifically to fix test problems with the first connections.

The latch in the above described embodiment has been described as having both the first and second inputs connected to the configuration inputs, but in different orders (and with different inversions).

While the first input needs to be connected to the configuration inputs, there is no requirement for the second input to be so connected - it can be connected to any signal in the design for example to enhance observability of nodes in the array.

The invention is also capable of assisting with a specific testability problem. Figure 10 shows a possible implementation of a statically configured multiplexer 100 comprising tri-state buffers 101 to 104 and a decoder 105 that only activates one of the buffers 101 to 104.

However, there is a testability problem with the multiplexer circuit 100. If an output of the decoder is stuck low, then it is possible for all the tri-state buffers 101 to 104 to be switched off simultaneously. If this happens, the internal node is un-driven, and its state is undefined.

This undefined state masks the propagation of the fault condition on the decoder 105 output, and an ATPG tool cannot fully evaluate the behaviour of the circuit. In particular, there is a risk that the floating node will coincidentally be floating at the expected test "pass" value, and so the fault will not be detected. There are several conventional solutions to this problem. One such solution is to generate (and use) multiple tests, since the probability of multiple tests all passing by coincidence (rather than because the circuit is working correctly) falls as the number of tests increases. However this increases both the test generation, and the test application time, and therefore increases both design and production cost.

It is possible to add extra hardware that can force the state of the internal node in the event of the tri-state drivers all being off. This means that decoder faults can be detected easily, without needing multiple tests, but there is a die area cost for the weak driver circuit.

Alternatively, the state of a configuration bit can be changed during a test, so that the selected input should change, and therefore the propagated data value should change. In the event of the newly selected buffer not being turned on, the internal node will be un-driven, and may retain the previous state.

However, just as in the previous case, there is no guarantee that the internal node will not coincidentally drift to the expected output value, and therefore multiple tests have to be used to reduce this possibility.

Again, it is possible to add extra hardware to help hold the state on the internal node. In the absence of it being driven from the tri-state drivers - commonly referred to as a bus keeper circuit. Just as before, this means that the need for multiple tests is removed but at some area cost.

The above described latch of Figure 7 with two inputs provides a solution to this problem in that it provides a way to implement both weak driver and bus keeper circuits at a low area cost.

Consider the circuit of Figure 7; if both enablel and enable2 are high, then a strongly driven signal on in1/not_in1 can propagate (with some attenuation) through the circuit to in2 (here acting as an output). Therefore, if in2 is connected to the internal node of a MUX like in Figure 9, the 2-input latch can act as a weak driver to force the state of that node.

Alternatively, if just enable2 is high, the latch will be coupled to the in2 input. Ordinarily, if in2/not_in2 are strongly driven then the internal state of the latch will follow the state of the external signal. However, if the drive on in2 /not- in2 is removed, then the latch will (as in the above example) provide a weak drive onto in2 (now effectively acting as an output). In other words, the latch will act as a bus keeper cell, helping in2 to retain its earlier state.

Thus, if connected to the internal node of a tri-state multiplexer, the dual- input latch is capable of acting as either an attenuating buffer, or as a bus keeper, depending only on the state of the enable inputs to determine which function it provides.

The above described embodiments relate to a latch cell with a differential input (in1/notJn1 ) and an enable input that drives a pair of n-channel transistors, Alternative implementations with a single-ended input and true/complement enable signals, as shown in Figure 1 1a, 1 1 b and 1 1 c are also possible.

Figure 1 1 a shows is similar to the latch of Figure 7 but the differential input provided by access transistors 71 -1 , 71 -2 and 72-1 , 72-2 have been replaced by pass-gates 1 1 1 and 1 12. The use of the pass gates with complementary N-channel and P-channel transistors is particularly appropriate for the in2 input of the dual-input cell when used as a weak buffer or a bus keeper, since it avoids the threshold voltage drop that would be seen when propagating a high value using the circuit of Figure 5.

The circuit of figure 1 1 b shows a variant whereby the second input 1 12 is inverted by connection to an opposing node of the cross-coupled inverter circuit to the connection node of the first pass gate 1 1 1. The circuit of figure 1 1 b is probably the most appropriate for use as a weak buffer, since it isolates the driven input (in1 ) from the weakly driven output (not_in2). Finally, it is of course possible to have latch cells with one differential input, and one single ended input, as shown in figure 1 1c.

Second Embodiment

It was shown in figure 4 how a conventional register that comprised two latches with complementary enable signals connected to a clock. Figure 12 illustrates a further embodiment of the present invention based on such a register 40. In this embodiment a register 120 is provided with a master and slave latch 121 and 122. In this embodiment, the slave latch 122 is provided with a second input in2 which is arranged in a manner analogous to that described above with reference to the latch 70. The second input in2 is connected to the slave latch 122 by means of a pass-gate 123. The register can be configured so that the second input in2 is un-driven and can also be used, as described above with reference to the latch 70 of figure 5, to weakly drive the internal node of a multiplexer or other circuit.

However, there are some potential timing issues relating to the interaction of the clock and the enable2 signals that will complicate the use of this circuit. More specifically, if clock is low and enable2 is high there are potentially 2 circuits trying to set the state of the slave latch. To avoid this by requiring enable2 to be high only when clock is low creates a timing dependency on the falling edge of the clock. As will be appreciated these issues will be taken into account when incorporating this circuit into a programmable logic device design and ATPG work flow. Configuration and Test set-up

As noted above only the connection pattern for the first input has to be chosen for efficient configuration. The connection pattern for the second input can be chosen simply in order to increase test coverage or to provide the functionality of the bus keeper or weak driver modes. To improve test coverage an iterative process can be used, where the second connections are made specifically to fix test problems with the first connections. This functionality will now be explained with reference to three examples shown in figures 13, 14 and 15 respectively.

Figure 13 shows a test set up whereby testing of the circuit is accomplished by appropriately configuring the value of enable2 of a memory cell 130 via a configuration interface 131 and a test interface 132. The set up of figure 13 could be used to implement the circuit solution discussed above with reference to figure 9

The memory cell 130 could comprise the two input latch 70 described previously with reference to figures 7 or 11. Alternatively, the register 120 described with reference figure 12 could be used.

The configuration interface 131 is arranged to receive configuration input signals external to a programmable logic device core 135 and to provide them to a configuration memory e.g. memory cell 130. Specifically, in this embodiment the signals are provided from the configuration interface to first input of the memory cell 130 during normal configuration of the PLD. The test interface 132 is arranged to provide an interface between a programmable logic device core 135 having the memory cell 130 and an external source of test signals. The test interface 132 is not used during normal operation of the device and is merely used for testing purposes in a test mode of the PLD. By providing an additional test interface in this manner the additional test functionality provided by the memory cell 130 can be exploited.

In particular, signal values are provided via the configuration interface

131 to enablel , the first input in1 (and in the test mode of operation, the second input in2) of the memory cell 130. The output of the memory cell 130 is provided to logic 133 of the programmable device. In this way, the configuration interface 131 can control the signal provided to the first input in1 together with enable 1 to load configuration data when the memory cell 130 is being used as a conventional configuration memory cell. However, in a special test mode the test interface provides a means for test systems to control enable 2 to increase test coverage.

For example, to operate the memory cell in the manner described previously with reference to figure 9, the configuration interface 131 would provide a configuration signal to the first input in1 and the signal would be inverted and provided to the second input in2. The test interface 132 would be able to toggle the signal provided to the enable2 so as to permit the test tool to load additional states during test. The logic 133 may comprise multiplexer circuits similar to those shown in figures 9 or 10. However, the configuration interface 131 is not limited to providing in2 with a signal that is merely the inverse of that provide to in1.

In figure 14, a further example is shown in which the input in2 of the memory cell 130 is connected to the logic 133 and the memory cell 130 is being used as a bus keeper or weak driver so the second input in2 is un-driven and is provided as an input to logic 133. As the memory cell 130 is configured to operate as a bus keeper or weak driver (i.e. the second input in2 actually provides an output) then in2 may also be provided as an input to the logic 133 of the PLD. By providing the arrangement shown in figure 14 it is possible to address floating node testability problems in logic. It can be used, for example, when problem like that shown in the circuit of figure 10 is found.

In figure 15 the signal for the second input in2 is provided by the configuration interface 131 independently from the signal for the first input in1. The signal provided to in2 by the configuration interface 131 is chosen to increase test coverage in a manner specific to the circuit design under test. As the second input in2 is chosen independently from first input in1 , this provides more flexibility to configure the circuit than the arrangement shown in figure 13. This is because in the arrangement shown in figure 15 the second input in2 is not constrained to be the inverse of the first input in1.

In a further alternative (not shown) the second input in2 is provided with a signal from the test interface 132 rather than the configuration interface 131. This permits an iterative process to be used where the inputs to the connections in2 and enable2 are made specifically to fix test problems with the first connections in1 and enable 1.

The invention is not limited to the interface configurations discussed here and as will be recognized by the skilled reader other configurations between the configuration and test interfaces 131 and 132 and the memory cell 130 are possible and can be selected on the basis of the chosen application and the logic of the PLD.

Also, it will be appreciated by the skilled reader that a test set-up such as that shown in Figure 13 could similarly be provided for circuits using memory cells according the previously described register of the second embodiment. In such an embodiment the second enable gate 'enable2' of the register is configured to receive signals from the test interface as required.

In addition, the above embodiments make reference to the application of the two input latch 70 and register 120 to the testing and operation of multiplexer logic. The invention is of course applicable to any logic circuit in a PLD which is configured by means of a configuration memory.

Claims

1. A configuration memory for a programmable logic device comprising a plurality of memory cells, each memory cell comprising:

a storage element;

an output;

and first input means and second input means each being independently operable to provide access to the storage element;

wherein the second input means of at least one of the plurality of memory cells is arranged to receive control signals from a test interface for providing test signals to the programmable logic device.

2. A configuration memory according to claim 1 further comprising

a test interface arranged to control at least the second input means of the at least one of the memory cells.

3. A configuration memory according to any preceding claim wherein said storage element comprises a latch comprising a pair of cross coupled inverters. 4. A configuration memory according to claim 3 wherein the first and second input means comprise an enable input wherein said access is provided upon receipt of a predetermined signal level at the enable input.

5. A configuration memory according to claim 4 wherein at least the first or the second input means of at least one of the plurality of memory cells comprises a pair of access transistors having differential inputs connected across the pair of cross-coupled inverters.

6. A configuration memory according to claim 4 wherein at least the first or the second input means of at least one of the plurality of memory cells comprises a transmission gate or pass-gate comprising a complimentary N- channel and P-channel transistor pair.

7. A configuration memory according to any preceding claim wherein the second input means of at least one of the plurality of memory cells is operable to provide an output signal when the second input is un-driven and arranged to provide access to the storage element such that the memory cell acts as a bus keeper circuit.

8. A configuration memory according to any preceding claim wherein the second input means of at least one of the plurality of memory cells is operable to provide an output signal when the second input is un-driven and the memory cell is configured such that both the first and second input means provide access to the storage element such that the memory cell acts as a weak driver circuit.

9. A configuration memory according to claim 1 wherein the storage element comprises a register having a master and slave latch circuit. 0. A configuration memory according to claim 9 wherein the second input means is provided to the slave latch.

1 1. A configuration memory according to claim 10 wherein the first input means is enabled by a clock signal and the second input means is enabled by an independent enable input.

12. A configuration memory according to any of claims 9 to 1 1 wherein the first input means comprises a first pair of access transistors having differential inputs connected across the master latch and a second pair of access transistors having differential inputs connected across the slave latch wherein the first and second pair of access transistors are arranged to receive complimentary signals from a clock. 13. A configuration memory according to any of claims 9 to 12 wherein the second input means comprises a transmission or pass gate comprising a complimentary NMOS and PMOS transistor pair.

14. A memory cell for a configuration memory of a programmable logic device comprising:

a storage element;

an output; and

first input means and second input means each being independently operable to provide access to the storage element;

wherein the second input means is arranged to receive control signals from a test interface for providing test signals to the programmable logic device.

15. A memory cell according to claim 14 wherein said storage element comprises a latch comprising a pair of cross-coupled inverters.

16. A memory cell according to any of claims 14 or 15 wherein the first and second input means comprise an enable input wherein said access is provided upon receipt of a predetermined signal level at the enable input.

17. A memory cell according to claim 16 wherein at least the first or second input means comprises a pair of access transistors having differential inputs connected across the pair of cross-coupled inverters.

18. A memory cell according to claim 17 wherein the at least the first or second input means comprises a transmission gate or pass-gate comprising a complimentary N-channel and P-channel transistor pair.

19. A memory cell according to any of claims 14 to 18 wherein the memory cell is arranged such that the second input means is operable to provide an output signal when the second input means is un-driven and arranged to provide access to the storage element such that the memory cell acts as a bus keeper circuit.

20. A memory cell according to any of claims 14 to 19 wherein the memory cell is arranged so that the second input means is operable to provide an output signal when the second input means is un-driven and the memory cell is configured such that both the first and second input means provide access to the storage element such that the memory cell acts as a weak driver circuit. Second Embodiment

21. A memory cell according to claim 14 wherein the storage element comprises a register having a master and slave latch circuit. 22. A memory cell according to claim 21 wherein the second input means is provided to the slave latch.

23. A memory cell according to claim 22 wherein the first input means is enabled by a clock signal and the second input means is enabled by an independent enable input.

24. A memory cell according to any of claims 21 to 23 wherein the first input means comprises a first pair of access transistors having differential inputs connected across the master latch and a second pair of access transistors having differential inputs connected across the slave latch wherein the first and second pair of access transistors are arranged to receive complimentary signals from a clock.

25. A memory cell according to any of claims 21 to 24 wherein the second input means comprises a transmission or pass gate comprising a complimentary

NMOS and PMOS transistor pair.

26. A configurable multiplexer circuit comprising a decoder, a plurality of buffered tri-state outputs and a memory cell according to any of claims 14 to 25 wherein the memory cell is configurable to operate as a bus-keeper circuit or a weak driver circuit.

27. A method of utilising a memory cell for a configuration memory of a programmable logic device comprising:

a storage element;

an output; and

first input means and second input means each being independently operable to provide access to the storage element said method comprising

configuring any of the first or second input means to receive configuration signals from a configuration or test interface for providing test or configuration signals to the programmable logic device.

28. A method of utilising a memory cell for a configuration memory of a programmable logic device comprising:

a storage element;

an output; and

first input means and second input means each being independently operable to provide access to the storage element said method comprising: arranging the second input means so that it is un-driven and

arranging the second input means to provide access to the storage element;

wherein the memory cell provides a weak driving signal to the second input means such that the memory cell acts as a bus keeper circuit.

29. A method of utilising a memory cell for a configuration memory of a programmable logic device comprising:

a storage element;

an output; and

first input means and second input means each being independently operable to provide access to the storage element said method comprising: arranging the second input means to be un-driven

providing a driving signal to the first input means; and

configuring the first and second input means such that they both provide access to the storage element so that the memory cell allows the signal driving the first input to propagate to the second input means.

30. A method according to claim 28 or 29 further comprising connecting the second input to an internal node of a logic circuit. 31. A method according to claim 30 wherein said logic circuit comprises a multiplexer.