WO2012121614A1

WO2012121614A1 - Systems and methods for power efficient data communications in wireless sensor networks

Info

Publication number: WO2012121614A1
Application number: PCT/NZ2012/000030
Authority: WO
Inventors: Stevan BERBER; Shudong FANG
Original assignee: Auckland Universives Limited
Priority date: 2011-03-10
Filing date: 2012-03-06
Publication date: 2012-09-13
Also published as: WO2012121614A8

Abstract

The present invention relates to data communications, particularly data communications in wireless sensor networks. The focus of embodiments described herein is the introduction of chip interleaving technologies into a transceiver (described in terms of a DSSS transceiver) to achieve an acceptable bit error rate at a significantly reduced transmitting power over a severely faded channel.

Description

SYSTEMS AND METHODS FOR POWER EFFICIENT DATA COMMUNICATIONS IN WIRELESS SENSOR NETWORKS

FIELD OF THE INVENTION

[0001] The present invention relates to data communications, particularly data communications in energy-constrained wireless networks, particularly wireless sensor networks. More specifically, embodiments have been developed to improve energy efficiency in such networks. For example, a chip interleaving technique is used to reduce the energy consumption of sensor nodes on data communication over fading channels. Although the present disclosure is focused on such embodiments, it will be appreciated that the concepts discussed herein have wider application.

BACKGROUND

[0002] Any discussion of the background art throughout the specification should in no way be considered as an admission that such art is widely known or forms part of common general knowledge in the field.

[0003] Wireless sensor networks (WSN) include a number of sensing and computing devices, these devices being networked via low-power wireless communications. The individual devices, commonly referred to as sensor nodes, are often battery-powered to capture environmental data.

[0004] A significant limitation on the lifetime of a WSN is the battery life of each individual sensor node. A WSN is usually designed/intended to operate for a time period lasting from several months to a few years subject to application requirements. However, in most cases, each sensor node is powered by a battery with finite energy. Furthermore, to contain hardware costs, each sensor node is embedded with a cheap radio which is typically made up of a short-range transceiver and an Omni-directional antenna. Thus, one of the core requirements facing the design of WSN communication algorithms is the energy conservation. In addition, the signal processing in the transceiver needs to be of low computing complexity.

[0005] The deployment environment of a WSN often presents wireless channels of hazardous nature that makes the data transmission via the low-cost transceiver susceptible to failure. One significant property of this nature is the channel fading which is caused by obstructive objects or moveable surroundings that may block the radio propagation path, or reflect, diffract and scatter the waveform between communicating nodes. Another property is the ubiquitous channel noise. The channel noise and fading, in particular the small-scale fading, can substantially distort the original waveform, resulting ultimately in symbol errors.

[0006] One approach to overcome complications associated with narrowband channel noise is via spanning the bandwidth of the transmitting symbol over wider frequency band, i.e. the spread spectrum technique. This approach, more specifically the direct sequence spread spectrum (DSSS) technique that spreads symbols into orthogonal chip sequences, has been outlined in IEEE 802.15.4 Standard to produce low-power transceiver suitable for sensor nodes.

[0007] Unfortunately, the DSSS technique is insufficient to overcome channel fading.

Accordingly, from a practical perspective, there are two main design options for dealing with the associated complications. One option is to increase transmitting power thereby to redeem the symbol error caused by fading, and keep the strength of the received signal above a detectable level. However, this offsets the energy efficiency of a transmitting node. The other option involves utilizing a sophisticated radio frequency (RF) transceiver with advanced signal processing or multiple antennas. However, this increases the node cost. Accordingly, although initially promising, the DSSS technique cannot be effectively applied in a situation where there is a desire to contain both energy consumption and hardware cost.

[0008] It follows that there is a need in the art for improved systems and methods for data communications in wireless sensor networks.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to overcome or ameliorate at least one of the disadvantages of the prior art, or to provide a useful alternative.

[0010] One embodiment provides a sensor node configured for operation in a wireless sensor network, the sensor node including:

one or more sensors; a processing unit and associated memory module, the memory module carrying software instructions executable via the processing unit; and

a transceiver for transmitting and/or receiving communications data over the wireless sensor network, the transceiver configured to apply a non-binary or/and binary chip interleaving technique in respect of communications data; and

a power supply for providing power to the processing unit, memory module and transceiver.

[0011] One embodiment provides a sensor node configured for operation in a wireless sensor network, the sensor node including:

one or more sensors;

a processing unit and associated memory module, the memory module carrying software instructions executable via the processing unit; and

a transceiver for transmitting and/or receiving communications data over the wireless sensor network, the transceiver configured to apply non-binary or binary sequences or the combinations thereof for data spreading and a chip interleaving technique in respect of communications data; and

[0012] One embodiment provides a wireless sensor network including a plurality of sensor nodes as described herein.

[0013] One embodiment provides a coordinator configured for operation in a for a wireless sensor network as described herein.

[0014] One embodiment provides a method for transmitting data in a wireless sensor network, the method including operating a chip interleaved transmitter that te-transmits communications data spread by non-binary or binary sequences or their combinations via a chip interleaving technique.

[0015] One embodiment provides a method for receiving data in a wireless sensor network, the method including operating a chip interleaved receiver to receive communications data via a chip de-interleaving technique. [0016] One embodiment provides a sensor node for a wireless sensor network system, the sensor node including a processor configured to perform a method as described herein.

[0017] One embodiment provides a wireless sensor network including a plurality of nodes configured to perform a method as described herein, such as a medium access method.

[0018] One embodiment provides a computer readable medium carrying a set of instructions that when executed by one or more processors cause the one or more processors to perform a method as described herein.

[0019] Reference throughout this specification to "one embodiment", "some embodiments" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment", "in some embodiments" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0020] As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0021] In the claims below and the description herein, any one of the terms comprising, comprised of or which comprises is an open term that means including at least the elements/features that follow, but not excluding others. Thus, the term comprising, when used in the claims, should not be interpreted as being limitative to the means or elements or steps listed thereafter. For example, the scope of the expression a device comprising A and B should not be limited to devices consisting only of elements A and B. Any one of the terms including or which includes or that includes as used herein is also an open term that also means including at least the elements/features that follow the term, but not excluding others. Thus, including is synonymous with and means comprising.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0023] FIG. 1 is a block diagram of a sensor node according to one embodiment.

[0024] FIG. 2 is a block diagram of a WSN according to one embodiment, including multiple sensor nodes that conduct communications in many-to-one form.

[0025] FIG. 3 schematically illustrates coordination of k nodes by a coordinator in time divided manner.

[0026] FIG. 4 is a block diagram of a CI-DSSS transceiver according to one embodiment, this transceiver incorporating a block chip interleaver, non-binary and/or binary sequence generators (for the transmitter), a block chip de-interleaver, and synchronized non-binary and/or binary sequence generators (for the receiver).

[0027] FIG. 5 is a block diagram of a CI-DSSS transceiver cording to one embodiment, based on synchronized coherent BPSK modulation.

[0028] FIG. 6 shows the BER curve of an exemplary CI-DSSS transceiver and DSSS transceiver in AWGN and Rayleigh fading channels. The spreading gain N increases from 4 to 32.

[0029] FIG. 7 schematically illustrates a sensor node according to one embodiment, based on a CIDS-CDMA transceiver.

[0030] FIG. 8 schematically illustrates an exemplary architecture of a WSN, based on a CIDS-CDMA transceiver, according to one embodiment.

[0031] FIG. 9 schematically illustrates a WSN made up of multiple nodes using CIDS- CDMA transceivers.

[0032] FIG. 10 shows the BER curve of an exemplary CIDS-CDMA transceiver and DS- CDMA transceiver in Rayleigh fading channel. The spreading gain N is equal to 64. DETAILED DESCRIPTION

[0033] The present invention relates to data communications, particularly data communications in wireless sensor networks. The focus of embodiments described herein is the introduction of non-binary and/or binary spreading sequences and chip interleaving technologies into a transceiver (described in terms of a DSSS transceiver) to achieve an acceptable bit error rate at a significantly reduced transmitting power over a severely faded channel.

GENERAL OVERVIEW

[0034] As noted further above, the DSSS technique is known to produce low-power transceiver suitable for sensor nodes, but is insufficient to overcome channel fading.

[0035] Embodiments disclosed herein saves the energy expense on DSSS communication by interleaving the transmitting order of a chip sequence over the fading channel. This is referred to as a chip interleaving technique, and is implemented by adding a chip interleaver and a de- interleaver into the DSSS transceiver. Using block chip interleaving as a conceptual example, in the transmitter chip sequences are written into a block chip interleaver in row form and read out in column form to be modulated. In the receiver, the reverse processing takes place such that the samples of the demodulated signals representing the received chip sequences are written into a block chip de- interleaver in row form and read out in column form.

[0036] By using chip interleaving, the required signal to noise ratio will be reduced. Chip interleaving introduces one form of time diversity into DSSS. The chips in a sequence are spaced out in transmission such that each of the de- interleaved chips of a chip sequence may be affected, in an ideal case, by an independent fading factor, whereas without chip interleaving the contiguous chips of a sequence are affected by the same fading factor. By chip interleaving, the orthogonality of a set of chip sequences is better protected. By utilizing chip interleaving transceiver, a desired symbol error rate can be attained at less transmitting power for data communication among sensor nodes. Therefore the energy efficiency of a sensor node can be significantly improved.

[0037] As used herein, unless stated explicitly otherwise, the term "chip interleaving technique" refers to a non-binary or/and binary chip interleaving technique. The value a chip takes can be binary or non-binary. SENSOR NODE ARCHITECTURE - CI-DSSS TRANCEIVER

[0038] Figure 1 illustrates a sensor node 110a using Chip Interleaved DSSS transceiver. Sensor node 110a includes one or more sensors 220, a processing unit (in the form of micro-computing unit 230) and associated memory module 210. Memory module 210 carries software instructions executable via the processing unit, these software instructions providing functionality to the sensor node.

[0039] A transceiver 250 is configured for transmitting and/or receiving communications data over the wireless sensor network, the transceiver being configured apply a non-binary or/and binary chip interleaving technique in respect of communications data. In this regard, a Chip Interleaved (CI) DSSS transceiver is used. The CI-DSSS transceiver is connected to at least one antenna (260aa). The sensor node transmits and receives signals via the transceiver and the antenna.

[0040] A power supply 240 provides power to the processing unit, memory module and transceiver (and, in this example, the sensors). The use of interleaving allows the sensor node to perform energy-efficient wireless communication, as discussed further below.

ARCHITECTURE OF A WSN BASED ON CI-DSSS TRANSCEIVERS

[0041] One embodiment of a WSN, as shown in FIG. 2, is made up of ^-number of sensor nodes (110a to 110k) that use CI-DSSS transceivers to communicate with a coordinating sensor node 120 (termed the coordinator) over a wireless fading channel 140. Coordinator 120 also uses a CI-DSSS transceiver to communicate. The transceivers used by these k nodes and the coordinator are the same in structure. Each of these (k+l) nodes has a unique identification number (ID). The CI-DSSS transceivers of these (k+l) nodes employ the same set of chip sequences to spread the transmitting symbols in the DSSS processing.

[0042] The access from the fc-nodes to the coordinator can be contention-based, for example using Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA). Alternatively, to avoid communication interference and collision, the coordinator coordinates the ^-number of nodes to transmit data in a time division manner, as shown in FIG. 3, although not limited to this manner. The coordinator assigns time slots for each node to upload data through the CI-DSSS transceiver. [0043] The number of time slots assigned to a sensor node is to the discretion of the coordinator upon the throughput requirement of the application tasks. In some applications, some sensor nodes need to upload date frequently, whilst other nodes transmit data on an irregular basis, such as upon requests or events, or sensor nodes may not transmit data at all for certain time period. Thus active nodes are assigned more slots and less active nodes are given less slots by the coordinator. Referring to FIG. 3, node «/ is assigned one time slot, node n is assigned no time slot, whereas node «3 is assigned four consecutive time slots.

[0044] Each sensor node is configured to suspend and resume data transmission upon instructions from the coordinator. The instructions can be made according to a few criterions, e.g. the quality of the channel between this node and the coordinator. Transmission instructions from the coordinator aim at saving the sensor node transmitting power by transmitting chip interleaved signals only in the time intervals when the channel possesses a desired quality. When the channel quality is estimated to degrade to an unacceptable level, the coordinator instructs the sensor node to put off data transmission until the next valid time interval. In one embodiment as shown in FIG. 3, a node, say node «3, is allocated four consecutive time slots, denoted as 7} (J = 1, 2, 3, 4.), to transmit data to the coordinator. In time slots Tj and T₂ the coordinator estimates the channel quality, for example the channel coherent time, based on the received signals. By the end of slot T₂, the channel coherence time is estimated to have been reduced to a length for which the chip interleaving technique takes minor effects on mitigating the busts of symbol error in slot 7). Then, in acknowledgement (ACK) the coordinator instructs node «? to suspend transmission and to resume when slot T4 becomes valid. By doing so, the chip- interleaved signals can be spaced out across a broader time interval according to the instructions from the coordinator.

ARCHITECTURE OF A CI-DSSS TRANSCEIVER

[0045] FIG. 4 presents an exemplary block diagram of the signal processing component of a CI-DSSS transceiver 250. In view of the disclosure below, it will be appropriate that the embodiments of the chip interleaving and associated methods are well-suited to modify the implementation of the DSSS transceiver outlined in the IEEE 802.15.4 Standard. [0046] In the transmitter, the input data are presented in the form of symbols through the transmission symbol component. Then the transmission symbols are sent to the spreader in which a symbol is directly spread into a chip sequence that can be binary sequence, non-binary sequence or the combination thereof. The symbol-to-chip- sequence mapping is in some embodiments performed according to a look-up table. The chip sequences for spreading different symbols are termed spreading sequences which possess pseudo-random (or random) nature and are orthogonal between one and another. In the chip sequences a chip can have a binary or non-binary value. The spreader is connected to the chip interleaver where the spreading sequences of a few symbols are interleaved, so that the contiguous chips of a spreading sequence are separated in a way that, ideally, each chip is affected with a statistically independent fading factor. . In this regard, a wide range of deterministic or random chip interleavers may be employed. The chip interleaver is connected to the pulse shaping filter which constrains the bandwidth of the interleaved chip stream to reduce the inter- symbol interference. To this end, a few conventional pulse shaping filters, such as the raised-cosine filter or half-sine filter may be applied. Then the pulse shaped signals are modulated at the modulator, amplified at the power amplifier and transmitted from the transmission antenna. In the modulator a wide range of modulation schemes, such as BPSK, OQPSK or QAM, etc, can be exploited to modulate the transmitting signal.

[0047] In the receiver, signals are detected and received by the reception antenna.

Then the received signals are demodulated and de-interleaved through the demodulator and chip de- interleaver, respectively. The demodulation scheme and chip de- interleaving approach are in correspondence to the modulation scheme and chip interleaving approach used in the transmitter. In the correlator the de-interleaved signals are correlated with the locally generated signals of the employed chip sequences. The output of the correlator is sent to the decision circuit to make decision on which symbol has been transmitted.

[0048] According to the embodiment of the architecture of CI-DSSS transceiver of this invention, FIG. 5 presents a block diagram illustrating a configuration of a CI-DSSS transceiver based on the block chip interleaver, although the configuration is not limited in this regard. In the transmitter binary symbols, that are bits denoted as Z> ,Z> ,..,Z> ^J,..,Z)j¾L., where stands for the A ^h block of grouped bits and h denotes the h^th block, are transmitted. In the spreader, a bit b ^} is spread using a spreading sequence containing N chips (<J^ ,..,a⁽ ,..a⁽ ) that are generated by a local pseudorandom (or random) sequence generator. The spreading gain in this example is equal to N. It has the value depending on the channel state following the basic rule: the longer the fades are the larger N values are. A chip αβ⁽ can take binary or non-binary value. Then a set of M bits are grouped together as the input of a block chip interleaver which has a capacity of M rows and N columns. The -number of chip sequences are written into the block chip interleaver in row and read out column-wise. Referring to FIG. 5, the input to the node n s chip interleaver is: a^a> a⁽¹⁾ a⁽¹⁾ a^(x) a⁽²⁾ a^(2> a^(2> a⁽²⁾ a ^u\^(,) > a^u2^(,) f -> a^uj⁽ >·^■■> a ^UM⁽ '···' a ^ul > a^u2 '••^•> a^uj f -> a^uN^M

[0049] and the output of the node w s chip interleaver is: a^(l) a⁽²⁾ a⁽ⁱ⁾ a^a) a^P) a⁽ⁱ⁾ a

a^n} a⁽²⁾ a⁽ⁱ⁾ a^m a ⁾ a^ft) a⁽ⁱ⁾ a^{M '}

[0050] Then the interleaved chip sequences are pulse shaped through the pulse shape filter and modulated using BPSK modulation, i.e. by multiplying with a cosine function cos(w_ct) where w_c is the carrier frequency generated by a local oscillator and t denotes time. The modulated signals are power amplified to be transmitted through the RF port connected to the antenna.

[0051] In the receiver signals are detected and received at the reception antenna. The antenna is connected to a band-pass filter for the carrier frequency band. The bandpass filter is connected to the demodulator where the de-modulation is considered to be coherent. This means the received signals are sent into a local Phase-Locked loop (PLL) device to produce a local carrier reference which is synchronized with the carrier of the received signals. The generated local carrier reference is a cosine function cos(w_ct) for the presented case. The received signals are multiplied with this cosine function and then pass through a low-pass filter to eliminate the high frequency component. Then the demodulated signals are written into the chip de-interleaver. The chip de- interleaving is performed by receiving the contents of the block interleaver in a row-wise manner, and then iteratively reading out the contents in a sequential column- wise fashion. The output of the chip de-interleaver is ready for correlation processing in the correlation component in which the chip sequences for spreading are known a priori. The output of the correlation component is then ready for the decision circuit to decide which bit has been transmitted.

[0052] FIG. 6 shows the bit error rate (BER) versus signal-to-noise ratio (Ε_/ Ν₀) for the configuration of a CI-DSSS transceiver demonstrated in FIG. 5 over the AWGN and Rayleigh flat-fading channel. By BER, the energy savings on transmitting signal over faded channel can be easily calculated from the gain of Ei N₀. The block chip interleaver in the CI-DSSS transceiver has a specific property that the number of row M is configured to be equal to the number of column N, although the implementation will take into account the statistical characteristics of the fading and is not limited to this configuration. FIG. 6 also shows the BER curves of a conventional DSSS transceiver (no chip interleaving processing) based on BPSK modulation in the presence of AWGN and Rayleigh flat-fading. According to FIG. 6, the Et N₀ needed by the CI-DSSS transceiver is much less than that required by the DSSS transceiver over the Rayleigh flat-fading channel. For a given BER, such as 10^"4, when the spreading gain is equal to 16, the Ei N₀ needed by the CI-DSSS transceiver is 23dB less than that required by the DSSS transceiver. Accordingly one may generally infer that the transmission power required by a sensor node based on a CI-DSSS transceiver is significantly saved by exploiting chip interleaving in a DSSS transceiver.

ARCHITECTURE OF A SENSOR NODE USING CIDS-CDMA TRANSCEIVER

[0053] A sensor node using Chip Interleaved DS-CDMA (CIDS-CDMA) transceiver is shown in FIG. 7. This sensor node comprises a few components, primarily including sensor(s), a battery as the energy source, a memory unit, a micro -controlling unit and a CIDS-CDMA transceiver which is connected to one Omni-directional antenna. Reference numerals corresponding to FIG. 1 are used.

[0054] The CIDS-CDMA transceiver exploits the time diversity of chip interleaving and the code orthogonality of CDMA to allow energy-efficient, reliable and high capacity sensor node communications. ARCHITECTURE OF A WSN BASED ON CIDS-CDMA TRANSCEIVER

[0055] FIG. 8 shows a WSN, part of this WSN being made up of ^-number of sensor nodes (110a to 100k) using CIDS-CDMA transceivers to communicate with an advance coordinating sensor node 120 (termed the advance coordinator) also using a CIDS-CDMA transceiver. In view to the embodiment in FIG. 8, the WSN based on CIDS-CDMA transceiver can adopt the two configuration forms discussed below, although the technology is not limited in this view. The key difference between these two configurations resides in the spreading codes allocation for a few local area sensor networks each acts as a part of the whole WSN.

[0056] In the first configuration, sensor nodes in the WSN embodiment are homogenous. This means that the CIDS-CDMA transceivers used by all the nodes in the WSN have the same structure. The spreading code is a set of chip sequences used by nodes in a local area sensor network. The spreading codes can take binary or non- binary values. The spreading code of a local area sensor network is orthogonal to that of a neighboring sensor network. In this regard, the CIDS-CDMA transceivers used by the k nodes and the relevant advance coordinator of a local area sensor network are reduced to the CI-DSSS transceivers depicted in Embodiment 1. Also the local area sensor network closely resembles the WSN in Embodiment 1. These (k+l) nodes which employ the CIDS-CDMA transceiver can operate in the same manner as the CI- DSSS based WSN described in Embodiment 1.

[0057] In the second configuration, the CIDS-CDMA transceivers used by sensor nodes in the WSN embodiment are heterogeneous: In a local area sensor network as a part of a bigger WSN, the spreading sequences used by one of the k sensor nodes are orthogonal to the spreading sequences used by another node of the k sensor nodes. The spreading codes can take binary or non-binary values. The advance coordinator stores all the spreading sequences of these k nodes. The spreading code for nodes in a local area sensor network can be (yet not necessarily) orthogonal to that for nodes in a neighboring sensor network. Due to the orthogonality of the spreading sequences in a local area sensor network, a few nodes among the ^-number of nodes may concurrently transmit to the advance coordinator. The advance coordinator takes one of the transmitting nodes to be the intended transmitting node; or it may process signals from multiple nodes as the intended nodes, depending on the internal algorithm of its transceiver. The advance coordinator can concurrently transmit instructions to multiple nodes, taking advantage of the orthogonality of the spreading sequences used by these k nodes: If there are multiple instructions for multiple recipient nodes, the advance coordinator uses the spreading sequences of an intended recipient node to spread the instructions, and then it mixes up the spread instructions and transmits them concurrently. A node receives the mixed instructions and uses its own spreading sequence to find out whether it is the intended recipient node.

[0058] FIG. 9 shows a specific apparatus of the second configuration of Embodiment 2, where the CIDS-CDMA transceiver on the advance coordinator performs coherent demodulation, although the implementation of transceiver structure is not limited in this regard. In all there are ^-number of nodes that intend to transmit to one advance coordinator. Suppose the 1^st node is the intended transmitting node. In this node's transmitter, binary symbols, that are bits denoted as

bf , where M stands for the M¹¹¹ block of grouped bits and h denotes the h^th block, are transmitted. Note that for the g^th node, the transmitting bits are denoted as b^, b^_2r ., b^_^., b^_M....

In the spreader of the 1 ^st node, a bit b J is spread using a chip sequence containing N chips (

) that are generated by a local pseudo-random sequence generator. The spreading gain is therefore equal to N. For the g^th node the spreading sequence in the spreader is denoted as

). The spreading sequences used by these k node are orthogonal to one another. A chip af_j or a can take a binary or non-binary value.

[0059] In the transmitter of the 1^st node, a set of M bits are grouped together as the input of a block chip interleaver which has a capacity of rows and N columns. The M-number of chip sequences are written into the block chip interleaver in row and read out column-wise. Then the interleaved chip sequences are pulse shaped through the pulse shape filter and then modulated using BPSK modulation, i.e. by multiplying with a cosine function cos(w_ct) where w_c is the carrier frequency generated by a local oscillator and t denotes time. The modulated signals are power amplified to be transmitted through the differential RF port connected to the antenna. [0060] In the receiver of the advance coordinator, signals are detected and received at the reception antenna. The antenna is connected to a bandpass filter for the carrier frequency band. The bandpass filter is connected to the demodulator for demodulation. Suppose the advanced coordinator takes the 1^st node as the intended node and the rest (k-l) nodes as the interfering nodes. Then the de-modulation is considered to be coherent to the incoming signal from the 1 ^st node. This means that in the receiver the locally generated carrier reference, i.e. a cosine function cos(w_ct), is synchronized in phase with the received signals from the 1^st node. The received signals are multiplied with this cosine function and then pass through a low-pass filter to eliminate the high frequency component. Then the demodulated signals are written into the chip de-interleaver. The chip de-interleaving is performed by receiving the contents of the block interleaver in a row-wise manner, and then iteratively reading out the contents in a sequential column-wise fashion. Note that the de- interleaved signals are the mixture of signals from the intended node as well as undesired nodes. The signals from the undesired nodes are interference to the signals from the intended node. The output of the chip de-interleaver is ready for correlation processing in the correlation component where the spreading sequences for the intended node is known a priori. The output of the correlation component is then ready for the decision circuit to decide which bit has been transmitted.

[0061] FIG. 10 shows the bit error rate (BER) versus signal-to-noise ratio (2¾ N₀) for the configuration of a CIDS-CDMA transceiver demonstrated in FIG. 9 over the AWGN and Rayleigh flat-fading channel. The block chip interleaver in the CIDS- CDMA transceiver has such a property that the number of row M is configured to be equal to the number of column N, although the invention is not limited to this configuration. FIG. 10 also shows the BER curves of a conventional DS-CDMA transceiver (no chip interleaving processing) based on BPSK modulation in the presence of AWGN and Rayleigh flat-fading. According to FIG. 10, the Et/N₀ needed by the CIDS-CDMA transceiver is much less than that required by the DS-CDMA transceiver over the Rayleigh flat fading channel. For a given BER, such as 10^"4, when the spreading gain is equal to 64 and there are four nodes simultaneously transmit data to the advance coordinator, the E_b/N₀ needed by the CIDS-CDMA transceiver is dozens of dBs less than that required by the DS-CDMA transceiver. Accordingly one may generally infer that the transmission power required by a sensor node based on a CIDS- CDMA transceiver is significantly saved by exploiting chip interleaving in a DS- CDMA transceiver.

CONCLUSIONS AND INTERPRETATION

[0062] It will be appreciated that the above disclosure provides for energy efficient communications in a wireless sensor network. For example, interleaving techniques are used to mitigate complications associated with the likes of channel fading.

[0063] Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as "processing," "formulating", "generating", "computing," "calculating," "determining", analyzing" or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities into other data similarly represented as physical quantities.

[0064] In a similar manner, the term "processor" may refer to any device or portion of a device that processes electronic data, e.g., from registers and/or memory to transform that electronic data into other electronic data that, e.g., may be stored in registers and/or memory. A "computer" or a "computing machine" or a "computing platform" may include one or more processors.

[0065] The methodologies described herein are, in one embodiment, performable by one or more processors that accept computer-readable (also called machine-readable) code containing a set of instructions that when executed by one or more of the processors carry out at least one of the methods described herein. Any processor capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken are included. Thus, one example is a typical processing system that includes one or more processors. Each processor may include one or more of a CPU, a graphics processing unit, and a programmable DSP unit. The processing system further may include a memory subsystem including main RAM and/or a static RAM, and/or ROM. A bus subsystem may be included for communicating between the components. The processing system further may be a distributed processing system with processors coupled by a network. If the processing system requires a display, such a display may be included, e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT) display. If manual data entry is required, the processing system also includes an input device such as one or more of an alphanumeric input unit such as a keyboard, a pointing control device such as a mouse, and so forth. The term memory unit as used herein, if clear from the context and unless explicitly stated otherwise, also encompasses a storage system such as a disk drive unit. The processing system in some configurations may include a sound output device, and a network interface device. The memory subsystem thus includes a computer-readable carrier medium that carries computer-readable code (e.g., software) including a set of instructions to cause performing, when executed by one or more processors, one of more of the methods described herein. Note that when the method includes several elements, e.g., several steps, no ordering of such elements is implied, unless specifically stated. The software may reside in the hard disk, or may also reside, completely or at least partially, within the RAM and/or within the processor during execution thereof by the computer system. Thus, the memory and the processor also constitute computer-readable carrier medium carrying computer-readable code.

[0066] Furthermore, a computer-readable carrier medium may form, or be included in a computer program product.

[0067] In alternative embodiments, the one or more processors operate as a standalone device or may be connected, e.g., networked to other processor(s), in a networked deployment, the one or more processors may operate in the capacity of a server or a user machine in server-user network environment, or as a peer machine in a peer-to- peer or distributed network environment. The one or more processors may form a personal computer (PC), a tablet PC, a set -top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine.

[0068] While only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. [0069] Thus, one embodiment of each of the methods described herein is in the form of a computer-readable carrier medium carrying a set of instructions, e.g., a computer program that is for execution on one or more processors, e.g., one or more processors that are part of web server arrangement. Thus, as will be appreciated by those skilled in the art, embodiments of the present invention may be embodied as a method, an apparatus such as a special purpose apparatus, an apparatus such as a data processing system, or a computer-readable carrier medium, e.g., a computer program product. The computer-readable carrier medium carries computer readable code including a set of instructions that when executed on one or more processors cause the processor or processors to implement a method. Accordingly, aspects of the present invention may take the form of a method, an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of carrier medium (e.g., a computer program product on a computer-readable storage medium) carrying computer-readable program code embodied in the medium.

[0070] The software may further be transmitted or received over a network via a network interface device. While the carrier medium is indicated in an exemplary embodiment to be a single medium, the term "carrier medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "carrier medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by one or more of the processors and that cause the one or more processors to perform any one or more of the methodologies of the present invention. A carrier medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical, magnetic disks, and magneto-optical disks. Volatile media includes dynamic memory, such as main memory. Transmission media includes coaxial cables, copper wire and fiber optics, including the wires that comprise a bus subsystem. Transmission media also may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications. For example, the term "carrier medium" shall accordingly be taken to included, but not be limited to, solid-state memories, a computer product embodied in optical and magnetic media; a medium bearing a propagated signal detectable by at least one processor of one or more processors and representing a set of instructions that, when executed, implement a method; a carrier wave bearing a propagated signal detectable by at least one processor of the one or more processors and representing the set of instructions a propagated signal and representing the set of instructions; and a transmission medium in a network bearing a propagated signal detectable by at least one processor of the one or more processors and representing the set of instructions.

[0071] It will be understood that the steps of methods discussed are performed in one embodiment by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer-readable code) stored in storage. It will also be understood that the invention is not limited to any particular implementation or programming technique and that the invention may be implemented using any appropriate techniques for implementing the functionality described herein. The invention is not limited to any particular programming language or operating system.

[0072] Similarly it should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, FIG., or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

[0073] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those skilled in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination. [0074] Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.

[0075] In the description provided herein, numerous specific details are set forth.

However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0076] Thus, while there has been described what are believed to be the preferred embodiments of the invention, those skilled in the art will recognize that other and further modifications may be made thereto without departing from the spirit of the invention, and it is intended to claim all such changes and modifications as fall within the scope of the invention. For example, any formulas given above are merely representative of procedures that may be used. Functionality may be added or deleted from the block diagrams and operations may be interchanged among functional blocks. Steps may be added or deleted to methods described within the scope of the present invention.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A sensor node configured for operation in a wireless sensor network, the sensor node including:

one or more sensors;

2. A sensor node according to claim 1 wherein the transceiver includes a non-binary and/or binary chip interleaved transmitter configured to transmit communications data via the chip interleaving technique.

3. A sensor node according to claim 2 wherein the transceiver is configured such that, for data transmissions, non-binary and/or binary chip sequences are written into a chip interleaver and read out to be modulated.

4. A sensor node according to claim 3 wherein the chip sequences are written into a block chip interleaver in row form and read out in column form to be modulated.

5. A sensor node according to claim 4 wherein, in respect of the chip interleaved transmitter, s of a block chip interleaver has N columns and M rows, and chip sequences of M-number of symbols are written in row form and read out in column form.

6. A sensor node according to any one of claims 2 to 5 wherein, for data

transmissions, transmitting symbols are spread into pseudo-random chip sequences, wherein the chip sequences for different symbols in an alphabet set are orthogonal between one and another.

7. A sensor node according to any one of claims 2 to 6 wherein the chip is configured to take a binary value.

8. A sensor node according to any one of claims 2 to 6 wherein the chip is configured to take a non-binary value that is deterministic, semi-random or random.

9. A sensor node according to any one of claims 2 to 8 wherein a chip sequence for one symbol has N chips, where N is an integer greater than 1 and, for data transmissions, the chip sequences for a group of M symbols, where M is an integer greater than 1, are interleaved.

10. A sensor node according to any one of claims 2 to 7 wherein, for data transmissions, chips adjacent to one another in a sequence are separated across a number of sequence blocks in an interleaved chip stream.

1 1. A sensor node according to any preceding claim wherein the transceiver includes a chip interleaved receiver configured to de- interleaving received communications data via the chip interleaving technique.

12. A sensor node according to claim 11 wherein, for received data, samples of demodulated signals representing received chip sequences are written into a block chip de- inter leaver in row form and read out in column form.

13. A sensor node according to claim 1 wherein, in the chip de- interleaved receiver, the chip interleaver can be designed and configured with respect to the chip interleaver in the transmitter..

14. A sensor node according to any preceding claim wherein the transceiver is a chip interleaved Direct Sequence Spread Spectrum (DSSS) transceiver.

15. A sensor node according to any preceding claim wherein the transceiver is a chip interleaved Direct Sequence Code Division Multiple Access (DS-CDMA) transceiver.

16. A wireless sensor network including a plurality of sensor nodes according to any one or more of the preceding claims.

17. A wireless sensor network according to claim 16 including:

^-number of sensor nodes; and

a coordinator;

wherein the k nodes are configured to transmit data to the coordinator using respective non-binary and/or binary chip interleaved/deinterleaved transceivers; and

wherein the coordinator transmits data to the k nodes using a non-binary and/or binary chip interleaved/deinterleaved transceiver.

18. A network according to claim 17 wherein the coordinator is configured to instruct any one of the k nodes to transmit, suspend and resume data transmissions, according to the quality of the channel between a node and the coordinator.

19. A network according to claim 18 wherein the channel quality is estimated by the coordinator according to signals received from the sensor nodes.

20. A network according to claim 19wherein, in the case that the channel quality is estimated to have been degraded to an unacceptable level, the coordinator instructs the sensor node to delay data transmission until a subsequent valid time interval, such that chip- interleaved signals are spaced out across a broader time interval subject to the channel estimate and transmission instructions made by the coordinator.

21. A coordinator configured for operation in a for a wireless sensor network according to any one of claims 16 to 20.

22. A method for transmitting data in a wireless sensor network, the method including operating a chip interleaved transmitter to transmit communications data via a non-binary and/or binary chip interleaving technique.

23. A method for receiving data in a wireless sensor network, the method including operating a chip interleaved receiver to receive communications data via a non-binary and/or binary chip de- interleaving technique.

24. A sensor for a wireless sensor network system, the sensor including a processor configured to perform a method according to claim 22 or claim 23.

25. A wireless sensor network including a plurality of nodes configured to perform a method according to claim 22 or claim 23.

26. A computer readable medium carrying a set of instructions that when executed by one or more processors cause the one or more processors to perform a method according to claim 22 or claim 23.