WO2012121056A1

WO2012121056A1 - Pixel circuit and display device

Info

Publication number: WO2012121056A1
Application number: PCT/JP2012/054885
Authority: WO
Inventors: 上田　直樹
Original assignee: シャープ株式会社
Priority date: 2011-03-10
Filing date: 2012-02-28
Publication date: 2012-09-13

Abstract

Provided is a pixel circuit, which performs accurate compensation and is capable of displaying stable images, while reducing power consumption. Also provided is a display device. A pixel circuit (2) is provided with: a display element unit (21), which is provided with a unit display element (LC), and an internal node (N1), which holds a pixel data voltage applied thereto; a first switch circuit (22), which is provided with transistors (T1, T2), which are connected in series, and have a connection point as an intermediate node (N2); a second switch circuit (23), which is provided with a transistor (T3), and has one end thereof connected to the intermediate node (N2); and a control circuit (24), which is provided with a transistor (T4), and controls a conduction state of the transistor (T3) on the basis of the pixel data voltage held by the internal node (N1). An output node (N3) is configured by connecting a first terminal of the transistor (T4) and a control terminal of the transistor (T3), and an electrical capacitance that controls a voltage held by the output node (N3) by means of a voltage held by the intermediate node (N2) is provided between the intermediate node (N2) and the output node (N3).

Description

Pixel circuit and display device

The present invention relates to a pixel circuit and a display device including the pixel circuit, and more particularly to an active matrix liquid crystal display device.

FIG. 17 is a block diagram showing a schematic configuration of a general active matrix type liquid crystal display device. As shown in FIG. 17, a general active matrix type liquid crystal display device has s × r pixel circuits provided at intersections of s source lines, r gate lines, and source lines and gate lines. And a source driver that applies a voltage to the pixel circuit via the source line and a gate driver that applies a voltage to the pixel circuit via the gate line (s and r are both natural numbers). In FIG. 18, each pixel circuit simply displays a transistor and a pixel electrode (black rectangular portion).

FIG. 18 is a circuit diagram showing a basic configuration of a pixel circuit included in a general active matrix type liquid crystal display device. As shown in FIG. 18, the pixel circuit includes a thin film transistor (TFT) in which a control terminal is connected to a gate line and a first terminal is connected to a source line, and a unit in which a second terminal of the TFT is connected to a pixel electrode. A liquid crystal display element; and an auxiliary capacitance element connected to the pixel electrode of the unit liquid crystal display element. The auxiliary capacitance element stabilizes the pixel data voltage applied to the pixel electrode. Specifically, in the auxiliary capacitance element, the electric capacity of the liquid crystal layer varies in black display / white display (display of a predetermined color when displaying a color image) due to the leakage current of TFT and the dielectric anisotropy of liquid crystal molecules. And fluctuations in the pixel data voltage applied to the pixel electrode due to voltage fluctuations or the like caused through parasitic capacitance between the pixel electrode and the peripheral wiring are suppressed. Further, by sequentially controlling the voltage of the gate line and sequentially turning on the TFTs connected to the gate line (on a gate line basis), the pixel data voltage is applied to the pixel electrode of each pixel circuit via the source line. To do.

In normal display mainly displaying moving images, even when the display content is a still image, the same voltage value (or voltage value with reversed polarity) is applied so that the pixel data voltage applied to the pixel electrode is updated every frame. ) Is repeatedly applied to the pixel electrode. Thereby, the fluctuation | variation of the liquid crystal voltage (absolute value) applied to a unit liquid crystal element is suppressed to the minimum, and the display of a high quality still image is ensured.

The power consumption for driving the liquid crystal display device is almost governed by the power consumption for driving the source line by the source driver, and can be generally expressed by the following relational expression (1). In Equation 1, P is power consumption, R is a refresh rate (number of refresh operations for one frame per unit time), C is a load capacity driven by the source driver, V is a drive voltage of the source driver, and r is a gate line. Number and s indicate the number of source lines, respectively. The refresh operation is an operation for restoring the original pixel data voltage by resolving the fluctuation caused in the liquid crystal voltage (absolute value) applied to the unit liquid crystal display element by reapplying the pixel data voltage. is there.

(Equation 1)
P∝R ・ C ・ V ²・ r ・ s

By the way, in the constant display mainly displaying a still image, it is not always necessary to reapply the pixel data voltage every frame. Therefore, in order to reduce the power consumption of the liquid crystal display device, the refresh rate during the constant display is lowered. However, when the refresh rate is lowered, the pixel data voltage applied to the pixel electrode varies due to the leakage current of the TFT. In addition, the average potential in each frame period also decreases. For this reason, the voltage fluctuation becomes a fluctuation in the display luminance (liquid crystal transmittance) of each pixel, and is observed as flicker. In addition, there is a risk that display quality may be deteriorated such that sufficient contrast cannot be obtained.

Here, as a method for solving the problem of deterioration in display quality due to a decrease in refresh rate in the constant display of still images, for example, configurations described in

Patent Documents

1 and 2 below are disclosed. In

Patent Documents

1 and 2, the TFT of the pixel circuit shown in FIG. 18 is composed of a series circuit of two TFTs (first TFT and second TFT), and the potential of the intermediate node is set to a pixel electrode by a unity gain buffer amplifier. The structure which controls so that it may become the same electric potential is disclosed. With such a configuration, no voltage is applied between the source and drain of the second TFT disposed on the pixel electrode side, so that the leakage current of the second TFT is greatly suppressed and the display quality is lowered. The problem can be solved (see FIGS. 19 and 20).

This is a solution that takes into account that the leakage current of the TFT greatly increases as the bias voltage between the source and drain increases. As shown in FIGS. 19 and 20, in the configurations described in

Patent Documents

1 and 2, in the first TFT connected to the source line, the bias voltage between the source and the drain increases, and the leakage current of the first TFT increases. Although there is a possibility, since the leakage current is compensated by the buffer amplifier, the pixel data voltage applied to the pixel electrode is not affected. With the configuration provided with such a buffer amplifier, the problem that the display quality is deteriorated due to the decrease in the refresh rate is solved, and the power consumption can be reduced due to the decrease in the refresh rate.

JP-A-5-142573 Japanese Patent Laid-Open No. 10-62817

With the spread of digital content (advertising, news, e-books, etc.) accompanying the evolution of communication infrastructure, in the digital content image display on mobile information terminals such as mobile phones and mobile Internet terminals (MID: Mobile ： Internet Device) A constant display of a still image is required. A portable information terminal that displays such digital contents uses a display device with low power consumption. However, since most of the time during which a still image is displayed when the terminal is used, the display is constantly updated. There is a demand for lower power consumption. However, the configuration having the operational amplifier in the pixel circuit as in

Patent Documents

1 and 2 is problematic because the power consumption is insufficient and the luminance of the display image is lowered.

On the other hand, by appropriately controlling the voltage to be compensated by using an element such as a TFT without providing such an operational amplifier, the pixel circuit can be simplified and the power consumption can be reduced. However, fluctuations caused by the control of the TFT (for example, a feedthrough voltage when the TFT is turned off) and a leak current of the TFT deteriorate the accuracy of the voltage to be compensated, so that the pixel data voltage (that is, , Display image) can be unstable, which is a problem.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a pixel circuit and a display device capable of displaying a stable image by performing compensation with high accuracy while reducing power consumption. is there.

In order to achieve the above object, the present invention provides:
A display element unit including a unit display element;
An internal node that forms part of the display element unit and holds a pixel data voltage applied to the display element unit;
The pixel having a series circuit of first and second transistor elements, connected to one end of a data signal line, connected to the other end of the internal node, and supplied from the data signal line via the series circuit A first switch circuit for transferring a data voltage to the internal node;
One end of a voltage supply line for supplying a compensation voltage is connected to the third transistor element, and the other end is connected to an intermediate node that is a connection point where the first and second transistor elements in the series circuit are connected in series. A second switch circuit that
A control circuit that includes a fourth transistor element, and controls a conduction state of the third transistor element based on the pixel data voltage held by the internal node.
Each of the first to fourth transistor elements includes a first terminal, a second terminal, and a control terminal for controlling conduction between the first and second terminals,
A control terminal of the first transistor element is connected to a first scanning signal line that turns on the first transistor element during an operation of transferring the pixel data voltage to the internal node;
A control terminal of the second transistor element is connected to a second scanning signal line that turns on the second transistor element during an operation of transferring the pixel data voltage to the internal node;
A control terminal of the third transistor element and a first terminal of the fourth transistor element are connected to form an output node of the control circuit;
A control terminal of the fourth transistor element is connected to the internal node, and a second terminal of the fourth transistor element is connected to a first control line for supplying a boost voltage;
There is provided a pixel circuit between the output node and the intermediate node, having a capacitance for controlling a voltage held by the output node with a voltage held by the intermediate node.

Furthermore, the pixel circuit having the above characteristics performs a self-refresh operation capable of compensating the pixel data voltage held by the internal node using the compensation voltage.
The self-refresh operation
When the pixel data voltage held by the internal node is equal to or higher than a predetermined voltage, the output node holds a voltage that makes the third transistor element conductive, whereby the second transistor element and the third transistor element Applying the compensation voltage to the internal node via
When the pixel data voltage held by the internal node is less than the predetermined voltage, the output node holds a voltage that makes the third transistor element non-conductive, thereby applying the compensation voltage to the internal node. It is preferable not to.

Furthermore, the pixel circuit having the above-described characteristics can be used as the self-refresh operation.
A first boost voltage is applied to the first control line, a voltage for turning on the first transistor element is applied to the first scanning signal line, and the second transistor is applied to the second scanning signal line. The intermediate node holds the reference voltage and the output node is applied by performing a first operation in which a voltage that makes the element non-conductive is applied and a reference voltage is applied to the data signal line. Holds a voltage corresponding to the pixel data voltage held by the internal node,
When the pixel data voltage held by the internal node is equal to or higher than the predetermined voltage, the first node holds a voltage that makes the third transistor element conductive by the first operation;
When the pixel data voltage held by the internal node is lower than the predetermined voltage, it is preferable that the output node holds a voltage that makes the third transistor element non-conductive by the first operation.

Furthermore, the pixel circuit having the above-described characteristics can be used as the self-refresh operation.
After the first operation,
A second operation is performed in which a voltage that makes the first transistor element non-conductive is applied to the first scanning signal line;
When the pixel data voltage held by the internal node is equal to or higher than the predetermined voltage, the second node causes the output node to be equal to or higher than a voltage obtained by adding the threshold voltage of the third transistor element to the compensation voltage. By holding the voltage, the third transistor element is made conductive, the intermediate node holds the compensation voltage,
When the pixel data voltage held by the internal node is lower than the predetermined voltage, the second node holds the voltage at which the third transistor element is turned off by the second operation. The intermediate node holds the reference voltage;
After the second operation,
It is preferable that a third operation in which a voltage that makes the second transistor element conductive is applied to the second scanning signal line.

Furthermore, in the pixel circuit having the above characteristics, it is preferable that the compensation voltage is equal to a maximum voltage of the pixel data voltage held by the internal node.

Furthermore, in the pixel circuit having the above characteristics, it is preferable that the reference voltage is equal to or lower than a minimum voltage of the pixel data voltage held by the internal node.

Further, in the pixel circuit having the above characteristics, it is preferable that the first boost voltage is equal to or higher than a voltage obtained by adding a threshold voltage of the third transistor element to the reference voltage.

Further, in the pixel circuit having the above characteristics, the predetermined voltage may be a voltage obtained by adding a threshold voltage of the third transistor element and a threshold voltage of the fourth transistor element to the reference voltage.

Furthermore, the pixel circuit having the above characteristics is in a self-refresh period in which at least one self-refresh operation is performed, and after the self-refresh operation,
A voltage for turning off the first transistor element is applied to the first scanning signal line, and a voltage for turning off the second transistor element is applied to the second scanning signal line, Preferably, a holding operation is performed in which a second boost voltage that is less than a voltage obtained by subtracting the threshold voltage of the third transistor element from the minimum voltage of the pixel data voltage held by the internal node is applied to one control line. .

Further, the pixel circuit having the above characteristics is provided after the self-refresh operation and before the holding operation is started.
A voltage that turns on the first transistor element is applied to the first scanning signal line, and a voltage that turns off the second transistor element is applied to the second scanning signal line. A protection operation is performed in which the second boost voltage is applied to the control line, and a protection voltage that is higher than the minimum voltage and lower than the maximum voltage of the pixel data voltage held by the internal node is applied to the data signal line. It is preferable.

Furthermore, in the pixel circuit having the above characteristics, the protection voltage may be an intermediate voltage between the minimum voltage and the maximum voltage of the pixel data voltage held by the internal node.

Furthermore, the pixel circuit having the above characteristics may have a self-refresh operation performed at least once before the self-refresh period.
Preferably, a third boost voltage that is less than a voltage obtained by subtracting a threshold voltage of the third transistor element from a minimum voltage of the pixel data voltage held by the internal node is applied to the first control line.

Furthermore, in the pixel circuit having the above characteristics, the first switch circuit includes a series circuit of the first and second transistor elements,
The first terminal of the first transistor element is the data signal line, the second terminal of the first transistor element, the first terminal of the second transistor element is the intermediate node, and the second terminal of the second transistor element. May be connected to the internal node.

Furthermore, in the pixel circuit having the above characteristics, the second switch circuit includes the third transistor element.
The first terminal of the third transistor element may be connected to the voltage supply line, and the second terminal of the third transistor element may be connected to the intermediate node.

Furthermore, in the pixel circuit having the above characteristics, the capacitance may include a parasitic capacitance between a control terminal and a second terminal of the third transistor element.

Furthermore, in the pixel circuit having the above characteristics, the electric capacity may include a capacitance of a first capacitance element having one end connected to the output node and the other end connected to the internal node.

Furthermore, in order to achieve the above object, the present invention provides:
A plurality of pixel circuits having the above characteristics are arranged in the row direction and the column direction to form a pixel circuit array,
A data signal line driving circuit for applying a voltage to the data signal line;
A scanning signal line driving circuit for applying a voltage to the first scanning signal line and the second scanning signal line;
A voltage supply line driving circuit for applying a voltage to the voltage supply line;
And a first control line driving circuit for applying a voltage to the first control line.

Furthermore, in the display device having the above characteristics, each of the pixel circuits may include a second capacitor element having one end connected to the internal node and the other end connected to the voltage supply line.

Further, the display device having the above characteristics further includes a second control line driving circuit for applying a voltage to the second control line,
Each of the pixel circuits may include a second capacitor element having one end connected to the internal node and the other end connected to the second control line.

Further, the display device having the above characteristics is arranged between the rows of the pixel circuits arranged in adjacent rows, and is commonly connected to a control terminal of the first transistor element provided in the pixel circuit. At least one first scanning signal line may be provided.

Further, the display device having the above characteristics is disposed between the rows of the pixel circuits arranged in adjacent rows, and is connected in common to the second terminal of the fourth transistor element provided in the pixel circuit. At least one first control line may be provided.

Further, in the display device having the above characteristics, the first control line connected in common to the second terminal of the fourth transistor element of each of the pixel circuits arranged in the same row is connected to each row. Provided,
The even-numbered drive line to which each of the first control lines provided for the even-numbered rows is connected, and the odd-numbered drive line to which each of the first control lines provided for the odd-numbered rows is connected. The first control line driving circuit may be separately connected.

Further, in the display device having the above characteristics, the first control line connected in common to the second terminal of the fourth transistor element of each of the pixel circuits arranged in the same row is connected to each row. Provided,
Each of the first control lines may be separately connected to the first control line driving circuit integrated with the scanning signal line driving circuit.

According to the pixel circuit and the display device having the above characteristics, the voltage of the intermediate node is controlled to the output node via the capacitance, and the third transistor of the second switch circuit controls the supply of the compensation voltage by the voltage of the output node. The conduction / non-conduction of the element is controlled. Therefore, when the second switch circuit is turned on, the compensation voltage can be supplied with high accuracy (without excess or shortage). Further, in the pixel circuit having the above characteristics, conduction / non-conduction of the third transistor element of the second switch circuit that controls supply of the compensation voltage is controlled by controlling the boost voltage. Therefore, when the third transistor element is turned off, the leakage current of the third transistor can be accurately suppressed. Therefore, it is possible to stabilize the pixel data voltage (that is, the display image) by performing compensation with high accuracy.

Further, in the pixel circuit having the above characteristics, when the pixel data voltage held in the internal node is equal to or higher than a predetermined voltage, the voltage at which the third transistor is turned on is held in the output node, so that the compensation voltage is set in the intermediate node. Applied. The compensation voltage applied to the intermediate node pushes up the voltage at the output node through the capacitance. Thereby, since the conduction state of the third transistor is maintained, the compensation voltage can be applied to the intermediate node (and thus the internal node) without excess or deficiency. On the other hand, if the pixel data voltage held by the internal node is lower than the predetermined voltage, the voltage at which the third transistor is turned off is held at the output node, so the compensation voltage is not applied to the intermediate node (and thus the internal node). . Thereby, since the non-conducting state of the third transistor is maintained, it is possible to prevent the compensation voltage from being applied to the intermediate node (and thus the internal node).

Note that when applied to a display device that performs color display, the pixel circuit of the present invention configures each sub-pixel corresponding to each color (for example, three primary colors of RGB) included in each pixel, and performs a monochrome display. When applied to the above, each pixel is constituted.

1 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to a first embodiment of the present invention. 1 is a partial cross-sectional schematic structure diagram of a liquid crystal display device according to a first embodiment of the present invention. 1 is a circuit diagram showing a basic circuit configuration of a pixel circuit included in a liquid crystal display device according to a first embodiment of the present invention. 1 is a circuit diagram showing a circuit configuration example of a pixel circuit included in a liquid crystal display device according to a first embodiment of the present invention. FIG. 3 is a timing chart showing an operation in the normal display mode of the liquid crystal display device according to the first embodiment of the present invention. FIG. 3 is a timing chart showing an operation during a self-refresh period of the liquid crystal display device according to the first embodiment of the present invention. The block diagram which shows an example of schematic structure of the liquid crystal display device which concerns on 2nd Embodiment of this invention. The circuit diagram which shows the basic circuit structure of the pixel circuit with which the liquid crystal display device which concerns on 2nd Embodiment of this invention is provided. FIG. 6 is a circuit diagram showing a circuit configuration example of a pixel circuit included in a liquid crystal display device according to a second embodiment of the present invention. Timing chart showing the operation of the liquid crystal display device according to the second embodiment of the present invention in the normal display mode. FIG. 5 is a timing chart showing the operation during the self-refresh period of the liquid crystal display device according to the second embodiment of the present invention. The block diagram which shows an example of schematic structure of the liquid crystal display device which concerns on 3rd Embodiment of this invention. The block diagram which shows an example of schematic structure of the liquid crystal display device which concerns on 4th Embodiment of this invention. The block diagram which shows an example of schematic structure of the liquid crystal display device which concerns on 5th Embodiment of this invention. The block diagram which shows an example of schematic structure of the liquid crystal display device which concerns on 6th Embodiment of this invention. Timing chart showing the operation in the self-refresh period when the modification <1> is applied to the liquid crystal display device according to the first embodiment of the present invention. A block diagram showing a schematic configuration of a general active matrix liquid crystal display device A circuit diagram showing a basic configuration of a pixel circuit included in a general active matrix liquid crystal display device Circuit diagram showing an example of a conventional pixel circuit having a unity gain buffer amplifier Circuit diagram showing another example of a conventional pixel circuit having a unity gain buffer amplifier

<< First Embodiment >>
<Liquid crystal display device>
A liquid crystal display device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a schematic configuration of the liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 1, the liquid crystal display device 1a includes an active matrix substrate 10, a common electrode 30, a display control circuit 11, a common electrode driving circuit 12, a source driver 13, a gate driver 14, and various wirings to be described later. On the active matrix substrate 10, a plurality of pixel circuits 2 are arranged in the row direction (vertical direction in the figure) and in the column direction (horizontal direction in the figure) to form a pixel circuit array. In the active matrix substrate 10 shown in FIG. 1, a total of n × m pixel circuits of n in the row direction and m in the column direction are arranged. Note that n and m are natural numbers. In FIG. 1, the top row is the first row, the bottom row is the nth row, the leftmost column is the first column, and the rightmost column is the mth column. And In the following, when referring to the pixel circuit 2 in a specific row and column, it is referred to as 2 (row, column). For example, the pixel circuit 2 arranged in the n-th row and the m-th column at the lower right in the drawing is referred to as 2 (n, m).

In FIG. 1, the pixel circuit 2 is displayed in a block form in order to avoid complicated drawing. Although details will be described later, the pixel circuit 2 includes a main circuit 2A for holding the pixel data voltage for controlling the display state of the “pixel”, and a pixel data voltage for holding the fluctuation of the pixel data voltage held by the main circuit 2A. And a self-refresh circuit 2B. In FIG. 1, the active matrix substrate 10 is illustrated on the upper side of the common electrode 30 for the sake of convenience in order to clearly display that various wirings are formed on the active matrix substrate 10.

For convenience, the minimum display unit corresponding to one pixel circuit 2 is referred to as a “pixel”. At this time, the “pixel data voltage” held in each pixel circuit 2 is a voltage for controlling the display / non-display (for example, black display) of each color (for example, the three primary colors of RGB) when performing color display. In the case of display, the voltage is used to control black display / white display.

FIG. 2 is a partial sectional schematic structural diagram of the liquid crystal display device according to the first embodiment of the present invention. FIG. 2 is a schematic cross-sectional structure diagram showing the relationship between the active matrix substrate 10 and the common electrode 30 and shows the structure of the display element unit 21 (see FIG. 3), which is a component of the pixel circuit 2. The active matrix substrate 10 is a light transmissive transparent substrate, and is made of, for example, glass or plastic. As shown in FIG. 1, the pixel circuit 2 connected to each wiring is formed on the active matrix substrate 10. In FIG. 2, the pixel electrode 20 is illustrated as a representative of the components of the pixel circuit 2. The pixel electrode 20 is made of a light transmissive transparent conductive material, for example, ITO (indium tin oxide).

Further, a light-transmitting counter substrate 31 is disposed so as to face the active matrix substrate 10, and a liquid crystal layer 33 is held in a gap between the two substrates. Polarizing plates (not shown) are attached to the outer surfaces of both substrates.

The liquid crystal layer 33 is sealed with a sealing material 32 in the peripheral portions of both substrates. A common electrode 30 made of a light-transmissive transparent conductive material such as ITO is formed on the counter substrate 31 so as to face the pixel electrode 20. The common electrode 30 is formed as a single film so as to spread over the counter substrate 31 substantially on one surface. Here, a unit liquid crystal display element LC (corresponding to a unit display element) is formed by one pixel electrode 20, a common electrode 30, and a liquid crystal layer 33 sandwiched therebetween.

When the liquid crystal display device 1a is a transmissive liquid crystal display device, for example, a backlight device (not shown) is disposed on the back side of the active matrix substrate 10, and light is emitted from the active matrix substrate 10 toward the counter substrate 31. Is irradiated. In addition, the schematic cross-sectional structures of liquid crystal display devices 1b to 1f (see FIGS. 7 to 15) of second to sixth embodiments to be described later are the same as the schematic cross-sectional structures shown in FIG.

As shown in FIG. 1, a plurality of wirings are formed on the active matrix substrate 10 in the vertical and horizontal directions. Specifically, n gate lines (GL (1), GL (2),..., GL (n)) extending in the horizontal direction (row direction) and the horizontal direction (row). N auxiliary gate lines (AGL (1), AGL (2),..., AGL (n)) in order from the top in the figure, and m auxiliary gate lines extending in the vertical direction (column direction). Source lines (SL (1), SL (2),..., SL (m)) are formed in order from the left in the figure. Hereinafter, for convenience, each source line (SL (1), SL (2),..., SL (m)) is generalized and referred to as a source line SL, and each gate line (GL (1), GL (2),..., GL (n)) are generally referred to as gate lines GL, and each auxiliary gate line (AGL (1), AGL (2),..., AGL (n)) is generally used. And referred to as an auxiliary gate line AGL.

In the liquid crystal display device 1a of the present embodiment, the same number of gate lines GL and auxiliary gate lines AGL as the number of rows n of the pixel circuit 2 are formed on the active matrix substrate 10. Then, m pixel circuits 2 (i, 1) to 2 (i, m) arranged in a certain row are connected to the same gate line GL (i) and auxiliary gate line AGL (i) (i is A natural number between 1 and n). Further, in the liquid crystal display device 1 a of this embodiment, the same number of source lines SL as the number of columns m of the pixel circuit 2 are formed on the active matrix substrate 10. Then, the n pixel circuits 2 (1, j) to 2 (n, j) arranged in a certain column are connected to the same source line SL (j) (j is a natural number of 1 to m).

Furthermore, in the liquid crystal display device 1a of the present embodiment, the auxiliary capacitance line CSL and the boost voltage supply line BST are formed on the active matrix substrate 10. Each of the auxiliary capacitance line CSL and the boost voltage supply line BST includes branch wirings that branch into n lines and extend in the horizontal direction (row direction) in order to connect to each pixel circuit 2. Similarly to the gate line GL and the auxiliary gate line AGL, the pixel circuit 2 is arranged for each of the n branch wirings of the auxiliary capacitance line CSL and the n branch wirings of the boost voltage supply line BST for each row. Connecting.

The source driver 13 and the gate driver 14 sequentially apply a voltage corresponding to an image to be displayed to the gate line GL, the auxiliary gate line AGL, and the source line SL, thereby forming pixels formed in each pixel circuit 2. A voltage is applied to the electrode 20. At this time, the gate driver 14 can individually apply voltages to the gate lines GL (1) to GL (n) and the auxiliary gate lines AGL (1) to AGL (n). Similarly, the source driver 13 can individually apply a voltage to each of the source lines SL (1) to SL (m). On the other hand, the common electrode drive circuit 12 applies a voltage to the entire storage capacitor line CSL including n branch wirings. Similarly, the display control circuit 11 applies a voltage to the entire boost voltage supply line BST including n branch wirings.

In addition, the liquid crystal display device 1a of the present embodiment includes a common electrode wiring CML for the common electrode driving circuit 12 to apply a voltage to the common electrode 30.

In the liquid crystal display device 1a of the present embodiment, the source line SL corresponds to the “data signal line”, the gate line GL corresponds to the “first scanning signal line”, and the auxiliary gate line AGL corresponds to the “second scanning signal line”. The auxiliary capacitance line CSL corresponds to the “voltage supply line”, and the boost voltage supply line BST corresponds to the “first control line”. The source driver 13 corresponds to the “data signal line driving circuit”, the gate driver 14 corresponds to the “scanning signal line driving circuit”, and a part of the common electrode driving circuit 12 corresponds to the “voltage supply line driving circuit”. A part of the display control circuit 11 corresponds to the “first control line driving circuit”.

The liquid crystal display device 1a can operate at least in the “always display mode” (details will be described later) in which the display is always performed. The liquid crystal display device 1a may be operable in an operation mode other than the constant display mode. For example, the “write operation” (operation for newly applying a voltage to the pixel electrode 20 via the source line SL) may be performed in “normal display mode” in which each frame is repeated. Further, the liquid crystal display device 1a may be any of a transmissive type, a reflective type, and a transflective type liquid crystal display device.

The display control circuit 11 performs “write operation” and “self-refresh operation” (operation in which a voltage corresponding to the pixel data voltage applied to the pixel electrode 20 is reapplied to the pixel electrode 20) in the normal display mode, This is a circuit for controlling the “write operation” in the display mode. During the writing operation, the display control circuit 11 receives a data signal Dv and a timing signal Ct representing an image to be displayed from an external signal source. Then, the display control circuit 11 uses the digital image signal DA and the data side timing control signal Stc to be supplied to the source driver 13 as signals for displaying an image on the display element unit 21 of the pixel circuit array based on the signals Dv and Ct. And a scanning side timing control signal Gtc to be supplied to the gate driver 14, a voltage control signal Sec to be supplied to the common electrode driving circuit 12, and a boost voltage V _BST to be applied to the boost voltage supply line BST. The display control circuit 11 may be partly or wholly formed in the source driver 13 or the gate driver 14.

The common electrode drive circuit 12 is a circuit that applies the auxiliary capacitance voltage V _CSL to the auxiliary capacitance line CSL and applies the common voltage V _COM to the common electrode wiring CML. Further, the common electrode drive circuit 12 switches the common voltage _VCOM between a high level and a low level at a predetermined timing under the control of the display control circuit 11, thereby changing the polarity of the voltage applied to the liquid crystal at a predetermined timing. “Common voltage AC drive” can be performed that reverses and suppresses burn-in of the display screen. The liquid crystal display device 1a, along with a constant common voltage V _COM, by switching the magnitude of the source line voltage V _SL to common-voltage V _COM at a predetermined timing, the voltage applied to the liquid crystal polarity a predetermined “Common voltage DC drive” may be performed that reverses the timing and suppresses burn-in of the display screen. Any of the driving methods can be realized by appropriately selecting various voltages to be applied to the pixel circuit 2, but in the following, the liquid crystal display device 1a of the present embodiment will be referred to as “common voltage AC driving” for the sake of concrete description. An example of performing the above will be described.

The source driver 13 is a circuit that applies a source line voltage V _SL having a predetermined voltage value to each source line SL at a predetermined timing during a write operation and a self-refresh operation under the control of the display control circuit 11. During the writing operation, the source driver 13 corresponds to the pixel values of one row (m) represented by the digital signal DA based on the digital image signal DA and the data-side timing control signal Stc, and the common voltage V _COM. A source line voltage V _SL that is a voltage suitable for the voltage level is generated every horizontal period. The source line voltage _VSL is, for example, a two-tone analog voltage (two discrete voltage values). Then, these source line voltages _VSL are respectively applied to the corresponding source lines SL. In the self-refresh operation, the source driver 13 is the same for all source lines SL connected to the target pixel circuit 2 (for example, all the pixel circuits 2) under the control of the display control circuit 11. A source line voltage _VSL having a predetermined voltage value is applied at timing (details will be described later).

The gate driver 14 applies a gate line voltage V _GL having a predetermined voltage value to each gate line GL at a predetermined timing during the write operation and the self-refresh operation under the control of the display control circuit 11 and each auxiliary gate. a circuit for applying an auxiliary gate line voltage V _AGL predetermined voltage value on line AGL. During a write operation, the gate driver 14 for applying a source line voltage V _SL of the relative pixel circuits 2 arranged in a given row, based on the scanning side timing control signal Gtc in the predetermined row The gate line voltage V _GL and the auxiliary gate line voltage V _AGL of the voltage value for enabling writing to the connected pixel circuit 2 are set to the gate line GL and the auxiliary gate line AGL connected to the pixel circuit 2 arranged. Apply. The gate driver 14 changes the source line voltage V _SL by changing the gate line GL and the auxiliary gate line AGL to which the voltages V _GL and V _AGL enabling the pixel circuit 2 to be written are changed every horizontal period. Sequentially applied to the pixel circuit 2. Further, during the self-refresh operation, the gate driver 14 controls the gate line voltage of a predetermined voltage value at a predetermined timing to all the gate lines GL connected to the target pixel circuit 2 under the control of the display control circuit 11. applies a V _GL, with respect to all the auxiliary gate line AGL to be connected to the pixel circuit 2 of interest to apply the auxiliary gate line voltage V _AGL predetermined voltage value at a predetermined timing (details will be described later). Note that the gate driver 14 may be formed on the active matrix substrate 10 as in the pixel circuit 2. Further, the display control circuit 11 instead of the gate driver 14 may apply the auxiliary gate line voltage VAGL to the auxiliary gate line _AGL .

When the liquid crystal display device 1a according to the present embodiment performs “common voltage AC driving”, the common voltage V _COM is changed between a high level and a low level every horizontal period and every frame period in the normal display mode. It may be switched. That is, in one frame period, the common voltage V _COM may be switched in two adjacent horizontal periods, and the common voltage V _COM may be switched in each corresponding horizontal period in two adjacent frame periods. On the other hand, in the constant display mode, the common voltage V _COM during one frame period may be maintained at the same voltage level, and the common voltage V _COM may be switched every predetermined number of frames.

<Pixel circuit>
A circuit configuration of the pixel circuit 2 included in the liquid crystal display device 1a according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a basic circuit configuration of the pixel circuit included in the liquid crystal display device according to the first embodiment of the present invention, and FIG. 4 is a pixel included in the liquid crystal display device according to the first embodiment of the present invention. It is a circuit diagram which shows the example of 1 circuit structure of a circuit.

As shown in FIG. 3, the pixel circuit 2 includes a main circuit 2A and a self-refresh circuit 2B. The main circuit 2A includes a display element unit 21 including a unit liquid crystal display element LC, a first switch circuit 22, and an auxiliary capacitive element Cs (corresponding to the second capacitive element). On the other hand, the self-refresh circuit 2B includes a second switch circuit 23, a control circuit 24, and a boost capacitor element Cbst. As described with reference to FIG. 2, the unit liquid crystal display element LC includes the pixel electrode 20 and the common electrode 30. Note that the basic circuit configuration shown in FIG. 3 is a high-level circuit configuration including the specific circuit configuration example shown in FIG.

The first switch circuit 22 includes a transistor T1 (corresponding to the first transistor element) and a transistor T2 (corresponding to the second transistor element) connected in series. The second switch circuit 23 includes a transistor T3 (corresponding to the third transistor element). The control circuit 24 includes a transistor T4 (corresponding to the fourth transistor element). Each of the transistors T1 to T4 includes a first terminal and a second terminal (source electrode and drain electrode), and a control terminal (gate electrode).

The source line SL is connected to one end of the first switch circuit 22, and the control terminal of the transistor T4 is connected to the other end to form an internal node N1. The internal node N1 holds the pixel data voltage V _N1 by applying the source line voltage V _SL from the source line SL during the write operation. The auxiliary capacitance element Cs has one end connected to the internal node N1 and the other end connected to the auxiliary capacitance line CSL. The auxiliary capacitance element Cs is supplementarily added for the purpose of enabling the internal node N1 to stably hold the pixel data voltage _VN1 . Further, the pixel data voltage V _N1 held in the internal node N1 is applied to the pixel electrode 20. That is, an image corresponding to the pixel data voltage V _N1 (more precisely, an image corresponding to the liquid crystal voltage V _LC that is the difference between the pixel data voltage V _N1 and the common voltage V _COM ) is displayed on the liquid crystal display device 1a. The

The transistor T1 of the first switch circuit 22 has a control terminal connected to the gate line GL. That is, the conduction state of the transistor T1 is controlled by the gate line voltage _VGL . The control terminal of the transistor T2 of the first switch circuit 22 is connected to the auxiliary gate line AGL. That is, the conduction state of the transistor T2 is controlled by the auxiliary gate line voltage _VAGL . The second terminal of the transistor T1 and the first terminal of the transistor T2 are connected to form an intermediate node N2. Therefore, when at least one of the transistors T1 and T2 is turned off, the source line SL and the internal node N1 are turned off, and the source line voltage _VSL is not applied to the internal node N1. Further, at least when the transistor T2 becomes non-conductive, the intermediate node N2 and the internal node N1 become non-conductive, and the intermediate node voltage V _N2 held by the intermediate node _N2 is not applied to the internal node N1. In the circuit configuration example shown in FIG. 4, the first switch circuit 22 is configured only by a series circuit of a transistor T1 and a transistor T2, the first terminal of the transistor T1 is connected to the source line SL, and the transistor T2 The second terminal is connected to the internal node N1.

The second switch circuit 23 has one end connected to the auxiliary capacitance line CSL and the other end connected to the intermediate node N2. The control terminal of the transistor T3 of the second switch circuit 23 is connected to the first terminal of the transistor T4 of the control circuit 24, thereby forming an output node N3. That is, the conduction state of the transistor T3 is controlled by the output node voltage V _N3 held by the output node _N3 . In the circuit configuration example shown in FIG. 4, the second switch circuit 23 includes only the transistor T3, the first terminal of the transistor T3 is connected to the auxiliary capacitance line CSL, and the second terminal is connected to the intermediate node N2. The

The transistor T4 of the control circuit 24 has a second terminal connected to the boost voltage supply line BST. Boost capacitor Cbst has one end connected to output node N3 and the other end connected to intermediate node N2. Therefore, the intermediate node voltage V _N2 and the output node voltage V _N3 affect each other via the boost capacitor element Cbst. That is, by the intermediate node voltage _{V N2,} the output node _{V N3} may be controlled (similarly, the output node _{V N3,} the intermediate node voltage _{V N2} can be controlled).

Note that if there is some electric capacitance (for example, a parasitic capacitance between the control terminal and the second terminal of the transistor T3), the output node voltage V _N3 can be controlled by the intermediate node voltage V _N2 . Therefore, the boost capacitor element Cbst can be eliminated. However, in the following, for the sake of concrete explanation, a case where the boost capacitor element Cbst is provided will be exemplified.

The four types of transistors T1 to T4 are all thin film transistors such as polycrystalline silicon TFTs or amorphous silicon TFTs formed on the active matrix substrate 10. Further, each of the transistors T1 to T4 may be configured by a single transistor, but may be configured by connecting a plurality of transistors in series and sharing a control terminal. In the following, for the sake of concrete explanation, a case where all the transistors T1 to T4 are N-channel TFTs and all the threshold voltages of the transistors T1 to T4 are 1V will be exemplified.

<Operation example of the constant display mode>
An example of the constant display mode of the pixel circuit 2 included in the liquid crystal display device 1a according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a timing chart showing an operation in the normal display mode of the pixel circuit included in the liquid crystal display device according to the first embodiment of the present invention. FIG. 6 is a timing chart showing an operation in the self-refresh period of the pixel circuit according to the first embodiment of the present invention. In FIGS. 5 and 6, for the convenience of illustration, the relative length of time in each period (the length in the horizontal direction in the figure) is not necessarily correct.

As shown in FIG. 5, in the constant display mode, the “writing period” and the “self-refresh period” are repeatedly performed. For example, the write operation is performed once in the “write period”, and the self-refresh operation is performed at least once in the “self-refresh period”. Specifically, the self-refresh period includes at least one “small period” (first to xth small period) in which the self-refresh operation is performed once (x is a natural number). X indicating the number of repetitions of the self-refresh operation is x = 59 in consideration of the effect of reducing the power consumption by the self-refresh operation and the deterioration of the liquid crystal caused by using the same common voltage V _COM during the self-refresh period. A degree is preferable. Furthermore, in this case, each of one writing period and one small period may be 16.7 ms (the total number of writing periods and small periods included in one second is 60).

In the writing period, the gate line voltage V _GL having a voltage value that makes the transistor T1 conductive (hereinafter, 10 V as an example) is, for example, gate lines GL (1), GL (2),. ) In this order. At the same time, the auxiliary gate line voltage _VAGL having a voltage value (hereinafter referred to as 10 V as an example) that makes the transistor T2 conductive is, for example, auxiliary gate lines AGL (1), AGL (2),. Applied in the order of (n). Note that, in the writing period, there is a timing at which the above 10 V is simultaneously applied to the gate line GL and the auxiliary gate line AGL connected to the pixel circuits 2 arranged in the same row. For example, in FIG. 5, the gate line voltage V _{GL (i)} of 10V is applied to the gate line GL (i), and the auxiliary gate line voltage V _{AGL (i) of} 10V is simultaneously applied to the auxiliary gate line AGL (i). Thereafter, a state where the gate line voltage V _{GL (i + 1)} of 10V is applied to the gate line GL (i + 1), and the auxiliary gate line voltage V _{AGL (i + 1) of} 10V is applied to the auxiliary gate line _{AGL (i + 1)} at the same time. It is shown as a specific example.

Through the above operation, the transistors T1 and T2 of the pixel circuit 2 arranged in a certain row are both in a conductive state. Then, the source line voltage V _SL applied to each of the source lines _SL (hereinafter, for example, two voltage values of 0V and 5V can be taken) are unit liquid crystal display elements LC included in the pixel circuit 2. The pixel data voltage V _N1 is held at the internal node N1. This operation is sequentially performed for all the pixel circuits 2 for each row, whereby the pixel data voltage V _N1 is held in the internal node N1 of each pixel circuit 2.

When the above-mentioned 10 V is not applied to the gate line GL, the gate line voltage V _GL having a voltage value that makes the transistor T1 non-conductive (hereinafter referred to as −5 V as an example) is applied to the gate line GL. Is done. Similarly, when the above-mentioned 10 V is not applied to the auxiliary gate line AGL, the auxiliary gate line voltage V _AGL having a voltage value (hereinafter referred to as −5 V as an example) that makes the transistor T2 nonconductive is set to the auxiliary gate line _AGL. Applied to line AGL.

Pixel data voltage V _N1 of the internal node N1 is held is approximately equal to the voltage value of the source line voltage V _SL immediately after the source line voltage V _SL is applied to the pixel electrode 20 of the unit liquid crystal display device LC, time It can vary over time. For example, in FIG. 5, the internal node N1 of the pixel circuit 2 (i, j) in which the source line voltage _{VSL (j) of} 5V is applied to the pixel electrode 20 of the unit liquid crystal display element LC via the source line _{SL (j).} Of the pixel data voltage V _{N1 (i, j)} held by the pixel line and the source line voltage V _{SL (j) of} 0 V is applied to the pixel electrode 20 of the unit liquid crystal display element LC via the source line _{SL (j)} . The fluctuation of the pixel data voltage V _{N1 (i + 1, j)} held by the internal node N1 of the pixel circuit 2 (i + 1, j) is shown as a specific example.

Therefore, in the liquid crystal display device 1a of the present embodiment, a self-refresh period is placed between two write periods, thereby increasing the time interval of the write period (lowering the refresh rate) and reducing power consumption. The fluctuation of the pixel data voltage V _N1 is suppressed by the self-refresh operation.

Further, as shown in FIG. 5, the common voltage V _COM (hereinafter, for example, two voltage values of 0V and 5V can be taken as an example) is the same in a certain writing period and the self-refresh period immediately after that. Become. In addition, the common voltage V _COM is different in two writing periods immediately before and after the self-refresh period. Further, the auxiliary capacitance voltage V _CSL is constant at a predetermined voltage value (hereinafter, 5 V as an example) regardless of the writing period and the self-refresh period. Further, the boost voltage V _BST is constant at a predetermined voltage value (hereinafter referred to as −5 V as an example) during the writing period.

<Self-refresh operation>
Next, details of the self-refresh operation will be described. As described above, the self-refresh period includes the first to xth sub-periods in which the self-refresh operation is performed once, but the operations performed in each sub-period are the same. Therefore, in the following, the first small period will be described as an example. In addition, when the pixel data voltage V _N1 is (substantially) 0 V (when the source line voltage V _SL of 0 V is applied to the pixel electrode 20 of the unit liquid crystal display element LC by the previous writing operation), the pixel data voltage A case where V _N1 is (substantially) 5 V (when a source line voltage V _SL of 5 V is applied to the pixel electrode 20 of the unit liquid crystal display element LC by the previous writing operation) will be described separately.

Each of the first to xth sub-periods included in the self-refresh period is the first to third operation periods in which the self-refresh operation is performed, and after the first to third operation periods, and the holding operation (internal node N1). And a holding operation period during which the voltage is not applied to the holding operation period. In the following, for the sake of concrete description, a self-refresh operation of a liquid crystal display device including the pixel circuit 2 shown in FIG. 4 will be exemplified.

・ When V _N1 is 0V [Before refresh period (write period)]
As described above, the boost voltage V _BST is −5 V during the writing period. Therefore, when the pixel data voltage V _N1 is 0V, the transistor T4 becomes conductive, and the output node voltage V _N3 decreases to −5V. On the other hand, the intermediate node voltage V _N2 is 0 V, which is the same as the pixel data voltage V _N1 .

The output node voltage V _N3 is sufficiently smaller than the voltage obtained by adding the threshold voltage of the transistor T3 to the intermediate node voltage V _N2 and the auxiliary capacitance voltage V _CSL . Therefore, when the self-refresh operation is not performed, the leakage current of the transistor T3 can be suitably suppressed. Therefore, it is possible to suppress the pixel data voltage V _N1 from fluctuating due to the leakage current of the transistor T3.

[First operation period]
In the first operation period, the gate line voltage V _GL is 10 V, the auxiliary gate line voltage V _AGL is −5 V, the source line voltage V _SL is 0 V, the intermediate node voltage V _N2 is 0 V, and the pixel data voltage V _N1 at the start of the first operation period. Is 0V. Therefore, the transistor T1 is turned on and the transistor T2 is turned off.

In the first operation period, the boost voltage V _BST increases to 5V. At this time, the pixel data voltage V _N1 is 0V, and the output node voltage V _N3 is −5V. Therefore, the transistor T4 is turned on until the output node voltage V _N3 becomes −1V, which is a voltage obtained by subtracting the threshold voltage of the transistor T4 from the pixel data voltage V _N1 . Further, at this time, the auxiliary capacitance voltage V _CSL is 5V, and the intermediate node voltage V _N2 is 0V. Therefore, the transistor T3 is turned off.

Since the transistor T1 is conductive state as described above, the transistors T2, T3 are non-conductive state, the source line voltage _{V SL} is 0V, the intermediate node voltage _{V N2} becomes 0V equal to the source line voltage _{V SL.}

[Second operation period]
In the second operation period, the gate line voltage _{V GL} is reduced to -5V. At this time, since the source line voltage V _SL is 0 V and the intermediate node voltage V _N2 is 0 V, the transistor T1 is turned off, and the intermediate node voltage V _N2 is maintained at 0 V. Except for this point, there is no difference from the end of the first operation period.

[Third operation period]
In the third operation period, the auxiliary gate line voltage _VAGL increases to 10V. At this time, since the intermediate node voltage V _N2 is 0 V and the pixel data voltage V _N1 is (substantially) 0 V, the transistor T2 becomes conductive, and the pixel data voltage V _N1 approaches the intermediate node voltage V _N2 .

As described above, by performing the self-refresh operation, the pixel data voltage V _N1 can be brought close to the source line voltage V _SL applied to the pixel electrode 20 of the unit liquid crystal display element LC in the writing period before the self-refresh period. It becomes possible.

[Holding operation period]
In the holding operation period, both the gate line voltage V _GL and the auxiliary gate line voltage V _AGL are −5V. At this time, since the source line voltage V _SL is 0 V, the intermediate node voltage V _N2 is 0 V, and the pixel data voltage V _N1 is 0 V, both the transistors T1 and T2 are turned off. Further, the boost voltage V _BST decreases to −5V. At this time, since the output node voltage V _N3 is −1V and the pixel data voltage V _N1 is 0V, the transistor T4 becomes conductive, and the output node voltage V _N3 decreases to −5V.

・ When V _N1 is 5V [Before refresh period (write period)]
As described above, the boost voltage V _BST is −5 V during the writing period. Therefore, when the pixel data voltage V _N1 is 5V, the transistor T4 is turned on, and the output node voltage V _N3 is decreased to −5V. On the other hand, the intermediate node voltage V _N2 is 5 V, which is the same as the pixel data voltage V _N1 .

[First operation period]
In the first operation period, the gate line voltage V _GL is 10 V, the auxiliary gate line voltage V _AGL is −5 V, the source line voltage V _SL is 0 V, the intermediate node voltage V _N2 is 5 V, and the pixel data voltage V _N1 at the start of the first operation period. Becomes 5V. Therefore, the transistor T1 is turned on and the transistor T2 is turned off.

In the first operation period, the boost voltage V _BST increases to 5V. At this time, the pixel data voltage V _N1 is 5V, and the output node voltage V _N3 is −5V. Therefore, the transistor T4 is turned on until the output node voltage V _N3 becomes 4V, which is a voltage obtained by subtracting the threshold voltage of the transistor T4 from the pixel data voltage V _N1 . Further, at this time, the auxiliary capacitance voltage V _CSL is 5V, and the intermediate node voltage V _N2 is 0V. Therefore, the transistor T3 becomes conductive.

As described above, when the transistors T1 and T3 are in the conductive state, T2 is in the nonconductive state, and the source line voltage _VSL is 0 V, the intermediate node voltage _VN2 is increased according to the ratio of the on resistances of the transistors T1 and T3. It will be. At this time, since the voltage applied to the control terminal of the transistor T1 is sufficiently larger than the voltage applied to the control terminal of the transistor T3, the on-resistance of the transistor T1 is sufficiently smaller than the on-resistance of the transistor T3. Therefore, the intermediate node voltage V _N2 approaches the source line voltage V _SL and becomes approximately 0V.

[Second operation period]
In the second operation period, the gate line voltage _{V GL} is reduced to -5V. At this time, since the source line voltage V _SL is 0 V and the intermediate node voltage V _N2 is 0 V, the transistor T1 is turned off. Further, at this time, since the boost voltage V _BST is 5 V and the output node voltage V _N3 is 4 V, the transistor T3 is in a conductive state. Therefore, the intermediate node voltage V _N2 increases from 0V.

When the intermediate node voltage V _N2 increases, the output node voltage V _N3 rises through the parasitic capacitance between the control terminal and the second terminal of the transistor T3 and the electric capacitance such as the boost capacitance element Cbst. Then, since a larger voltage is applied from boost line BST to intermediate node N2 via transistor T3, intermediate node voltage V _N2 further increases and output node voltage V _N3 further increases. That is, the transistor T3 and the electric capacity operate as a bootstrap circuit.

As a result of the above operation, when the output node voltage V _N3 becomes 6 V or more, which is a voltage obtained by adding the threshold voltage of the transistor T3 to the boost voltage V _BST , the intermediate node voltage V _N2 becomes 5 V equal to the boost voltage V _BST. .

[Third operation period]
In the third operation period, the auxiliary gate line voltage _VAGL increases to 10V. At this time, since the intermediate node voltage V _N2 is 5 V and the pixel data voltage V _N1 is (substantially) 5 V, the transistor T2 becomes conductive, and the pixel data voltage V _N1 approaches the intermediate node voltage V _N2 .

[Holding operation period]
In the holding operation period, both the gate line voltage V _GL and the auxiliary gate line voltage V _AGL are −5V. At this time, since the source line voltage V _SL is 0 V, the intermediate node voltage V _N2 is 5 V, and the pixel data voltage V _N1 is 5 V, both the transistors T1 and T2 are turned off. Further, the boost voltage V _BST decreases to −5V. At this time, since the output node voltage V _N3 is 6V (or higher) and the pixel data voltage V _N1 is 5V, the transistor T4 becomes conductive, and the output node voltage V _N3 decreases to −5V.

For the sake of specific description, the self-refresh operation and the holding operation have been described using specific voltage values. However, operations other than the specific voltage values described above can be similarly performed. However, it is preferable to select a voltage value that satisfies at least the following conditions in order to perform a satisfactory operation.

When the source line voltage V _SL (corresponding to the reference voltage) during the self-refresh period is equal to or lower than the minimum voltage that the pixel data voltage V _N1 can take, the pixel data voltage V _N1 is preferably compensated for, and the This is preferable because the operation can be executed with high accuracy. The auxiliary capacitance voltage V _{CSL (corresponding} to the compensation voltage), if equal to the maximum voltage which can be taken of the pixel data voltage V _N1, it is possible to suitably compensate the pixel data voltage V _N1, preferred.

Further, the source line voltage V _SL during the self-refresh period, when the auxiliary capacitance voltage V _CSL transistor T3, is smaller than the voltage that together by subtracting the threshold voltage of T4, the transistor T3 becomes conductive state in the second operation period This is preferable because the intermediate node voltage V _N2 can be made substantially equal to the auxiliary capacitance voltage V _CSL .

Further, if the boost voltage V _BST (corresponding to the first boost voltage) in the first to third operation periods is equal to or higher than the voltage obtained by adding the threshold voltage of the transistor T3 to the source line voltage V _SL during the self-refresh period, The node voltage V _N3 is preferable because it can take a voltage that makes the transistor T3 conductive.

Further, when the boost voltage V _BST (corresponding to the second boost voltage) in the holding operation period is less than the voltage obtained by subtracting the threshold voltage of the transistor T3 from the minimum voltage that the pixel data voltage V _N1 can take, the output node voltage V _N3 Can take a voltage that makes the transistor T3 non-conductive. The same applies to the boost voltage V _BST (corresponding to the third boost voltage) in the writing period.

By the way, when the pixel data voltage V _N1 is equal to or higher than a predetermined voltage (corresponding to a predetermined voltage) obtained by adding the threshold voltages of the transistors T3 and T4 to the source line voltage V _SL during the self-refresh period, the transistor in the first operation period. Since T3 becomes conductive, the intermediate node voltage V _N2 increases, and the output node voltage V _N3 is pushed up via the electric capacity. Therefore, the boost voltage V _BST can be applied to the intermediate node N2 without excess or deficiency. On the other hand, if the pixel data voltage V _N1 is less than the predetermined voltage, the transistor T3 is turned off in the first operation period, so that the boost voltage V _BST is not applied to the intermediate node N2, and the intermediate node voltage V _N2 becomes large equal to the source line voltage V _SL during the self-refresh period is. The threshold voltage of the transistor T3, T4 is the case sufficiently large for a range of voltages that can be taken of the pixel data voltage V _N1, than the minimum voltage of the source line voltage V _SL of the pixel data voltage V _N1 during the self-refresh period By reducing the size, these two operations can be executed with high accuracy.

<< Second Embodiment >>
Next, a liquid crystal display device according to a second embodiment of the present invention will be described below with reference to the drawings. The liquid crystal display device of the present embodiment is mostly in common with the liquid crystal display device 1a of the first embodiment described above. Therefore, in the following, the liquid crystal display device according to the present embodiment will be described with a focus on the portions that are not common to the liquid crystal display device 1a of the first embodiment, and the common portions will be described for the liquid crystal display device 1a according to the first embodiment. The detailed description will be omitted as appropriate. In addition, in the liquid crystal display device according to the present embodiment, portions common to the liquid crystal display device 1a according to the first embodiment are denoted by the same reference numerals and illustrated and described.

FIG. 7 is a block diagram showing an example of a schematic configuration of the liquid crystal display device according to the second embodiment of the present invention. As shown in FIG. 7, the liquid crystal display device 1b of the present embodiment is the same as the liquid crystal display device 1a of the first embodiment, except that a reference voltage supply line REF is provided.

The reference voltage supply line REF includes branch wirings that branch into n lines and extend in the horizontal direction (row direction) in order to be connected to each pixel circuit 2. Similarly to the gate line GL and the auxiliary gate line AGL, the pixel circuit 2 is connected to each of the n branch lines of the reference voltage supply line REF for each row. Note that the display control circuit 11b applies the reference voltage _VREF to the reference voltage supply line REF.

In the liquid crystal display device 1b of the present embodiment, unlike the liquid crystal display device 1a of the first embodiment, the auxiliary capacitance line CSL corresponds to the “second control line” and the reference voltage supply line REF becomes the “voltage supply line”. Correspond. A part of the display control circuit 11b corresponds to a “voltage supply line driving circuit”, and a part of the common electrode driving circuit 12 corresponds to a “second control line driving circuit”. Further, the reference voltage V _REF corresponds to the “compensation voltage”.

FIG. 8 is a circuit diagram showing a basic circuit configuration of a pixel circuit included in the liquid crystal display device according to the second embodiment of the present invention. FIG. 9 is a circuit diagram showing a circuit configuration example of the pixel circuit included in the liquid crystal display device according to the second embodiment of the present invention. As shown in FIGS. 8 and 9, in the liquid crystal display device 1b of the present embodiment, only the other end of the auxiliary capacitive element Cs is connected to the auxiliary capacitive line CSL. Then, as shown in FIG. 8, one end of the second switch circuit 23 is connected to the reference voltage supply line REF. As shown in FIG. 9, the first terminal of the transistor T3 is connected to the reference voltage supply line REF.

That is, the liquid crystal display device 1b of the present embodiment uses the auxiliary capacitance line CSL (see FIGS. 1, 3 and 4) of the liquid crystal display device 1a of the first embodiment as the reference voltage supply line REF and the auxiliary capacitance line CSL. It can be said that it was realized with two.

FIG. 10 is a timing chart showing an operation in the constant display mode of the liquid crystal display device according to the second embodiment of the present invention. As shown in FIG. 10, in the liquid crystal display device 1b of the present embodiment, the reference voltage _VREF is constant at a predetermined voltage value (hereinafter, 5V is taken as an example). On the other hand, the auxiliary capacitance voltage V _CSL is equal to the common voltage V _COM . FIG. 11 is a timing chart showing the operation during the self-refresh period of the liquid crystal display device according to the second embodiment of the present invention. The operation of the liquid crystal display device 1b of the present embodiment is the same as that of the first embodiment except that the auxiliary capacitance voltage V _CSL (see FIGS. 5 and 6) in the liquid crystal display device 1a of the first embodiment is replaced with the reference voltage V _REF. The operation is the same as that of the liquid crystal display device 1a. 5 and 6 showing the operation of the display device 1a of the first embodiment, FIG. 10 and FIG. 11 showing the operation of the display device 1b of the present embodiment are also relative to each other for convenience of illustration. The length of time (the horizontal length in the figure) is not necessarily correct.

As in the liquid crystal display device 1a of the first embodiment, the display screen can be brightened by reducing the number of wirings on the active matrix substrate 10 collectively. On the other hand, when the plurality of types of wirings are provided as they are, as in the liquid crystal display device 1b of the present embodiment, the voltage supplied to each part of the pixel circuit 2 can be made more suitable. . As a result, a more stable image can be displayed.

<< Third Embodiment >>
Next, a liquid crystal display device according to a third embodiment of the present invention will be described below with reference to the drawings. The liquid crystal display device of the present embodiment is mostly in common with the liquid crystal display device 1a of the first embodiment described above. Therefore, in the following, the liquid crystal display device according to the present embodiment will be described with a focus on the portions that are not common to the liquid crystal display device 1a of the first embodiment, and the common portions will be described for the liquid crystal display device 1a according to the first embodiment. The detailed description will be omitted as appropriate. In addition, in the liquid crystal display device according to the present embodiment, portions that are common to the liquid crystal display device according to the first embodiment are denoted by the same reference numerals and illustrated and described.

FIG. 12 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to the third embodiment of the present invention. As shown in FIG. 12, the liquid crystal display device 1c of the present embodiment is arranged between the rows of the pixel circuits 2 arranged in adjacent rows and is connected to each of the pixel circuits 2 in the two rows. Is the same as the liquid crystal display device 1a of the first embodiment except that at least one of the above is provided.

In FIG. 12, the active matrix substrate 10 is provided with the pixel circuits 2 in even rows (n is an even number), and the gate lines GL (2k−) are arranged between the pixel circuits 2 arranged in the 2k−1 and 2k rows. 1_2k) is illustrated (k is a natural number between 1 and n / 2).

The configuration of the pixel circuit 2 is the same as that of the liquid crystal display device 1a of the first embodiment. That is, the gate line GL of the liquid crystal display device 1c of this embodiment is also connected to the transistor T1 of the pixel circuit 2 (see FIGS. 3 and 4). The operation of the liquid crystal display device 1c of the present embodiment is also the same as that of the liquid crystal display device 1a of the first embodiment (see FIGS. 5 and 6). However, the gate driver 14c included in the liquid crystal display device 1c according to the present embodiment has a timing at which the transistor T1 of the pixel circuit 2 arranged in the 2k-1 row is to be turned on and the pixel circuit arranged in the 2k row. The gate line voltage V _GL having a voltage value (for example, 10 V) that makes the transistor T1 conductive is applied at both the timing when the second transistor T1 should be conductive.

As described above, in the liquid crystal display device 1c of the present embodiment, the gate lines GL that are wiring on the active matrix substrate 10 can be reduced collectively. Therefore, the display screen can be brightened.

In the liquid crystal display device 1c of the present embodiment, the configuration example in which the gate lines GL are collectively reduced has been described. However, instead of (or in addition to) this, the auxiliary gate lines AGL may be reduced in number. . However, it is preferable to reduce only one of the gate line GL and the auxiliary gate line AGL so that the pixel circuit 2 can be controlled for each row.

Further, n branch lines (see FIGS. 1 and 7) of the auxiliary capacitance line CSL and the boost voltage supply line BST in the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment, and the second As for the n branch wirings (see FIG. 7) of the reference voltage supply line REF in the liquid crystal display device 1b of the embodiment, at least one line is reduced as in the case of the gate lines GL of the liquid crystal display device 1c of the present embodiment. Is possible.

In addition, in the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment, wirings extending in the horizontal direction (row direction) (n lines of gate lines GL, auxiliary gate lines AGL, and auxiliary capacitance lines CSL). At least one of the above-described branch wirings, n branch wirings of the boost voltage supply line BST, and n branch wirings of the reference voltage supply line REF) may be reduced as described above. .

<< Fourth Embodiment >>
Next, a liquid crystal display device according to a fourth embodiment of the present invention will be described with reference to the drawings. The liquid crystal display device of the present embodiment is mostly in common with the liquid crystal display device 1a of the first embodiment described above. Therefore, in the following, the liquid crystal display device according to the present embodiment will be described with a focus on the portions that are not common to the liquid crystal display device 1a of the first embodiment, and the common portions will be described for the liquid crystal display device 1a according to the first embodiment. The detailed description will be omitted as appropriate. In addition, in the liquid crystal display device according to the present embodiment, portions that are common to the liquid crystal display device according to the first embodiment are denoted by the same reference numerals and illustrated and described.

FIG. 13 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to the fourth embodiment of the present invention. As shown in FIG. 13, the liquid crystal display device 1d of the present embodiment is arranged between the rows of the pixel circuits 2 arranged in adjacent rows and is connected to each of the pixel circuits 2 in the two rows. And at least one of the branch lines of the boost voltage supply line BST is arranged between the rows of the pixel circuits 2 arranged in adjacent rows and is connected to each of the pixel circuits 2 in the two rows. Except for this point, it is the same as the liquid crystal display device 1a of the first embodiment. The gate line GL is the same as that of the liquid crystal display device 1c of the third embodiment (see FIG. 12).

In FIG. 13, the active matrix substrate 10 is provided with pixel circuits 2 in a row that is a multiple of 4 (n is a multiple of 4), and gates are arranged between the pixel circuits 2 arranged in the 2k−1 and 2k rows. An example in which the line GL (2k-1_2k) is arranged and the branch wiring of the boost voltage supply line BST is arranged between the pixel circuits 2 arranged in the 4t-2 row and the 4t-1 row (T is a natural number between 1 and n / 4).

The configuration of the pixel circuit 2 is the same as that of the liquid crystal display device 1a of the first embodiment. That is, the gate line GL of the liquid crystal display device 1d of this embodiment is also connected to the transistor T1 of the pixel circuit 2, and the boost voltage supply line BST of the liquid crystal display device 1d of this embodiment is also connected to the transistor T4 (FIG. 3 and FIG. 4). The operation of the liquid crystal display device 1d of the present embodiment is also the same as that of the liquid crystal display device 1a of the first embodiment (see FIGS. 5 and 6). However, the gate driver 14d provided in the liquid crystal display device 1d according to the present embodiment has a timing at which the transistor T1 of the pixel circuit 2 arranged in the 2k-1 row is to be turned on and the pixel circuit arranged in the 2k row. The gate line voltage V _GL having a voltage value (for example, 10 V) that makes the transistor T1 conductive is applied at both the timing when the second transistor T1 should be conductive.

As described above, in the liquid crystal display device 1d of the present embodiment, the number of branch lines of the gate lines GL and the boost voltage supply lines BST that are lines on the active matrix substrate 10 can be reduced. Therefore, the display screen can be brightened.

Further, by making the space between the rows of the pixel circuit 2 in which the gate line GL and the branch wiring of the boost voltage supply line BST are arranged as shown in the example shown in FIG. 13, the wiring can be simplified and made uniform. it can.

In the liquid crystal display device 1d of the present embodiment, the configuration example in which the branch lines of the gate line GL and the boost voltage supply line BST are collectively reduced has been described. However, instead of (or in addition to) the gate line GL, the auxiliary gate A configuration may be adopted in which the number of lines AGL is reduced. However, it is preferable to reduce only one of the gate line GL and the auxiliary gate line AGL so that the pixel circuit 2 can be controlled for each row.

In addition, n branch lines (see FIGS. 1 and 7) of the auxiliary capacitance line CSL in the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment, and the liquid crystal display device of the second embodiment. As for the n branch wirings (see FIG. 7) of the reference voltage supply line REF in 1b as well as the 3n / 4 branch wirings of the boost voltage supply line BST of the liquid crystal display device 1d according to the present embodiment, the number is reduced. Is possible.

In addition, in the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment, wirings extending in the horizontal direction (row direction) (n lines of gate lines GL, auxiliary gate lines AGL, and auxiliary capacitance lines CSL). At least one of the plurality of branch wirings, n branch wirings of the boost voltage supply line BST, and n branch wirings of the reference voltage supply line REF as described above. good. In this case, it is preferable to change the line spacing of the pixel circuits 2 in which the collected wirings are arranged because the wirings can be simplified and uniformized.

<< Fifth Embodiment >>
Next, a liquid crystal display device according to a fifth embodiment of the present invention is described below with reference to the drawings. The liquid crystal display device of the present embodiment is mostly in common with the liquid crystal display device 1a of the first embodiment described above. Therefore, in the following, the liquid crystal display device according to the present embodiment will be described with a focus on the portions that are not common to the liquid crystal display device 1a of the first embodiment, and the common portions will be described for the liquid crystal display device 1a according to the first embodiment. The detailed description will be omitted as appropriate. In addition, in the liquid crystal display device according to the present embodiment, portions that are common to the liquid crystal display device according to the first embodiment are denoted by the same reference numerals and illustrated and described.

FIG. 14 is a block diagram showing an example of a schematic configuration of a liquid crystal display device according to the fifth embodiment of the present invention. As shown in FIG. 14, the liquid crystal display device 1e of the present embodiment has a boost voltage supply line BST (o) connected to the pixel circuit 2 in which branch lines extending in the horizontal direction (row direction) are arranged in odd rows. And a boost voltage supply line BST (o), BST connected to the pixel circuit 2 in which branch lines extending in the horizontal direction (row direction) are arranged in even rows. Except that (e) is separately connected to the display control circuit 11e, it is the same as the liquid crystal display device 1a of the first embodiment.

In FIG. 14, the active matrix substrate 10 is provided with the pixel circuits 2 in even rows (n is an even number), and n / 2 branch wirings extending in the lateral direction (row direction) of the boost voltage supply line BST (o). When connected to the pixel circuits 2 arranged in the 2k-1 rows, and n / 2 branch lines of the boost voltage supply line BST (e) are respectively connected to the pixel circuits 2 arranged in the 2k rows Is illustrated.

As described above, in the liquid crystal display device 1e of this embodiment, the display control circuit 11e can apply a voltage independently to the boost voltage supply lines BST (o) and BST (e). Therefore, for example, the self-refresh operation can be independently performed in the pixel circuits 2 arranged in the even rows and the pixel circuits 2 arranged in the odd rows.

Note that the liquid crystal display device 1e of the present embodiment is described as including two boost voltage supply lines BST (o) and BST (e) and connecting each branch wiring to the pixel circuit 2 by skipping one row. However, u boost voltage supply lines may be provided, and each branch wiring may be connected to the pixel circuit 2 by skipping (u−1) rows (u is a natural number of 2 or more and less than n). Further, a part or all of the branch wiring included in at least one boost voltage supply line may be connected to each pixel circuit arranged in an adjacent row.

In addition, the wiring (auxiliary capacitance line CSL, boost voltage supply line) having n branch wirings extending in the horizontal direction (row direction) of the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment. Any one type or a plurality of types of BST and reference voltage supply line REF) may be divided into two or more and less than n wirings, and a voltage may be applied to each of them independently.

<< Sixth Embodiment >>
Next, a liquid crystal display device according to a sixth embodiment of the present invention is described below with reference to the drawings. The liquid crystal display device of the present embodiment is mostly in common with the liquid crystal display device 1a of the first embodiment described above. Therefore, in the following, the liquid crystal display device according to the present embodiment will be described with a focus on the portions that are not common to the liquid crystal display device 1a of the first embodiment, and the common portions will be described for the liquid crystal display device 1a according to the first embodiment. The detailed description will be omitted as appropriate. In addition, in the liquid crystal display device according to the present embodiment, portions that are common to the liquid crystal display device according to the first embodiment are denoted by the same reference numerals and illustrated and described.

FIG. 15 is a block diagram showing an example of a schematic configuration of the liquid crystal display device according to the sixth embodiment of the present invention. As shown in FIG. 15, the liquid crystal display device 1f of this embodiment includes n boost voltage supply lines extending in the horizontal direction (row direction) (BST (1), BST (2),. .., BST (n)), and is the same as the liquid crystal display device 1a of the first embodiment, except that each boost voltage supply line BST is separately connected to the gate driver 14f. In the liquid crystal display device 1f of the present embodiment, a part of the gate driver 14f corresponds to the “first control line driving circuit”. In the following, for convenience, each boost voltage supply line BST (1), BST (2),..., BST (n) is generalized and referred to as a boost voltage supply line BST.

As described above, in the liquid crystal display device 1f of the present embodiment, the gate driver 14f can apply a voltage independently to the boost voltage supply lines BST (1) to BST (n). Therefore, for example, an operation such as a self-refresh operation can be performed for each pixel circuit 2 arranged in each row.

Note that the wiring (auxiliary capacitance line CSL, boost voltage supply line) having n branch wirings extending in the horizontal direction (row direction) of the liquid crystal display device 1a of the first embodiment and the liquid crystal display device 1b of the second embodiment. Any one type or a plurality of types (BST, reference voltage supply line REF) may be divided into n wirings, and a voltage may be applied to each of them independently.

<< Modification >>
Various modifications of the liquid crystal display devices 1a to 1f of the first to sixth embodiments described above will be described below.

<1> When the boost voltage V _BST is decreased in order to suppress the leakage current of the transistor T3 in the holding operation period in a small period included in the self-refresh period, the parasitic capacitance between the control terminal and the second terminal of the transistor T3 The intermediate node voltage V _N2 falls through the electric capacitance such as the boost capacitance element Cbst (see FIGS. 3 to 6). At this time, there is a concern that the difference between the intermediate node voltage V _N2 and the pixel data voltage V _N1 becomes large, a leakage current of the transistor T2 occurs, and the pixel data voltage V _N1 becomes unstable.

Therefore, in the modification <1>, the “protection operation” is performed (providing the protection operation period) after the self-refresh operation (after the first to third operation periods) and before the holding operation (before the holding operation period). This protection operation will be described with reference to the drawings while exemplifying the case where the present modification is applied to the liquid crystal display device 1a of the first embodiment.

FIG. 16 is a timing chart showing the operation in the self-refresh period when the modification <1> is applied to the liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 16, in the protection operation period, the gate line voltage V _GL is a voltage that makes the transistor T1 conductive (for example, 10V), and the auxiliary gate line voltage V _AGL is a voltage that makes the transistor T2 non-conductive (for example, -5V), and the source line voltage _VSL is not less than the minimum voltage and not more than the maximum voltage that the pixel data voltage _VN1 can take (for example, not less than 0V and not more than 5V, for example, an intermediate voltage between the minimum voltage and the maximum voltage) 2.5V (corresponding to the protection voltage)), the boost voltage V _BST becomes a voltage equal to the holding operation period (for example, −5V).

In this protection operation, the boost voltage V _BST decreases to a voltage equal to the holding operation period (that is, the intermediate node voltage V _N2 tends to be pushed down). However, this time the transistor T1 is conductive, not lowered thrust intermediate node voltage V _N2, becomes equal to the source line voltage V _SL. Therefore, by performing this protection operation before the above-described holding operation, the intermediate node voltage V _N2 during the holding operation can be brought close to the pixel data voltage V _N1 . Therefore, the pixel data voltage V _N1 during the holding operation can be stabilized.

Note that if the source line voltage V _SL during the protection operation is an intermediate voltage between the minimum voltage and the maximum voltage that the pixel data voltage V _N1 can take, it depends on whether the pixel data voltage V _N1 is the minimum voltage or the maximum voltage. Therefore, the difference between the pixel data voltage V _N1 and the intermediate node voltage V _N2 during the holding operation can be preferably suppressed, which is preferable.

Further, in FIG. 16, the case where the present modification is applied to the liquid crystal display device 1 a according to the first embodiment has been specifically illustrated and described, but this modification is only for the liquid crystal display device 1 a according to the first embodiment. The present invention is not limited to this, and the present invention can be similarly applied to the liquid crystal display devices 1b to 1f according to the second to sixth embodiments.

<2> In the liquid crystal display devices 1a to 1f (see FIGS. 1, 7, and 12 to 15) of the above-described embodiments, the voltage supplied to the auxiliary capacitance line CSL is controlled collectively. Although illustrated, a configuration that can be controlled for each predetermined row (for example, for each row) (for example, a driver that individually applies a voltage to the auxiliary capacitance line CSL divided for each row) The pixel data voltage V _N1 may be pushed up via the auxiliary capacitor Cs for each row.

<3> The liquid crystal display devices 1a to 1f of the above-described embodiments are configured to include the self-refresh circuit 2B for all the pixel circuits 2 configured on the active matrix substrate 10. On the other hand, when the active matrix substrate 10 is configured to include two types of pixel circuits, a transmissive pixel circuit that performs transmissive liquid crystal display and a reflective pixel circuit that performs reflective liquid crystal display, only the pixel circuit of the reflective pixel circuit is provided. The self-refresh circuit 2B may be provided, and the pixel circuit in the transmissive display unit may not include the self-refresh circuit 2B. In this case, an image is displayed by the transmissive pixel circuit in the normal display mode, and an image is displayed by the reflective pixel circuit in the constant display mode. With this configuration, the number of elements formed on the entire active matrix substrate 10 can be reduced.

<4> In the liquid crystal display devices 1a to 1f of the above-described embodiments, each pixel circuit 2 includes the auxiliary capacitance element Cs. However, the pixel circuit 2 may be configured not to include the auxiliary capacitance element Cs. In this case, a wiring for applying a voltage to the auxiliary capacitance element Cs is not necessary, but a wiring for applying a voltage to the first terminal of the transistor T3 is necessary. When this modification <3> is applied, the pixel circuit 2 included in the liquid crystal display device 1a of the first embodiment and the pixel circuit 2 included in the display device 1b of the second embodiment have the same circuit configuration. .

<5> In the liquid crystal display devices 1a to 1f of the above-described embodiments, the display element unit 21 of each pixel circuit 2 includes only the unit liquid crystal display element LC. However, the internal node N1 and the unit liquid crystal display element LC An analog amplifier may be provided between the pixel electrode 20 and the pixel electrode 20. In this case, the voltage applied to the internal node N1 is amplified by the amplification factor set by the analog amplifier, and the amplified voltage is applied to the pixel electrode 20 of the unit liquid crystal display element LC.

<6> In the liquid crystal display devices 1a to 1f of the above-described embodiments, the transistors T1 to T4 in each pixel circuit 2 have been described as N-channel type polycrystalline silicon TFTs, but P-channel type TFTs were used. A configuration or a configuration using an amorphous silicon TFT is also possible. Even in a liquid crystal display device having a configuration using a P-channel TFT, it is the same as the liquid crystal display devices 1a to 1f of the above-described embodiments by taking measures such as reversing the sign of the voltage value indicated as the operating condition. It is possible to operate the pixel circuit 2 at the same time, and the same effect can be obtained.

<7> In each of the above-described embodiments, the liquid crystal display devices 1a to 1f have been described as examples. However, the present invention is not limited to this. The present invention can be applied to devices other than the liquid crystal display device as long as the display device can hold the pixel data voltage and display an image based on the pixel data voltage.

<8> In the liquid crystal display devices 1a to 1f of the above-described embodiments, the voltage values that the pixel data voltage V _N1 and the common voltage V _COM can take in the constant display mode are 0 V and 5 V, and the voltages applied to various wirings Are -5V, 0V, 5V, and 10V, but these voltage values can be appropriately changed according to the characteristics (threshold voltage, etc.) of the unit liquid crystal display element and the transistor used.

DESCRIPTION OF SYMBOLS 1a-1f: Liquid crystal display device 2: Pixel circuit 2A: Main circuit 2B: Self-refresh circuit 10: Active matrix board |

substrate

11, 11b, 11e, 11f: Display control circuit 12: Electrode drive circuit 13:

Source driver

14, 14c, 14d , 14f: Gate driver 20: Pixel electrode 21: Display element 22: First switch circuit 23: Second switch circuit 24: Control circuit 30: Electrode 31: Substrate 32: Sealing material 33: Liquid crystal layer GL: Auxiliary gate line AGL : Auxiliary gate line SL: Source line BST: Boost voltage supply line REF: Reference voltage supply line CML: Common electrode wiring CSL: Auxiliary capacitance line LC: Unit liquid crystal display element N1: Internal node N2: Intermediate node N3: Output node T1 ~ T4: Transistor Cs: Complement Capacity element Cbst: boost capacity element

Claims

A display element unit including a unit display element;
An internal node that forms part of the display element unit and holds a pixel data voltage applied to the display element unit;
The pixel having a series circuit of first and second transistor elements, connected to one end of a data signal line, connected to the other end of the internal node, and supplied from the data signal line via the series circuit A first switch circuit for transferring a data voltage to the internal node;
One end of a voltage supply line for supplying a compensation voltage is connected to the third transistor element, and the other end is connected to an intermediate node that is a connection point where the first and second transistor elements in the series circuit are connected in series. A second switch circuit that
A control circuit that includes a fourth transistor element, and controls a conduction state of the third transistor element based on the pixel data voltage held by the internal node.
Each of the first to fourth transistor elements includes a first terminal, a second terminal, and a control terminal for controlling conduction between the first and second terminals,
A control terminal of the first transistor element is connected to a first scanning signal line that turns on the first transistor element during an operation of transferring the pixel data voltage to the internal node;
A control terminal of the second transistor element is connected to a second scanning signal line that turns on the second transistor element during an operation of transferring the pixel data voltage to the internal node;
A control terminal of the third transistor element and a first terminal of the fourth transistor element are connected to form an output node of the control circuit;
A control terminal of the fourth transistor element is connected to the internal node, and a second terminal of the fourth transistor element is connected to a first control line for supplying a boost voltage;
A pixel circuit having a capacitance between the output node and the intermediate node for controlling a voltage held by the output node with a voltage held by the intermediate node.
A self-refresh operation capable of compensating the pixel data voltage held by the internal node using the compensation voltage;
The self-refresh operation
When the pixel data voltage held by the internal node is equal to or higher than a predetermined voltage, the output node holds a voltage that makes the third transistor element conductive, whereby the second transistor element and the third transistor element Applying the compensation voltage to the internal node via
When the pixel data voltage held by the internal node is less than the predetermined voltage, the output node holds a voltage that makes the third transistor element non-conductive, thereby applying the compensation voltage to the internal node. The pixel circuit according to claim 1, wherein the pixel circuit is not.
As the self-refresh operation,
A first boost voltage is applied to the first control line, a voltage for turning on the first transistor element is applied to the first scanning signal line, and the second transistor is applied to the second scanning signal line. The intermediate node holds the reference voltage and the output node is applied by performing a first operation in which a voltage that makes the element non-conductive is applied and a reference voltage is applied to the data signal line. Holds a voltage corresponding to the pixel data voltage held by the internal node,
When the pixel data voltage held by the internal node is equal to or higher than the predetermined voltage, the first node holds a voltage that makes the third transistor element conductive by the first operation;
When the pixel data voltage held by the internal node is lower than the predetermined voltage, the output node holds a voltage that makes the third transistor element non-conductive by the first operation. The pixel circuit according to claim 2.
As the self-refresh operation,
After the first operation,
A second operation is performed in which a voltage that makes the first transistor element non-conductive is applied to the first scanning signal line;
When the pixel data voltage held by the internal node is equal to or higher than the predetermined voltage, the second node causes the output node to be equal to or higher than a voltage obtained by adding the threshold voltage of the third transistor element to the compensation voltage. By holding the voltage, the third transistor element is made conductive, the intermediate node holds the compensation voltage,
When the pixel data voltage held by the internal node is lower than the predetermined voltage, the second node holds the voltage at which the third transistor element is turned off by the second operation. The intermediate node holds the reference voltage;
After the second operation,
4. The pixel circuit according to claim 3, wherein a third operation is performed in which a voltage that makes the second transistor element conductive is applied to the second scanning signal line. 5.
5. The pixel circuit according to claim 4, wherein the compensation voltage is equal to a maximum voltage of the pixel data voltage held by the internal node.
6. The pixel circuit according to claim 4, wherein the reference voltage is equal to or lower than a minimum voltage of the pixel data voltage held by the internal node.
7. The pixel circuit according to claim 3, wherein the first boost voltage is equal to or higher than a voltage obtained by adding a threshold voltage of the third transistor element to the reference voltage.
The predetermined voltage is a voltage obtained by adding a threshold voltage of the third transistor element and a threshold voltage of the fourth transistor element to the reference voltage. Pixel circuit.
The self-refresh operation is performed at least once, and after the self-refresh operation,
A voltage for turning off the first transistor element is applied to the first scanning signal line, and a voltage for turning off the second transistor element is applied to the second scanning signal line, A holding operation is performed in which a second boost voltage that is less than a voltage obtained by subtracting a threshold voltage of the third transistor element from a minimum voltage of the pixel data voltage held by the internal node is applied to one control line. The pixel circuit according to any one of claims 3 to 8.
After the self refresh operation and before the start of the holding operation,
A voltage that turns on the first transistor element is applied to the first scanning signal line, and a voltage that turns off the second transistor element is applied to the second scanning signal line. A protection operation is performed in which the second boost voltage is applied to the control line, and a protection voltage that is higher than the minimum voltage and lower than the maximum voltage of the pixel data voltage held by the internal node is applied to the data signal line. The pixel circuit according to claim 9.
The pixel circuit according to claim 10, wherein the protection voltage is an intermediate voltage between a minimum voltage and a maximum voltage of the pixel data voltage held by the internal node.
Before the self-refresh period in which at least one self-refresh operation is performed,
The third boost voltage that is less than a voltage obtained by subtracting a threshold voltage of the third transistor element from a minimum voltage of the pixel data voltage held by the internal node is applied to the first control line. Item 12. The pixel circuit according to any one of Items 2 to 11.
The first switch circuit comprises a series circuit of the first and second transistor elements;
The first terminal of the first transistor element is the data signal line, the second terminal of the first transistor element, the first terminal of the second transistor element is the intermediate node, and the second terminal of the second transistor element. The pixel circuit according to any one of claims 1 to 12, wherein the pixel circuit is connected to the internal node.
The second switch circuit includes the third transistor element;
The first terminal of the third transistor element is connected to the voltage supply line, and the second terminal of the third transistor element is connected to the intermediate node, respectively. The pixel circuit according to the item.
15. The pixel circuit according to claim 1, wherein the electric capacitance includes a parasitic capacitance between a control terminal and a second terminal of the third transistor element.
The capacitance according to any one of claims 1 to 15, wherein the capacitance includes a capacitance of a first capacitive element having one end connected to the output node and the other end connected to the intermediate node. Pixel circuit.
A pixel circuit array is configured by arranging a plurality of pixel circuits according to any one of claims 1 to 16 respectively in a row direction and a column direction,
A data signal line driving circuit for applying a voltage to the data signal line;
A scanning signal line driving circuit for applying a voltage to the first scanning signal line and the second scanning signal line;
A voltage supply line driving circuit for applying a voltage to the voltage supply line;
And a first control line driving circuit for applying a voltage to the first control line.
The display device according to claim 17, wherein each of the pixel circuits includes a second capacitor element having one end connected to the internal node and the other end connected to the voltage supply line.
A second control line driving circuit for applying a voltage to the second control line;
18. The display device according to claim 17, wherein each of the pixel circuits includes a second capacitor element having one end connected to the internal node and the other end connected to the second control line.
At least one first scanning signal line that is arranged between rows of the pixel circuits arranged in adjacent rows and is commonly connected to a control terminal of the first transistor element provided in the pixel circuit. The display device according to any one of claims 17 to 19, further comprising:
At least one first control line that is arranged between rows of the pixel circuits arranged in adjacent rows and is commonly connected to a second terminal of the fourth transistor element provided in the pixel circuit. The display device according to any one of claims 17 to 20, further comprising:
The first control line connected in common to the second terminal of the fourth transistor element of each of the pixel circuits arranged in the same row is provided for each row;
The even-numbered drive line to which each of the first control lines provided for the even-numbered rows is connected, and the odd-numbered drive line to which each of the first control lines provided for the odd-numbered rows is connected. The display device according to any one of claims 17 to 20, wherein the display device is separately connected to the first control line driving circuit.
The first control line connected in common to the second terminal of the fourth transistor element of each of the pixel circuits arranged in the same row is provided for each row;
21. Each of the first control lines is separately connected to the first control line driving circuit integrated with the scanning signal line driving circuit. Display device.