WO2012112310A1 - Flexible light emitting semiconductor device having thin dielectric substrate - Google Patents
Flexible light emitting semiconductor device having thin dielectric substrate Download PDFInfo
- Publication number
- WO2012112310A1 WO2012112310A1 PCT/US2012/023572 US2012023572W WO2012112310A1 WO 2012112310 A1 WO2012112310 A1 WO 2012112310A1 US 2012023572 W US2012023572 W US 2012023572W WO 2012112310 A1 WO2012112310 A1 WO 2012112310A1
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- conductive
- layer
- article
- dielectric layer
- flexible
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/062—Means for thermal insulation, e.g. for protection of parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
Definitions
- This invention relates to flexible high power light emitting semiconductor devices.
- LES light emitting semi-conductors
- LEDs light emitting diodes
- LESD LES devices
- packages containing LESDs have several drawbacks.
- High power LESDs generate a substantial amount of heat that must be managed.
- Thermal management deals with problems arising from heat dissipation and thermal stresses, which is currently a key factor in limiting the performances of light-emitting diodes.
- LES devices are commonly prone to damage caused by buildup of heat generated from within the devices, as well as heat from sunlight in the case of outside lighting applications. Excessive heat buildup can cause deterioration of the materials used in the LES devices, such as encapsulants for the LESDs.
- encapsulants for the LESDs.
- LESDs are attached to flexible- circuit laminates, which may also include other electrical components, the heat dissipation problems are greatly increased.
- At least one aspect of the present invention provides a cost-effective thermal management solution for current and future high power LESD constructions through a flexible LESD construction having a thin dielectric substrate and adjacent conductive layers.
- the ability to dissipate large amounts of heat is needed for the operation of high power LES arrays.
- heat dissipation can be managed by positioning the LESDs of the flexible LES device near the conductive material by controlling the overall, i.e., bulk, thickness of the dielectric substrate.
- At least one aspect of the present invention provides an article comprising a flexible thermally dissipative dielectric layer having two major surfaces and a bulk thickness up to about 20 micrometers; a first conductive layer on a first major surface of the dielectric layer and a second conductive layer on a second major surface of the dielectric layer; the first conductive layer having a pattern comprising at least one conductive feature; and at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature.
- a flexible thermally dissipative dielectric layer having two major surfaces and a bulk thickness up to about 20 micrometers
- a first conductive layer on a first major surface of the dielectric layer and a second conductive layer on a second major surface of the dielectric layer
- the first conductive layer having a pattern comprising at least one conductive feature
- at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature at least one light emitting semiconductor device
- At least one aspect of the present invention provides an article comprising a flexible thermally dissipative dielectric layer having first and second major surfaces, a bulk thickness up to about 20 micrometers, and at lest one protrusion extending from the first major surface; a first conductive layer on the first major surface of the dielectric layer and a second conductive layer on the second major surface of the dielectric layer;
- the first conductive layer having a pattern comprising at least one conductive feature; and at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature; wherein the at least one protrusion is adjacent at least one LESD.
- LESD light emitting semiconductor device
- At least one aspect of the present invention provides a method of making a flexible light emitting semiconductor device comprising providing a thermally dissipative flexible dielectric substrate having a first major surface and a second major surface and a bulk thickness up to about 20 micrometers and further having a first conductive layer on the first major surface and a second conductive layer on the second major surface; creating at least one conductive feature in the first conductive layer; and
- “bulk thickness” means the thickness of the majority of the dielectric layer
- LES means light emitting semiconductor(s), including light emitting diodes and laser diodes,
- LESD means light emitting semiconductor devices, including light emitting diode device(s) and laser diode device(s).
- An LESD may be a bare LES die construction, a complete packaged LES construction, or an intermediate LES construction comprising more than the bare die, but less than all the components for a complete LES package, such that the terms LES and LESD may be used interchangeably and refer to one or all of the different LES constructions.
- the term “flexible LES device” or “flexible LESD” typically refers to the flexible article containing the bare die light emitting semiconductor, packaged LES construction, or intermediate LES construction.
- the flexible LES devices provide excellent heat dissipation, which is especially applicable for high power LESDs.
- the thin dielectric layer can facilitate distribution of heat in the X, Y, and Z
- the LESDs on the thin flexible dielectric substrate can be wired in series, in
- the flexible LES devices can be bent in simple or compound curves.
- the use of a flexible substrate in the flexible LESDs eliminates the cost associated with conventional submounts.
- the flexible LES devices can provide a robust, cost-effective thermal management solution to current and future high power LESD constructions.
- the above summary of the present invention is not intended to describe each disclosed embodiment or every implementation of the present invention.
- the Figures and detailed description that follow below more particularly exemplify illustrative embodiments.
- Fig. 1 depicts an embodiment of a flexible LESD of the present invention.
- Figs. 2A-2B depict a process for preparing a substrate of the present invention.
- Fig. 3 depicts an embodiment of a flexible LESD of the present invention.
- Fig. 4 depicts an embodiment of a flexible LESD of the present invention.
- Fig. 5 depicts an embodiment of a flexible LESD of the present invention.
- Fig. 6 depicts the results of thermal modeling for a flexible LES device of the present
- the terms “coat,” “coating,” “coated,” and the like are not limited to a particular type of application method such as spray coating, dip coating, flood coating, etc., and may refer to a material deposited by any method suitable for the material described, including deposition methods such vapor deposition methods, plating methods, coating methods, etc.
- directional terminology such as “top,” “bottom,” “front,” “back,” “above,” “below,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. In general similar reference numbers are used for similar features in the various embodiments. Unless indicated otherwise, these similar features may comprise the same materials, have the same attributes, and serve the same or similar functions. Additional or optional features described for one embodiment may also be additional or optional features for other embodiments, even if not explicitly stated, where appropriate.
- At least one embodiment of the present invention provides a flexible structure having two conductive layers and an intermediate flexible thermally dissipative dielectric layer for thermally isolating semiconducting devices mounted on the flexible structure, wherein the dielectric layer has a bulk thickness of less than about 20 microns, less than about 10 microns, or less than about 5 micrometers. In at least one embodiment the dielectric layer has a bulk thickness between about 2 and about 10 micrometer.
- the top conductive layer is patterned to include an electrical circuit and conductive features, including electrically isolated areas on which the LESDs may be mounted.
- the dielectric layer may be formed either by coating a thin layer of the dielectric material on a copper foil or by starting with a thick layer of dielectric material and reducing its thickness to the desired thickness, e.g., by chemical etching.
- the thin dielectric layer facilitates dissipating heat efficiently.
- At least one embodiment of the present invention provides a flexible LESD construction formed by adding conductive layers to a dielectric substrate.
- the conductive layers may comprise conductive material deposited thereon in any suitable manner, such as coating, vapor deposition, plating etc., but the conductive material is typically plated either using electro or electroless plating.
- the total copper thickness is less than 200 micrometers, preferably less than 100 micrometers, and most preferably less than 50 micrometers.
- the dielectric substrate may be clad on one or both sides with a conductive layer. If the conductive layer(s) are to be formed into circuits, they may be pre-patterned, or may be patterned during the process of making the flexible LES devices.
- the conductive layers may be any suitable material, but are typically copper. At least one conductive layer is typically patterned to form a circuit and conductive features, including isolated conductive features to which LESDs may be attached. LESDs are typically attached, directly, or indirectly, to the conductive features using a known die bonding method such as eutectic, solder (including solder bumps for flip chip mounting), adhesive, and fusion bonding.
- a thermally and electrically conducting layer is located on the second surface of the dielectric substrate and may be patterned into an electrical circuit using conventional flexible circuit manufacturing processes. At least one embodiment of the present invention is illustrated in Fig.
- Dielectric substrate 12 is preferably thin, having a preferred thickness of about 20 micrometers or less, more preferably 10 micrometers or less. In some embodiments, the thickness of dielectric substrate 12 is between about 2 and about 10 micrometers. In some embodiments, the thickness of dielectric substrate 12 is about 5 micrometers.
- LESD 24 is wire bonded to an electrically conductive circuit, for example using conductive bumps 20 (which may be Au, AuSn, AuGe, AuSi, or other suitable materials).
- Conductive layer 16 is preferably thermally conductive and optionally electrically conductive. In some embodiments, conductive layer 16 comprises an electrically conductive circuit. In some embodiments, a passivation or bonding layer 22 is located beneath LESD 24 to facilitate bonding LESD 24 to an underlying layer.
- Suitable dielectric substrates for the present invention include polyesters, polycarbonates, liquid crystal polymers, and polyimides. Polyimides are preferred. Suitable polyimides include those available under the trade names KAPTON, available from DuPont; APICAL, available from Kaneka Texas corporation; SKC Kolon PI, available from SKC Kolon PI Inc.; and UPILEX and UPISEL, available from Ube-Nitto Kasei Industries, Japan.
- polyimides available under the trade designations UPILEX S, UPILEX SN, and UPISEL VT, all available from Ube-Nitto Kasei Industries. These polyimides are made from monomers such as biphenyl tetracarboxylic dianhydride (BBDA) and phenyl diamine (PDA).
- BBDA biphenyl tetracarboxylic dianhydride
- PDA phenyl diamine
- the dielectric substrate may further comprise thermally conductive particles in a suitable amount.
- thermally conductive particles include, but are not limited to, alumina nitride, boron nitride, silicon carbide, and combinations thereof.
- the starting dielectric substrate may be thinned using any suitable method such as chemical etching, plasma etching, focused ion-beam etching, and laser ablation.
- Chemical etching may be preferred in some embodiments.
- Any suitable etchant may be used and may vary depending on the dielectric substrate material.
- Suitable etchants may include alkali metal salts, e.g. potassium hydroxide; alkali metal salts with one or both of solubilizers, e.g., amines, and alcohols, such as ethylene glycol.
- Suitable chemical etchants for some embodiments of the present invention include KOH/ ethanol amine/ ethylene glycol etchants such as those described in more detail in U.S. Patent Publication No.
- Suitable chemical etchants for some embodiments of the present invention include a KOH/glycine etchants such as those described in more detail in co-pending U.S. Provisional Patent Application No. 61/409791, incorporated herein by reference.
- the dielectric substrates may be treated with an alkaline KOH/ potassium permanganate (PPM) solution, e.g., a solution of about 0.7 to about 1.0 wt% KOH and about 3 wt% KMn0 4 .
- PPM alkaline KOH/ potassium permanganate
- UPISEL VT dielectric substrate clad on one side with a copper layer 54 (the structure being commercially available under the trade designation UPILEX N from Ube Industries, Japan).
- UPISEL VT is constructed of a core layer 50 comprising UPILEX S and thin outer layers 52a, 52b comprising a thermoplastic polyimide (TPPI).
- TPPI thermoplastic polyimide
- the UPISEL VT may be etched using any suitable chemistry, such as KOH/ ethanol amine/ ethylene glycol described in more detail on U.S. Patent Publication. No. 2007-0120089-A1.
- Suitable etchant chemistries are the KOH /glycine, and KOH/glycine/ethylene diamine chemistries described in more detail in co-pending U.S. Provisional Patent
- the KOH/ glycine etchant provides a slow, controlled etching.
- the etching rate can be increased by adding ethylene diamine to the etchant formulation.
- the controlled thinning of the dielectric substrate can be accomplished by using eximer laser, by plasma etching, or by other suitable methods.
- the dielectric substrate is formed by coating and curing polymeric material on a conductive layer.
- polymeric material for example, to form a polyimide layer on copper, polyamic acid resin can be coated on a copper foil to a desired thickness.
- an imidization process can be carried out to form a uniform polyimide layer.
- the dielectric layers may be initially clad on one or both sides with a conductive layer. If the conductive layer(s) are to be formed into circuits, they may be pre- patterned, or may be patterned during the process of making the flexible LES devices.
- a multilayer flexible substrate (having multiple layers of dielectric and conductive material) may also be used as a substrate.
- the conductive layers may be any suitable material, but are typically copper.
- a conductive layer is to be added to one or both sides of the dielectric layer after it is formed to the desired thickness, this can be done by lamination of a metal foil to the dielectric, but is more typically done by some type of metal deposition process.
- Conductive features and circuits can be formed as part of a metal deposition process.
- a standard semi-additive deposition method of forming a circuit would include providing a vapor deposited tie layer, typically of CrOx, NiCr, or NiCrOx, vapor depositing thereon a metal seed layer that typically, but not necessarily, comprises the same metal as the subsequently plated metal layer, patterning a photomask on the seed layer using a traditional photolithography process, plating a conductive material (any suitable material, but typically copper), on the exposed portions of the seed layer using either electro or electroless plating, stripping the photomask, and removing the remaining, now-exposed portion of the seed and tie layers.
- the individual LESDs may be bonded onto the conductive features using any suitable bonding mechanism. Different types of bonding can be employed such as eutectic, flip chip, fusion and adhesive bonding.
- the LESDs preferably have a passivation layer (typically gold/tin but may be any suitable passivation material, e.g., metals such as Au and intermetallic alloys(s) such as AuSn, AuGe, AuSi) applied to their bottom surfaces to facilitate bonding the LESDs to the gold passivated conductive features.
- the temperature used for attaching LESDs to the conductive features is typically between about 250°C and 325°C, most typically about 285°C for eutectic bonding (for Au/Sn).
- the LESDs may be adhered by other methods such as organic die attach, e.g., using silver epoxy, or soldering. Eutectic bonding is considered a direct bonding method while soldering is considered an indirect bonding method.
- At least some embodiments of the flexible LES devices of the present invention provide excellent heat management properties. Due at least in part to the thinness of the dielectric substrate, heat generated by the LESDs can be readily transmitted away from the LESD and to the conductive layer on the bottom side of the dielectric substrate. The heat can then disperse throughout the conductive layer in multiple directions (e.g., the downward Z direction and all X and Y directions), which can provide faster and more efficient heat dissipation away from the LESD. Additionally, according to at least one embodiment of the present invention, the amount of conductive material in the conductive layers can be controlled to further influence heat management. For example, increasing the amount of conductive material can increase the conductive layer's capacity for heat dissipation.
- Fig. 3 illustrates an embodiment of the present invention in which conductive layer 16 has been patterned to provide open section 26 extending to the dielectric layer 12 between conductive features 14 of conductive layer 17 on which LESDs 24 are bonded.
- This patterning helps to thermally isolate the adjacent conductive features and enhance thermal management of the LESDs. For example, if one LESD produces more heat than a neighboring LESD, heat could travel through thermally conductive layer 16 from the hotter LESD to the cooler LESD, thereby potentially interfering with the function of the cooler LESD. By thermally isolating the LESDs, the heat generated by each LESD can be managed individually.
- Fig. 4 illustrates another embodiment of the present invention similar to the embodiment of Fig. 3. In Fig.
- an insulative layer 30 has been added between dielectric layer 12 and one of the conductive features 14.
- This structure can be made, for example, by using a photolithography method to pattern insulative layer on dielectric layer 12, then using a standard semi-additive process to add the conductive layer(s) to the structure.
- An LESD generating less heat than an adjacent LESD would preferably be placed above insulation layer 30.
- Insulation layer 30 may comprise any suitable material, including but not limited to, polyimides, epoxies, acrylics, etc.
- conductive layer 16 is continuous between the locations of adjacent LESDs (unlike open section of Fig. 3 and the open section shown in Fig. 4). In this embodiment, insulative layer 30 can provide thermal isolation between the LESDs.
- Fig. 5 illustrates yet another embodiment of the present invention similar to the embodiment of Fig. 3.
- the thin dielectric layer 12 includes protrusions 32.
- These protrusions 32 are typically adjacent to, or between, conductive features on which LESDs are bonded.
- the protrusions can provide enhanced thermal isolation between adjacent LESDs and can also improve the overall mechanical strength of the dielectric layer and flexible LESD article.
- the thickness of the protrusion 32 may be any thickness but is typically about 2 to about 20 times the bulk thickness of the thin dielectric layer 12.
- the protrusions 32 may be made, for example, by starting with a dielectric substrate having a thickness equal to the desired height of the protrusions 32, photomasking the areas where the protrusions are desired and etching the exposed portions of the dielectric substrate to the desired bulk thickness.
- the protrusions and thin layer having a bulk thickness are formed using embossing or microreplication processes.
- the protrusions may be any suitable size or shape and may be, for example, pyramids, truncated pyramids, cubes, hemispheres, etc. They may be individuated features or may form continuous features that are adjacent to, or are between, multiple conductive features.
- a plurality of protrusions may also be located on the flexible substrate in any suitable pattern or configuration, e.g., grids, serpentine shapes, circles, etc.
- the dielectric substrate and copper layers thereon provide a thin and compliant support for the LESD packages.
- the LESDs can be packaged directly on the flexible substrate, e.g., by applying an encapsulating material over individual LESDs and the conductive features on which they are located, or by applying an encapsulant over an array of LESDs and the conductive layer around such LESDs.
- the encapsulant is preferably a transparent (i.e., having a transmittance over 99%) molding compound. It may optionally be suitable to act as a lens when cured. Silicones and epoxies are suitable encapsulating compounds. It may further contain optical diffusing particles distributed therein.
- Suitable molding compounds may be purchased, e.g., from Shin-Etsu Chemical Co., Ltd., of Japan and NuSil Silicone Technology of Santa Barbara, Calif.
- a wavelength converting material such as a phosphor coating
- An underfill material may optionally be applied prior to encapsulating the LESD.
- the flexible LES devices may also be enclosed in a waterproof/weatherproof, transparent casing, which may be made from any suitable polymeric transparent material.
- the flexible LES devices can be made in a batch process or a continuous process such as a roll-to-roll process that is often used in making flexible circuits.
- Arrays of LESDs can be formed in any desired pattern on the flexible substrate.
- the LESDs can then be divided as desired to obtain the LESD, e.g., singulated into individual LESDs, strips of LESDs, or arrays of LESDs, e.g., by stamping or by slitting the substrate. Accordingly, an entire reel of LESDs on a flexible substrate can be shipped without the need for the traditional tape and reel process in which individual LESDs are typically transported in individual pockets of a carrier tape.
- the flexible LESDs can be attached to an additional substrate, for example by attaching the conductive layer on the second major surface of the dielectric substrate to an additional substrate with a thermally conductive adhesive.
- the thermally conductive adhesive can further facilitate the transfer of heat away from the LESD.
- the conductive layer on the second major surface of the dielectric substrate may be treated with metals or other materials that will facilitate its adhesion to an additional substrate.
- the LES devices can be attached to any desired substrate, depending on their intended use.
- the additional substrate may be thermally and/or electrically conductive or may be a semiconductor, ceramic, or polymeric substrate, which may or may not be thermally conductive.
- the additional substrates can be flexible metal substrates, rigid metal substrates, heat sinks, dielectric substrates, circuit boards, etc.
- the flexible LES devices can be directly attached to an end user's circuit board, thereby eliminating the need for conventional lead frame materials. If the LES devices are for use as a lighting strip, they could be enclosed in a waterproof/weatherproof, transparent casing, as described above. If the LESDs are in strip or array form, the LESDs may be electrically connected to one or more of the other LESDs in the strip or array. Additional elements such as Zener diodes and Schottky diodes can also be added to the top or bottom surface of the LESD, e.g. using direct wafer bonding or flip chip processes, prior to be division of the LESDs into the flexible LES devices. These elements may also be electrically connected to the LESDs.
- the flexible LES device is thinner than conventional single or multiple LESD packages because the dielectric substrate is thinner than conventional LESD package substrates.
- This enables the flexible LES devices of the present invention to be used in applications with tight volume restrictions, such as cell phones and camera flashes.
- the flexible LES devices of the present invention can provide a package profile of approximately 0.7 to 4 mm, and in some embodiments 0.7 to 2 mm whereas conventional LESD package profiles are typically greater than 4 mm and are approximately 4.8 mm to 6.00 mm.
- the flexible LES devices can be flexed or bent to easily fit into a non-linear or non- planar assembly if desired.
- the general procedure for preparing the etchants included first dissolving 37 wt% potassium hydroxide (KOH) in water by mixing, followed by the subsequent addition of 3.5 wt% ethylene glycol and 22 wt% ethanolamine.
- the etching was controlled by timing to create a thin layer of polyimide having a bulk thickness, which took approximately 15 minutes.
- the sample was then subjected to a chemical etching process using the Etching Method described above for approximately 15 minutes to create a thinned down polyimide substrate having a bulk thickness of about 5 ⁇ .
- the exposed PI surface of the sample was first subjected to seeding of a chrome tie layer having a thickness of 2-20 nm by vacuum deposition, then to depositing copper to a thickness of about 100 nm on the tie layer by vacuum deposition to form a conductive coating.
- the conductive coating was then subjected to electroplating to build up the conductive copper coating to a final thickness of about 3 ⁇ . This provided a structure of a conductive coating in the etched thinned down PI dielectric substrate.
- Photoresist was then applied on both sides of the copper clad (on one side) and copper coated (on the other side) dielectric substrate and patterned on the copper coated side by a re-registration photolithography process.
- 45 ⁇ of copper was electrodeposited onto both the exposed portions of the thin electrodeposited copper on the etched PI side and the copper cladded side.
- the exposed portions of the 3 ⁇ copper layer and the chrome tie layer were removed to create circuit patterns on the dielectric substrate. This resulted in conductive electrodes having a thickness of 45 ⁇ on the thinned down polyimide substrate.
- Conductive circuits were formed on a thinned down flexible dielectric substrate using the Circuit-Forming Method described above.
- the thinned down substrate had a bulk thickness of about 5 ⁇ and a conductive coating of electroplated copper of about 45 ⁇ .
- Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate with gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., using 1 mil diameter gold wire.
- the assembly was tested using a power supply available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility.
- Conductive circuits were formed on a thinned down flexible dielectric substrate using the Circuit-Forming Method described above.
- the thinned down substrate had a bulk thickness of about 5 ⁇ and a conductive coating of electroplated copper of about 45 ⁇ .
- Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate through gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., with 1 mil diameter gold wire.
- the assembly was tested using a power supply available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility.
- EX4210R voltage rating 42 V, current rating 10 A
- Fig. 6 shows the results of thermal modeling that was executed to replicate heat transfer of the flexible LESD devices of the present invention having thin dielectric layers between LEDs and a thermally conductive layer.
- the thermal modeling was conducted using a Computer Aided Design (CAD) software program available under the trade designation Pro/ENGINEER from PTC, Needham, MA, U.S.A.
- CAD Computer Aided Design
- the design parameters used for the modeling to calculate the heat dissipation on of the thinned down polyimide having a bulk thickness of about 5 ⁇ are as follows:
- the modeling for the above construction shows an effective heat dissipation of about 6.3°C/W.
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Abstract
Provided is a flexible light emitting semiconductor device that includes a thin flexible dielectric substrate having first and second major surfaces with a conductive layer on the first and second major surfaces.
Description
FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE HAVING THIN
DIELECTRIC SUBSTRATE
TECHNICAL FIELD
This invention relates to flexible high power light emitting semiconductor devices.
BACKGROUND
Conventional light emitting semi-conductors (LES), including light emitting diodes (LEDs) and laser diodes, and LES devices (LESD) and packages containing LESDs have several drawbacks. High power LESDs generate a substantial amount of heat that must be managed. Thermal management deals with problems arising from heat dissipation and thermal stresses, which is currently a key factor in limiting the performances of light-emitting diodes.
In general, LES devices are commonly prone to damage caused by buildup of heat generated from within the devices, as well as heat from sunlight in the case of outside lighting applications. Excessive heat buildup can cause deterioration of the materials used in the LES devices, such as encapsulants for the LESDs. When LESDs are attached to flexible- circuit laminates, which may also include other electrical components, the heat dissipation problems are greatly increased.
Additionally, conventional LES devices and packages tend to be thick, which limits their uses in low form factor applications. Consequently, there is a continuing need to improve the design of flexible LES devices and packages to improve their thermal dissipation properties, as well as to allow for their use in low form factors.
SUMMARY
At least one aspect of the present invention provides a cost-effective thermal management solution for current and future high power LESD constructions through a flexible LESD construction having a thin dielectric substrate and adjacent conductive layers. The ability to dissipate large amounts of heat is needed for the operation of high power LES arrays. According to at least one embodiment of the present invention, heat dissipation can be managed by positioning the LESDs of the flexible LES device near the conductive material by controlling the overall, i.e., bulk, thickness of the dielectric substrate.
Many LED illumination systems use a combination of red, green, and blue LEDs. In some systems, the LEDs must be adjacent to each other. At least one embodiment of the present invention allows each of the different types of LEDs to be independently thermally connected to heat sinks so that each LED operates at an optimal temperature.
At least one aspect of the present invention provides an article comprising a flexible thermally dissipative dielectric layer having two major surfaces and a bulk thickness up to about 20 micrometers; a first conductive layer on a first major surface of the dielectric layer and a second conductive layer on a second major surface of the dielectric layer; the first conductive layer having a pattern comprising at least one conductive feature; and at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature.
At least one aspect of the present invention provides an article comprising a flexible thermally dissipative dielectric layer having first and second major surfaces, a bulk thickness up to about 20 micrometers, and at lest one protrusion extending from the first major surface; a first conductive layer on the first major surface of the dielectric layer and a second conductive layer on the second major surface of the dielectric layer;
the first conductive layer having a pattern comprising at least one conductive feature; and at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature; wherein the at least one protrusion is adjacent at least one LESD.
At least one aspect of the present invention provides a method of making a flexible light emitting semiconductor device comprising providing a thermally dissipative flexible dielectric substrate having a first major surface and a second major surface and a bulk thickness up to about 20 micrometers and further having a first conductive layer on the first major surface and a second conductive layer on the second major surface; creating at least one conductive feature in the first conductive layer; and
bonding a light emitting semiconductor directly or indirectly to the at least one conductive feature.
As used in this application:
"bulk thickness" means the thickness of the majority of the dielectric layer;
"LES" means light emitting semiconductor(s), including light emitting diodes and laser diodes,
"LESD" means light emitting semiconductor devices, including light emitting diode device(s) and laser diode device(s). An LESD may be a bare LES die construction, a complete packaged LES construction, or an intermediate LES construction comprising more than the bare die, but less than all the components for a complete LES package, such that the terms LES and LESD may be used interchangeably and refer to one or all of the different LES constructions. The term "flexible LES device" or "flexible LESD" typically refers to the flexible article containing the bare die light emitting semiconductor, packaged LES
construction, or intermediate LES construction. Examples of the type of complete packaged LES constructions that may be suitable for use in embodiments of the present invention Golden DRAGON LEDs, available from OSRAM Opto Semiconductors GmbH, Germany; LUXION LEDs, available from Philips Lumileds Lighting Company, USA; and XLAMP LEDs, available from Cree, Inc., USA.
An advantage of at least one embodiment of the present invention is:
The flexible LES devices provide excellent heat dissipation, which is especially applicable for high power LESDs.
The thin dielectric layer can facilitate distribution of heat in the X, Y, and Z
directions.
The LESDs on the thin flexible dielectric substrate can be wired in series, in
parallel, or individually depending the required applications.
The flexible LES devices can be bent in simple or compound curves. The use of a flexible substrate in the flexible LESDs eliminates the cost associated with conventional submounts.
The flexible LES devices can provide a robust, cost-effective thermal management solution to current and future high power LESD constructions. The above summary of the present invention is not intended to describe each disclosed embodiment or every implementation of the present invention. The Figures and detailed description that follow below more particularly exemplify illustrative embodiments.
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 depicts an embodiment of a flexible LESD of the present invention.
Figs. 2A-2B depict a process for preparing a substrate of the present invention.
Fig. 3 depicts an embodiment of a flexible LESD of the present invention.
Fig. 4 depicts an embodiment of a flexible LESD of the present invention.
Fig. 5 depicts an embodiment of a flexible LESD of the present invention.
Fig. 6 depicts the results of thermal modeling for a flexible LES device of the present
invention.
DETAILED DESCRIPTION
In the following description, reference is made to the accompanying set of drawings that form a part of the description hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are
contemplated and may be made without departing from the scope or spirit of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense.
Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein. The use of numerical ranges by endpoints includes all numbers within that range (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.
Unless otherwise indicated, the terms "coat," "coating," "coated," and the like are not limited to a particular type of application method such as spray coating, dip coating, flood coating, etc., and may refer to a material deposited by any method suitable for the material described, including deposition methods such vapor deposition methods, plating methods, coating methods, etc. In addition, directional terminology, such as "top," "bottom," "front," "back," "above," "below," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. In general similar reference numbers are used for similar features in the various embodiments. Unless indicated otherwise, these similar features may comprise the same materials, have the same attributes, and serve the same or similar functions. Additional or optional features described for one embodiment may also be additional or optional features for other embodiments, even if not explicitly stated, where appropriate.
At least one embodiment of the present invention provides a flexible structure having two conductive layers and an intermediate flexible thermally dissipative dielectric layer for thermally isolating semiconducting devices mounted on the flexible structure, wherein the dielectric layer has a bulk thickness of less than about 20 microns, less than about 10 microns, or less than about 5 micrometers. In at least one embodiment the dielectric layer has a bulk thickness between about 2 and about 10 micrometer. The top conductive layer is patterned to include an electrical circuit and conductive features, including electrically isolated areas on which the LESDs may be mounted. The dielectric layer may be formed either by coating a thin layer of the dielectric material on a copper foil or by starting with a thick layer of dielectric material and reducing its thickness to the desired thickness, e.g., by chemical etching. The thin dielectric layer facilitates dissipating heat efficiently.
At least one embodiment of the present invention provides a flexible LESD construction formed by adding conductive layers to a dielectric substrate. The conductive layers may comprise conductive material deposited thereon in any suitable manner, such as coating, vapor deposition, plating etc., but the conductive material is typically plated either using electro or electroless plating. In at least one embodiment, the total copper thickness is less than 200 micrometers, preferably less than 100 micrometers, and most preferably less than 50 micrometers.
As an alternative to depositing metal on the dielectric substrate, the dielectric substrate may be clad on one or both sides with a conductive layer. If the conductive layer(s) are to be formed into circuits, they may be pre-patterned, or may be patterned during the process of making the flexible LES devices.
The conductive layers may be any suitable material, but are typically copper. At least one conductive layer is typically patterned to form a circuit and conductive features, including isolated conductive features to which LESDs may be attached. LESDs are typically attached, directly, or indirectly, to the conductive features using a known die bonding method such as eutectic, solder (including solder bumps for flip chip mounting), adhesive, and fusion bonding. In at least one embodiment of the present invention, a thermally and electrically conducting layer is located on the second surface of the dielectric substrate and may be patterned into an electrical circuit using conventional flexible circuit manufacturing processes. At least one embodiment of the present invention is illustrated in Fig. 1, which shows a flexible dielectric substrate 12 having a conductive layer 16 located on its bottom surface and a conductive layer 17 located on its top surface. Conductive layer 17 is patterned to include conductive features 14, which support LESDs 24, and typically an electrically conductive circuit. Dielectric substrate 12 is preferably thin, having a preferred thickness of about 20 micrometers or less, more preferably 10 micrometers or less. In some embodiments, the thickness of dielectric substrate 12 is between about 2 and about 10 micrometers. In some embodiments, the thickness of dielectric substrate 12 is about 5 micrometers. In some embodiments, LESD 24 is wire bonded to an electrically conductive circuit, for example using conductive bumps 20 (which may be Au, AuSn, AuGe, AuSi, or other suitable materials). Conductive layer 16 is preferably thermally conductive and optionally electrically conductive. In some embodiments, conductive layer 16 comprises an electrically conductive circuit. In some embodiments, a passivation or bonding layer 22 is located beneath LESD 24 to facilitate bonding LESD 24 to an underlying layer.
Suitable dielectric substrates for the present invention include polyesters, polycarbonates, liquid crystal polymers, and polyimides. Polyimides are preferred. Suitable polyimides include those available under the trade names KAPTON, available from DuPont; APICAL, available from Kaneka Texas corporation; SKC Kolon PI, available from SKC Kolon PI Inc.; and UPILEX and UPISEL, available from Ube-Nitto Kasei Industries, Japan. Most preferred are polyimides available under the trade designations UPILEX S, UPILEX SN, and UPISEL VT, all available from Ube-Nitto Kasei Industries. These polyimides are made from monomers such as biphenyl tetracarboxylic dianhydride (BBDA) and phenyl diamine (PDA).
The dielectric substrate may further comprise thermally conductive particles in a suitable amount. Examples of suitable thermally conductive particles include, but are not limited to, alumina nitride, boron nitride, silicon carbide, and combinations thereof.
If the starting dielectric substrate is thicker than desired, it may be thinned using any suitable method such as chemical etching, plasma etching, focused ion-beam etching, and laser ablation. Chemical etching may be preferred in some embodiments. Any suitable etchant may be used and may vary depending on the dielectric substrate material. Suitable etchants may include alkali metal salts, e.g. potassium hydroxide; alkali metal salts with one or both of solubilizers, e.g., amines, and alcohols, such as ethylene glycol. Suitable chemical etchants for some embodiments of the present invention include KOH/ ethanol amine/ ethylene glycol etchants such as those described in more detail in U.S. Patent Publication No. 2007-0120089-A1, incorporated herein by reference. Other suitable chemical etchants for some embodiments of the present invention include a KOH/glycine etchants such as those described in more detail in co-pending U.S. Provisional Patent Application No. 61/409791, incorporated herein by reference. Subsequent to etching, the dielectric substrates may be treated with an alkaline KOH/ potassium permanganate (PPM) solution, e.g., a solution of about 0.7 to about 1.0 wt% KOH and about 3 wt% KMn04. Figs. 2A-2B illustrate a UPISEL VT dielectric substrate clad on one side with a copper layer 54 (the structure being commercially available under the trade designation UPILEX N from Ube Industries, Japan). As shown in Fig. 2A, UPISEL VT is constructed of a core layer 50 comprising UPILEX S and thin outer layers 52a, 52b comprising a thermoplastic polyimide (TPPI). To produce a thin dielectric substrate, the UPISEL VT may be etched using any suitable chemistry, such as KOH/ ethanol amine/ ethylene glycol described in more detail on U.S. Patent Publication. No. 2007-0120089-A1. With this etchant, it was found that the hydrophobic nature and higher modulus of the UPILEX S resulted in etching by a dissolution mechanism. Because
this etchant formulation etched the UPILEX S quickly, the etching was stopped before reached the second TPPI layer, then a subsequent etching was performed with a KOH/ potassium permanganate (PPM) solution, comprising about 0.7 to about 1.0 wt% KOH and about 3 wt% KMn04, which was not an effective etchant of the TPPI layer, to remove the remaining thin layer of UPILEX S core, thereby leaving the thin outer TPPI layer 52b as the dielectric substrate, as shown in Fig. 2B.
Other suitable etchant chemistries are the KOH /glycine, and KOH/glycine/ethylene diamine chemistries described in more detail in co-pending U.S. Provisional Patent
Application No. 61/409791. The KOH/ glycine etchant provides a slow, controlled etching. The etching rate can be increased by adding ethylene diamine to the etchant formulation.
As an alternative to chemical etching, the controlled thinning of the dielectric substrate can be accomplished by using eximer laser, by plasma etching, or by other suitable methods.
In another embodiment of the invention, the dielectric substrate is formed by coating and curing polymeric material on a conductive layer. For example, to form a polyimide layer on copper, polyamic acid resin can be coated on a copper foil to a desired thickness.
Subsequently, an imidization process can be carried out to form a uniform polyimide layer.
The dielectric layers (substrates) may be initially clad on one or both sides with a conductive layer. If the conductive layer(s) are to be formed into circuits, they may be pre- patterned, or may be patterned during the process of making the flexible LES devices. A multilayer flexible substrate (having multiple layers of dielectric and conductive material) may also be used as a substrate. The conductive layers may be any suitable material, but are typically copper.
If a conductive layer is to be added to one or both sides of the dielectric layer after it is formed to the desired thickness, this can be done by lamination of a metal foil to the dielectric, but is more typically done by some type of metal deposition process.
Conductive features and circuits can be formed as part of a metal deposition process. For example, a standard semi-additive deposition method of forming a circuit would include providing a vapor deposited tie layer, typically of CrOx, NiCr, or NiCrOx, vapor depositing thereon a metal seed layer that typically, but not necessarily, comprises the same metal as the subsequently plated metal layer, patterning a photomask on the seed layer using a traditional photolithography process, plating a conductive material (any suitable material, but typically copper), on the exposed portions of the seed layer using either electro or electroless plating,
stripping the photomask, and removing the remaining, now-exposed portion of the seed and tie layers.
Subsequent passivation with gold, tin, silver, etc. of the conductive features onto which the LESDs will be bonded can be carried out to facilitate such bonding. The individual LESDs may be bonded onto the conductive features using any suitable bonding mechanism. Different types of bonding can be employed such as eutectic, flip chip, fusion and adhesive bonding. The LESDs preferably have a passivation layer (typically gold/tin but may be any suitable passivation material, e.g., metals such as Au and intermetallic alloys(s) such as AuSn, AuGe, AuSi) applied to their bottom surfaces to facilitate bonding the LESDs to the gold passivated conductive features. The temperature used for attaching LESDs to the conductive features is typically between about 250°C and 325°C, most typically about 285°C for eutectic bonding (for Au/Sn). The LESDs may be adhered by other methods such as organic die attach, e.g., using silver epoxy, or soldering. Eutectic bonding is considered a direct bonding method while soldering is considered an indirect bonding method.
At least some embodiments of the flexible LES devices of the present invention provide excellent heat management properties. Due at least in part to the thinness of the dielectric substrate, heat generated by the LESDs can be readily transmitted away from the LESD and to the conductive layer on the bottom side of the dielectric substrate. The heat can then disperse throughout the conductive layer in multiple directions (e.g., the downward Z direction and all X and Y directions), which can provide faster and more efficient heat dissipation away from the LESD. Additionally, according to at least one embodiment of the present invention, the amount of conductive material in the conductive layers can be controlled to further influence heat management. For example, increasing the amount of conductive material can increase the conductive layer's capacity for heat dissipation.
Fig. 3 illustrates an embodiment of the present invention in which conductive layer 16 has been patterned to provide open section 26 extending to the dielectric layer 12 between conductive features 14 of conductive layer 17 on which LESDs 24 are bonded. This patterning helps to thermally isolate the adjacent conductive features and enhance thermal management of the LESDs. For example, if one LESD produces more heat than a neighboring LESD, heat could travel through thermally conductive layer 16 from the hotter LESD to the cooler LESD, thereby potentially interfering with the function of the cooler LESD. By thermally isolating the LESDs, the heat generated by each LESD can be managed individually.
Fig. 4 illustrates another embodiment of the present invention similar to the embodiment of Fig. 3. In Fig. 4, an insulative layer 30 has been added between dielectric layer 12 and one of the conductive features 14. This structure can be made, for example, by using a photolithography method to pattern insulative layer on dielectric layer 12, then using a standard semi-additive process to add the conductive layer(s) to the structure. An LESD generating less heat than an adjacent LESD would preferably be placed above insulation layer 30. Insulation layer 30 may comprise any suitable material, including but not limited to, polyimides, epoxies, acrylics, etc. In at least one alternate embodiment, conductive layer 16 is continuous between the locations of adjacent LESDs (unlike open section of Fig. 3 and the open section shown in Fig. 4). In this embodiment, insulative layer 30 can provide thermal isolation between the LESDs.
Fig. 5 illustrates yet another embodiment of the present invention similar to the embodiment of Fig. 3. In Fig. 5, the thin dielectric layer 12 includes protrusions 32. These protrusions 32 are typically adjacent to, or between, conductive features on which LESDs are bonded. The protrusions can provide enhanced thermal isolation between adjacent LESDs and can also improve the overall mechanical strength of the dielectric layer and flexible LESD article. The thickness of the protrusion 32 may be any thickness but is typically about 2 to about 20 times the bulk thickness of the thin dielectric layer 12. The protrusions 32 may be made, for example, by starting with a dielectric substrate having a thickness equal to the desired height of the protrusions 32, photomasking the areas where the protrusions are desired and etching the exposed portions of the dielectric substrate to the desired bulk thickness. In at least one other embodiment, the protrusions and thin layer having a bulk thickness are formed using embossing or microreplication processes. The protrusions may be any suitable size or shape and may be, for example, pyramids, truncated pyramids, cubes, hemispheres, etc. They may be individuated features or may form continuous features that are adjacent to, or are between, multiple conductive features. A plurality of protrusions may also be located on the flexible substrate in any suitable pattern or configuration, e.g., grids, serpentine shapes, circles, etc.
In at least one embodiment, the dielectric substrate and copper layers thereon provide a thin and compliant support for the LESD packages. The LESDs can be packaged directly on the flexible substrate, e.g., by applying an encapsulating material over individual LESDs and the conductive features on which they are located, or by applying an encapsulant over an array of LESDs and the conductive layer around such LESDs. The encapsulant is preferably a transparent (i.e., having a transmittance over 99%) molding compound. It may optionally
be suitable to act as a lens when cured. Silicones and epoxies are suitable encapsulating compounds. It may further contain optical diffusing particles distributed therein. Suitable molding compounds may be purchased, e.g., from Shin-Etsu Chemical Co., Ltd., of Japan and NuSil Silicone Technology of Santa Barbara, Calif. If desired, a wavelength converting material, such as a phosphor coating, may be deposited on top of the LESD prior to encapsulation. An underfill material may optionally be applied prior to encapsulating the LESD. The flexible LES devices may also be enclosed in a waterproof/weatherproof, transparent casing, which may be made from any suitable polymeric transparent material.
The flexible LES devices can be made in a batch process or a continuous process such as a roll-to-roll process that is often used in making flexible circuits. Arrays of LESDs can be formed in any desired pattern on the flexible substrate. The LESDs can then be divided as desired to obtain the LESD, e.g., singulated into individual LESDs, strips of LESDs, or arrays of LESDs, e.g., by stamping or by slitting the substrate. Accordingly, an entire reel of LESDs on a flexible substrate can be shipped without the need for the traditional tape and reel process in which individual LESDs are typically transported in individual pockets of a carrier tape.
Before or after forming individual, strips, or arrays of LESDs, the flexible LESDs can be attached to an additional substrate, for example by attaching the conductive layer on the second major surface of the dielectric substrate to an additional substrate with a thermally conductive adhesive. The thermally conductive adhesive can further facilitate the transfer of heat away from the LESD. Alternatively, the conductive layer on the second major surface of the dielectric substrate may be treated with metals or other materials that will facilitate its adhesion to an additional substrate. The LES devices can be attached to any desired substrate, depending on their intended use. The additional substrate may be thermally and/or electrically conductive or may be a semiconductor, ceramic, or polymeric substrate, which may or may not be thermally conductive. For example, the additional substrates can be flexible metal substrates, rigid metal substrates, heat sinks, dielectric substrates, circuit boards, etc.
If the LES devices are for use on a circuit board, the flexible LES devices, whether in singulated, strip, or array form can be directly attached to an end user's circuit board, thereby eliminating the need for conventional lead frame materials. If the LES devices are for use as a lighting strip, they could be enclosed in a waterproof/weatherproof, transparent casing, as described above.
If the LESDs are in strip or array form, the LESDs may be electrically connected to one or more of the other LESDs in the strip or array. Additional elements such as Zener diodes and Schottky diodes can also be added to the top or bottom surface of the LESD, e.g. using direct wafer bonding or flip chip processes, prior to be division of the LESDs into the flexible LES devices. These elements may also be electrically connected to the LESDs.
In at least one embodiment of the present invention, the flexible LES device is thinner than conventional single or multiple LESD packages because the dielectric substrate is thinner than conventional LESD package substrates. This enables the flexible LES devices of the present invention to be used in applications with tight volume restrictions, such as cell phones and camera flashes. For example, the flexible LES devices of the present invention can provide a package profile of approximately 0.7 to 4 mm, and in some embodiments 0.7 to 2 mm whereas conventional LESD package profiles are typically greater than 4 mm and are approximately 4.8 mm to 6.00 mm. Moreover, in at least one embodiment of the present invention, the flexible LES devices can be flexed or bent to easily fit into a non-linear or non- planar assembly if desired.
EXAMPLES
This invention is illustrated by the following examples, but the particular materials and amounts thereof recited in these examples, as well as other conditions and details should not be construed to unduly limit this invention.
Etching Method
The general procedure for preparing the etchants included first dissolving 37 wt% potassium hydroxide (KOH) in water by mixing, followed by the subsequent addition of 3.5 wt% ethylene glycol and 22 wt% ethanolamine. Samples of 50 μιη polyimide dielectric substrate with 3 μιη copper layer clad on one side, available under the trade designation UPISEL-N from Ube-Nitto Kasei Co., Ltd. Industries, Tokyo, Japan, was subjected to selective etching from the PI side using aqueous photoresist, available under the trade designation HM-4056 from Hitachi Chemicals, Japan, as an etch mask. The etching was controlled by timing to create a thin layer of polyimide having a bulk thickness, which took approximately 15 minutes.
Circuit-Forming Method
A 20 inch (50.8 cm) wide by 10 m long sample of 50 μιη polyimide with 3 μιη copper clad on one side, available under the trade designation UPISEL-N from Ube-Nitto Kasei Co., Ltd. Industries, Tokyo, Japan, was first slit into a 13.4 inch (34.04 cm) width. Following
removal of the 18 μιη copper carrier layer from the copper (Cu) side, the polyimide was thinned down to a bulk thickness in the sample by laminating dry film photoresist, available under the trade designation HM4056 from Hitachi Chemicals, Ltd. on both sides and creating a patterned etch mask on the polyimide side using a photolithography process. The sample was then subjected to a chemical etching process using the Etching Method described above for approximately 15 minutes to create a thinned down polyimide substrate having a bulk thickness of about 5 μιη. After removing the photoresist from both sides, the exposed PI surface of the sample was first subjected to seeding of a chrome tie layer having a thickness of 2-20 nm by vacuum deposition, then to depositing copper to a thickness of about 100 nm on the tie layer by vacuum deposition to form a conductive coating. The conductive coating was then subjected to electroplating to build up the conductive copper coating to a final thickness of about 3 μιη. This provided a structure of a conductive coating in the etched thinned down PI dielectric substrate. Photoresist was then applied on both sides of the copper clad (on one side) and copper coated (on the other side) dielectric substrate and patterned on the copper coated side by a re-registration photolithography process. 45 μιη of copper was electrodeposited onto both the exposed portions of the thin electrodeposited copper on the etched PI side and the copper cladded side. Then after the photoresist was removed from both sides, the exposed portions of the 3 μιη copper layer and the chrome tie layer were removed to create circuit patterns on the dielectric substrate. This resulted in conductive electrodes having a thickness of 45 μιη on the thinned down polyimide substrate.
Example 1
Following is an example of packaging LESDs on a flexible substrate, specifically, mounting blue LEDs on a thinned down flexible dielectric substrate with organic die attach.
Conductive circuits were formed on a thinned down flexible dielectric substrate using the Circuit-Forming Method described above. The thinned down substrate had a bulk thickness of about 5 μιη and a conductive coating of electroplated copper of about 45 μιη. A Cree EZ 290 Gen II LED, available as part number CA460EZ290-S2100-2 from Cree, Inc., Durham, NC, U.S.A., was bonded to the conductive coating using a silver epoxy organic die attach available from Quantum Materials, San Diego, U.S.A. with thermal curing done at 150 °C for 1 hour. Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate with gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., using 1 mil diameter gold wire. The assembly was tested using a power supply
available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility.
Example 2
Following is another example of packaging LESDs on a fiexible substrate, specifically, mounting blue LEDs on a thinned down fiexible dielectric substrate with indirect die bonding.
Conductive circuits were formed on a thinned down flexible dielectric substrate using the Circuit-Forming Method described above. The thinned down substrate had a bulk thickness of about 5 μιη and a conductive coating of electroplated copper of about 45 μιη. A Cree EZ 290 Gen II LED, available as part number CA460EZ290-S2100-2 from Cree, Inc., Durham, NC, U.S.A., was bonded to the conductive coating using solder in between the LED and the conductive coating. Each LED was wire bonded to the conductive circuit on the top surface of the dielectric substrate through gold bonding pads using a manual wire bonder, available under the trade designation 4524D from Kulicke and Soffa Industries, Inc., Fort Washington, PA, U.S.A., with 1 mil diameter gold wire. The assembly was tested using a power supply available as model number EX4210R (voltage rating 42 V, current rating 10 A) from Thurlby Thandar Instruments Limited (TTi), Huntingdon, Cambridgeshire, United Kingdom. The LEDs were bright blue when lit up and the assembly showed flexibility. Example 3
Fig. 6 shows the results of thermal modeling that was executed to replicate heat transfer of the flexible LESD devices of the present invention having thin dielectric layers between LEDs and a thermally conductive layer. The thermal modeling was conducted using a Computer Aided Design (CAD) software program available under the trade designation Pro/ENGINEER from PTC, Needham, MA, U.S.A. The design parameters used for the modeling to calculate the heat dissipation on of the thinned down polyimide having a bulk thickness of about 5 μιη are as follows:
• 10 x 10 x 2 mm aluminum plate, with outer edges held at a constant 25 °C temperature.
· 4 x 4 x 0.05 mm gold-tin eutectic solder.
• 4 x 4 x 0.05 mm electroplate copper.
• 10 x 10 x 0.05 mm polyimide circuit (with center area thickness 4 x 4 x X, where X is 0.05 mm). Material properties of UPILEX-S were used.
• 4 x 4 x Y top copper electroplate, where Y is 50 mm.
• 1 x 1 x 0.2 mm thin GaN LED on Silicon. The thermal properties of silicon were used. The silicon to copper solder was not added, because the thermal conductivity of the solder is about the same as that of the silicon. · The thermal load on the top of the LED was 1500 mW (assuming a 2 Watt
LED with 25 % external optical efficiency).
The modeling for the above construction shows an effective heat dissipation of about 6.3°C/W.
Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. An article comprising:
a flexible thermally dissipative dielectric layer having two major surfaces and a bulk thickness up to about 20 micrometers;
a first conductive layer on a first major surface of the dielectric layer and a second conductive layer on a second major surface of the dielectric layer;
the first conductive layer having a pattern comprising at least one conductive feature; and
at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature.
2. An article comprising:
a flexible thermally dissipative dielectric layer having first and second major surfaces, a bulk thickness up to about 20 micrometers, and at lest one protrusion extending from the first major surface;
a first conductive layer on the first major surface of the dielectric layer and a second conductive layer on the second major surface of the dielectric layer; the first conductive layer having a pattern comprising at least one conductive feature; and
at least one light emitting semiconductor device (LESD) supported by the at least one conductive feature; wherein the at least one protrusion is adjacent at least one LESD.
3. The article of claim 1 or 2 wherein the dielectric layer has a bulk thickness up to about 10 micrometer.
4. The article of claim 1 or 2 wherein the dielectric layer has a bulk thickness between about 2 and about 10 micrometer.
5. The article of claim 1 or 2 wherein the dielectric layer has a bulk thickness of about 5 micrometer.
6. The article of claim 1 or 2 wherein the dielectric layer comprises thermally
conductive particles selected from the group consisting of alumina nitride, boron nitride, silicon carbide, and combinations thereof.
7. The article of claim 1 or 2 wherein the first conductive layer further comprises at least one circuit.
8. The article of claim 2 wherein the at least one protrusion is up to 20 times as thick as the bulk thickness.
9. The article of claim 2 wherein the at least one protrusion is between about 2 and about 10 times as thick as the bulk thickness.
10. The article of any of claims 2, 7, or 8 wherein the at least one protrusion is located between at least two LESDs.
11. The article of claim 1 or 2 wherein the conductive layer on the second surface of the dielectric layer is patterned.
12. The article of claim 11 wherein the conductive layer on the second surface of the dielectric layer is patterned to include an opening between adjacent conductive features on the first surface of the dielectric layer.
13. The article of claim 12 wherein one of the adjacent conductive features is supported by an insulative layer between the dielectric substrate and first conductive layer.
14. The article of claim 1 or 2 wherein the conductive layer on the second major surface of the dielectric layer comprises a circuit.
15. The article of claim 1 or 2 wherein the conductive layer on the second major surface of the dielectric layer is attached to a thermally conductive rigid substrate by a thermally conductive adhesive.
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