WO2012107973A1 - Électrode résistant à la corrosion pour un dispositif semi-conducteur électroluminescent, ainsi que procédé de fabrication de celle-ci - Google Patents

Électrode résistant à la corrosion pour un dispositif semi-conducteur électroluminescent, ainsi que procédé de fabrication de celle-ci Download PDF

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Publication number
WO2012107973A1
WO2012107973A1 PCT/JP2011/004536 JP2011004536W WO2012107973A1 WO 2012107973 A1 WO2012107973 A1 WO 2012107973A1 JP 2011004536 W JP2011004536 W JP 2011004536W WO 2012107973 A1 WO2012107973 A1 WO 2012107973A1
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Prior art keywords
light emitting
protective film
metal protective
contact electrode
opening
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PCT/JP2011/004536
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English (en)
Inventor
Yuko Kato
Hidefumi Yasuda
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Kabushiki Kaisha Toshiba
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • Embodiments described herein relate generally to a semiconductor light emitting device and a method for manufacturing the same.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device of an embodiment.
  • FIGS. 2A to 9B are schematic cross-sectional views illustrating a method for manufacturing the semiconductor light emitting device of the embodiment.
  • FIG. 10 is a schematic cross-sectional view of a semiconductor light emitting device of another embodiment.
  • FIG. 11 is a schematic cross-sectional view of a semiconductor light emitting device of yet another embodiment.
  • FIG. 12 is a schematic cross-sectional view of a semiconductor light emitting device of still yet another embodiment.
  • FIGS. 13A and 13B are schematic views illustrating the planar layout of the main components of the semiconductor light emitting device of the embodiment.
  • a semiconductor light emitting device includes a semiconductor layer, an insulating film, a p-side contact electrode, an n-side contact electrode, a p-side metal protective film, and an n-side metal protective film.
  • the semiconductor layer includes a light emitting layer, a first surface, and a second surface. The second surface is formed on a side opposite to the first surface. The second surface has a light emitting portion including the light emitting layer and a non-light emitting portion not including the light emitting layer.
  • the insulating film is provided on the second surface. The insulating film has a first opening connecting with the light emitting portion and a second opening connecting with the non-light emitting portion.
  • the p-side contact electrode is provided in contact with the light emitting portion inside the first opening.
  • the n-side contact electrode is provided in contact with the non-light emitting portion inside the second opening.
  • the p-side metal protective film covers a top surface and a side surface of the p-side contact electrode.
  • the n-side metal protective film covers a top surface and a side surface of the n-side contact electrode.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device 10 of the embodiment.
  • the semiconductor light emitting device 10 includes a semiconductor layer 4.
  • the semiconductor layer 4 includes a first surface 4a and a second surface formed in an uneven configuration on a side opposite to the first surface 4a. Electrodes, interconnect layers, and resin layers are provided on the second surface side. Light is emitted to the outside mainly from the first surface 4a on the side opposite to the second surface.
  • the semiconductor layer 4 includes a first semiconductor layer 1 and a second semiconductor layer 2. Both the first semiconductor layer 1 and the second semiconductor layer 2 include, for example, III-V nitride semiconductor.
  • the first semiconductor layer 1 includes, for example, a foundation buffer layer, an n-type layer, etc.; and the n-type layer functions as a lateral-direction path of current.
  • the second semiconductor layer 2 has a stacked structure in which a light emitting layer (an active layer) 3 is interposed between an n-type layer and a p-type layer.
  • the second surface of the semiconductor layer 4 is patterned into an uneven configuration.
  • the second surface includes a light emitting portion 5 formed in a protruding configuration that includes the light emitting layer 3, and a non-light emitting portion 6 that does not include the light emitting layer 3.
  • a p-side contact electrode 13 is provided on the top surface of the second semiconductor layer 2 which is the top surface of the light emitting portion 5.
  • An n-side contact electrode 14 is provided on the top surface of the first semiconductor layer 1 which is the top surface of the non-light emitting portion 6.
  • the p-side contact electrode 13 includes, for example, a first nickel (Ni) film provided on the top surface of the second semiconductor layer 2, a silver (Ag) film provided on the first nickel film, and a second nickel film provided on the silver film.
  • the first nickel film has ohmic contact with the top surface of the second semiconductor layer 2 which is, for example, a III-V nitride semiconductor.
  • the reflectance of the silver is 98% with respect to light of 600 nm or more, 98% with respect to light near 500 to 600 nm, and 97% with respect to light near 450 to 500 nm; and the silver has high reflectance for wavelengths in the visible region.
  • the second nickel film prevents sulfidization of the silver film during the plating and the wet etching described below.
  • the n-side contact electrode 14 includes, for example, a first titanium (Ti) film provided on the top surface of the first semiconductor layer 1, an aluminum (Al) film provided on the first titanium film, a tantalum (Ta) film provided on the aluminum film, a second titanium film provided on the tantalum film, and a platinum (Pt) film provided on the second titanium film.
  • the first titanium film has ohmic contact with the top surface of the first semiconductor layer 1 which is, for example, III-V nitride semiconductor.
  • the tantalum film functions as a barrier metal that prevents the alloying of the metals thereon and thereunder.
  • the area of the light emitting portion 5 is larger than the area of the non-light emitting portion 6; and there are cases where the surface area of the light emitting portion 5 is less than the surface area of the non-light emitting portion 6.
  • the area of the p-side contact electrode 13 provided in the light emitting portion 5 is larger than the area of the n-side contact electrode 14 provided in the non-light emitting portion 6; and there are cases where the area of the p-side contact electrode 13 provided in the light emitting portion 5 is less than the area of the n-side contact electrode 14 provided in the non-light emitting portion 6.
  • the area of the light emitting portion 5 is larger than the area of the non-light emitting portion 6.
  • An insulating film 17 is provided on the second surface of the semiconductor layer 4.
  • the insulating film 17 is an inorganic film such as, for example, a silicon oxide film.
  • the insulating film 17 covers a portion of the top surface of the light emitting portion 5 and a portion of the top surface of the non-light emitting portion 6.
  • the insulating film 17 also covers the side surface of the light emitting portion 5 having the protruding configuration.
  • the insulating film 17 has a first opening 17a and a second opening 17b.
  • the first opening 17a connects with the top surface of the light emitting portion 5; and the second opening 17b connects with the top surface of the non-light emitting portion 6.
  • An inner wall of the first opening 17a is tilted with respect to the top surface of the light emitting portion 5. Specifically, the opening area of the first opening 17a increases from the top surface side of the light emitting portion 5 toward the top surface side of the insulating film 17. In other words, the cross section of the first opening 17a in FIG. 1 is formed in a trapezoidal configuration.
  • an inner wall of the second opening 17b is tilted with respect to the top surface of the non-light emitting portion 6.
  • the opening area of the second opening 17b increases from the top surface side of the non-light emitting portion 6 toward the top surface side of the insulating film 17.
  • the cross section of the second opening 17b in FIG. 1 is formed in a trapezoidal configuration.
  • the p-side contact electrode 13 has ohmic contact with the top surface of the light emitting portion 5 (the top surface of the second semiconductor layer 2) inside the first opening 17a.
  • the n-side contact electrode 14 has ohmic contact with the top surface of the non-light emitting portion 6 (the top surface of the first semiconductor layer 1) inside the second opening 17b.
  • the planar size of the bottom face of the first opening 17a on the light emitting portion 5 side is larger than the planar size of the p-side contact electrode 13; and the inner wall of the first opening 17a is separate from the side surface of the p-side contact electrode 13.
  • the planar size of the bottom face of the second opening 17b on the non-light emitting portion 6 side is larger than the planar size of the n-side contact electrode 14; and the inner wall of the second opening 17b is separate from the side surface of the n-side contact electrode 14.
  • the insulating film 17 is thicker than the p-side contact electrode 13; and the depth of the first opening 17a is larger than the thickness of the p-side contact electrode 13.
  • the insulating film 17 is thicker than the n-side contact electrode 14; and the depth of the second opening 17b is larger than the thickness of the n-side contact electrode 14.
  • a p-side metal protective film 15 is provided on the top surface and the side surface of the p-side contact electrode 13.
  • the p-side metal protective film 15 is provided also on the top surface of the light emitting portion 5 in the gap between the inner wall of the first opening 17a and the side surface of the p-side contact electrode 13.
  • the p-side metal protective film 15 is provided also on the inner wall of the first opening 17a to fill the gap.
  • a portion of the p-side metal protective film 15 also is provided to rise onto the top surface of the insulating film 17 around the first opening 17a.
  • the p-side metal protective film 15 has a planar size larger than those of the p-side contact electrode 13 and the first opening 17a, and covers the top surface and the side surface of the p-side contact electrode 13.
  • FIG. 13A illustrates an example of the planar layout of the main components of the semiconductor light emitting device 10.
  • FIG. 13B illustrates another specific example of the planar layout. As illustrated in FIGS. 13A and 13B, the p-side metal protective film 15 covers all around the p-side contact electrode 13 or the entire side surface of the p-side contact electrode 13.
  • the p-side metal protective film 15 includes, for example, a first titanium (Ti) film, a platinum (Pt) film provided on the first titanium film, a gold (Au) film provided on the platinum film, and a second titanium film provided on the gold film in order from the p-side contact electrode 13 side.
  • the gold film which does not undergo reactions such as oxidization and sulfidization, is thickest.
  • the second titanium film has excellent adhesion with an insulating layer (e.g., polyimide) 18 described below.
  • an insulating layer e.g., polyimide
  • a nickel (Ni) film or a molybdenum (Mo) film may be used instead of the second titanium film.
  • An n-side metal protective film 16 is provided on the top surface and the side surface of the n-side contact electrode 14.
  • the n-side metal protective film 16 is provided also on the top surface of the non-light emitting portion 6 in the gap between the inner wall of the second opening 17b and the side surface of the n-side contact electrode 14.
  • the n-side metal protective film 16 is provided also on the inner wall of the second opening 17b to fill the gap.
  • a portion of the n-side metal protective film 16 is also provided to rise onto the top surface of the insulating film 17 around the second opening 17b.
  • the n-side metal protective film 16 has a planar size larger than those of the n-side contact electrode 14 and the second opening 17b, and covers the top surface and the side surface of the n-side contact electrode 14. As illustrated in FIGS. 13A and 13B, the n-side metal protective film 16 covers the entire side surface of the n-side contact electrode 14. The n-side metal protective film 16 is thicker than the n-side contact electrode 14.
  • the n-side metal protective film 16 includes, for example, a first titanium (Ti) film, a platinum (Pt) film provided on the first titanium film, a gold (Au) film provided on the platinum film, and a second titanium film provided on the gold film in order from the n-side contact electrode 14 side.
  • the gold film which does not undergo reactions such as oxidization and sulfidization, is thickest.
  • the second titanium film has excellent adhesion with the insulating layer (e.g., polyimide) 18 described below.
  • a nickel (Ni) film or a molybdenum (Mo) film may be used instead of the second titanium film.
  • the insulating layer 18 also covers the insulating film 17 and the side surface of the first semiconductor layer 1.
  • the insulating layer 18 is, for example, a resin such as polyimide having excellent patternability of ultra-fine openings.
  • an inorganic substance such as silicon oxide, silicon nitride, etc., may be used as the insulating layer 18.
  • the insulating layer 18 has a first via 18a that reaches the p-side metal protective film 15 and a second via 18b that reaches the n-side metal protective film 16.
  • the insulating layer 18 includes an interconnect surface 18c on the side opposite to the p-side metal protective film 15 and the n-side metal protective film 16.
  • a p-side re-interconnect layer 21 and an n-side re-interconnect layer 22 are provided apart from each other on the interconnect surface 18c.
  • the p-side re-interconnect layer 21 is provided also inside the first via 18a and is electrically connected to the p-side metal protective film 15 and the p-side contact electrode 13.
  • the n-side re-interconnect layer 22 is provided also inside the second via 18b and is electrically connected to the n-side metal protective film 16 and the n-side contact electrode 14.
  • the p-side re-interconnect layer 21 and the n-side re-interconnect layer 22 are made of, for example, copper (Cu).
  • a metal film 19 is provided between the p-side re-interconnect layer 21 and the p-side metal protective film 15, and between the p-side re-interconnect layer 21 and the insulating layer 18.
  • the metal film 19 includes a copper (Cu) film and a titanium (Ti) film provided in order from the p-side re-interconnect layer 21 side.
  • the metal film 19 is provided also between the n-side re-interconnect layer 22 and the n-side metal protective film 16, and between the n-side re-interconnect layer 22 and the insulating layer 18.
  • a p-side metal pillar 23 is provided on the surface of the p-side re-interconnect layer 21 on the side opposite to the p-side metal protective film 15.
  • the metal film 19, the p-side re-interconnect layer 21, and the p-side metal pillar 23 are included in the p-side interconnect layer of the embodiment.
  • a resin layer 25 is provided as a second insulating layer on the interconnect surface 18c of the insulating layer 18, between the p-side re-interconnect layer 21 and the n-side re-interconnect layer 22, and between the p-side metal pillar 23 and the n-side metal pillar 24.
  • the surface of the p-side metal pillar 23 on the side opposite to the p-side re-interconnect layer 21 is exposed from the resin layer 25 and functions as the p-side external terminal for the mounting.
  • the surface of the n-side metal pillar 24 on the side opposite to the n-side re-interconnect layer 22 is exposed from the resin layer 25 and functions as the n-side external terminal for the mounting.
  • the p-side external terminal and the n-side external terminal are bonded with a bonding agent such as solder, another metal, electrically conductive material, etc., to pads formed in the mounting substrate.
  • the p-side external terminal and the n-side external terminal are formed in the same surface; and the mounting surface of the semiconductor light emitting device 10 is a substantially flat surface.
  • the current distribution of the light emitting portion 5 depends on the positions and the number of the first vias 18a.
  • the first via 18a may be connected to the p-side metal protective film 15 at a position away from the region where the p-side metal pillar 23 spreads.
  • the p-side re-interconnect layer 21 and the p-side metal pillar 23 can be formed using a low-resistance metal such as, for example, copper.
  • the heat conduction and the heat dissipation of the p-side re-interconnect layer 21 and the p-side metal pillar 23 increase and it is possible to efficiently release the heat of the light emitting portion 5 as the planar sizes of the p-side re-interconnect layer 21 and the p-side metal pillar 23 increase.
  • the area of the surface of the n-side re-interconnect layer 22 on the side opposite to the n-side metal protective film 16 is larger than the area of the n-side contact electrode 14.
  • the p-side interconnect layer which includes the p-side re-interconnect layer 21 and the p-side metal pillar 23 is thicker than the p-side contact electrode 13.
  • the n-side interconnect layer which includes the n-side re-interconnect layer 22 and the n-side metal pillar 24 is thicker than the n-side contact electrode 14.
  • the p-side metal pillar 23 is thicker than the p-side re-interconnect layer 21; and the n-side metal pillar 24 is thicker than the n-side re-interconnect layer 22.
  • the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 filled between the p-side metal pillar 23 and the n-side metal pillar 24 increase the mechanical strength of the semiconductor light emitting device 10.
  • Copper, gold, nickel, silver, etc. can be used as the materials of the p-side re-interconnect layer 21, the n-side re-interconnect layer 22, the p-side metal pillar 23, and the n-side metal pillar 24. Of these, good thermal conductivity, high migration resistance, and excellent adhesion with the insulating materials are obtained when copper is used.
  • the resin layer 25 reinforces the p-side metal pillar 23 and the n-side metal pillar 24. It may be desirable for the resin layer 25 to have a coefficient of thermal expansion near to or the same as that of the mounting substrate.
  • a resin layer 25 include, for example, an epoxy resin, a silicone resin, a fluorocarbon resin, etc.
  • the embodiment it is possible to maintain the mechanical strength by the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 being thick even in the case where the semiconductor layer 4 is thin and there is no substrate to support the semiconductor layer 4.
  • a lens 26 and a phosphor layer 27 are provided on the first surface 4a of the semiconductor layer 4 as a transparent body which is transparent to the light emitted from the light emitting layer 3.
  • the lens 26 is provided on the phosphor layer 27.
  • the phosphor layer 27 may be provided on the lens 26.
  • a structure may be used in which only the phosphor layer 27 or only the lens 26 is provided on the first surface 4a.
  • the phosphor layer 27 includes a transparent resin and a phosphor dispersed in the transparent resin.
  • the phosphor layer 27 is capable of absorbing the light emitted from the light emitting layer 3 and emitting a wavelength-converted light. Therefore, the semiconductor light emitting device 10 is capable of emitting a mixed light of the light from the light emitting layer 3 and the wavelength-converted light of the phosphor layer 27.
  • white, lamp, etc. can be obtained as the mixed color of a blue light from the light emitting layer 3 and a yellow light which is the wavelength-converted light of the phosphor layer 27 in the case where the light emitting layer 3 is III-V nitride semiconductor and the phosphor is a yellow phosphor configured to emit the yellow light.
  • the phosphor layer 27 may have a configuration including multiple types of phosphors (e.g., a red phosphor configured to emit red light and a green phosphor configured to emit green light).
  • the light emitted from the light emitting layer 3 is emitted to the outside mainly from the first surface 4a via the phosphor layer 27 and the lens 26.
  • the p-side contact electrode 13 Because the lower surface of the p-side metal protective film 15 has a concave configuration, the chemical liquids do not easily overflow outside the portion having the concave configuration.
  • the lower surface of the n-side metal protective film 16 (the surface on the n-side re-interconnect layer 22 side) has a dish-like configuration; and the edge portion is raised higher than the central portion.
  • the lower surface of the n-side metal protective film 16 has a concave configuration. Therefore, it is easier to protect the n-side contact electrode 14 because the distance of the interface along which the chemical liquids, etc., are conveyed is long.
  • the p-side contact electrode 13 and the n-side contact electrode 14 include a metal that has good ohmic contact with the semiconductor layer 4.
  • FIG. 2A illustrates a stacked body in which the semiconductor layer 4 including the first semiconductor layer 1 and the second semiconductor layer 2 is formed on a major surface of a substrate 8.
  • the first semiconductor layer 1 is formed on the major surface of the substrate 8; and the second semiconductor layer 2 that includes the light emitting layer 3 is formed on the first semiconductor layer 1.
  • the surface of the first semiconductor layer 1 contacting the substrate 8 becomes the first surface 4a of the semiconductor layer 4.
  • first semiconductor layer 1 and the second semiconductor layer 2 are, for example, III-V nitride semiconductors
  • these can be deposited on, for example, a sapphire substrate, a Si substrate using MOCVD (Metal Organic Chemical Vapor Deposition).
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a portion of the first semiconductor layer 1 is exposed by removing a portion of the second semiconductor layer 2 as illustrated in FIG. 2B by, for example, RIE using a not-illustrated resist.
  • the portion where the first semiconductor layer 1 is exposed becomes the non-light emitting portion 6 which does not include the light emitting layer 3.
  • the second semiconductor layer 2 that remains in the protruding configuration becomes the light emitting portion 5 which includes the light emitting layer 3.
  • the insulating film 17 is formed on the entire surface of the second surface of the semiconductor layer 4 which includes the light emitting portion 5 and the non-light emitting portion 6.
  • the insulating film 17 is, for example, a silicon oxide film.
  • the n-side contact electrode 14 is formed on the front surface of the non-light emitting portion 6 inside the second opening 17b.
  • the resist mask 61 used during the etching that made the second opening 17b remains; and the n-side contact electrode 14 is formed by, for example, vapor deposition using the resist mask 61 as a mask.
  • the contact electrode is formed continuing from the etching of the opening using the same resist mask. Therefore, the bottom face of the opening is not covered with the resist mask. Therefore, the contact electrode can be formed on the exposed surface as-is after the etching; and the increase of the contact resistance can be suppressed.
  • the first opening 17a and the second opening 17b may be made simultaneously; the resist mask used in the etching of these openings may remain as-is; and the p-side contact electrode 13 and the n-side contact electrode 14 may be formed simultaneously from the same material continuing from the etching.
  • a resist mask 52 is formed on the insulating film 17 as illustrated in FIG. 4B.
  • An opening 52a and an opening 52b are made in the resist mask 52.
  • the resist mask 52 is formed such that a portion of the insulating film 17 is exposed from the opening 52a and the opening 52b of the resist mask 52.
  • the resist mask 52 is formed such that the inner wall of the first opening 17a, the inner wall of the second opening 17b, and the flat portion (the top surface) of the insulating film 17 are exposed.
  • the p-side metal protective film 15 and the n-side metal protective film 16 are formed using the resist mask 52 as a mask.
  • the p-side metal protective film 15 and the n-side metal protective film 16 are formed simultaneously using, for example, vapor deposition.
  • a gap is made between the inner wall of the first opening 17a and the side surface of the p-side contact electrode 13.
  • the gap also is exposed at the bottom portion of the opening 52a. Accordingly, the p-side metal protective film 15 fills the gap and covers the side surface of the p-side contact electrode 13.
  • the p-side metal protective film 15 covers the step-like portion that extends from the inner wall of the first opening 17a over the top surface of the insulating film 17; and the planar size of the p-side metal protective film 15 is larger than the planar size of the p-side contact electrode 13.
  • the inner wall of the first opening 17a is separate from the side surface of the p-side contact electrode 13. Therefore, the entire side surface of the p-side contact electrode 13 in the thickness direction is exposed in the state prior to the forming of the p-side metal protective film 15. Accordingly, the p-side metal protective film 15 can reliably cover all of the exposed surfaces of the p-side contact electrode 13. At this time, the p-side metal protective film 15 has a concave configuration.
  • One other opening 52b made in the resist mask 52 is made on the second opening 17b made in the insulating film 17; and the width of the opening 52b is wider than the width of the second opening 17b.
  • the top surface of the n-side contact electrode 14 is exposed at the bottom portion of the opening 52b.
  • the n-side metal protective film 16 is formed on the bottom portion of the opening 52b. Accordingly, the n-side metal protective film 16 covers the top surface of the n-side contact electrode 14.
  • a gap is made between the inner wall of the second opening 17b and the side surface of the n-side contact electrode 14.
  • the gap also is exposed at the bottom portion of the opening 52b. Accordingly, the n-side metal protective film 16 fills the gap and covers the side surface of the n-side contact electrode 14.
  • the n-side metal protective film 16 covers the step-like portion that extends from the inner wall of the second opening 17b over the top surface of the insulating film 17; and the planar size of the n-side metal protective film 16 is larger than the planar size of the n-side contact electrode 14.
  • the inner wall of the second opening 17b is separate from the side surface of the n-side contact electrode 14. Therefore, the entire side surface of the n-side contact electrode 14 in the thickness direction is exposed in the state prior to the forming of the n-side metal protective film 16. Accordingly, the n-side metal protective film 16 can reliably cover all of the exposed surfaces of the n-side contact electrode 14. At this time, the n-side metal protective film 16 has a concave configuration.
  • a trench 62 piercing the first semiconductor layer 1 is made to reach the substrate 8 by, for example, Reactive Ion Etching (RIE) using a resist mask 53.
  • RIE Reactive Ion Etching
  • An opening 53a is made in the resist mask 53; and the trench 62 is made under the opening 53a.
  • the trench 62 is made in the dicing region formed in, for example, a lattice configuration on the substrate 8 in the wafer state.
  • the trench 62 also is made in, for example, a lattice configuration and separates the semiconductor layer 4 into multiple chips on the substrate 8.
  • the resist used when forming the p-side contact electrode 13, the n-side contact electrode 14, the p-side metal protective film 15, and the n-side metal protective film 16 can be easily coated onto the second surface side which has no large unevenness in the case where the trench 62 is made after forming the p-side contact electrode 13, the n-side contact electrode 14, the p-side metal protective film 15, and the n-side metal protective film 16.
  • the insulating film 17 of the dicing region Prior to the forming of the resist mask 53, the insulating film 17 of the dicing region is removed as illustrated in FIG. 5A. During the etching that makes the trench 62, the resist mask 53 is consumed also in the surface direction. In other words, the width of the opening 53a widens from the position illustrated by the solid line to the position illustrated by the double dot-dash line. The insulating film 17 of the dicing region is removed beforehand such that the insulating film 17 is not exposed by the widening of the opening 53a at this time.
  • the insulating film 17 of the dicing region is undesirably exposed by the consumption of the resist mask 53, the insulating film 17 substantially becomes the etching mask thereafter; and as illustrated by the broken line in FIG. 5B, a step easily forms undesirably in the side wall of the trench 62 (the side surface of the first semiconductor layer 1). This step may cause cracks to occur in the semiconductor layer 4 when removing the substrate 8 described below by laser lift-off or chemical wet etching off.
  • the problem recited above can be avoided by removing the insulating film 17 beforehand such that the insulating film 17 is not exposed inside the opening 53a of the resist mask 53 that was widened during the etching.
  • the trench 62 may be made prior to the forming of the p-side contact electrode 13, the n-side contact electrode 14, the p-side metal protective film 15, and the n-side metal protective film 16.
  • the first via 18a and the second via 18b are made in the insulating layer 18.
  • the first via 18a reaches the p-side metal protective film 15.
  • the second via 18b reaches the n-side metal protective film 16.
  • the insulating layer 18 is filled into the trench 62.
  • An organic material such as, for example, photosensitive polyimide, benzocyclobutene, etc., can be used as the insulating layer 18. In such a case, it is possible to directly perform the exposure and the development of the insulating layer 18 without using a resist.
  • an inorganic film such as a silicon nitride film, a silicon oxide film, etc., may be used as the insulating layer 18. In the case of an inorganic film, the first via 18a and the second via 18b are obtained by etching after the resist is patterned.
  • the outermost surfaces of the p-side metal protective film 15 and the n-side metal protective film 16 are films such as, for example, titanium (Ti), nickel (Ni), molybdenum (Mo), etc., which have good adhesion with polyimide.
  • a titanium (Ti) film is formed first by sputtering; and subsequently, a copper (Cu) film is formed on the titanium film by sputtering.
  • a clean surface of the gold (Au) is exposed at the outermost surface of the p-side metal protective film 15 and the outermost surface of the n-side metal protective film 16 by the sputter etching or the milling recited above.
  • the metal film 19 is formed by forming a titanium (Ti) film, which has excellent adhesion with gold, on the clean surface of the gold (Au) and by forming a copper (Cu) film on the titanium film. Thereby, the adhesion can be improved between the metal film 19, which is the power supply layer for the plating, and the metal protective films 15 and 16.
  • the metal film 19 is unnecessary in the case where the interconnect layers are not formed using plating.
  • a resist (not illustrated) is formed selectively on the metal film 19; and Cu electroplating is performed using the metal film 19 as the power supply layer.
  • the coverability of differences in levels degrades easily at the portions where the difference in levels of the underlying insulating layer 18 (portions 80 and 90 enclosed with the broken line in FIG. 7A) is large; and breakage of the metal film 19 occurs easily at the portions 80 and 90.
  • the breakage of the p-side metal protective film 15 occurs less easily.
  • the n-side metal protective film 16 being thicker than the n-side contact electrode 14, the breakage of the n-side metal protective film 16 occurs less easily.
  • the p-side metal pillar 23 and the n-side metal pillar 24, which function as the external terminals, are separated by a distance such that the p-side metal pillar 23 and the n-side metal pillar 24 are not shorted to each other by the solder, etc., when mounting to the mounting substrate.
  • the first surface 4a of the semiconductor layer 4 from which the substrate 8 is removed is cleaned.
  • the gallium (Ga) adhered to the first surface 4a is removed using, for example, hydrochloric acid, etc.
  • the first surface 4a is etched using, for example, a KOH (potassium hydroxide) aqueous solution, TMAH (tetramethylammonium hydroxide), etc.
  • a KOH potassium hydroxide
  • TMAH tetramethylammonium hydroxide
  • an unevenness is formed in the first surface 4a due to the difference of the etching rates that depend on the crystal plane orientation.
  • the unevenness may be formed in the first surface 4a by performing the etching after the patterning using the resist. The light extraction efficiency can be increased by the unevenness being formed in the first surface 4a.
  • the process of forming the phosphor layer 27 includes, for example, a process of supplying a liquid transparent resin having dispersed phosphor particles using a method such as printing, potting, molding, compression molding, etc., and a subsequent process of thermal curing.
  • the transparent resin is transmissive to the light emitted from the light emitting layer 3 and the light emitted by the phosphor; and, for example, a material such as a silicone resin, an acrylic resin, liquid glass, etc., may be used.
  • the resin layer 25, the insulating layer 18, the phosphor layer 27, and the lens 26 are cut at the position of the trench 62 to singulate into the multiple semiconductor light emitting device 10.
  • the cutting is performed using a dicing blade.
  • the cutting may be performed using laser irradiation.
  • the singulated semiconductor light emitting device 10 may have a single-chip structure including one semiconductor layer 4 or a multi-chip structure including multiple semiconductor layers 4.
  • the p-side metal protective film 15 and the n-side metal protective film 16 protect the p-side contact electrode 13 and the n-side contact electrode 14 from the chemical liquids, etc., used in the processes performed after the formation of these contact electrodes.
  • the p-side metal protective film 15 and the n-side metal protective film 16 also protect the p-side contact electrode 13 and the n-side contact electrode 14 from the sulfur, etc., in the air that permeates into the insulating layer 18. As a result, the corrosion and the increased resistance of the p-side contact electrode 13 and the n-side contact electrode 14 can be prevented.
  • a gap can be made between the inner wall of the first opening 17a and the side surface of the p-side contact electrode 13 by forming the inner wall of the first opening 17a as a tapered surface.
  • the side surface of the p-side contact electrode 13 can be covered with the p-side metal protective film 15 by filling the p-side metal protective film 15 into the gap.
  • a gap can be made between the inner wall of the second opening 17b and the side surface of the n-side contact electrode 14 by forming the inner wall of the second opening 17b as a tapered surface.
  • the side surface of the n-side contact electrode 14 can be covered with the n-side metal protective film 16 by filling the n-side metal protective film 16 into the gap.
  • the entire side surface of the p-side contact electrode 13 can be reliably covered with the p-side metal protective film 15 by the inner wall of the bottom portion of the first opening 17a on the second semiconductor layer 2 side being separate from the side surface of the p-side contact electrode 13.
  • the entire side surface of the n-side contact electrode 14 can be reliably covered with the n-side metal protective film 16 by the inner wall of the bottom portion of the second opening 17b on the first semiconductor layer 1 side being separate from the side surface of the n-side contact electrode 14.
  • the substrate 8 may thinly remain on the first surface 4a.
  • the substrate 8 can be polished using, for example, a grinder for polishing a semiconductor wafer back face, etc.
  • the substrate 8 is, for example, a sapphire substrate and is transmissive to the light emitted from the nitride semiconductor-type light emitting layer. In such a case, because there is no phosphor layer, light having the same wavelength as the light emitted from the light emitting layer is emitted to the outside from the semiconductor light emitting device. The mechanical strength can be increased and a structure having high reliability is possible by leaving the substrate 8.
  • the phosphor layer 27 may be formed on the substrate 8.
  • the p-side metal protective film 15 functions as the p-side external terminal
  • the n-side metal protective film 16 functions as the n-side external terminal.
  • the p-side metal protective film 15 and the n-side metal protective film 16 are bonded to pads of the mounting substrate with solder, etc. It is not always necessary for any of the substrate 8, the lens 26, and the phosphor layer 27 to be on the first surface 4a.
  • the red phosphor layer, the yellow phosphor layer, the green phosphor layer, and the blue phosphor layer described below can be used as the phosphor layer described above.
  • the red phosphor layer can contain, for example, a nitride-based phosphor of CaAlSiN 3 :Eu or a SiAlON-based phosphor.
  • (M 1-x , R x ) a1 AlSi b1 O c1 N d1 Compositional Formula (1) can be used (where M is at least one type of metal element excluding Si and Al, and it may be desirable for M to be at least one selected from Ca and Sr; R is a light emission center element, and it may be desirable for R to be Eu; and x, a1, b1, c1, and d1 satisfy the following relationships: x is larger than 0 and 1 or less, a1 is larger than 0.6 and less than 0.95, b1 is larger than 2 and less than 3.9, c1 is larger than 0.25 and less than 0.45, and d1 is larger than 4 and less than 5.7).
  • the temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current density region can be increased further.
  • the yellow phosphor layer can contain, for example, a silicate-based phosphor of (Sr, Ca, Ba) 2 SiO 4 :Eu.
  • the green phosphor layer can contain, for example, a halophosphate-based phosphor of (Ba, Ca, Mg) 10 (PO 4 ) 6 Cl 2 :Eu or a SiAlON-based phosphor.
  • (M 1-x , R x ) a2 AlSi b2 O c2 N d2 Compositional Formula (2) can be used (where M is at least one type of metal element excluding Si and Al, and it may be desirable for M to be at least one selected from Ca and Sr; R is a light emission center element, and it may be desirable for R to be Eu; and x, a2, b2, c2, and d2 satisfy the following relationships: x is larger than 0 and 1 or less, a2 is larger than 0.93 and less than 1.3, b2 is larger than 4.0 and less than 5.8, c2 is larger than 0.6 and less than 1, and d2 is larger than 6 and less than 11).
  • the temperature characteristics of the wavelength conversion efficiency can be improved; and the efficiency in the high current density region can be increased further.
  • the blue phosphor layer can contain, for example, an oxide-based phosphor of BaMgAl 10 O 17 :Eu.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

Dans un mode de réalisation, un dispositif semi-conducteur électroluminescent comprend une couche semi-conductrice (4), un film isolant (17), une électrode de contact côté p (13), une électrode de contact côté n (14), un film métallique de protection côté p (17) et un film métallique de protection côté n. La couche semi-conductrice comprend une couche électroluminescente (13). Une seconde surface de la couche semi-conductrice est formée sur un côté opposé à la première surface. La seconde surface comprend une partie électroluminescente qui comprend la couche électroluminescente et une partie non électroluminescente qui ne comprend pas la couche électroluminescente. L'électrode de contact côté p est mise au contact de la partie électroluminescente à l'intérieur d'une première ouverture du film d'isolation. L'électrode de contact côté n est mise au contact de la partie non électroluminescente à l'intérieur d'une seconde ouverture du film d'isolation. Le film métallique de protection côté p recouvre une surface supérieure et une surface latérale de l'électrode de contact côté p. Le film métallique de protection côté n recouvre une surface supérieure et une surface latérale de l'électrode de contact côté n.
PCT/JP2011/004536 2011-02-10 2011-08-10 Électrode résistant à la corrosion pour un dispositif semi-conducteur électroluminescent, ainsi que procédé de fabrication de celle-ci WO2012107973A1 (fr)

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US9029893B2 (en) 2013-02-18 2015-05-12 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing the same
US9812611B2 (en) 2015-04-03 2017-11-07 Soko Kagaku Co., Ltd. Nitride semiconductor ultraviolet light-emitting element and nitride semiconductor ultraviolet light-emitting device
EP3213354B1 (fr) * 2014-10-27 2020-06-17 Lumileds Holding B.V. Dispositif d'émission de lumière directionnelle et son procédé de production
CN114141921A (zh) * 2020-09-04 2022-03-04 光波株式会社 紫外线发光器件和包括其的发光器件封装件

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TWI667812B (zh) * 2014-05-19 2019-08-01 晶元光電股份有限公司 光電元件及其製造方法
JP6318991B2 (ja) * 2014-08-30 2018-05-09 日亜化学工業株式会社 発光装置の製造方法
KR102323686B1 (ko) 2014-10-21 2021-11-11 서울바이오시스 주식회사 발광 소자 및 그 제조 방법
DE102015114579B4 (de) * 2015-09-01 2021-07-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiterchip
EP3724931B1 (fr) * 2017-12-14 2023-02-15 Lumileds LLC Procédé de prévention de la contamination d'une puce led
TWI714319B (zh) * 2019-10-28 2020-12-21 錼創顯示科技股份有限公司 微型發光二極體裝置

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CN114141921A (zh) * 2020-09-04 2022-03-04 光波株式会社 紫外线发光器件和包括其的发光器件封装件
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