WO2012102342A1 - Power amplifier circuit, as well as transmission device and communication device using same - Google Patents

Power amplifier circuit, as well as transmission device and communication device using same Download PDF

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Publication number
WO2012102342A1
WO2012102342A1 PCT/JP2012/051662 JP2012051662W WO2012102342A1 WO 2012102342 A1 WO2012102342 A1 WO 2012102342A1 JP 2012051662 W JP2012051662 W JP 2012051662W WO 2012102342 A1 WO2012102342 A1 WO 2012102342A1
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Prior art keywords
signal
circuit
input
transistor
terminal
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PCT/JP2012/051662
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French (fr)
Japanese (ja)
Inventor
伸治 磯山
泰彦 福岡
昭 長山
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京セラ株式会社
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Publication of WO2012102342A1 publication Critical patent/WO2012102342A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
    • H03F1/0266—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0458—Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

Definitions

  • the present invention relates to a power amplifying circuit, a transmission device and a communication device using the same, and more particularly to a power amplifying circuit for amplifying a pulse signal and a transmission device and a communication device using the same.
  • a power amplifier circuit in which a signal is input to the gate terminal of a transistor and an amplified signal is output from the drain terminal of the transistor.
  • a DC blocking capacitor is provided between the input terminal and the gate terminal of the transistor. It is inserted (see, for example, Patent Document 1).
  • the above-described conventional power amplifier circuit has a problem that when the pulse signal is amplified, the efficiency decreases as the duty ratio increases.
  • the present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplifying circuit capable of amplifying a pulsed signal with high efficiency, and a transmission apparatus and communication using the same. To provide an apparatus.
  • the capacitor that outputs the second signal by inputting the first signal directly or with the amplitude changed, and the third signal or the first signal having a duty ratio equal to the first signal are input.
  • a conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal, and a second signal that is added to the gate terminal after the second signal and the fourth signal are added.
  • 1 transistor, a first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential, and a drain terminal of the first transistor And an output matching circuit connected thereto.
  • a pulse-shaped signal is a periodic and discrete signal.
  • the waveform is not limited to a rectangle, and includes a signal such as a half-end rectified wave, for example.
  • a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
  • FIG. 1 is a circuit diagram showing a power amplifier circuit of a first example of an embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing an example of the integrating circuit 8 in FIG.
  • FIG. 3 is a circuit diagram showing an example of the DC addition circuit 11 in FIG.
  • the power amplifier circuit of this example includes a terminal 1, a terminal 2, a transistor 4, an amplifier 5, a capacitor 6, an output matching circuit 16, a low-pass filter circuit 17, and a conversion.
  • the circuit 31 is provided.
  • the transistor 4 is an n-channel FET, and its pinch-off voltage (threshold voltage for flowing drain current) is Vp.
  • the capacitor 6 has one end connected to the terminal 1 via the amplifier 5 and the other end connected to the gate terminal of the transistor 4.
  • the capacitor 6 prevents the DC bias voltage applied to the gate terminal of the transistor 4 from being applied to the amplifier 5 and an external circuit (not shown) connected to the terminal 1.
  • the terminal 1 receives a first signal S1 which is a pulse signal from an external circuit (not shown).
  • the first signal S1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and input to the gate terminal of the transistor 4 as the second signal S2.
  • the conversion circuit 31 includes a detection circuit 7, an integration circuit 8, a DC addition circuit 11, and a resistor 15.
  • the detection circuit 7 is composed of one resistor and one diode connected in series. One end is connected to the terminal 1 and the other end is connected to the terminal 9 of the integrating circuit 8.
  • the diode is oriented such that the anode is located on the terminal 1 side and the cathode is located on the integrating circuit 8 side.
  • the integration circuit 8 is configured such that the terminal 9 and the terminal 10 are connected via a resistor 21 and the terminal 10 is connected to a ground potential via a capacitor 22. With such a configuration, a low-pass filter circuit is formed, thereby constituting an integrating circuit.
  • the integration circuit 8 outputs a signal having a DC voltage having a magnitude corresponding to the duty ratio of the first signal S1.
  • An active low-pass filter or a passive low-pass filter may be added to attenuate high-frequency components.
  • the DC adder circuit 11 includes resistors 23, 24, and 26, an OP amplifier 25, and terminals 12, 13, and 14, as shown in FIG.
  • One ends of the resistors 23 and 24 are connected to each other and connected to one end of the resistor 26 and one input terminal of the OP amplifier.
  • the other ends of the resistors 23 and 24 are connected to terminals 12 and 13, respectively.
  • Terminal 12 is connected to terminal 10 of integrating circuit 8.
  • Terminal 13 is connected to DC bias potential Vg.
  • the output terminal of the OP amplifier is connected to the other end of the resistor 26 and the terminal 14.
  • the DC addition circuit 11 adds the output signal of the integration circuit 8 input to the terminal 12 and the DC bias voltage Vg input to the terminal 13 and outputs the result from the terminal 14.
  • the resistor 15 has one end connected to the terminal 14 of the DC addition circuit 11 and the other end connected to the other end of the capacitor 6 and the gate terminal of the transistor 4.
  • the conversion circuit 31 having such a configuration receives the first signal S1 and outputs a fourth signal S4 having a DC voltage that increases or decreases according to the increase or decrease of the duty ratio of the first signal S1.
  • the input to the conversion circuit 31 may be any signal having the same duty ratio as that of the first signal S1.
  • the gate terminal of the transistor 4 is connected to the other end of the capacitor 6 and the other end of the resistor 15 of the conversion circuit 31.
  • the second signal S2 and the fourth signal S4 are added and input to the gate terminal of the transistor 4. .
  • the low-pass filter circuit 17 is composed of one inductor, and one end is connected to the drain terminal of the transistor 4 and the other end is connected to the power supply potential Vdd.
  • the low-pass filter circuit 17 supplies the power supply potential Vdd to the drain terminal of the transistor 4 and prevents a high-frequency signal from flowing out to the power supply potential Vdd side.
  • the output matching circuit 16 has one end connected to the drain terminal of the transistor 4 and the other end connected to the terminal 2.
  • the output matching circuit 16 is for matching the impedance between the drain terminal of the transistor 4 and the terminal 2.
  • the output matching circuit 16 can be configured, for example, by connecting a DC cut capacitor and an LC series resonance circuit that resonates at the fundamental frequency in series. With this configuration, only the fundamental wave component of the signal output from the drain terminal of the transistor 4 can be output from the terminal 2.
  • the power amplifier circuit of this example having such a configuration can amplify the first signal S1 input to the terminal 1 by the amplifier 5 and the transistor 4 and output it from the terminal 2. Further, according to the power amplifier circuit of this example, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
  • FIGS. 4A to 4D are graphs for explaining the effect of the present invention, in which the horizontal axis indicates time and the vertical axis indicates the voltage of the pulse signal.
  • Vp is a pinch-off voltage of the transistor 4, and a drain current corresponding to the voltage of the pulse signal flows while the voltage of the pulse signal input to the gate terminal of the transistor 4 exceeds Vp.
  • the first signal S1 input to the terminal 1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and the second signal S2 is input to the gate terminal of the transistor 4.
  • the first signal S1 is a pulse-like signal
  • the DC component is cut by the capacitor 6 so that the waveform of the pulse signal is entirely shifted to the negative voltage side.
  • the shift amount at this time is proportional to the average voltage of the pulse signal. Therefore, the shift amount increases in accordance with the duty ratio of the pulse signal, and becomes maximum when the duty ratio is 0.5.
  • FIG. 4A The waveform of a square pulse wave with a duty ratio of 0.5 before the DC component is cut is shown in FIG. 4A, and the waveform of a square pulse wave with a duty ratio of 0.5 after the DC component is cut is shown.
  • FIG. 4C shows a waveform of a square pulse wave with a duty ratio of 0.1 before the DC component is cut, and a square pulse wave with a duty ratio of 0.1 after the DC component is cut.
  • the waveform is shown in FIG.
  • the shift amount to the negative voltage side due to the cut of the direct current component is 1 / th of the wave height of the pulse signal. 2
  • the shift amount to the negative voltage side due to the cut of the direct current component is the wave height of the pulse signal. 1/10.
  • the DC cut capacitor When the direct current component is cut, the voltage of the signal input to the gate terminal of the transistor decreases, and the signal output from the drain terminal of the transistor decreases. This reduces the efficiency of the power amplifier circuit. And the efficiency of a power amplifier circuit falls large, so that the duty ratio of the signal input into a power amplifier circuit is large.
  • the fourth signal S4 having a DC voltage that increases or decreases in accordance with the increase or decrease of the duty ratio of the input signal (first signal S1) is output from the conversion circuit 31, and is converted into the second signal S2. The sum is added to the gate terminal of the transistor 4.
  • the power amplifier circuit of this example functions as a power amplifier circuit capable of amplifying a pulse signal with high efficiency. Note that the effect of the power amplifier circuit of this example increases as the duty ratio of the input first signal S1 increases.
  • the present invention is not limited to this.
  • the first signal S1 input from the terminal 1 may be input to the capacitor 6 as it is.
  • the conversion circuit 31, the detection circuit 7, the integration circuit 8, the DC addition circuit 11, the low-pass filter circuit 17, and the output matching circuit 16 are limited to the circuit configuration described above. is not. Each can be replaced with another circuit configuration having a similar function.
  • FIG. 5 is a circuit diagram showing a power amplifier circuit according to a second example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
  • the output matching circuit 16 includes a capacitor 18, an LC series resonance circuit 19, and a low-pass filter circuit 20.
  • the LC series resonance circuit 19 is connected in series between the input and output of the output matching circuit 16 (between the drain terminal and the terminal 2 of the transistor 4).
  • the LC series resonant circuit 19 is composed of one inductor and one capacitor connected in series with each other, and the inductance of the inductor and the capacitance of the capacitor so as to resonate at the fundamental frequency of the first signal S1. Is set.
  • the low-pass filter circuit 20 is cascade-connected to the LC series resonance circuit 19 and connects the LC series resonance circuit 19 and the terminal 2.
  • the low-pass filter circuit 20 is composed of a ⁇ -type circuit composed of two capacitors and one inductor.
  • the low-pass filter circuit 20 allows a signal having a fundamental frequency of the first signal S1 to pass therethrough and harmonics of the first signal S1.
  • the capacitance of the capacitor and the inductance of the inductor are set so as to attenuate the wave frequency signal.
  • the capacitor 18 is connected between the drain terminal of the first transistor 4 and a reference potential (ground potential).
  • the output matching circuit 16 since the output matching circuit 16 includes the cascaded LC series resonance circuit 19 and the low-pass filter circuit 20, an input signal (first output) In a region where the duty ratio of one signal S1) is large, a high and constant efficiency can be obtained. Although the mechanism for obtaining this effect has not been clearly identified, it is considered that the output matching circuit 16 reflects the harmonic component in the signal output from the drain terminal of the transistor 4.
  • the low-pass filter circuit 20 is not limited to a ⁇ -type circuit composed of two capacitors and one inductor.
  • the low-pass filter circuit 20 may be constituted by one inductor connected in series between the input and output and one capacitor connecting between the input and output and the ground potential.
  • the low-pass filter circuit 20 may be provided.
  • FIG. 6 is a circuit diagram showing a power amplifier circuit of a third example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
  • the power amplifier circuit of this example does not include terminal 1 as compared with the power amplifier circuit shown in FIG. 1, and includes transistor 33, transistor 34, terminal 41, terminal 42, and so on. Is further provided.
  • the fifth signal S5 is input from the external circuit (not shown) to the terminal 41
  • the sixth signal S6 is input from the external circuit (not shown) to the terminal 42.
  • the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases.
  • the transistors 33 and 34 are n-channel FETs, and their pinch-off voltage (threshold voltage for flowing a drain current) is Vp.
  • the transistor 33 has a gate terminal connected to the terminal 42, a source terminal connected to the terminal 41, and a drain terminal connected to the gate terminal of the transistor 4 via the amplifier 5 and the capacitor 6.
  • the fifth signal S5 is input to the source terminal
  • the sixth signal S6 is input to the gate terminal
  • the output signal from the drain terminal is input to the amplifier 5 as the first signal S1.
  • the transistor 34 has a gate terminal connected to the terminal 41, a source terminal connected to the terminal 42, and a drain terminal connected to one end of the detection circuit 7.
  • the sixth signal S6 is input to the source terminal
  • the fifth signal S5 is input to the gate terminal
  • the output signal from the drain terminal is input to one end of the detection circuit 7 as the third signal S3. Is done.
  • a DC bias voltage is supplied to the gate terminals of the transistors 33 and 34 from a bias circuit (not shown).
  • the transistors 33 and 34 are n-channel transistors, when a positive voltage equal to or higher than the pinch-off voltage Vp is applied to the gate terminal, the drain terminal and the source terminal become conductive. Therefore, the transistor 33 passes the fifth signal S5 and outputs it as the first signal S1 from the drain terminal while the voltage of the sixth signal S6 is a positive voltage equal to or higher than Vp. While the fifth signal S5 is a positive voltage equal to or higher than Vp, the transistor 34 passes the sixth signal S6 and outputs it from the drain terminal as the third signal S3.
  • the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases, the first signal S1 output from the drain terminal of the transistor 33 and the output from the drain terminal of the transistor 34 are output.
  • the third signal S3 is a pulse signal having the same duty ratio.
  • the first signal S1 is output from the drain terminal of the transistor 33 only while the voltage of the sixth signal S6 is a positive voltage higher than Vp, the period during which the first signal S1 is a positive voltage higher than Vp. Corresponds to a period in which both the fifth signal S5 and the sixth signal S6 are positive voltages larger than the pinch-off voltage Vp.
  • the first signal S1 is amplified by the amplifier 5, passes through the capacitor 6, is input to the gate terminal of the transistor 4 as the second signal S2, and the transistor 4 is turned on and off.
  • the time during which the transistor 4 is ON varies depending on the phase difference between the fifth signal S5 and the sixth signal S6. That is, when the phase difference between the fifth signal S5 and the sixth signal S6 is small, the time during which the transistor 4 is ON is long, and when the phase difference between the fifth signal S5 and the sixth signal S6 is large, the transistor The time during which 4 is ON is shortened. Thereby, the increase / decrease in the phase difference between the fifth signal S5 and the sixth signal S6 is replaced with the increase / decrease in the time during which the transistor 4 is in the ON state.
  • the drain voltage of the transistor 4 also includes the same frequency component as the fifth signal S5 and the sixth signal S6.
  • the fundamental wave component (the same frequency component as the fifth signal S5 and the sixth signal S6) is extracted from the drain voltage of the transistor 4 by the output matching circuit 16, and is output from the terminal 2.
  • This output signal has an amplitude that increases and decreases contrary to the increase and decrease of the phase difference between the fifth signal S5 and the sixth signal S6, and is an amplified signal obtained by synthesizing the fifth signal S5 and the sixth signal S6. .
  • the power amplifier circuit functions as a power amplifier circuit that can amplify and output two constant envelope signals by vector addition.
  • the voltage drop applied to the gate terminal of the transistor 4 that occurs when the phase difference between the fifth signal S5 and the sixth signal S6 is small can be reduced by the conversion circuit 31. Therefore, according to the power amplifier circuit of this example, it is possible to obtain a power amplifier circuit in which a decrease in amplification efficiency when the phase difference between the fifth signal S5 and the sixth signal S6 is large is reduced.
  • the sixth signal S6 is input to the gate terminal of the transistor 33 and the fifth signal S5 is input to the gate terminal of the transistor 34.
  • the signal input to the gate terminal of the transistor 33 may be a signal in phase with the sixth signal S6, and the signal input to the gate terminal of the transistor 34 may be a signal in phase with the fifth signal S5.
  • FIG. 7 is a circuit diagram showing a power amplifier circuit according to a fourth example of the embodiment of the present invention. 7, in addition to the power amplifier circuit 61 shown in FIG. 6, the power amplifier circuit of this example is configured to convert an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal S5. And a constant envelope signal generation circuit 62 that converts the second constant envelope signal to be the sixth signal S6 and outputs the second constant envelope signal.
  • the first constant envelope signal (fifth signal S5) and the second constant envelope signal (sixth signal S6) are constant envelope signals having the same frequency and amplitude and different phases.
  • the constant envelope signal generation circuit 62 various well-known constant envelope signal generation circuits can be used, and either a digital circuit or an analog circuit may be used.
  • the first constant envelope signal and the second constant signal having a phase difference that increases or decreases the input signal having the envelope fluctuation in the opposite direction to the increase or decrease in the amplitude of the input signal.
  • the first constant envelope signal and the second constant signal After being converted into an envelope signal, it can be amplified with high power supply efficiency, and an output signal having an amplified envelope variation can be output. Thereby, a power amplifier circuit with high power supply efficiency can be obtained.
  • FIG. 8 is a block diagram showing a transmission apparatus according to a fifth example of the embodiment of the present invention.
  • the transmission apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, and an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70. Yes.
  • the transmission signal output from the transmission circuit 81 is amplified using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a transmitter with low power consumption can be obtained.
  • FIG. 9 is a block diagram showing a communication apparatus according to a sixth example of the embodiment of the present invention.
  • the communication apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70, and an antenna 82. And a receiving circuit 83 connected thereto.
  • An antenna sharing circuit 84 is inserted between the antenna 82 and the power amplification circuit 70 and the reception circuit 83. That is, the power amplifying circuit 70 and the receiving circuit 83 are connected to the antenna 82 via the antenna sharing circuit 84.
  • the transmission signal output from the transmission circuit 81 is amplified using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a communication apparatus with low power consumption can be obtained.
  • the antenna sharing circuit 84 is not always necessary and may be omitted.
  • the transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V.
  • the power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V.
  • the input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.
  • the graph shown in FIG. 10 shows that the power amplifier circuit of the present invention has higher drain efficiency than the power amplifier circuit of the comparative example.
  • the difference between the drain efficiency of the power amplifier circuit of the present invention and the drain efficiency of the power amplifier circuit of the comparative example may increase. Recognize.
  • the transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V.
  • the power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V.
  • the input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.
  • the capacitance of the capacitor 18 was 0.3 pF.
  • the LC series resonance circuit 19 is composed of an inductor of 11.8 nH and a capacitor of 4.3 pF.
  • the low-pass filter circuit 20 is composed of a ⁇ -type circuit composed of 3.9 pF and 3 pF capacitors and a 19.1 nH inductor.
  • the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5).
  • the vertical axis represents drain efficiency.

Abstract

[Problem] To provide a power amplifier circuit capable of amplifying a pulsed signal with high efficiency as well as a transmission device and a communication device using the same. [Solution] This power amplifier circuit is provided with: a capacitor (6) into which is input a first signal (S1) and which outputs a second signal (S2); a conversion circuit (31) into which is input a third signal (S3) of the same duty ratio as the first signal (S1), or the first signal (S1), and which outputs a fourth signal (S4) having a DC voltage which increases or decreases according to an increase or decrease of the duty ratio of the signal which has been input; a transistor (4) for which the second signal (S2) and the fourth signal (S4) are summed and input into a gate terminal; a first lowpass filter circuit (17) such that one end is connected to the drain terminal of the transistor (4) and the other end is connected to a supply potential (Vdd); and an output matching circuit (16) which is connected to the drain terminal of the transistor (4).

Description

電力増幅回路ならびにそれを用いた送信装置および通信装置Power amplifier circuit and transmitter and communication device using the same
　本発明は、電力増幅回路ならびにそれを用いた送信装置および通信装置に関するものであり、特に、パルス状の信号を増幅する電力増幅回路ならびにそれを用いた送信装置および通信装置に関するものである。 The present invention relates to a power amplifying circuit, a transmission device and a communication device using the same, and more particularly to a power amplifying circuit for amplifying a pulse signal and a transmission device and a communication device using the same.
　従来、トランジスタのゲート端子に信号が入力されて、トランジスタのドレイン端子から増幅された信号を出力する電力増幅回路が知られている。このような電力増幅回路では、トランジスタのゲート端子に供給される直流バイアス電圧が前段側の回路に加わるのを防止するために、入力端子とトランジスタのゲート端子との間に直流遮断用のキャパシタが挿入される（例えば、特許文献１を参照。）。 Conventionally, a power amplifier circuit is known in which a signal is input to the gate terminal of a transistor and an amplified signal is output from the drain terminal of the transistor. In such a power amplifier circuit, in order to prevent the DC bias voltage supplied to the gate terminal of the transistor from being applied to the circuit on the previous stage, a DC blocking capacitor is provided between the input terminal and the gate terminal of the transistor. It is inserted (see, for example, Patent Document 1).
特開2010－21927号公報JP 2010-21927 A
　しかしながら、上述した従来の電力増幅回路においては、パルス状の信号を増幅するときには、デューティー比が大きくなると効率が低下するといった問題があった。 However, the above-described conventional power amplifier circuit has a problem that when the pulse signal is amplified, the efficiency decreases as the duty ratio increases.
　本発明はこのような従来の技術における問題点に鑑みて案出されたものであり、その目的は、パルス状の信号を高効率で増幅可能な電力増幅回路ならびにそれを用いた送信装置および通信装置を提供することにある。 The present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplifying circuit capable of amplifying a pulsed signal with high efficiency, and a transmission apparatus and communication using the same. To provide an apparatus.
　本発明の電力増幅回路は、第１信号が直接または振幅を変えて入力されて第２信号を出力するキャパシタと、前記第１信号とデューティー比が等しい第３信号または前記第１信号が入力されて、入力された信号のデューティー比の増減に応じて増減する直流電圧を有する第４信号を出力する変換回路と、前記第２信号および前記第４信号が加算されてゲート端子に入力される第１のトランジスタと、一方端が前記第１のトランジスタのドレイン端子に接続されているとともに他方端が電源電位に接続される第１の低域通過フィルタ回路と、前記第１のトランジスタのドレイン端子に接続された出力整合回路とを備えることを特徴とするものである。 In the power amplifier circuit of the present invention, the capacitor that outputs the second signal by inputting the first signal directly or with the amplitude changed, and the third signal or the first signal having a duty ratio equal to the first signal are input. A conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal, and a second signal that is added to the gate terminal after the second signal and the fourth signal are added. 1 transistor, a first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential, and a drain terminal of the first transistor And an output matching circuit connected thereto.
　なお、本明細書において、パルス状の信号とは、周期的かつ離散的な信号のことである。波形は矩形に限るものではなく、例えば、半端整流波のような信号も含むものである。 In addition, in this specification, a pulse-shaped signal is a periodic and discrete signal. The waveform is not limited to a rectangle, and includes a signal such as a half-end rectified wave, for example.
　本発明の電力増幅回路によれば、パルス状の信号を高効率で増幅可能な電力増幅回路を得ることができる。 According to the power amplifier circuit of the present invention, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
本発明の実施の形態の第１の例の電力増幅回路を示す回路図である。It is a circuit diagram showing a power amplifier circuit of the 1st example of an embodiment of the invention. 図１における積分回路の一例を示す回路図である。It is a circuit diagram which shows an example of the integration circuit in FIG. 図１におけるＤＣ加算器の一例を示す回路図である。It is a circuit diagram which shows an example of the DC adder in FIG. （ａ）～（ｄ）は、本発明の効果が得られるメカニズムを説明するための図である。(A)-(d) is a figure for demonstrating the mechanism in which the effect of this invention is acquired. 本発明の実施の形態の第２の例の電力増幅回路を示す回路図である。It is a circuit diagram which shows the power amplifier circuit of the 2nd example of embodiment of this invention. 本発明の実施の形態の第３の例の電力増幅回路を示す回路図である。It is a circuit diagram which shows the power amplifier circuit of the 3rd example of embodiment of this invention. 本発明の実施の形態の第４の例の電力増幅回路を示す回路図である。It is a circuit diagram which shows the power amplifier circuit of the 4th example of embodiment of this invention. 本発明の実施の形態の第５の例の送信装置を示すブロック図である。It is a block diagram which shows the transmission apparatus of the 5th example of embodiment of this invention. 本発明の実施の形態の第６の例の通信装置を示すブロック図である。It is a block diagram which shows the communication apparatus of the 6th example of embodiment of this invention. 本発明の実施の形態の第１の例の電力増幅回路および比較例の電力増幅回路のシミュレーション結果を示すグラフである。It is a graph which shows the simulation result of the power amplifier circuit of the 1st example of embodiment of this invention, and the power amplifier circuit of a comparative example. 本発明の実施の形態の第２の例の電力増幅回路のシミュレーション結果を示すグラフである。It is a graph which shows the simulation result of the power amplification circuit of the 2nd example of an embodiment of the invention.
　以下、本発明の電力増幅回路ならびにそれを用いた送信装置および通信装置を添付の図面を参照しつつ詳細に説明する。 Hereinafter, a power amplification circuit of the present invention and a transmission device and a communication device using the same will be described in detail with reference to the accompanying drawings.
　（実施の形態の第１の例）
  図１は本発明の実施の形態の第１の例の電力増幅回路を示す回路図である。図２は図１における積分回路８の一例を示す回路図である。図３は図１における直流加算回路11の一例を示す回路図である。 (First example of embodiment)
FIG. 1 is a circuit diagram showing a power amplifier circuit of a first example of an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the integrating circuit 8 in FIG. FIG. 3 is a circuit diagram showing an example of the DC addition circuit 11 in FIG.
　本例の電力増幅回路は、図１に示すように、端子１と、端子２と、トランジスタ４と、増幅器５と、キャパシタ６と、出力整合回路16と、低域通過フィルタ回路17と、変換回路31とを備えている。なお、トランジスタ４はｎチャネルＦＥＴであり、そのピンチオフ電圧（ドレイン電流を流す閾値電圧）をＶｐとする。 As shown in FIG. 1, the power amplifier circuit of this example includes a terminal 1, a terminal 2, a transistor 4, an amplifier 5, a capacitor 6, an output matching circuit 16, a low-pass filter circuit 17, and a conversion. The circuit 31 is provided. The transistor 4 is an n-channel FET, and its pinch-off voltage (threshold voltage for flowing drain current) is Vp.
　キャパシタ６は、一方端が増幅器５を介して端子１に接続されており、他方端がトランジスタ４のゲート端子に接続されている。キャパシタ６は、トランジスタ４のゲート端子に加えられる直流バイアス電圧が、増幅器５や端子１に接続される図示せぬ外部回路に加わるのを防止する。端子１には図示せぬ外部回路からパルス状の信号である第１信号Ｓ１が入力される。第１信号Ｓ１は、増幅器５で増幅され、キャパシタ６で直流成分がカットされて、第２信号Ｓ２としてトランジスタ４のゲート端子に入力される。 The capacitor 6 has one end connected to the terminal 1 via the amplifier 5 and the other end connected to the gate terminal of the transistor 4. The capacitor 6 prevents the DC bias voltage applied to the gate terminal of the transistor 4 from being applied to the amplifier 5 and an external circuit (not shown) connected to the terminal 1. The terminal 1 receives a first signal S1 which is a pulse signal from an external circuit (not shown). The first signal S1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and input to the gate terminal of the transistor 4 as the second signal S2.
　変換回路31は、検波回路７と、積分回路８と、直流加算回路11と、抵抗15とを備えている。検波回路７は、直列に接続された１つの抵抗および１つのダイオードで構成されており、一方端が端子１に接続されているとともに、他方端が積分回路８の端子９に接続されている。なお、ダイオードは、アノードが端子１側でカソードが積分回路８側に位置するような向きとされている。 The conversion circuit 31 includes a detection circuit 7, an integration circuit 8, a DC addition circuit 11, and a resistor 15. The detection circuit 7 is composed of one resistor and one diode connected in series. One end is connected to the terminal 1 and the other end is connected to the terminal 9 of the integrating circuit 8. The diode is oriented such that the anode is located on the terminal 1 side and the cathode is located on the integrating circuit 8 side.
　積分回路８は、図２に示すように、端子９と端子10とが抵抗21を介して接続されるとともに、端子10がキャパシタ22を介してグランド電位に接続されて構成されている。このような構成によって低域通過フィルタ回路が形成されており、これによって積分回路を構成している。積分回路８は、第１信号Ｓ１のデューティー比に応じた大きさを備える直流電圧を有する信号を出力する。なお、高周波成分を減衰させるためにアクティブローパスフィルタやパッシブローパスフィルタを追加しても構わない。 As shown in FIG. 2, the integration circuit 8 is configured such that the terminal 9 and the terminal 10 are connected via a resistor 21 and the terminal 10 is connected to a ground potential via a capacitor 22. With such a configuration, a low-pass filter circuit is formed, thereby constituting an integrating circuit. The integration circuit 8 outputs a signal having a DC voltage having a magnitude corresponding to the duty ratio of the first signal S1. An active low-pass filter or a passive low-pass filter may be added to attenuate high-frequency components.
　直流加算回路11は、図３に示すように、抵抗23，24，26と、ＯＰアンプ25と、端子12，13，14とを備えている。抵抗23，24の一方端同士が接続されて、抵抗26の一方端およびＯＰアンプの一方の入力端子に接続されている。抵抗23，24の他方端は、それぞれ端子12，13に接続されている。端子12は積分回路８の端子10に接続されている。端子13は直流バイアス電位Ｖｇに接続されている。ＯＰアンプの出力端は、抵抗26の他方端および端子14に接続されている。直流加算回路11は、端子12に入力された積分回路８の出力信号と、端子13に入力された直流バイアス電圧Ｖｇとを加算して、端子14から出力する。 The DC adder circuit 11 includes resistors 23, 24, and 26, an OP amplifier 25, and terminals 12, 13, and 14, as shown in FIG. One ends of the resistors 23 and 24 are connected to each other and connected to one end of the resistor 26 and one input terminal of the OP amplifier. The other ends of the resistors 23 and 24 are connected to terminals 12 and 13, respectively. Terminal 12 is connected to terminal 10 of integrating circuit 8. Terminal 13 is connected to DC bias potential Vg. The output terminal of the OP amplifier is connected to the other end of the resistor 26 and the terminal 14. The DC addition circuit 11 adds the output signal of the integration circuit 8 input to the terminal 12 and the DC bias voltage Vg input to the terminal 13 and outputs the result from the terminal 14.
　抵抗15は、一方端が直流加算回路11の端子14に接続されているとともに、他方端がキャパシタ６の他方端およびトランジスタ４のゲート端子に接続されている。 The resistor 15 has one end connected to the terminal 14 of the DC addition circuit 11 and the other end connected to the other end of the capacitor 6 and the gate terminal of the transistor 4.
　このような構成を備える変換回路31は、第１信号Ｓ１が入力されて、第１信号Ｓ１のデューティー比の増減に応じて増減する直流電圧を有する第４信号Ｓ４を出力する。なお、変換回路31に入力されるのは、第１信号Ｓ１とデューティー比が等しい信号であればよい。 The conversion circuit 31 having such a configuration receives the first signal S1 and outputs a fourth signal S4 having a DC voltage that increases or decreases according to the increase or decrease of the duty ratio of the first signal S1. Note that the input to the conversion circuit 31 may be any signal having the same duty ratio as that of the first signal S1.
　トランジスタ４のゲート端子は、キャパシタ６の他方端および変換回路31の抵抗15の他方端に接続されており、第２信号Ｓ２および第４信号Ｓ４が加算されてトランジスタ４のゲート端子に入力される。 The gate terminal of the transistor 4 is connected to the other end of the capacitor 6 and the other end of the resistor 15 of the conversion circuit 31. The second signal S2 and the fourth signal S4 are added and input to the gate terminal of the transistor 4. .
　低域通過フィルタ回路17は、１つのインダクタで構成されており、一方端がトランジスタ４のドレイン端子に接続されているとともに他方端が電源電位Ｖｄｄに接続されている。低域通過フィルタ回路17は、電源電位Ｖｄｄをトランジスタ４のドレイン端子に供給するとともに、高周波信号が電源電位Ｖｄｄ側へ流出するのを防止する。 The low-pass filter circuit 17 is composed of one inductor, and one end is connected to the drain terminal of the transistor 4 and the other end is connected to the power supply potential Vdd. The low-pass filter circuit 17 supplies the power supply potential Vdd to the drain terminal of the transistor 4 and prevents a high-frequency signal from flowing out to the power supply potential Vdd side.
　出力整合回路16は、一方端がトランジスタ４のドレイン端子に接続されており、他方端が端子２に接続されている。出力整合回路16は、トランジスタ４のドレイン端子と端子２との間でインピーダンスを整合させるものである。出力整合回路16は、例えば、ＤＣカットキャパシタと、前記基本波の周波数で共振するＬＣ直列共振回路とを直列に接続して構成することができる。このような構成にすると、トランジスタ４のドレイン端子から出力される信号の基本波成分のみを端子２から出力することができる。 The output matching circuit 16 has one end connected to the drain terminal of the transistor 4 and the other end connected to the terminal 2. The output matching circuit 16 is for matching the impedance between the drain terminal of the transistor 4 and the terminal 2. The output matching circuit 16 can be configured, for example, by connecting a DC cut capacitor and an LC series resonance circuit that resonates at the fundamental frequency in series. With this configuration, only the fundamental wave component of the signal output from the drain terminal of the transistor 4 can be output from the terminal 2.
　このような構成を備える本例の電力増幅回路は、端子１に入力された第１信号Ｓ１を増幅器５およびトランジスタ４で増幅して端子２から出力することができる。また、本例の電力増幅回路によれば、パルス信号を高効率で増幅可能な電力増幅回路を得ることができる。 The power amplifier circuit of this example having such a configuration can amplify the first signal S1 input to the terminal 1 by the amplifier 5 and the transistor 4 and output it from the terminal 2. Further, according to the power amplifier circuit of this example, a power amplifier circuit capable of amplifying a pulse signal with high efficiency can be obtained.
　この効果が得られるメカニズムを図４（ａ）～（ｄ）を用いて説明する。図４（ａ）～（ｄ）は本発明の効果を説明するためのグラフであり、横軸は時間を示し、縦軸はパルス信号の電圧を示す。また、Ｖｐは、トランジスタ４のピンチオフ電圧であり、トランジスタ４のゲート端子に入力されるパルス信号の電圧がＶｐを超えている間、パルス信号の電圧に応じたドレイン電流が流れる。 The mechanism for obtaining this effect will be described with reference to FIGS. 4A to 4D are graphs for explaining the effect of the present invention, in which the horizontal axis indicates time and the vertical axis indicates the voltage of the pulse signal. Vp is a pinch-off voltage of the transistor 4, and a drain current corresponding to the voltage of the pulse signal flows while the voltage of the pulse signal input to the gate terminal of the transistor 4 exceeds Vp.
　端子１に入力された第１信号Ｓ１は、増幅器５で増幅された後に、キャパシタ６によって直流成分がカットされて、第２信号Ｓ２がトランジスタ４のゲート端子に入力される。第１信号Ｓ１がパルス状の信号であるとき、キャパシタ６によって直流成分がカットされることにより、パルス信号の波形が負電圧側へ全体的にシフトする。このときのシフト量は、パルス状の信号の平均電圧に比例する。よって、シフト量は、パルス状の信号のデューティー比に応じて増加し、デューティー比が0.5のときに最大となる。 The first signal S1 input to the terminal 1 is amplified by the amplifier 5, the direct current component is cut by the capacitor 6, and the second signal S2 is input to the gate terminal of the transistor 4. When the first signal S1 is a pulse-like signal, the DC component is cut by the capacitor 6 so that the waveform of the pulse signal is entirely shifted to the negative voltage side. The shift amount at this time is proportional to the average voltage of the pulse signal. Therefore, the shift amount increases in accordance with the duty ratio of the pulse signal, and becomes maximum when the duty ratio is 0.5.
　デューティー比が0.5の方形のパルス波の、直流成分がカットされる前の波形を図４（ａ）に示し、デューティー比が0.5の方形のパルス波の、直流成分がカットされた後の波形を図４（ｂ）に示す。また、デューティー比が0.1の方形のパルス波の、直流成分がカットされる前の波形を図４（ｃ）に示し、デューティー比が0.1の方形のパルス波の、直流成分がカットされた後の波形を図４（ｄ）に示す。 The waveform of a square pulse wave with a duty ratio of 0.5 before the DC component is cut is shown in FIG. 4A, and the waveform of a square pulse wave with a duty ratio of 0.5 after the DC component is cut is shown. As shown in FIG. FIG. 4C shows a waveform of a square pulse wave with a duty ratio of 0.1 before the DC component is cut, and a square pulse wave with a duty ratio of 0.1 after the DC component is cut. The waveform is shown in FIG.
　図４（ａ），（ｂ）に示すように、デューティー比が0.5の方形のパルス信号の場合、直流成分がカットされることによる負電圧側へのシフト量は、パルス信号の波高の１／２になる。また、図４（ｃ），（ｄ）に示すように、デューティー比が0.1の方形のパルス信号の場合、直流成分がカットされることによる負電圧側へのシフト量は、パルス信号の波高の１／10になる。 As shown in FIGS. 4A and 4B, in the case of a square pulse signal with a duty ratio of 0.5, the shift amount to the negative voltage side due to the cut of the direct current component is 1 / th of the wave height of the pulse signal. 2 As shown in FIGS. 4C and 4D, in the case of a square pulse signal with a duty ratio of 0.1, the shift amount to the negative voltage side due to the cut of the direct current component is the wave height of the pulse signal. 1/10.
　このように、入力されたパルス状の信号を、ＤＣカットキャパシタを介してトランジスタのゲート端子に入力して、トランジスタのドレイン端子から増幅後の信号を出力する電力増幅回路においては、ＤＣカットキャパシタによって直流成分がカットされることにより、トランジスタのゲート端子に入力される信号の電圧が低下して、トランジスタのドレイン端子から出力される信号が小さくなる。これによって電力増幅回路の効率は低下する。そして、電力増幅回路に入力される信号のデューティー比が大きいほど、電力増幅回路の効率は大きく低下する。 In this way, in the power amplifier circuit that inputs the input pulse-like signal to the gate terminal of the transistor via the DC cut capacitor and outputs the amplified signal from the drain terminal of the transistor, the DC cut capacitor When the direct current component is cut, the voltage of the signal input to the gate terminal of the transistor decreases, and the signal output from the drain terminal of the transistor decreases. This reduces the efficiency of the power amplifier circuit. And the efficiency of a power amplifier circuit falls large, so that the duty ratio of the signal input into a power amplifier circuit is large.
　本例の電力増幅回路では、入力される信号（第１信号Ｓ１）のデューティー比の増減に応じて増減する直流電圧を有する第４信号Ｓ４が変換回路31から出力されて、第２信号Ｓ２に加算されてトランジスタ４のゲート端子に入力される。第１信号Ｓ１のデューティー比が増加すると、それに伴って第４信号Ｓ４の電圧が高くなるので、トランジスタ４のゲート端子に加わる信号の電圧低下を低減することができる。よって、本例の電力増幅回路は、パルス状の信号を高効率で増幅可能な電力増幅回路として機能する。なお、入力される第１信号Ｓ１のデューティー比が大きいほど、本例の電力増幅回路の効果も大きくなる。 In the power amplifier circuit of this example, the fourth signal S4 having a DC voltage that increases or decreases in accordance with the increase or decrease of the duty ratio of the input signal (first signal S1) is output from the conversion circuit 31, and is converted into the second signal S2. The sum is added to the gate terminal of the transistor 4. As the duty ratio of the first signal S1 increases, the voltage of the fourth signal S4 increases accordingly, so that the voltage drop of the signal applied to the gate terminal of the transistor 4 can be reduced. Therefore, the power amplifier circuit of this example functions as a power amplifier circuit capable of amplifying a pulse signal with high efficiency. Note that the effect of the power amplifier circuit of this example increases as the duty ratio of the input first signal S1 increases.
　なお、本例の電力増幅回路においては、端子１から入力された第１信号Ｓ１が増幅器５で増幅された後に、キャパシタ６に入力される例を示したが、これに限定されるものではない。例えば、端子１から入力された第１信号Ｓ１が、そのままキャパシタ６に入力されるようにしても構わない。 In the power amplifier circuit of this example, the example in which the first signal S1 input from the terminal 1 is amplified by the amplifier 5 and then input to the capacitor 6 is shown, but the present invention is not limited to this. . For example, the first signal S1 input from the terminal 1 may be input to the capacitor 6 as it is.
　また、本例の電力増幅回路において、変換回路31，検波回路７，積分回路８，直流加算回路11，低域通過フィルタ回路17および出力整合回路16としては、前述した回路構成に限定されるものではない。同様の機能を有する他の回路構成にそれぞれ置き換えることが可能である。 In the power amplifier circuit of this example, the conversion circuit 31, the detection circuit 7, the integration circuit 8, the DC addition circuit 11, the low-pass filter circuit 17, and the output matching circuit 16 are limited to the circuit configuration described above. is not. Each can be replaced with another circuit configuration having a similar function.
　（実施の形態の第２の例）
  図５は、本発明の実施の形態の第２の例の電力増幅回路を示す回路図である。なお、本例においては前述した実施の形態の第１の例と異なる点のみについて説明し、同様の構成要素については同一の参照符号を用いて重複する説明を省略する。 (Second example of embodiment)
FIG. 5 is a circuit diagram showing a power amplifier circuit according to a second example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
　本例の電力増幅回路においては、図５に示すように、出力整合回路16が、キャパシタ18と、ＬＣ直列共振回路19と、低域通過フィルタ回路20とによって構成されている。 In the power amplifier circuit of this example, as shown in FIG. 5, the output matching circuit 16 includes a capacitor 18, an LC series resonance circuit 19, and a low-pass filter circuit 20.
　ＬＣ直列共振回路19は、出力整合回路16の入出力間（トランジスタ４のドレイン端子と端子２との間）に直列に接続されている。また、ＬＣ直列共振回路19は、互いに直列に接続された１つのインダクタと１つのキャパシタとで構成されており、第１信号Ｓ１の基本波の周波数で共振するようにインダクタのインダクタンスおよびキャパシタのキャパシタンスが設定されている。 The LC series resonance circuit 19 is connected in series between the input and output of the output matching circuit 16 (between the drain terminal and the terminal 2 of the transistor 4). The LC series resonant circuit 19 is composed of one inductor and one capacitor connected in series with each other, and the inductance of the inductor and the capacitance of the capacitor so as to resonate at the fundamental frequency of the first signal S1. Is set.
　低域通過フィルタ回路20は、ＬＣ直列共振回路19に縦続接続されており、ＬＣ直列共振回路19と端子２とを接続している。また、低域通過フィルタ回路20は、２つのキャパシタと１つのインダクタとからなるπ型回路によって構成されており、第１信号Ｓ１の基本波の周波数の信号を通過させるとともに第１信号Ｓ１の高調波の周波数の信号を減衰させるように、キャパシタのキャパシタンスおよびインダクタのインダクタンスが設定されている。 The low-pass filter circuit 20 is cascade-connected to the LC series resonance circuit 19 and connects the LC series resonance circuit 19 and the terminal 2. The low-pass filter circuit 20 is composed of a π-type circuit composed of two capacitors and one inductor. The low-pass filter circuit 20 allows a signal having a fundamental frequency of the first signal S1 to pass therethrough and harmonics of the first signal S1. The capacitance of the capacitor and the inductance of the inductor are set so as to attenuate the wave frequency signal.
  キャパシタ18は、第１のトランジスタ４のドレイン端子と基準電位（グランド電位）との間に接続されている。 The capacitor 18 is connected between the drain terminal of the first transistor 4 and a reference potential (ground potential).
　このような構成を備える本例の電力増幅回路は、出力整合回路16が、縦続接続されたＬＣ直列共振回路19および低域通過フィルタ回路20を有していることから、入力される信号（第１信号Ｓ１）のデューティー比が大きい領域において、高く一定の効率を得ることができる。この効果が得られるメカニズムは明確に特定できていないが、トランジスタ４のドレイン端子から出力される信号における高調波成分を出力整合回路16が反射するためではないかと考えられる。 In the power amplifier circuit of this example having such a configuration, since the output matching circuit 16 includes the cascaded LC series resonance circuit 19 and the low-pass filter circuit 20, an input signal (first output) In a region where the duty ratio of one signal S1) is large, a high and constant efficiency can be obtained. Although the mechanism for obtaining this effect has not been clearly identified, it is considered that the output matching circuit 16 reflects the harmonic component in the signal output from the drain terminal of the transistor 4.
　なお、低域通過フィルタ回路20は、２つのキャパシタと１つのインダクタとからなるπ型回路に限定されるものではない。例えば、入出力間に直列に接続された１つのインダクタと、入出力間とグランド電位との間を接続する１つのキャパシタとで構成された低域通過フィルタ回路20としても良く、他の回路構成を備えた低域通過フィルタ回路20としても構わない。 The low-pass filter circuit 20 is not limited to a π-type circuit composed of two capacitors and one inductor. For example, the low-pass filter circuit 20 may be constituted by one inductor connected in series between the input and output and one capacitor connecting between the input and output and the ground potential. The low-pass filter circuit 20 may be provided.
　（実施の形態の第３の例）
  図６は、本発明の実施の形態の第３の例の電力増幅回路を示す回路図である。なお、本例においては前述した実施の形態の第１の例と異なる点のみについて説明し、同様の構成要素については同一の参照符号を用いて重複する説明を省略する。 (Third example of embodiment)
FIG. 6 is a circuit diagram showing a power amplifier circuit of a third example of the embodiment of the present invention. Note that in this example, only differences from the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.
　本例の電力増幅回路は、図６に示すように、図１に示した電力増幅回路と比較すると、端子１を備えておらず、トランジスタ33と、トランジスタ34と、端子41と、端子42とをさらに備えている。本例の電力増幅回路では、第５信号Ｓ５が、図示せぬ外部回路から端子41に入力されるとともに、第６信号Ｓ６が、図示せぬ外部回路から端子42に入力される。なお、第５信号Ｓ５および第６信号Ｓ６は、互いに周波数および振幅が等しく位相が異なる定包絡線信号である。また、トランジスタ33，34はｎチャネルＦＥＴであり、そのピンチオフ電圧（ドレイン電流を流す閾値電圧）をＶｐとする。 As shown in FIG. 6, the power amplifier circuit of this example does not include terminal 1 as compared with the power amplifier circuit shown in FIG. 1, and includes transistor 33, transistor 34, terminal 41, terminal 42, and so on. Is further provided. In the power amplifier circuit of this example, the fifth signal S5 is input from the external circuit (not shown) to the terminal 41, and the sixth signal S6 is input from the external circuit (not shown) to the terminal 42. The fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases. The transistors 33 and 34 are n-channel FETs, and their pinch-off voltage (threshold voltage for flowing a drain current) is Vp.
　トランジスタ33は、ゲート端子が端子42に接続されており、ソース端子が端子41に接続されており、ドレイン端子が増幅器５およびキャパシタ６を介してトランジスタ４のゲート端子に接続されている。そして、トランジスタ33は、ソース端子に第５信号Ｓ５が入力され、ゲート端子に第６信号Ｓ６が入力されるとともに、ドレイン端子からの出力信号が第１信号Ｓ１として増幅器５に入力される。 The transistor 33 has a gate terminal connected to the terminal 42, a source terminal connected to the terminal 41, and a drain terminal connected to the gate terminal of the transistor 4 via the amplifier 5 and the capacitor 6. In the transistor 33, the fifth signal S5 is input to the source terminal, the sixth signal S6 is input to the gate terminal, and the output signal from the drain terminal is input to the amplifier 5 as the first signal S1.
　トランジスタ34は、ゲート端子が端子41に接続されており、ソース端子が端子42に接続されており、ドレイン端子が検波回路７の一方端に接続されている。そして、トランジスタ34は、ソース端子に第６信号Ｓ６が入力され、ゲート端子に第５信号Ｓ５が入力されるとともに、ドレイン端子からの出力信号が第３信号Ｓ３として検波回路７の一方端に入力される。なお、図示しないバイアス回路より、トランジスタ33，34のゲート端子にそれぞれ直流バイアス電圧が供給される。 The transistor 34 has a gate terminal connected to the terminal 41, a source terminal connected to the terminal 42, and a drain terminal connected to one end of the detection circuit 7. In the transistor 34, the sixth signal S6 is input to the source terminal, the fifth signal S5 is input to the gate terminal, and the output signal from the drain terminal is input to one end of the detection circuit 7 as the third signal S3. Is done. A DC bias voltage is supplied to the gate terminals of the transistors 33 and 34 from a bias circuit (not shown).
　トランジスタ33，34は、ｎチャネルトランジスタであるため、ピンチオフ電圧Ｖｐ以上の正電圧がゲート端子に印加されると、ドレイン端子とソース端子との間が導通する。よって、トランジスタ33は、第６信号Ｓ６の電圧がＶｐ以上の正電圧である間、第５信号Ｓ５を通過させてドレイン端子から第１信号Ｓ１として出力する。トランジスタ34は、第５信号Ｓ５がＶｐ以上の正電圧である間、第６信号Ｓ６を通過させてドレイン端子から第３信号Ｓ３として出力する。第５信号Ｓ５および第６信号Ｓ６は、互いに周波数および振幅が等しく位相が異なる定包絡線信号であるため、トランジスタ33のドレイン端子から出力される第１信号Ｓ１と、トランジスタ34のドレイン端子から出力される第３信号Ｓ３とは、互いにデューティー比が等しいパルス状の信号となる。 Since the transistors 33 and 34 are n-channel transistors, when a positive voltage equal to or higher than the pinch-off voltage Vp is applied to the gate terminal, the drain terminal and the source terminal become conductive. Therefore, the transistor 33 passes the fifth signal S5 and outputs it as the first signal S1 from the drain terminal while the voltage of the sixth signal S6 is a positive voltage equal to or higher than Vp. While the fifth signal S5 is a positive voltage equal to or higher than Vp, the transistor 34 passes the sixth signal S6 and outputs it from the drain terminal as the third signal S3. Since the fifth signal S5 and the sixth signal S6 are constant envelope signals having the same frequency and amplitude and different phases, the first signal S1 output from the drain terminal of the transistor 33 and the output from the drain terminal of the transistor 34 are output. The third signal S3 is a pulse signal having the same duty ratio.
　また、第６信号Ｓ６の電圧がＶｐより大きい正の電圧である間だけ、トランジスタ33のドレイン端子から第１信号Ｓ１が出力されるため、第１信号Ｓ１がＶｐより大きい正の電圧である期間は、第５信号Ｓ５および第６信号Ｓ６が共にピンチオフ電圧Ｖｐより大きい正の電圧である期間に一致する。そして、第１信号Ｓ１は、増幅器５で増幅され、キャパシタ６を通過して、第２信号Ｓ２としてトランジスタ４のゲート端子に入力され、トランジスタ４をＯＮ－ＯＦＦする。 Further, since the first signal S1 is output from the drain terminal of the transistor 33 only while the voltage of the sixth signal S6 is a positive voltage higher than Vp, the period during which the first signal S1 is a positive voltage higher than Vp. Corresponds to a period in which both the fifth signal S5 and the sixth signal S6 are positive voltages larger than the pinch-off voltage Vp. The first signal S1 is amplified by the amplifier 5, passes through the capacitor 6, is input to the gate terminal of the transistor 4 as the second signal S2, and the transistor 4 is turned on and off.
　したがって、トランジスタ４がＯＮ状態の時間は、第５信号Ｓ５と第６信号Ｓ６との位相差によって変化する。すなわち、第５信号Ｓ５と第６信号Ｓ６との位相差が小さい場合、トランジスタ４がＯＮ状態である時間は長くなり、第５信号Ｓ５と第６信号Ｓ６との位相差が大きい場合は、トランジスタ４がＯＮ状態である時間は短くなる。これにより、第５信号Ｓ５と第６信号Ｓ６との位相差の増減が、トランジスタ４がＯＮ状態である時間の増減に置き換えられる。 Therefore, the time during which the transistor 4 is ON varies depending on the phase difference between the fifth signal S5 and the sixth signal S6. That is, when the phase difference between the fifth signal S5 and the sixth signal S6 is small, the time during which the transistor 4 is ON is long, and when the phase difference between the fifth signal S5 and the sixth signal S6 is large, the transistor The time during which 4 is ON is shortened. Thereby, the increase / decrease in the phase difference between the fifth signal S5 and the sixth signal S6 is replaced with the increase / decrease in the time during which the transistor 4 is in the ON state.
　なお、第５信号Ｓ５および第６信号Ｓ６がともにＶｐより大きい正の電圧である期間は、第５信号Ｓ５および第６信号Ｓ６と同じ周期で発生するため、トランジスタ４がＯＮ状態になる期間も第５信号Ｓ５および第６信号Ｓ６と同じ周期で発生する。そのため、トランジスタ４のドレイン電圧も第５信号Ｓ５および第６信号Ｓ６と同じ周波数成分を含むことになる。 Note that the period in which both the fifth signal S5 and the sixth signal S6 are positive voltages greater than Vp occurs in the same cycle as the fifth signal S5 and the sixth signal S6, and therefore the period in which the transistor 4 is in the ON state is also included. It is generated in the same cycle as the fifth signal S5 and the sixth signal S6. Therefore, the drain voltage of the transistor 4 also includes the same frequency component as the fifth signal S5 and the sixth signal S6.
　そして、出力整合回路16によって、トランジスタ４のドレイン電圧から基本波成分（第５信号Ｓ５および第６信号Ｓ６と同じ周波数成分）が抽出されて端子２から出力される。この出力信号は、第５信号Ｓ５および第６信号Ｓ６の位相差の増減とは逆に振幅が増減するものであり、第５信号Ｓ５および第６信号Ｓ６が合成されて増幅されたものになる。このようにして、電力増幅回路は、２つの定包絡線信号をベクトル加算して増幅して出力することが可能な電力増幅回路として機能する。 Then, the fundamental wave component (the same frequency component as the fifth signal S5 and the sixth signal S6) is extracted from the drain voltage of the transistor 4 by the output matching circuit 16, and is output from the terminal 2. This output signal has an amplitude that increases and decreases contrary to the increase and decrease of the phase difference between the fifth signal S5 and the sixth signal S6, and is an amplified signal obtained by synthesizing the fifth signal S5 and the sixth signal S6. . In this way, the power amplifier circuit functions as a power amplifier circuit that can amplify and output two constant envelope signals by vector addition.
　また、第５信号Ｓ５および第６信号Ｓ６の位相差が小さいときに生じる、トランジスタ４のゲート端子に加わる電圧の低下を、変換回路31によって低減することができる。よって、本例の電力増幅回路によれば、第５信号Ｓ５および第６信号Ｓ６の位相差が大きいときの増幅効率の低下が低減された電力増幅回路を得ることができる。 Moreover, the voltage drop applied to the gate terminal of the transistor 4 that occurs when the phase difference between the fifth signal S5 and the sixth signal S6 is small can be reduced by the conversion circuit 31. Therefore, according to the power amplifier circuit of this example, it is possible to obtain a power amplifier circuit in which a decrease in amplification efficiency when the phase difference between the fifth signal S5 and the sixth signal S6 is large is reduced.
　なお、本例においては、トランジスタ33のゲート端子に第６信号Ｓ６が入力され、トランジスタ34のゲート端子に第５信号Ｓ５が入力される例を示したが、これに限定されるものではない。トランジスタ33のゲート端子に入力されるのは、第６信号Ｓ６と同相の信号であれば良く、トランジスタ34のゲート端子に入力されるのは、第５信号Ｓ５と同相の信号であれば良い。 In this example, the sixth signal S6 is input to the gate terminal of the transistor 33 and the fifth signal S5 is input to the gate terminal of the transistor 34. However, the present invention is not limited to this. The signal input to the gate terminal of the transistor 33 may be a signal in phase with the sixth signal S6, and the signal input to the gate terminal of the transistor 34 may be a signal in phase with the fifth signal S5.
　（実施の形態の第４の例）
  図７は本発明の実施の形態の第４の例の電力増幅回路を示す回路図である。本例の電力増幅回路は、図７に示すように、図６に示した電力増幅回路61に加えて、包絡線変動を有する入力信号を、第５信号Ｓ５となる第１定包絡線信号と、第６信号Ｓ６となる第２定包絡線信号とに変換して出力する定包絡線信号生成回路62をさらに備えている。なお、第１定包絡線信号（第５信号Ｓ５）および第２定包絡線信号（第６信号Ｓ６）は、互いに周波数および振幅が等しく位相が異なる定包絡線信号である。また、定包絡線信号生成回路62としては、よく知られている種々の定包絡線信号生成回路を使用することができ、デジタル方式の回路でもアナログ方式の回路でも構わない。 (Fourth example of embodiment)
FIG. 7 is a circuit diagram showing a power amplifier circuit according to a fourth example of the embodiment of the present invention. 7, in addition to the power amplifier circuit 61 shown in FIG. 6, the power amplifier circuit of this example is configured to convert an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal S5. And a constant envelope signal generation circuit 62 that converts the second constant envelope signal to be the sixth signal S6 and outputs the second constant envelope signal. The first constant envelope signal (fifth signal S5) and the second constant envelope signal (sixth signal S6) are constant envelope signals having the same frequency and amplitude and different phases. As the constant envelope signal generation circuit 62, various well-known constant envelope signal generation circuits can be used, and either a digital circuit or an analog circuit may be used.
　このような構成を備える本例の電力増幅回路によれば、包絡線変動を有する入力信号を、入力信号の振幅の増減と逆に増減する位相差を有する第１定包絡線信号および第２定包絡線信号に変換した後に、高い電源効率で増幅して、増幅された包絡線変動を有する出力信号を出力することができる。これにより、電源効率の高い電力増幅回路を得ることができる。 According to the power amplifier circuit of this example having such a configuration, the first constant envelope signal and the second constant signal having a phase difference that increases or decreases the input signal having the envelope fluctuation in the opposite direction to the increase or decrease in the amplitude of the input signal. After being converted into an envelope signal, it can be amplified with high power supply efficiency, and an output signal having an amplified envelope variation can be output. Thereby, a power amplifier circuit with high power supply efficiency can be obtained.
　（実施の形態の第５の例）
   図８は本発明の実施の形態の第５の例の送信装置を示すブロック図である。本例の送信装置は、図８に示すように、送信回路81と、図７に示す電力増幅回路70と、電力増幅回路70を介して送信回路81に接続されたアンテナ82とを有している。このような構成を有する本例の送信装置によれば、送信回路81から出力された送信信号を、消費電力が小さく電源効率が高い本発明の電力増幅回路70を用いて増幅してアンテナ82に出力することができるので、消費電力が小さい送信装置を得ることができる。 (Fifth example of embodiment)
FIG. 8 is a block diagram showing a transmission apparatus according to a fifth example of the embodiment of the present invention. As shown in FIG. 8, the transmission apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, and an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70. Yes. According to the transmission apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplification circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a transmitter with low power consumption can be obtained.
　（実施の形態の第６の例）
  図９は本発明の実施の形態の第６の例の通信装置を示すブロック図である。本例の通信装置は、図９に示すように、送信回路81と、図７に示す電力増幅回路70と、電力増幅回路70を介して送信回路81に接続されたアンテナ82と、アンテナ82に接続された受信回路83とを有している。なお、アンテナ82と、電力増幅回路70および受信回路83との間にはアンテナ共用回路84が挿入されている。すなわち、電力増幅回路70および受信回路83は、アンテナ共用回路84を介してアンテナ82に接続されている。このような構成を有する本例の通信装置によれば、送信回路81から出力された送信信号を、消費電力が小さく電源効率が高い本発明の電力増幅回路70を用いて増幅してアンテナ82に出力することができるので、消費電力が小さい通信装置を得ることができる。なお、アンテナ共用回路84は、必ず必要ではなく、なくても構わない。 (Sixth example of embodiment)
FIG. 9 is a block diagram showing a communication apparatus according to a sixth example of the embodiment of the present invention. As shown in FIG. 9, the communication apparatus of this example includes a transmission circuit 81, a power amplification circuit 70 shown in FIG. 7, an antenna 82 connected to the transmission circuit 81 via the power amplification circuit 70, and an antenna 82. And a receiving circuit 83 connected thereto. An antenna sharing circuit 84 is inserted between the antenna 82 and the power amplification circuit 70 and the reception circuit 83. That is, the power amplifying circuit 70 and the receiving circuit 83 are connected to the antenna 82 via the antenna sharing circuit 84. According to the communication apparatus of the present example having such a configuration, the transmission signal output from the transmission circuit 81 is amplified using the power amplifier circuit 70 of the present invention with low power consumption and high power supply efficiency, and is supplied to the antenna 82. Since it can output, a communication apparatus with low power consumption can be obtained. The antenna sharing circuit 84 is not always necessary and may be omitted.
　まず、図１に示した本発明の実施の形態の第１の例の電力増幅回路における電気特性を回路シミュレーションによって算出した。トランジスタ４はガリウム砒素ＦＥＴとし、ピンチオフ電圧Ｖｐを0.3Ｖとした。電源電位Ｖｄｄを4.5Ｖとし、直流バイアス電圧Ｖｇを0.2Ｖとした。入力信号は矩形状のパルス信号とし、周波数を700ＭＨｚとし、波高を0.6Ｖとした。 First, the electrical characteristics in the power amplifier circuit of the first example of the embodiment of the present invention shown in FIG. 1 were calculated by circuit simulation. The transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V. The power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V. The input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V.
　このシミュレーションの結果を図10のグラフに実線で示す。グラフにおいて、横軸はバックオフであり、入力信号のデューティー比が最大（0.5）のときのバックオフが０である。縦軸はドレイン効率である。また、図１に示す電力増幅回路から変換回路31を取り除いた比較例の電力増幅回路のシミュレーション結果を図10のグラフに破線で示す。 The result of this simulation is shown by a solid line in the graph of FIG. In the graph, the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5). The vertical axis represents drain efficiency. Further, a simulation result of the power amplifier circuit of the comparative example in which the conversion circuit 31 is removed from the power amplifier circuit shown in FIG. 1 is shown by a broken line in the graph of FIG.
　図10に示すグラフによれば、本発明の電力増幅回路は、比較例の電力増幅回路よりもドレイン効率が高いことがわかる。また、特にバックオフが０に近いとき（入力信号のデューティー比が大きいとき）に、本発明の電力増幅回路のドレイン効率と、比較例の電力増幅回路のドレイン効率との差が大きくなることがわかる。 The graph shown in FIG. 10 shows that the power amplifier circuit of the present invention has higher drain efficiency than the power amplifier circuit of the comparative example. In particular, when the back-off is close to 0 (when the duty ratio of the input signal is large), the difference between the drain efficiency of the power amplifier circuit of the present invention and the drain efficiency of the power amplifier circuit of the comparative example may increase. Recognize.
　次に、図５に示した本発明の実施の形態の第２の例の電力増幅回路における電気特性を回路シミュレーションによって算出した。トランジスタ４はガリウム砒素ＦＥＴとし、ピンチオフ電圧Ｖｐを0.3Ｖとした。電源電位Ｖｄｄを4.5Ｖとし、直流バイアス電圧Ｖｇを0.2Ｖとした。入力信号は矩形状のパルス信号とし、周波数を700ＭＨｚとし、波高を0.6Ｖとした。キャパシタ18のキャパシタンスを0.3ｐＦとした。ＬＣ直列共振回路19は、11.8ｎＨのインダクタと4.3ｐＦのキャパシタで構成した。低域通過フィルタ回路20は、3.9ｐＦおよび３ｐＦのキャパシタと19.1ｎＨのインダクタからなるπ型回路によって構成した。 Next, the electrical characteristics in the power amplifier circuit of the second example of the embodiment of the present invention shown in FIG. 5 were calculated by circuit simulation. The transistor 4 was a gallium arsenide FET, and the pinch-off voltage Vp was 0.3V. The power supply potential Vdd was 4.5V, and the DC bias voltage Vg was 0.2V. The input signal was a rectangular pulse signal, the frequency was 700 MHz, and the wave height was 0.6V. The capacitance of the capacitor 18 was 0.3 pF. The LC series resonance circuit 19 is composed of an inductor of 11.8 nH and a capacitor of 4.3 pF. The low-pass filter circuit 20 is composed of a π-type circuit composed of 3.9 pF and 3 pF capacitors and a 19.1 nH inductor.
　このシミュレーションの結果を図11のグラフに示す。グラフにおいて、横軸はバックオフであり、入力信号のデューティー比が最大（0.5）のときのバックオフが０である。縦軸はドレイン効率である。 The results of this simulation are shown in the graph of FIG. In the graph, the horizontal axis is backoff, and the backoff is 0 when the duty ratio of the input signal is maximum (0.5). The vertical axis represents drain efficiency.
　図11に示すグラフによれば、入力信号のデューティー比が大きく、バックオフが０～－14ｄＢの領域において、80％程度と高く一定したドレイン効率が得られており、優れた特性を有する電力増幅器であることがわかる。 According to the graph shown in FIG. 11, a power amplifier having an excellent characteristic in which the drain efficiency is as high as about 80% in a region where the duty ratio of the input signal is large and the back-off is 0 to -14 dB. It can be seen that it is.
  これらのシミュレーション結果により、本発明の有効性が確認できた。 (9) The effectiveness of the present invention was confirmed by these simulation results.
　４，33，34：トランジスタ
　６，18，22：キャパシタ
　16：出力整合回路
　17，20：低域通過フィルタ回路
　19：ＬＣ直列共振回路
　61，70：電力増幅回路
　62：定包絡線信号生成回路
　81：送信回路
　82：アンテナ
　83：受信回路 4, 33, 34: Transistor 6, 18, 22: Capacitor 16: Output matching circuit 17, 20: Low-pass filter circuit 19: LC series resonance circuit 61, 70: Power amplifier circuit 62: Constant envelope signal generation circuit 81 : Transmitter circuit 82: Antenna 83: Receiver circuit

Claims (6)

  1. 　第１信号が直接または振幅を変えて入力されて第２信号を出力するキャパシタと、
    前記第１信号とデューティー比が等しい第３信号または前記第１信号が入力されて、入力された信号のデューティー比の増減に応じて増減する直流電圧を有する第４信号を出力する変換回路と、
    前記第２信号および前記第４信号が加算されてゲート端子に入力される第１のトランジスタと、
    一方端が前記第１のトランジスタのドレイン端子に接続されているとともに他方端が電源電位に接続される第１の低域通過フィルタ回路と、
    前記第１のトランジスタのドレイン端子に接続された出力整合回路とを備えることを特徴とする電力増幅回路。     A capacitor that receives the first signal directly or with a different amplitude and outputs the second signal;
    A conversion circuit that outputs a fourth signal having a DC voltage that increases or decreases in accordance with an increase or decrease in the duty ratio of the input signal when the third signal or the first signal having the same duty ratio as the first signal is input;
    A first transistor in which the second signal and the fourth signal are added and input to a gate terminal;
    A first low-pass filter circuit having one end connected to the drain terminal of the first transistor and the other end connected to a power supply potential;
    And an output matching circuit connected to a drain terminal of the first transistor.
  2. 　前記出力整合回路は、
    入出力間に直列に接続された、前記第１信号の基本波の周波数で共振するＬＣ直列共振回路と、
    該ＬＣ直列共振回路に縦続接続された、前記第１信号の基本波の周波数の信号を通過させるとともに高調波の周波数の信号を減衰させる第２の低域通過フィルタ回路と、
    前記第１のトランジスタのドレイン端子と基準電位との間に接続されたキャパシタとを少なくとも有していることを特徴とする請求項１に記載の電力増幅回路。     The output matching circuit includes:
    An LC series resonance circuit that is connected in series between the input and output and resonates at the frequency of the fundamental wave of the first signal;
    A second low-pass filter circuit cascaded to the LC series resonance circuit for passing the fundamental frequency signal of the first signal and attenuating the harmonic frequency signal;
    The power amplifier circuit according to claim 1, further comprising at least a capacitor connected between a drain terminal of the first transistor and a reference potential.
  3. 　ソース端子に第５信号が入力され、ゲート端子に第６信号または該第６信号と同相の信号が入力されるとともに、前記第１信号となる信号がドレイン端子から出力される第２のトランジスタと、
    ソース端子に前記第６信号が入力され、ゲート端子に前記第５信号または該第５信号と同相の信号が入力されるとともに、前記第３信号となる信号がドレイン端子から出力される第３のトランジスタとをさらに備え、
    前記第３信号が前記変換回路に入力されることを特徴とする請求項１に記載の電力増幅回路。     A second signal in which a fifth signal is input to the source terminal, a sixth signal or a signal in phase with the sixth signal is input to the gate terminal, and a signal to be the first signal is output from the drain terminal; ,
    The sixth signal is input to the source terminal, the fifth signal or a signal having the same phase as the fifth signal is input to the gate terminal, and a signal serving as the third signal is output from the drain terminal. A transistor,
    The power amplification circuit according to claim 1, wherein the third signal is input to the conversion circuit.
  4. 　包絡線変動を有する入力信号を、前記第５信号となる第１定包絡線信号と、前記第６信号となる第２定包絡線信号とに変換して出力する定包絡線信号生成回路をさらに備えることを特徴とする請求項３に記載の電力増幅回路。 A constant envelope signal generation circuit that converts an input signal having an envelope variation into a first constant envelope signal that becomes the fifth signal and a second constant envelope signal that becomes the sixth signal, and outputs the converted signal; The power amplifier circuit according to claim 3, further comprising:
  5. 　送信回路と、請求項４に記載の電力増幅回路と、該電力増幅回路を介して前記送信回路に接続されたアンテナとを少なくとも有していることを特徴とする送信装置。 A transmission device comprising: a transmission circuit; the power amplification circuit according to claim 4; and an antenna connected to the transmission circuit via the power amplification circuit.
  6. 　送信回路と、請求項４に記載の電力増幅回路と、該電力増幅回路を介して前記送信回路に接続されたアンテナと、該アンテナに接続された受信回路とを少なくとも有していることを特徴とする通信装置。 It has at least a transmission circuit, the power amplification circuit according to claim 4, an antenna connected to the transmission circuit via the power amplification circuit, and a reception circuit connected to the antenna. A communication device.
PCT/JP2012/051662 2011-01-27 2012-01-26 Power amplifier circuit, as well as transmission device and communication device using same WO2012102342A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311057A (en) * 1993-04-26 1994-11-04 Nec Corp Radio power transmitter
JP2003204590A (en) * 2002-01-08 2003-07-18 Yamaha Corp Class-d amplifier
JP2004350276A (en) * 2003-05-19 2004-12-09 Samsung Electronics Co Ltd Integrable voltage-regulating ultra-high frequency power amplifier
JP2008167289A (en) * 2006-12-28 2008-07-17 Samsung Electronics Co Ltd Transmission apparatus
JP2009182906A (en) * 2008-01-31 2009-08-13 Kyocera Corp Amplifier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311057A (en) * 1993-04-26 1994-11-04 Nec Corp Radio power transmitter
JP2003204590A (en) * 2002-01-08 2003-07-18 Yamaha Corp Class-d amplifier
JP2004350276A (en) * 2003-05-19 2004-12-09 Samsung Electronics Co Ltd Integrable voltage-regulating ultra-high frequency power amplifier
JP2008167289A (en) * 2006-12-28 2008-07-17 Samsung Electronics Co Ltd Transmission apparatus
JP2009182906A (en) * 2008-01-31 2009-08-13 Kyocera Corp Amplifier

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