WO2012099937A3 - Higher-level redundancy information computation - Google Patents

Higher-level redundancy information computation Download PDF

Info

Publication number
WO2012099937A3
WO2012099937A3 PCT/US2012/021682 US2012021682W WO2012099937A3 WO 2012099937 A3 WO2012099937 A3 WO 2012099937A3 US 2012021682 W US2012021682 W US 2012021682W WO 2012099937 A3 WO2012099937 A3 WO 2012099937A3
Authority
WO
WIPO (PCT)
Prior art keywords
level redundancy
redundancy information
order
ssd
computed
Prior art date
Application number
PCT/US2012/021682
Other languages
French (fr)
Other versions
WO2012099937A2 (en
Inventor
Jeremy Isaac Nathaniel Werner
Leonid Baryudin
Timothy Canepa
Earl Cohen
Original Assignee
Lsi Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US13/979,805 priority Critical patent/US8656101B2/en
Priority to JP2013550554A priority patent/JP2014507717A/en
Priority to KR1020147019498A priority patent/KR101564569B1/en
Priority to EP12736920.5A priority patent/EP2666091A2/en
Priority to CN201280012139.7A priority patent/CN103415844B/en
Priority to KR1020137021636A priority patent/KR101454807B1/en
Application filed by Lsi Corporation filed Critical Lsi Corporation
Publication of WO2012099937A2 publication Critical patent/WO2012099937A2/en
Publication of WO2012099937A3 publication Critical patent/WO2012099937A3/en
Priority to US13/675,874 priority patent/US9727414B2/en
Priority to US14/181,252 priority patent/US9183140B2/en
Priority to US15/670,941 priority patent/US10613929B2/en
Priority to US16/825,148 priority patent/US11379301B2/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16Protection against loss of memory contents
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108Parity data distribution in semiconductor storages, e.g. in SSD
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2094Redundant storage or storage space

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero "index" as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.
PCT/US2012/021682 2010-12-01 2012-01-18 Higher-level redundancy information computation WO2012099937A2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP2013550554A JP2014507717A (en) 2011-01-18 2012-01-18 Calculation of higher level redundant information
KR1020147019498A KR101564569B1 (en) 2011-01-18 2012-01-18 Higher-level redundancy information computation
EP12736920.5A EP2666091A2 (en) 2011-01-18 2012-01-18 Higher-level redundancy information computation
CN201280012139.7A CN103415844B (en) 2011-01-18 2012-01-18 For the system and method that senior redundant information calculates
KR1020137021636A KR101454807B1 (en) 2011-01-18 2012-01-18 Higher-level redundancy information computation
US13/979,805 US8656101B2 (en) 2011-01-18 2012-01-18 Higher-level redundancy information computation
US13/675,874 US9727414B2 (en) 2010-12-01 2012-11-13 Fractional redundant array of silicon independent elements
US14/181,252 US9183140B2 (en) 2011-01-18 2014-02-14 Higher-level redundancy information computation
US15/670,941 US10613929B2 (en) 2010-12-01 2017-08-07 Fractional redundant array of silicon independent elements
US16/825,148 US11379301B2 (en) 2010-12-01 2020-03-20 Fractional redundant array of silicon independent elements

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161433918P 2011-01-18 2011-01-18
US61/433,918 2011-01-18

Related Child Applications (3)

Application Number Title Priority Date Filing Date
US13/979,805 A-371-Of-International US8656101B2 (en) 2011-01-18 2012-01-18 Higher-level redundancy information computation
US13/675,874 Continuation-In-Part US9727414B2 (en) 2010-12-01 2012-11-13 Fractional redundant array of silicon independent elements
US14/181,252 Continuation US9183140B2 (en) 2011-01-18 2014-02-14 Higher-level redundancy information computation

Publications (2)

Publication Number Publication Date
WO2012099937A2 WO2012099937A2 (en) 2012-07-26
WO2012099937A3 true WO2012099937A3 (en) 2012-09-13

Family

ID=46516340

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/021682 WO2012099937A2 (en) 2010-12-01 2012-01-18 Higher-level redundancy information computation

Country Status (7)

Country Link
US (2) US8656101B2 (en)
EP (1) EP2666091A2 (en)
JP (1) JP2014507717A (en)
KR (2) KR101564569B1 (en)
CN (1) CN103415844B (en)
TW (1) TW201241615A (en)
WO (1) WO2012099937A2 (en)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101541040B1 (en) 2010-03-12 2015-08-03 엘에스아이 코포레이션 Ldpc erasure decoding for flash memories
US9582431B2 (en) 2010-03-22 2017-02-28 Seagate Technology Llc Storage address space to NVM address, span, and length mapping/converting
US9569320B2 (en) 2010-12-01 2017-02-14 Seagate Technology Llc Non-volatile memory program failure recovery via redundant arrays
WO2012099937A2 (en) 2011-01-18 2012-07-26 Lsi Corporation Higher-level redundancy information computation
CN103348330B (en) 2010-12-01 2017-05-24 希捷科技有限公司 dynamic higher-level redundancy mode management with independent silicon elements
US8719663B2 (en) 2010-12-12 2014-05-06 Lsi Corporation Cross-decoding for non-volatile storage
JP5346978B2 (en) * 2011-04-15 2013-11-20 シャープ株式会社 Interface device, wiring board, and information processing device
JP5346979B2 (en) * 2011-04-18 2013-11-20 シャープ株式会社 Interface device, wiring board, and information processing device
EP2742429A4 (en) 2011-08-09 2015-03-25 Lsi Corp I/o device and computing host interoperation
US8799598B2 (en) * 2012-02-17 2014-08-05 Spansion Llc Redundancy loading efficiency
US8856431B2 (en) 2012-08-02 2014-10-07 Lsi Corporation Mixed granularity higher-level redundancy for non-volatile memory
SG11201501405XA (en) * 2012-09-21 2015-05-28 Nyse Group Inc High performance data streaming
US9395924B2 (en) 2013-01-22 2016-07-19 Seagate Technology Llc Management of and region selection for writes to non-volatile memory
US20140281802A1 (en) * 2013-03-15 2014-09-18 SEAKR Engineering, Inc. Multi-dimensional error detection and correction memory and computing architecture
EP2830226A1 (en) * 2013-07-24 2015-01-28 Pierre Arrigo Encoding and decoding methods and devices
JP6443794B2 (en) * 2013-08-16 2018-12-26 エルエスアイ コーポレーション Translation layer partitioned between host and controller
JP5978259B2 (en) * 2013-08-16 2016-08-24 エルエスアイ コーポレーション Sequential read optimization variable size flash translation layer
US9535628B2 (en) * 2013-10-10 2017-01-03 Apple Inc. Memory system with shared file system
US20150199293A1 (en) * 2013-11-20 2015-07-16 Hangzhou Dianzi University Method and apparatus with interface for redundant array of independent modules
US9455020B2 (en) * 2014-06-05 2016-09-27 Micron Technology, Inc. Apparatuses and methods for performing an exclusive or operation using sensing circuitry
US10652193B2 (en) * 2014-06-18 2020-05-12 Western Digital Technologies, Inc. Managing and accessing data storage systems
CN104050061B (en) * 2014-07-01 2016-01-20 中国航天科工集团第二研究院七〇六所 A kind of Based PC Ie bus many master control board redundancies standby system
US9766972B2 (en) * 2014-08-07 2017-09-19 Pure Storage, Inc. Masking defective bits in a storage array
US9575853B2 (en) * 2014-12-12 2017-02-21 Intel Corporation Accelerated data recovery in a storage system
US10162700B2 (en) * 2014-12-23 2018-12-25 International Business Machines Corporation Workload-adaptive data packing algorithm
US9678665B2 (en) * 2015-03-06 2017-06-13 Western Digital Technologies, Inc. Methods and systems for memory page allocation
US10275310B2 (en) 2015-03-09 2019-04-30 Western Digital Technologies, Inc. Updating exclusive-or parity data
CN106155812A (en) 2015-04-28 2016-11-23 阿里巴巴集团控股有限公司 Method, device, system and the electronic equipment of a kind of resource management to fictitious host computer
CN106339179B (en) * 2015-07-06 2020-11-17 上海宝存信息科技有限公司 Host device, access system, and access method
US10191841B2 (en) 2015-07-06 2019-01-29 Shannon Systems Ltd. Host device, access system, and access method
US9734009B2 (en) * 2015-10-08 2017-08-15 Sandisk Technologies Llc Data encoding techniques for a device
US9946596B2 (en) 2016-01-29 2018-04-17 Toshiba Memory Corporation Global error recovery system
US10275376B2 (en) 2016-03-02 2019-04-30 Western Digital Technologies, Inc. Efficient cross device redundancy implementation on high performance direct attached non-volatile storage with data reduction
US10275165B2 (en) 2016-09-12 2019-04-30 Toshiba Memory Corporation Memory controller
US10606767B2 (en) * 2017-05-19 2020-03-31 Samsung Electronics Co., Ltd. Ethernet-attached SSD for automotive applications
US10474527B1 (en) 2017-06-30 2019-11-12 Seagate Technology Llc Host-assisted error recovery
TWI651650B (en) * 2018-02-05 2019-02-21 大陸商深圳大心電子科技有限公司 Memory management method and storage controller using the same
US11204819B2 (en) * 2018-12-21 2021-12-21 Samsung Electronics Co., Ltd. System and method for offloading application functions to a device
CN110572864A (en) * 2019-08-28 2019-12-13 惠州Tcl移动通信有限公司 storage and calling method of network-resident frequency band, mobile terminal and computer storage medium
US11531590B2 (en) 2019-09-17 2022-12-20 Western Digital Technologies, Inc. Method and system for host-assisted data recovery assurance for data center storage device architectures
TWI785702B (en) * 2021-05-07 2022-12-01 旺宏電子股份有限公司 Storage device for generating identity code and identity code generating method
US11984166B2 (en) 2021-05-07 2024-05-14 Macronix International Co., Ltd. Storage device for generating identity code and identity code generating method
US20230015697A1 (en) * 2021-07-13 2023-01-19 Citrix Systems, Inc. Application programming interface (api) authorization
CN117274027B (en) * 2023-08-22 2024-05-24 北京辉羲智能科技有限公司 Image processing chip with hardware safety redundancy

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651135A (en) * 1994-03-30 1997-07-22 Kabushiki Kaisha Toshiba Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency
US6594728B1 (en) * 1994-10-14 2003-07-15 Mips Technologies, Inc. Cache memory with dual-way arrays and multiplexed parallel output
US20050240731A1 (en) * 2004-04-22 2005-10-27 Steely Simon C Jr Managing a multi-way associative cache

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US565113A (en) * 1896-08-04 graves
US5099484A (en) 1989-06-09 1992-03-24 Digital Equipment Corporation Multiple bit error detection and correction system employing a modified Reed-Solomon code incorporating address parity and catastrophic failure detection
US5418921A (en) * 1992-05-05 1995-05-23 International Business Machines Corporation Method and means for fast writing data to LRU cached based DASD arrays under diverse fault tolerant modes
US5666512A (en) * 1995-02-10 1997-09-09 Hewlett-Packard Company Disk array having hot spare resources and methods for using hot spare resources to store user data
US5862158A (en) 1995-11-08 1999-01-19 International Business Machines Corporation Efficient method for providing fault tolerance against double device failures in multiple device systems
JPH10222314A (en) * 1997-01-31 1998-08-21 Xing:Kk Storage device array system
US6557123B1 (en) 1999-08-02 2003-04-29 Inostor Corporation Data redundancy methods and apparatus
US7117397B1 (en) * 1999-12-15 2006-10-03 Fujitsu Limited Apparatus and method for preventing an erroneous operation at the time of detection of a system failure
US6594796B1 (en) 2000-06-30 2003-07-15 Oak Technology, Inc. Simultaneous processing for error detection and P-parity and Q-parity ECC encoding
KR100388208B1 (en) 2001-05-25 2003-06-19 주식회사 하이닉스반도체 Redundancy circuit of semicontor memory device
US6961890B2 (en) 2001-08-16 2005-11-01 Hewlett-Packard Development Company, L.P. Dynamic variable-length error correction code
US7073115B2 (en) 2001-12-28 2006-07-04 Network Appliance, Inc. Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups
US7372731B2 (en) 2003-06-17 2008-05-13 Sandisk Il Ltd. Flash memories with adaptive reference voltages
US20090193184A1 (en) 2003-12-02 2009-07-30 Super Talent Electronics Inc. Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System
US8122193B2 (en) 2004-12-21 2012-02-21 Samsung Electronics Co., Ltd. Storage device and user device including the same
US8200887B2 (en) 2007-03-29 2012-06-12 Violin Memory, Inc. Memory management system and method
WO2007012920A1 (en) * 2005-07-27 2007-02-01 Adaptec, Inc. Method and system for improving the performance of reed-solomon parity operations in redundant array of inexpensive disks
KR100732628B1 (en) 2005-07-28 2007-06-27 삼성전자주식회사 Flash memory device capable of multi-bit data and single-bit data
US7681109B2 (en) 2005-10-13 2010-03-16 Ramot At Tel Aviv University Ltd. Method of error correction in MBC flash memory
US20070143541A1 (en) 2005-12-19 2007-06-21 Lsi Logic Corporation Methods and structure for improved migration of raid logical volumes
US7809994B2 (en) 2006-05-17 2010-10-05 Sandisk Corporation Error correction coding for multiple-sector pages in flash memory devices
US7739576B2 (en) 2006-08-31 2010-06-15 Micron Technology, Inc. Variable strength ECC
US20080126839A1 (en) 2006-09-19 2008-05-29 Satish Sangapu Optimized reconstruction and copyback methodology for a failed drive in the presence of a global hot spare disc
US8171380B2 (en) 2006-10-10 2012-05-01 Marvell World Trade Ltd. Adaptive systems and methods for storing and retrieving data to and from memory cells
US20080140724A1 (en) 2006-12-06 2008-06-12 David Flynn Apparatus, system, and method for servicing object requests within a storage controller
US7505319B2 (en) 2007-01-31 2009-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for high efficiency redundancy scheme for multi-segment SRAM
WO2008099723A1 (en) 2007-02-01 2008-08-21 Kabushiki Kaisha Toshiba Semiconductor memory with reed- solomon decoder
US8122323B2 (en) 2007-03-08 2012-02-21 Intel Corporation Method, apparatus, and system for dynamic ECC code rate adjustment
US20080276124A1 (en) 2007-05-04 2008-11-06 Hetzler Steven R Incomplete write protection for disk array
US8429492B2 (en) 2007-11-30 2013-04-23 Marvell World Trade Ltd. Error correcting code predication system and method
US9152496B2 (en) 2007-12-21 2015-10-06 Cypress Semiconductor Corporation High performance flash channel interface
US8443260B2 (en) 2007-12-27 2013-05-14 Sandisk Il Ltd. Error correction in copy back memory operations
US8724381B2 (en) 2008-03-11 2014-05-13 Agere Systems Llc Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
EP2297742B1 (en) * 2008-05-16 2013-07-24 Fusion-io, Inc. Apparatus, system, and method for detecting and replacing failed data storage
US8959280B2 (en) 2008-06-18 2015-02-17 Super Talent Technology, Corp. Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear
US20100017649A1 (en) 2008-07-19 2010-01-21 Nanostar Corporation Data storage system with wear-leveling algorithm
US20100017650A1 (en) 2008-07-19 2010-01-21 Nanostar Corporation, U.S.A Non-volatile memory data storage system with reliability management
US8041984B2 (en) 2008-10-17 2011-10-18 International Business Machines Corporation Redundancy information for adjusting threshold for component failure in a multi-layer system
KR101059673B1 (en) 2008-12-26 2011-08-25 서울대학교산학협력단 Storage device and method for dynamically adjusting reliability or storage capacity
US8438455B2 (en) * 2008-12-31 2013-05-07 Intel Corporation Error correction in a solid state disk
US8065558B2 (en) 2009-03-24 2011-11-22 Lsi Corporation Data volume rebuilder and methods for arranging data volumes for improved RAID reconstruction performance
CN101882472A (en) 2009-05-05 2010-11-10 建兴电子科技股份有限公司 Flash memory with variable error-correcting code mechanism and control method thereof
US8307258B2 (en) 2009-05-18 2012-11-06 Fusion-10, Inc Apparatus, system, and method for reconfiguring an array to operate with less storage elements
JP4843695B2 (en) * 2009-06-26 2011-12-21 株式会社東芝 Disk array control device and disk array device
US7856528B1 (en) 2009-08-11 2010-12-21 Texas Memory Systems, Inc. Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system
US8402217B2 (en) 2009-09-15 2013-03-19 Marvell International Ltd. Implementing RAID in solid state memory
US8266501B2 (en) 2009-09-29 2012-09-11 Micron Technology, Inc. Stripe based memory operation
KR101541040B1 (en) 2010-03-12 2015-08-03 엘에스아이 코포레이션 Ldpc erasure decoding for flash memories
US9189385B2 (en) 2010-03-22 2015-11-17 Seagate Technology Llc Scalable data structures for control and management of non-volatile storage
KR101606718B1 (en) 2010-10-27 2016-03-28 엘에스아이 코포레이션 Adaptive ecc techniques for flash memory based data storage
US9727414B2 (en) * 2010-12-01 2017-08-08 Seagate Technology Llc Fractional redundant array of silicon independent elements
US9569320B2 (en) 2010-12-01 2017-02-14 Seagate Technology Llc Non-volatile memory program failure recovery via redundant arrays
WO2012099937A2 (en) 2011-01-18 2012-07-26 Lsi Corporation Higher-level redundancy information computation
CN103348330B (en) 2010-12-01 2017-05-24 希捷科技有限公司 dynamic higher-level redundancy mode management with independent silicon elements
US8719663B2 (en) 2010-12-12 2014-05-06 Lsi Corporation Cross-decoding for non-volatile storage
US8595415B2 (en) 2011-02-02 2013-11-26 Micron Technology, Inc. At least semi-autonomous modules in a memory system and methods
US8856431B2 (en) 2012-08-02 2014-10-07 Lsi Corporation Mixed granularity higher-level redundancy for non-volatile memory
KR20140086223A (en) 2012-12-28 2014-07-08 주식회사 옵토스타 Parity re-synchronization sturcture of disk array and the method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5651135A (en) * 1994-03-30 1997-07-22 Kabushiki Kaisha Toshiba Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency
US6594728B1 (en) * 1994-10-14 2003-07-15 Mips Technologies, Inc. Cache memory with dual-way arrays and multiplexed parallel output
US20050240731A1 (en) * 2004-04-22 2005-10-27 Steely Simon C Jr Managing a multi-way associative cache

Also Published As

Publication number Publication date
KR20140094661A (en) 2014-07-30
US9183140B2 (en) 2015-11-10
CN103415844A (en) 2013-11-27
US20130290618A1 (en) 2013-10-31
KR101564569B1 (en) 2015-11-03
US20140237166A1 (en) 2014-08-21
TW201241615A (en) 2012-10-16
KR101454807B1 (en) 2014-11-04
EP2666091A2 (en) 2013-11-27
US8656101B2 (en) 2014-02-18
KR20130118370A (en) 2013-10-29
CN103415844B (en) 2016-04-20
WO2012099937A2 (en) 2012-07-26
JP2014507717A (en) 2014-03-27

Similar Documents

Publication Publication Date Title
WO2012099937A3 (en) Higher-level redundancy information computation
US8726140B2 (en) Dummy data padding and error code correcting memory controller, data processing method thereof, and memory system including the same
US9088303B2 (en) Codewords that span pages of memory
US9197247B2 (en) Memory system and error correction method
US8433979B2 (en) Nested multiple erasure correcting codes for storage arrays
KR101636785B1 (en) Dynamic higher-level redundancy mode management with independent silicon elements
KR102572357B1 (en) Raid-6 data storage device and data processing system having the same
TWI528174B (en) Selection of redundant storage configuration based on available memory space
US20140064048A1 (en) Scalable Storage Protection
US9058291B2 (en) Multiple erasure correcting codes for storage arrays
WO2011116071A3 (en) Mlc self-raid flash data protection scheme
JP2014507717A5 (en)
JP2015508917A (en) Method, system and program for storing data in storage array using erasure error correction code
CN103135946B (en) Solid state drive(SSD)-based file layout method in large-scale storage system
CN104541253A (en) Techniques associated with protecting system critical data written to non-volatile memory
US20150089328A1 (en) Flex Erasure Coding of Controllers of Primary Hard Disk Drives Controller
Blaum Construction of PMDS and SD codes extending RAID 5
US20190273515A1 (en) Apparatuses and methods for interleaved bch codes
WO2014167535A3 (en) Restoring ecc syndrome in non-volatile memory devices
US9286156B2 (en) Data storage device and method for processing error correction code thereof
JP2015135676A (en) Method and/or apparatus for interleaving codewords over multiple flash planes
US10404282B2 (en) Apparatuses and methods for integrated interleaved Reed-Solomon encoding and decoding
KR101646149B1 (en) Software defined storaging method for data sharing and maintenance on distributed storage environment
US20120274487A1 (en) Apparatus for encoding and decoding, data storage apparatus and method for encoding and decoding
TW201602775A (en) Computing system with data protection mechanism and method of operation thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201280012139.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12736920

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 13979805

Country of ref document: US

ENP Entry into the national phase

Ref document number: 2013550554

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2012736920

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20137021636

Country of ref document: KR

Kind code of ref document: A