WO2012094109A1 - Transistor à longueur de canal réduite - Google Patents

Transistor à longueur de canal réduite Download PDF

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Publication number
WO2012094109A1
WO2012094109A1 PCT/US2011/064757 US2011064757W WO2012094109A1 WO 2012094109 A1 WO2012094109 A1 WO 2012094109A1 US 2011064757 W US2011064757 W US 2011064757W WO 2012094109 A1 WO2012094109 A1 WO 2012094109A1
Authority
WO
WIPO (PCT)
Prior art keywords
material layer
electrically conductive
conductive material
thickness
electrically
Prior art date
Application number
PCT/US2011/064757
Other languages
English (en)
Inventor
Lee William Tutt
Shelby Forrester Nelson
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/986,199 external-priority patent/US7985684B1/en
Priority claimed from US12/986,206 external-priority patent/US8383469B2/en
Priority claimed from US12/986,197 external-priority patent/US8847232B2/en
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Publication of WO2012094109A1 publication Critical patent/WO2012094109A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • deposition processes which can be used to deposit thin films on vertical or inclined surfaces of a substrate relief.
  • the thickness of the coating decreases as the depth of the relief increases, for example, as the length of the vertical or inclined wall increases.
  • layers deposited using these types of deposition processes have considerable differences in thickness over the length of the relief.
  • These types of deposition processes include plasma-enhanced chemical vapor deposition (PECVD) and diffusion-limited deposition of silicon oxide using tetraethyl orthosilicate (TEOS).
  • Electrode(s) 710 includes a third electrically conductive material layer 700. When there is more than one electrode 710, different discrete discontinuous portions of third electrically conductive material layer 700 form electrodes 710. Electrode 810 includes a fourth electrically conductive material layer 800. Electrode(s) 710 and electrode 810 are positioned spaced apart from each other at different locations of transistor 100. Electrode(s) 710 and electrode 810 can be different portions of the same material layer. When this happens, the third and fourth electrically conductive material layers 700 and 800 are different discrete discontinuous portions of the same material layer, for example, material layer 700.
  • the semiconductor device is actuated in the following manner. After transistor 100 is provided, a voltage is applied between the third electrically conductive material layer 700 and the fourth electrically conductive material layer 800. A voltage is also applied to the first electrically conductive material layer 120 to electrically connect the third electrically conductive material layer 700 and the fourth electrically conductive material layer 800. Since first electrically conductive material layer 120 and second electrically conductive material layer 130 are both electrically conductive and in contact with each other, applying a voltage to one layer, for example, layer 120, is considered to be equivalent to applying a voltage to both layers, layers 120 and 130, or the other layer, for example, layer 130. The third electrically conductive material layer 700 and the fourth electrically conductive material layer 800 can be the same material layer or can be different material layers.
  • overhang 180 (which can be referred to as a second reentrant profile) in which second electrically conductive material layer 130 extends beyond first electrically conductive material layer 120, shown in Figure 4.
  • first electrically conductive material layer 120 underhangs the second electrically conductive material layer 130.
  • electrically insulating material layer 150 After removal of photoresist material layer 140 (shown in Figure 5), if such is necessary, substrate 110 and the remaining exposed portions of electrically conductive material layers 120 and 130 are conformally coated with an electrically insulating material layer 150, shown in Figure 6.
  • the thickness of the electrically insulating material layer 1 0 is less than the thickness of first electrically conductive material layer 120, and preferably half the thickness of first electrically conductive material layer 120 so that the overhang 180 between the substrate 110 and the second electrically conductive material layer 130 can be substantially filled in.
  • Electrically insulating material layer 150 is conformally coated with a semiconductor material layer 160, shown in Figure 7.
  • An electrically conductive material layer for example, material layer 700 or material layer 700 and material layer 800, is directionally (or nonconformally) deposited (shown using arrows 900) over semiconductor material layer 160, shown in Figure 8A.
  • Conductive material layer 130 is a uniform material layer with no pattern.
  • a resist material layer 140 is applied to conductive material layer 130. Resist 140 is patterned.
  • a flexible support or substrate 110 is used in some example embodiments of the present invention.
  • Using a flexible substrate 110 allows for roll processing, which can be continuous, providing economy of scale and economy of manufacturing over flat or rigid supports.
  • the flexible support chosen is preferably capable of wrapping around the circumference of a cylinder of less than about 50 cm in diameter, more preferably 25 cm in diameter, and ' most preferably 10 cm in diameter, without distorting or breaking, using low force as by unaided hands.
  • the preferred flexible support can be rolled upon itself.
  • resist 140 is removed.
  • gentle cleaning can be performed on the material layer stack, if desired, provided that the cleaning process does not remove the reentrant profile 170.
  • a semiconductor material 160 is then coated using a conformal coating deposition process which helps to maintain the reentrant profile 170.
  • This conformal coating process can be the same process used previously to coat the dielectric material. Alternatively, the conformal coating process can be different.
  • a preferred process for conformally coating includes atomic layer deposition (ALD) or spatial ALD (S-ALD), a derivative of ALD. Either process yields a uniform thickness on a highly varying topology.
  • Atomic Layer Deposition is a process which is used to . produce coatings with thicknesses that can be considered consistent, uniform, or even exact.
  • ALD produces coatings that can be considered conformal or even highly conformal material layers.
  • an ALD process accomplishes substrate coating by alternating between two or more reactive materials commonly referred to as precursors, in a vacuum chamber. A first precursor is applied to react with the substrate. The excess of the first precursor is removed is removed from the vacuum chamber. A second precursor is then applied to react with the substrate. The excess of the second precursor is removed from the vacuum chamber and the process is repeated.
  • a patterned material layer of photoresist was formed by spin coating at 1000 rpra Microposit SI 805 resist (Rohm and Haas Electronic

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor qui comprend un substrat. Une première couche de matériau conducteur, ayant une certaine épaisseur, est placée sur le substrat. Une seconde couche de matériau conducteur est placée sur la première couche de matériau conducteur et au contact de celle-ci. La seconde couche de matériau conducteur surplombe la première couche de matériau conducteur. Une couche de matériau électriquement isolant, ayant une certaine épaisseur, est placée de manière conforme sur la seconde couche de matériau conducteur, sur la première couche de matériau conducteur et au moins sur une partie du substrat. L'épaisseur de la première couche de matériau conducteur est supérieure à celle de la couche de matériau électriquement isolant.
PCT/US2011/064757 2011-01-07 2011-12-14 Transistor à longueur de canal réduite WO2012094109A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US12/986,206 2011-01-07
US12/986,199 US7985684B1 (en) 2011-01-07 2011-01-07 Actuating transistor including reduced channel length
US12/986,197 2011-01-07
US12/986,206 US8383469B2 (en) 2011-01-07 2011-01-07 Producing transistor including reduced channel length
US12/986,197 US8847232B2 (en) 2011-01-07 2011-01-07 Transistor including reduced channel length
US12/986,199 2011-01-07

Publications (1)

Publication Number Publication Date
WO2012094109A1 true WO2012094109A1 (fr) 2012-07-12

Family

ID=45446223

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/064757 WO2012094109A1 (fr) 2011-01-07 2011-12-14 Transistor à longueur de canal réduite

Country Status (2)

Country Link
TW (1) TW201240095A (fr)
WO (1) WO2012094109A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140863U (fr) * 1989-04-26 1990-11-26
US5780911A (en) * 1995-11-29 1998-07-14 Lg Semicon Co., Ltd. Thin film transistor and method for fabricating the same
JP2008060522A (ja) * 2006-01-24 2008-03-13 Ricoh Co Ltd 電子素子、電流制御装置、演算装置及び表示装置
US20080166884A1 (en) 2007-01-08 2008-07-10 Nelson Shelby F Delivery device comprising gas diffuser for thin film deposition
US7413982B2 (en) 2006-03-29 2008-08-19 Eastman Kodak Company Process for atomic layer deposition
US7456429B2 (en) 2006-03-29 2008-11-25 Eastman Kodak Company Apparatus for atomic layer deposition
US20090130858A1 (en) 2007-01-08 2009-05-21 Levy David H Deposition system and method using a delivery head separated from a substrate by gas pressure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140863U (fr) * 1989-04-26 1990-11-26
US5780911A (en) * 1995-11-29 1998-07-14 Lg Semicon Co., Ltd. Thin film transistor and method for fabricating the same
JP2008060522A (ja) * 2006-01-24 2008-03-13 Ricoh Co Ltd 電子素子、電流制御装置、演算装置及び表示装置
US7413982B2 (en) 2006-03-29 2008-08-19 Eastman Kodak Company Process for atomic layer deposition
US7456429B2 (en) 2006-03-29 2008-11-25 Eastman Kodak Company Apparatus for atomic layer deposition
US20080166884A1 (en) 2007-01-08 2008-07-10 Nelson Shelby F Delivery device comprising gas diffuser for thin film deposition
US20090130858A1 (en) 2007-01-08 2009-05-21 Levy David H Deposition system and method using a delivery head separated from a substrate by gas pressure

Also Published As

Publication number Publication date
TW201240095A (en) 2012-10-01

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