WO2012092894A2 - 一种多核处理器系统 - Google Patents
一种多核处理器系统 Download PDFInfo
- Publication number
- WO2012092894A2 WO2012092894A2 PCT/CN2012/070827 CN2012070827W WO2012092894A2 WO 2012092894 A2 WO2012092894 A2 WO 2012092894A2 CN 2012070827 W CN2012070827 W CN 2012070827W WO 2012092894 A2 WO2012092894 A2 WO 2012092894A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- level hardware
- hardware message
- message queues
- level
- queues
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/54—Indexing scheme relating to G06F9/54
- G06F2209/548—Queue
Definitions
- the present invention relates to the field of processor technologies, and in particular, to a multi-core processor system. Background technique
- Chip Multi Processors implements multiple Processor Units (CPUs) in a single chip. Each CPU can also be called a core. Each core in the CMP shares certain resources and can execute different processes in parallel. Data sharing and synchronization are sometimes required between programs executed by each core of the CMP, so the hardware structure of the CMP must support communication between the cores.
- a bus shared cache (Cache) structure there are two mainstream communication mechanisms between the cores, one is a bus shared cache (Cache) structure, and the other is a hardware message queue structure.
- Bus sharing Cache structure means that each core has a shared secondary or tertiary Cache, which is used to store more commonly used data, and to ensure data consistency between cores by connecting the buses of each core. Communication between cores can be achieved through a shared data segment.
- the hardware message queue structure refers to implementing a set of queues for each core in hardware. The operation of the queue improves the efficiency of communication between cores compared with the bus shared Cache structure.
- the present invention is directed to a multi-core processor system to provide higher performance inter-core message interaction and task scheduling.
- An aspect of the present invention provides a multi-core processor system, including: a plurality of central processor units and a plurality of sets of first-level hardware message queues;
- Each central processing unit is coupled to a set of first level hardware message queues for processing messages in the first level hardware message queue; wherein each set of first level hardware message queues includes a plurality of first level hardware Message queue; and in each group of first-level hardware message queues, the first-level hardware message queues with higher priority are preferentially scheduled, and the first-level hardware message queues of the same priority are cyclically scheduled according to the rotation scheduling weights.
- Another aspect of the present invention also provides a multi-core processor system, including: a plurality of central processor units, a plurality of sets of first-level hardware message queues, and a plurality of sets of second-level hardware message queues;
- Each central processing unit is coupled to a set of first level hardware message queues for processing messages in the first level hardware message queue; wherein each set of first level hardware message queues includes a plurality of first level hardware a message queue; and each set of second level hardware message queues is respectively connected to at least one set of first level hardware message queues for pushing messages to the first level message queue.
- the multi-core processor system provided by various aspects of the present invention can meet higher performance inter-core message interaction and task scheduling, and improve the efficiency and performance of the multi-core processor system.
- FIG. 1 is a multi-core processor system according to an embodiment of the present invention. detailed description
- One embodiment of the present invention provides a multi-core processor system.
- the system includes:
- each central processing unit is respectively connected to a set of first-level hardware message queues for processing messages in the first-level hardware message queue; wherein, each The first-level hardware message queue of the group includes a plurality of first-level hardware message queues; and, in each group of the first-level hardware message queues, the first-level hardware message queues with high priority are preferentially scheduled, and the first priority of the same level
- the level hardware message queue is rotated and scheduled according to the round-robin scheduling weight.
- Another embodiment of the present invention also provides a multi-core processor system.
- the system includes:
- each central processing unit is coupled to a set of first level hardware message queues for processing first level hardware messages a message in the queue; wherein each set of first-level hardware message queues includes a plurality of first-level hardware message queues; and each set of second-level hardware message queues is respectively connected to at least one set of first-level hardware message queues, Push messages to the first level message queue.
- the read speed of the first-level hardware message queue in the foregoing embodiment is higher than that of the second-level hardware message queue, and the first-level hardware message queue supports less messages than the second-level hardware message queue supports.
- the embodiment provides a multi-core processor system 100.
- the multi-core processor system 100 includes: a plurality of central processor units 101 (CoreO, Corel, Core2, Core3) and a plurality of sets of first-level hardware messages. Queue 102.
- Each central processing unit 101 is connected to a set of first level hardware message queues 102 for processing messages in the first level hardware message queue; each set of first level hardware message queues 102 includes a plurality of first level Hardware message queue.
- the multi-core processor system may further include a plurality of sets of second-level hardware message queues 103, as shown in FIG. 1, two sets of second-level hardware message queues of GroupO and Group1.
- Each set of second level hardware message queues 103 is respectively connected to at least one set of first level hardware message queues 102 for pushing messages to the first level message queue.
- the first level hardware message queue may be a high speed hardware message queue set near the location of the core, and the high speed hardware message queue has a higher read speed than the second level hardware message queue.
- the location of the second-level hardware message queue is far from the core, but the number of messages that can be supported is greater than the number of messages supported by the first-level hardware message queue.
- the multi-core processor system 100 provided in this embodiment can support a flexible, configurable scheduling queuing strategy for message queues.
- RR (Round Robin) scheduling Polls each queue, and dispatches if there is a message in the queue.
- PQ (Priority Queue) scheduling A scheduling algorithm based on priority queues. The algorithm schedules according to the priority of the queue. The high priority is scheduled first, and the low priority is scheduled. If the high-priority queue is not empty, the queue with the highest priority is scheduled to be dequeued. The low-priority queue is scheduled only after the queue with the highest priority is empty.
- WRR Weight Round Robin Scheduling: WRR evolves on the basis of RR scheduling. It performs round-robin scheduling between queues, and schedules messages in each queue according to the weight of each queue.
- Figure 1 shows a set of first-level hardware message queues 102 connected to Corel configured as PQ+WRR scheduling policies, and a set of first-level hardware message queues 102 connected to Core2 are configured as RR scheduling policies.
- the PQ+WRR scheduling policy is described in detail below.
- the PQ+WRR scheduling policy can include:
- Different scheduling weights are configured for multiple queues of the same priority (PQi+1). If there is no message in the queue (PQ0 ⁇ PQi) with higher priority than the queue, each queue message is scheduled to be dequeued according to the WRR policy.
- scheduling policy shown in FIG. 1 is only an example.
- other scheduling policies can be configured according to design requirements, for example, all first-level hardware messages.
- Queue 102 is configured as a PQ+WRR scheduling policy.
- the scheduling policy may also be configured according to design requirements. For example, FIG. 1 shows two sets of second-level hardware message queues 103.
- the scheduling policy is configured as PQ+WRR, ⁇
- the first-level hardware message queue is empty or the message queue watermark is lower than the preset value, all queues in the group are traversed according to the priority from high to low. If there is only one queue in a certain priority and there is a message in the queue, Mapping the message schedule to the first level hardware queue;
- the queues of the same priority are scheduled according to the WRR scheduling policy.
- a set of second-level hardware message queues may be mapped to a first-level hardware message queue corresponding to multiple cores.
- Figure 1 shows a second-level hardware message queue group. Groupl can map to the first-level hardware message queues corresponding to Corel, Core2, and Core3. Those skilled in the art will appreciate that other mapping schemes may also be configured, and the example of Figure 1 is not intended to limit the invention.
- the mapping scheme of the first-level hardware message queue corresponding to a core of the second-level hardware message queue group mapping is:
- RR Simple Round Robin
- each functional unit in each embodiment may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
- TAG message tag
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2012/070827 WO2012092894A2 (zh) | 2012-02-01 | 2012-02-01 | 一种多核处理器系统 |
CN201280000273.5A CN102713852B (zh) | 2012-02-01 | 2012-02-01 | 一种多核处理器系统 |
EP12732067.9A EP2801907A4 (en) | 2012-02-01 | 2012-02-01 | MULTICOVER PROCESSOR SYSTEM |
US14/263,338 US9152482B2 (en) | 2012-02-01 | 2014-04-28 | Multi-core processor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2012/070827 WO2012092894A2 (zh) | 2012-02-01 | 2012-02-01 | 一种多核处理器系统 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/263,338 Continuation US9152482B2 (en) | 2012-02-01 | 2014-04-28 | Multi-core processor system |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2012092894A2 true WO2012092894A2 (zh) | 2012-07-12 |
WO2012092894A3 WO2012092894A3 (zh) | 2012-12-27 |
Family
ID=46457753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2012/070827 WO2012092894A2 (zh) | 2012-02-01 | 2012-02-01 | 一种多核处理器系统 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9152482B2 (zh) |
EP (1) | EP2801907A4 (zh) |
CN (1) | CN102713852B (zh) |
WO (1) | WO2012092894A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9355506B2 (en) | 2014-06-27 | 2016-05-31 | Continental Automotive France | Method for managing fault messages of a motor vehicle |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3000250B1 (fr) * | 2012-12-20 | 2015-02-13 | Thales Sa | Systeme de processeur multi-coeurs de traitement d'informations |
CN103942101A (zh) * | 2013-01-21 | 2014-07-23 | 中国科学院声学研究所 | 一种基于多核网络处理器的实时任务调度方法及系统 |
CN104158764B (zh) * | 2014-08-12 | 2018-02-06 | 新华三技术有限公司 | 报文处理方法及装置 |
CN105700949A (zh) * | 2014-11-24 | 2016-06-22 | 中兴通讯股份有限公司 | 一种多核处理器下的数据处理方法及装置 |
CN104899089A (zh) * | 2015-05-25 | 2015-09-09 | 常州北大众志网络计算机有限公司 | 一种面向异构多核体系的任务调度方法 |
KR20170023280A (ko) * | 2015-08-19 | 2017-03-03 | 한국전자통신연구원 | 멀티코어 프로세서 시스템 및 상기 시스템에서의 공유 캐시 관리 방법 |
US10445271B2 (en) | 2016-01-04 | 2019-10-15 | Intel Corporation | Multi-core communication acceleration using hardware queue device |
CN106201676A (zh) * | 2016-06-28 | 2016-12-07 | 浪潮软件集团有限公司 | 一种任务分配方法及装置 |
CN107171918B (zh) * | 2017-04-26 | 2020-06-16 | 成都成电光信科技股份有限公司 | 支持优先级的gjb289a总线模块中的消息收发方法 |
CN107613529B (zh) * | 2017-07-31 | 2021-06-01 | 上海华为技术有限公司 | 消息处理方法以及基站 |
WO2022041876A1 (zh) * | 2020-08-28 | 2022-03-03 | 华为技术有限公司 | 数据传输的方法和系统 |
CN114564420B (zh) * | 2022-01-19 | 2023-08-18 | 中国电子科技集团公司第十研究所 | 多核处理器共享并行总线的方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5745778A (en) * | 1994-01-26 | 1998-04-28 | Data General Corporation | Apparatus and method for improved CPU affinity in a multiprocessor system |
CN100458757C (zh) | 2005-07-28 | 2009-02-04 | 大唐移动通信设备有限公司 | 嵌入式实时操作系统中多核处理器的核间通信方法及装置 |
US20070083735A1 (en) | 2005-08-29 | 2007-04-12 | Glew Andrew F | Hierarchical processor |
CN100550833C (zh) * | 2005-11-24 | 2009-10-14 | 武汉烽火网络有限责任公司 | 以太网交换缓存及调度的方法和装置 |
CN100558080C (zh) * | 2006-12-12 | 2009-11-04 | 华为技术有限公司 | 集群消息传送方法及分布式集群系统 |
US7937532B2 (en) * | 2007-03-30 | 2011-05-03 | Intel Corporation | Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine |
US8544014B2 (en) * | 2007-07-24 | 2013-09-24 | Microsoft Corporation | Scheduling threads in multi-core systems |
CN101217499B (zh) | 2008-01-21 | 2010-12-01 | 中兴通讯股份有限公司 | 队列调度方法 |
US8549524B2 (en) * | 2009-12-23 | 2013-10-01 | Sap Ag | Task scheduler for cooperative tasks and threads for multiprocessors and multicore systems |
US8479219B2 (en) * | 2010-06-30 | 2013-07-02 | International Business Machines Corporation | Allocating space in message queue for heterogeneous messages |
CN101923491A (zh) * | 2010-08-11 | 2010-12-22 | 上海交通大学 | 多核环境下线程组地址空间调度和切换线程的方法 |
US9176912B2 (en) * | 2011-09-07 | 2015-11-03 | Altera Corporation | Processor to message-based network interface using speculative techniques |
-
2012
- 2012-02-01 CN CN201280000273.5A patent/CN102713852B/zh active Active
- 2012-02-01 WO PCT/CN2012/070827 patent/WO2012092894A2/zh active Application Filing
- 2012-02-01 EP EP12732067.9A patent/EP2801907A4/en not_active Withdrawn
-
2014
- 2014-04-28 US US14/263,338 patent/US9152482B2/en active Active
Non-Patent Citations (2)
Title |
---|
None |
See also references of EP2801907A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9355506B2 (en) | 2014-06-27 | 2016-05-31 | Continental Automotive France | Method for managing fault messages of a motor vehicle |
Also Published As
Publication number | Publication date |
---|---|
US9152482B2 (en) | 2015-10-06 |
CN102713852A (zh) | 2012-10-03 |
WO2012092894A3 (zh) | 2012-12-27 |
US20140229957A1 (en) | 2014-08-14 |
EP2801907A4 (en) | 2014-12-03 |
CN102713852B (zh) | 2014-06-04 |
EP2801907A2 (en) | 2014-11-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2012092894A2 (zh) | 一种多核处理器系统 | |
US11036556B1 (en) | Concurrent program execution optimization | |
CN103605576B (zh) | 一种基于多线程的MapReduce执行系统 | |
JP6290462B2 (ja) | ネットワーク・アクセス可能なブロック・ストレージのための協調アドミッション制御 | |
CN104102548B (zh) | 任务资源调度处理方法和系统 | |
US20040024873A1 (en) | Load balancing the servicing of received packets | |
CN102298539A (zh) | 一种用于分布式并行处理的共享资源调度方法及系统 | |
CN109697122A (zh) | 任务处理方法、设备及计算机存储介质 | |
CN102541803A (zh) | 数据发送方法和计算机 | |
Willmann et al. | An Evaluation of Network Stack Parallelization Strategies in Modern Operating Systems. | |
US11861406B2 (en) | Dynamic microservices allocation mechanism | |
US20160253216A1 (en) | Ordering schemes for network and storage i/o requests for minimizing workload idle time and inter-workload interference | |
CN102571580A (zh) | 数据接收方法和计算机 | |
Fei et al. | FlexNFV: Flexible network service chaining with dynamic scaling | |
US8510491B1 (en) | Method and apparatus for efficient interrupt event notification for a scalable input/output device | |
EP3084603B1 (en) | System and method for supporting adaptive busy wait in a computing environment | |
JP6283376B2 (ja) | クラスタにおけるワークシェアリング多重化をサポートするためのシステムおよび方法 | |
Lee et al. | Transparent many‐core partitioning for high‐performance big data I/O | |
TW202139019A (zh) | 用於封包處理的方法及系統、以及非暫時性電腦可讀媒體 | |
CN102955685A (zh) | 多核dsp及其系统和调度器 | |
Cao et al. | Design of hpc node with heterogeneous processors | |
CN112799811A (zh) | 一种边缘网关的高并发线程池任务调度方法 | |
Wijeyeratnam | An MPI messaging layer for network processors | |
Raj et al. | Virtualization Services: Accelerated I/O Support in Multi-Core Systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201280000273.5 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12732067 Country of ref document: EP Kind code of ref document: A2 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
REEP | Request for entry into the european phase |
Ref document number: 2012732067 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012732067 Country of ref document: EP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12732067 Country of ref document: EP Kind code of ref document: A2 |