WO2012091253A1 - Localized emitter solar cell and method for manufacturing same - Google Patents

Localized emitter solar cell and method for manufacturing same Download PDF

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Publication number
WO2012091253A1
WO2012091253A1 PCT/KR2011/007257 KR2011007257W WO2012091253A1 WO 2012091253 A1 WO2012091253 A1 WO 2012091253A1 KR 2011007257 W KR2011007257 W KR 2011007257W WO 2012091253 A1 WO2012091253 A1 WO 2012091253A1
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Prior art keywords
substrate
doped region
forming
conductive
solar cell
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PCT/KR2011/007257
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French (fr)
Korean (ko)
Inventor
이준성
양수미
송석현
정상윤
안수범
이경원
주상민
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현대중공업 주식회사
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Priority claimed from KR1020100139773A external-priority patent/KR101199649B1/en
Priority claimed from KR1020100139771A external-priority patent/KR101173399B1/en
Priority claimed from KR1020100139769A external-priority patent/KR101181625B1/en
Priority claimed from KR1020100139772A external-priority patent/KR101114198B1/en
Application filed by 현대중공업 주식회사 filed Critical 현대중공업 주식회사
Publication of WO2012091253A1 publication Critical patent/WO2012091253A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a localized emitter solar cell and a method of manufacturing the same, and more particularly, to a localized emitter solar cell having a emitter and an electrode locally at a light receiving site of a substrate and a method of manufacturing the same.
  • the solar cell is a key element of photovoltaic power generation that converts sunlight directly into electricity, and is basically a diode composed of a p-n junction.
  • solar cells are classified into various types according to the shape of the light absorption layer or the impurity ions, which are pn junction layers.
  • Examples of the light absorption layer include silicon (Si).
  • the silicon substrate type used as the light absorption layer is divided into a thin film type which forms a light absorption layer by depositing silicon in a thin film form.
  • a second conductive semiconductor layer 12 which is an emitter layer, is stacked on the first conductive semiconductor layer 11, and a finger bar or the upper surface of the second conductive semiconductor layer 12 is formed.
  • a front electrode 14 having a pattern such as a bus bar is formed and a rear electrode 15 is provided on a lower surface of the first conductive semiconductor layer 11.
  • the first conductive semiconductor layer 11 and the second conductive semiconductor layer 12 are implemented on one silicon substrate 10, and the lower portion of the silicon substrate 10 is the first conductive semiconductor layer 11.
  • the upper portion of the silicon substrate 10 is divided into the second conductive semiconductor layer 12, and a lower concentration doped layer of the first conductive impurity for forming a backside electric field is formed below the first conductive semiconductor layer 11. 10-1) and the second conductive semiconductor layer 12 having the front electrode 14 formed on an upper surface thereof, are provided with a highly doped region 10-2 of the second conductive impurity.
  • impurities including impurities such as a PSG (Phosphorus Silicate Glass) film or a BSG (Boron Silicate Glass) film formed on the surface of the substrate 10 by a diffusion process are formed.
  • a highly doped region 10-2, that is, an emitter, of the second conductive impurity is selectively formed.
  • the highly doped layer 10-1 of the first conductivity type impurity forms a backside electric field having a higher energy barrier than the first conductivity type semiconductor layer 11, the first conductivity type semiconductor layer 11 is later formed.
  • the small number of carriers (1) generated by the solar light incident in the inside serves to block the movement to the rear electrode (15).
  • a high concentration doping layer 10-1 of the first conductivity type impurity is formed under the first conductivity type semiconductor layer 11 through a firing process.
  • an insulating process of forming a trench for disconnection of a predetermined depth is performed along the circumference of the front surface of the substrate using a laser.
  • the silicon substrate 10 is immersed in a solution containing the second conductive impurity ions and subsequently subjected to a heat treatment process, thereby forming the second conductive impurity ions into a silicon substrate ( 10), the second conductive semiconductor layer is formed on the side of the substrate in addition to the upper portion of the silicon substrate 10.
  • the second conductive semiconductor layer formed on the side of the substrate is the front electrode 14; Since the back electrode 15 is shorted to act as a factor of reducing photoelectric conversion efficiency of the solar cell, the front electrode 14 and the rear surface of the second conductive semiconductor layer formed on the side of the silicon substrate 10 are reduced. This is because it is necessary to interrupt the electrical connection between the electrodes 15.
  • the second conductivity type is n-type, as the solar light enters the first conductive semiconductor
  • the electrons, which are the minority carriers 1 generated in the layer 11 move toward the front surface of the silicon substrate 10 on which the second conductive semiconductor layer 12, that is, the emitter layer, is formed.
  • the hole which is the majority carrier 2 is moved toward the rear side of the silicon substrate 10.
  • the impurity doping concentration in the depth direction is highest at the top and decreases toward the bottom, and accordingly, the conduction band is lowered toward the top in the energy band structure.
  • the semiconductor layer 12, that is, the emitter layer is formed on the entire light-receiving surface of the silicon substrate 10, the minority transport photogenerated in the first conductive semiconductor layer 11 by the depth energy band structure of the emitter layer. The self moves along the emitter layer, and in particular, moves along the surface of the silicon substrate 10 above the emitter layer adjacent to the anti-reflection film 13 and is collected by the front electrode 14.
  • the minority transporter 1 since the surface area of the silicon substrate 10, which is the movement path of the minority transporter 1, is a high density of defects in which a large number of crystal defects and impurities exist, the minority transporter 1 has such a conventional solar cell. There is a fear that it may be easily lost by recombination before being collected by the front electrode 14.
  • the front electrode 14 having a large line width W within a range of 100 ⁇ m to 140 ⁇ m must be formed on the front surface of the silicon substrate 10, that is, the light receiving surface, it is sufficient to maintain the light receiving rate.
  • the distance d between the front electrodes 14 is very large, within 1800 ⁇ m to 2300 ⁇ m, so that the minority carriers 1 generated in the first conductive semiconductor layer 11 Since the distance to the front electrode 14 along the surface portion of the silicon substrate 10 becomes longer, the minority transporter 1 is recombined on the surface of the silicon substrate 10 before being collected by the front electrode 14. The likelihood of disappearance increases.
  • the conventional solar cell has a problem in that the photoelectric conversion efficiency is low due to its high recombination rate of the minority transporter 1 photogenerated in the silicon substrate 10.
  • a conventional solar cell requires a complicated process procedure such as a cleaning process for removing an oxide film and an insulation process for forming a trench for disconnection, and thus, a manufacturing period and a manufacturing cost are high.
  • the present invention has been made to solve the problems described above, and provides a localized emitter solar cell having an emitter and an electrode locally at a light receiving portion of a substrate, and an object thereof.
  • the present invention provides a localized emitter solar cell having a secondary electrode layer for transferring a small number of carriers collected through the emitter between the emitter and the electrode to the electrode, and a method thereof.
  • the present invention also provides a localized emitter solar cell having a doped region of a conductive impurity having a polarity opposite to that of the emitter in a light receiving portion of the light receiving portion of the substrate except for the emitter forming region, and a method of manufacturing the same. There is a purpose.
  • the localized emitter solar cell according to the first embodiment of the present invention for achieving the object as described above comprises a first conductive substrate of silicon material having a front electrode and a rear electrode on the upper and lower surfaces,
  • the highly doped region of the second conductive impurity is locally formed in the upper layer of the substrate, and the front electrode is formed in contact with the heavily doped region of the second conductive impurity.
  • the method of manufacturing a localized emitter solar cell comprises the steps of preparing a substrate of the first conductive type; Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate; Applying a back metal material to a back side of the substrate; Applying a front metal material over the high concentration doped region of the second conductive impurity through a screen printing process; It is preferable to include the step of forming a front electrode and a back electrode on the front and rear surfaces of the substrate by the firing process.
  • the method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention includes the steps of preparing a substrate of a first conductivity type; Forming a dielectric layer on the surface of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; Locally removing the anti-reflection film and the dielectric layer formed on the front surface of the substrate through a laser doping method, and forming a highly doped region of the second conductive impurity locally on the front surface of the substrate; And forming a front electrode on the high concentration doped region of the second conductive impurity by performing a plating process.
  • the localized emitter solar cell according to the second embodiment of the present invention includes a first conductive substrate of silicon material having a front electrode and a rear electrode on the upper and lower surfaces thereof, and a second layer on the upper portion of the substrate.
  • a high concentration doped region of a conductive impurity is locally formed, and a dielectric layer and an auxiliary electrode layer are sequentially stacked between the substrate and the front electrode.
  • the method of manufacturing a localized emitter solar cell comprises the steps of preparing a substrate of the first conductive type; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate; Depositing an auxiliary electrode layer on the substrate; It is preferable to include forming a front electrode on the auxiliary electrode layer.
  • the localized emitter solar cell according to the third embodiment of the present invention includes a first conductive substrate made of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces, and the front of the substrate
  • a high concentration doped region of the second conductive impurity in which the electrode is formed in contact is locally formed, and a high concentration doped region of the first conductive impurity is formed in a portion of the upper portion of the substrate except for the formation region of the high concentration doped region of the second conductive impurity.
  • a region is formed, wherein the highly doped region of the first conductive impurity is formed so as not to contact the heavily doped region of the second conductive impurities and the front electrode.
  • the method of manufacturing a localized emitter solar cell comprises the steps of preparing a substrate of the first conductive type; Forming a highly doped region of a first conductivity type impurity locally in an upper layer of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity.
  • Making a step It is preferable to include the step of forming a front electrode on top of the high concentration doped region of the second conductive type impurity by the plating process.
  • the method of manufacturing a localized emitter solar cell according to the third embodiment of the present invention includes the steps of preparing a substrate of a first conductivity type; Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity. Making a step; And forming a front electrode on the high concentration doped region of the second conductive impurity by performing a plating process.
  • the localized emitter solar cell according to the fourth embodiment of the present invention includes a first conductive substrate of silicon material having a front electrode and a rear electrode on upper and lower surfaces thereof, and a second layer formed on an upper layer of the substrate.
  • a high concentration doped region of a conductive impurity is locally formed, and a high concentration doped region of a first conductive impurity is formed in a portion of the upper portion of the substrate except for a portion of the high concentration doped region of the second conductive impurity.
  • a dielectric layer and an auxiliary electrode layer are sequentially stacked between the front electrode and the front electrode.
  • the method of manufacturing a localized emitter solar cell comprises the steps of preparing a substrate of the first conductive type; Forming a heavily doped region of a first conductivity type impurity locally on the substrate; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity.
  • the method of manufacturing a localized emitter solar cell includes the steps of preparing a substrate of a first conductivity type; Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity.
  • Making a step Depositing an auxiliary electrode layer on the substrate; And forming a front electrode on the auxiliary electrode layer.
  • the emitter is electrically conductive to the light receiving site except for the emitter formation region of the light receiving site including the emitter and the electrode.
  • the localized emitter solar cell and a method for manufacturing the same while having a local emitter and an electrode at the light receiving portion of the substrate, a small number of carriers collected through the emitter between the emitter and the electrode
  • an auxiliary electrode layer for transferring to the electrode regardless of the shape of the electrode pattern, such as the line width, number and spacing of the electrode, it is possible to safely deliver a small number of carriers generated in the substrate to the electrode, the electrode to be formed on the light receiving portion of the substrate
  • the localized emitter solar cell and the manufacturing method according to the present invention there is no need to perform the cleaning process for removing the oxide film, the insulation process for forming the trench for disconnection, etc. It can shorten and reduce the manufacturing cost.
  • FIG. 1 is a cross-sectional view showing the structure of a typical solar cell.
  • Figure 2 is a cross-sectional view showing the structure of a localized emitter solar cell according to a first embodiment of the present invention.
  • FIG. 3 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention.
  • 4 to 10 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a first embodiment of the present invention.
  • FIG. 11 is a plan view of a localized emitter solar cell according to a second embodiment of the present invention.
  • FIG. 12 is a cross-sectional view of the localized emitter solar cell according to AA ′ in FIG. 11.
  • FIG. 13 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention.
  • FIG. 14 to 21 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention.
  • FIG. 22 is a cross-sectional view illustrating a structure of a localized emitter solar cell according to a third embodiment of the present invention.
  • FIG. 23 is a cross-sectional view showing the structure of a front electrode in FIG. 22; FIG.
  • 24 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to the third embodiment of the present invention.
  • 25 to 30 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a third embodiment of the present invention.
  • 31 is a plan view of a localized emitter solar cell according to a fourth embodiment of the present invention.
  • FIG. 32 is a cross-sectional view of the localized emitter solar cell according to AA ′ in FIG. 31.
  • FIG 33 is a flowchart illustrating a method of manufacturing a localized emitter solar cell according to the fourth embodiment of the present invention.
  • 34 to 42 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a fourth embodiment of the present invention.
  • a localized emitter solar cell and a method for manufacturing the same according to the first embodiment of the present invention will be described below.
  • the localized emitter solar cell includes a first conductive substrate 10 made of silicon material having front and rear electrodes 14 and 15 disposed on upper and lower surfaces thereof.
  • a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and the front electrode 14 has a high concentration doped region 10 of the second conductive impurity.
  • the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
  • the heavily doped region 10-2 of the second conductive type impurity forms a pn junction in the substrate 10, thereby enabling movement of a small number of phototransmitters generated by solar incidence, thereby allowing the inside of the substrate 10 to be moved.
  • a potential difference may be generated and serves to reduce the contact resistance between the metallic front electrode 14 and the interface between the substrate 10.
  • the high concentration doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 ⁇ m to 2300 ⁇ m) in order to reduce the moving distance of the few carriers generated in the substrate 10. If the distance between the front electrode 14 to be formed in contact with the upper surface is too narrow, there is a risk of shading loss due to the electrode, so the distance between the front electrode 14 to be formed in contact with the upper surface is reduced. It is preferable to be formed to have an appropriate width (for example, about 20 to 40 ⁇ m) in consideration.
  • dielectric layers 20 and 21 are formed on the upper and lower surfaces of the substrate 10 except for the portion where the front electrode 14 is formed, and silicon having dielectric properties is formed on the dielectric layer 20 formed on the upper surface of the substrate 10.
  • An anti-reflective coating (ARC) 13 composed of oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like is stacked.
  • the dielectric layers 20 and 21 may serve as passivation, for example, BSG (Boron Silicate Glass). If the first conductivity type is n-type, PSG (Phosphorus Silicate Glass) is formed. Can be.
  • the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
  • the front electrode 14 may be formed, for example, in a finger line pattern or the like, and may be formed on the substrate 10 so as to correspond to the formation position of the highly doped region 10-2 of the locally formed second conductive impurities. Since it is formed on the surface, it is preferably formed with a line width (W) of about 20 ⁇ m 40 ⁇ m, the spacing (d) between the electrodes is preferably formed to be about 450 ⁇ m 2300 ⁇ m.
  • the front electrode 14 according to the present invention has a line width of about 1/2 to 1/4 of the size of a general solar cell, the distance between electrodes is 1/2 of the gap between the front electrodes of a general solar cell. Even if it is narrowed to about 1/4, the light receiving surface of the same level as the light receiving surface of a general solar cell can be ensured.
  • a first conductive silicon substrate 10 is prepared (S100).
  • step S100 a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defective portion generated as a result of the cutting process of the substrate 10.
  • a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defective portion generated as a result of the cutting process of the substrate 10.
  • KOH potassium hydroxide
  • the highly doped region 10-2 of the second conductive type impurity is locally formed on the upper layer of the substrate 10 corresponding to the portion where the front electrode 14 is to be formed.
  • S110 To form (S110).
  • an impurity ion implantation process or laser doping may be performed.
  • the diffusion process using the impurity paste 5 of the second conductive type as a source is performed. Perform.
  • the diffusion barrier may or may not be used.
  • the second conductive type impurity paste 5 is locally patterned on the entire surface of the substrate 10, and is contained in the second conductive type impurity paste 5.
  • a high concentration doped region of a second conductive type impurity that is locally heavily doped on the upper layer of the substrate 10 may be subjected to a heat treatment process to diffuse the impurity into the substrate 10. It is preferable to form 10-2).
  • the highly doped region 10-2 of the second conductive impurity formed in the upper layer portion of the substrate 10 through step S110 is formed of, for example, an n ++ region, and serves to form an electric field on the entire surface of the substrate 10. In charge.
  • the dielectric layers 20 and 21 are naturally formed (S120).
  • an antireflection film 13 is formed on the entire surface of the substrate 10 through a chemical vapor deposition process (S130).
  • the anti-reflection film 13 may be composed of a silicon nitride film (Si 3 N 4 ), for example, forming the silicon nitride film through a PECVD process, discharge and activate the source gas SiH 4 and NH 3 in a plasma state It can be implemented through a method for producing a silicon nitride film.
  • the anti-reflection film 13 may be made of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), or the like.
  • the back metal material 15-1 including aluminum (Al), silver (Ag), and the like is applied to the back of the substrate 10.
  • silver (Ag) or the like is formed on the entire surface of the substrate 10, particularly on the high concentration doped region 10-2 of the second conductive impurities formed on the upper layer of the substrate 10.
  • the firing process is performed to form the front electrode 14 and the rear electrode 15 on the front and rear surfaces of the substrate 10 (S140).
  • the high concentration doping layer 10-1 of the first conductivity type impurity which is made of aluminum (Al) as a source, of the metal material applied to the lower surface of the substrate 10 by the heat treatment during the firing process is performed. It forms naturally in the lower layer of (10).
  • a localized emitter solar cell as shown in FIG. 2 may be finally manufactured.
  • the above step S130 is performed, and then on the rear surface of the substrate 10.
  • the back metal material 15-1 including aluminum (Al), silver (Ag), and the like is coated, and a firing process is performed to form the back electrode 15 on the back of the substrate 10. As shown in FIG.
  • the second conductive type formed on the upper layer of the substrate 10 by plating is performed.
  • the front electrode 14 is formed on top of the highly doped region 10-2 of impurities, As also it may be produced the localized emitter solar cell as shown in Fig.
  • the seed layer may be formed by only performing metal plating so as to directly contact the high concentration doped region 10-2 of the second conductivity type impurity, or lowering the specific resistance when contacting the substrate 10.
  • the front electrode 14 may be formed by metal plating on the seed layer 14-2. Can be. Accordingly, as shown in FIG. 10, the front electrode 14 may include a seed layer 14-2 in a lower layer directly contacting the substrate 10.
  • the localized emitter solar cell according to the second embodiment of the present invention is a silicon-based substrate having a first conductive type having a front electrode 14 and a rear electrode 15 at upper and lower portions thereof. And a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and the dielectric layer 20 is formed between the substrate 10 and the front electrode 14. ) And the auxiliary electrode layer 30 are sequentially stacked.
  • the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
  • the heavily doped region 10-2 of the second conductive type impurity forms a pn junction in the substrate 10, thereby enabling movement of a small number of phototransmitters generated by solar incidence, thereby allowing the inside of the substrate 10 to be moved.
  • a potential difference may be generated and serves to reduce the contact resistance between the metallic front electrode 14 and the interface between the substrate 10.
  • the highly doped region 10-2 of the second conductive type impurity is formed in a dot pattern having a regular size and spacing on the upper layer of the substrate 10 as shown in FIG. 11A, or FIG. 11.
  • the upper layer of the substrate 10 is preferably formed with a line pattern having a regular line width and spacing, but has a dot pattern having an irregular size and spacing, or an irregular line width and spacing. It may also be formed in a line pattern. That is, the heavily doped region 10-2 of the second conductive type impurity may be formed in the upper layer of the substrate 10 in various forms without restriction of the pattern form.
  • the highly doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 ⁇ m to 2300 ⁇ m) in order to reduce the moving distance of the photo-generated minority transporter in the substrate 10. It is preferably formed to have a suitable width (for example, about 20 ⁇ m to 40 ⁇ m).
  • the dielectric layer 20 is formed on a portion of the upper surface of the substrate 10 except for the exposed portion of the highly doped region 10-2 of the second conductive impurity.
  • the dielectric layer 20 may be formed of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like, and the front passivation of the substrate 10 may be performed. (Passivation) Plays a role.
  • the auxiliary electrode layer 30 is formed by being stacked on the dielectric layer 20 so as to directly contact the heavily doped region 10-2 of the second conductive impurity.
  • the auxiliary electrode layer 30 is photogenerated in the substrate 10, and a few carriers collected through the high concentration doping region 10-2 of the second conductivity type impurity can move to the front electrode 14 by moving. It is composed of a material that provides a migration path, for example, it may be made of a transparent conductive oxide film (TCO).
  • TCO transparent conductive oxide film
  • the dielectric layer 20 and the auxiliary electrode layer 30 are each formed to have a predetermined thickness in consideration of refractive index, so that an anti-reflection film (ARC) can prevent light reflection loss of the upper surface of the substrate 10, that is, the light receiving surface.
  • ARC anti-reflection film
  • the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
  • the front electrode 14 may trap a small number of carriers through the auxiliary electrode layer 30 stacked on the entire upper surface of the substrate 10, the second conductive type is locally formed on the upper layer of the substrate 10. Since the patterning does not have to correspond to the formation position of the highly doped region 10-2 of the impurity, the upper portion of the auxiliary electrode layer 30 does not correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity. It can be formed on the side. Of course, if necessary, the front electrode 14 may be formed on the upper surface of the auxiliary electrode layer 30 to correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity.
  • the front electrode 14 may be formed in a pattern such as a finger line shape, wherein the front electrode 14 has a narrow line width (W) of about 20 ⁇ m to 40 ⁇ m, and between electrodes of about 1800 ⁇ m to 2300 ⁇ m. It is formed to have a distance (d) or, if necessary, is formed to exceed 2300 ⁇ m within a range that does not exceed the light receiving surface of the substrate 10, thereby ensuring a much wider light receiving surface than the light receiving surface of a typical solar cell. have.
  • the front electrode 14 may be formed in a direction parallel or perpendicular to the pattern of the highly doped region 10-2 of the second conductive impurity.
  • a first conductive silicon substrate 10 is prepared (S200).
  • step S200 a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • KOH potassium hydroxide
  • the dielectric layers 20 and 21 are formed on the surface of the substrate 10 by performing a heat treatment process (S210).
  • the dielectric layers 20 and 21 are made of BSG (Boron Silicate Glass) or the like. If the first conductivity type is n-type, it is preferable that the dielectric layers 20 and 21 are made of PSG (Phosphorus Silicate Glass).
  • step S210 the dielectric layer 20 including the silicon nitride layer Si 3 N 4 is formed only on the upper surface of the substrate 10 by performing a chemical vapor deposition process such as a plasma enhanced chemical vapor deposition (PECVD) process. can do.
  • a chemical vapor deposition process such as a plasma enhanced chemical vapor deposition (PECVD) process. can do.
  • PECVD plasma enhanced chemical vapor deposition
  • a rear metal material 15-1 including aluminum (Al), silver (Ag), and the like is applied to the rear surface of the substrate 10, and the firing process is performed.
  • the rear electrode 15 is formed on the lower surface of the substrate 10 (S220).
  • a high concentration doping layer 10-1 of the first conductive type impurity which is made of aluminum (Al) as a source, of the metal material applied to the lower surface of the substrate 10 by the heat treatment during the firing process is performed. It is naturally formed in the lower layer of (10), wherein the dielectric layer 21 formed on the lower surface of the substrate through the above step S210 is the first conductive impurity due to the doping of the first conductive impurity sourced from aluminum (Al). It is preferably included in the high concentration doping layer (10-1).
  • the laser doping process is performed to locally remove the dielectric layer 20 formed on the substrate 10 and to remove the dielectric layer 20.
  • a second conductive dopant is doped in the upper layer of the substrate 10
  • a high concentration doped region 10-2 of the second conductive dopant is locally exposed in the upper layer of the substrate 10 (S230).
  • the high concentration doped region 10-2 of the second conductive impurity formed on the upper layer of the substrate 10 through step S230 may be formed of, for example, a heavy doped n ++ region, and may be formed of the substrate 10. It is responsible for forming the electric field from the front.
  • the auxiliary electrode layer 30 is deposited on the substrate 10 (S240).
  • the auxiliary electrode layer 30 formed on the substrate 10 through the step S240 is not only deposited on the dielectric layer 20 but also a highly doped region of the second conductive impurity locally exposed in the upper layer of the substrate 10. It is deposited to be in direct contact with (10-2).
  • step S240 As shown in FIG. 19 by performing a screen printing process, the front electrode 14 in a pattern such as to widen the interval (d) as much as possible to secure the maximum light receiving surface on the auxiliary electrode layer (30) To form (S250).
  • the front metal material including silver (Ag) is coated on the auxiliary electrode layer 30 in a desired pattern, and then the firing process is preferably performed.
  • Localized emitter solar cells as illustrated in FIGS. 11 to 12 may be manufactured by the above-described steps S200 to S250.
  • the seed layer 20-1 which lowers the specific resistance upon contact with the substrate 10 is formed of a high concentration doped region of the second conductive impurity.
  • the auxiliary electrode layer 30 is deposited on the substrate 10, and then, the above-described step S250 is performed to perform the above-described step S250.
  • Localized emitter solar cells as shown in FIG. 12 may be fabricated.
  • the auxiliary electrode layer 30 formed on the substrate 10 is also deposited on the dielectric layer 20, but the high concentration doped region 10-2 of the second conductive impurity formed locally exposed on the upper layer of the substrate 10. Is deposited to contact the plating layer 20-1.
  • a first conductive substrate 10 made of silicon material having a front electrode 14 and a rear electrode 15 disposed on upper and lower surfaces thereof.
  • a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer of the substrate 10, and a high concentration doped region of the second conductive impurity in the upper portion of the substrate 10 (
  • the highly doped region 10-3 of the first conductivity type impurity is formed in a portion other than the formation portion of 10-2).
  • the front electrode 14 has a structure in contact with the highly doped region 10-2 of the second conductive type impurity.
  • the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
  • the highly doped region 10-2 of the second conductive type impurity is formed in the upper layer of the substrate 10 to form a pn junction in the substrate 10, thereby enabling the movement of the minority carriers photogenerated by solar incidence. As a result, a potential difference may be generated in the substrate 10, and the contact resistance between the metallic front electrode 14 and the interface between the substrate 10 may be reduced.
  • the high concentration doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 ⁇ m to 2300 ⁇ m) in order to reduce the moving distance of the few carriers generated in the substrate 10. If the distance between the front electrode 14 to be formed in contact with the upper surface is too narrow, there is a risk of shading loss due to the electrode, so the distance between the front electrode 14 to be formed in contact with the upper surface is reduced. It is preferable to be formed to have an appropriate width (for example, about 20 to 40 ⁇ m) in consideration.
  • the heavily doped region 10-3 of the first conductive impurity is formed on the upper layer of the substrate 10 so as not to contact the heavily doped region 10-2 of the second conductive impurity and the front electrode 14. As a result, the surface of the substrate 10 of the photogenerated minority transporter is prevented.
  • the highly doped region 10-3 of the first conductivity type impurity may be formed on the substrate 10 so as to alternate with the heavily doped region 10-2 of the second conductivity type impurity at a predetermined interval.
  • the minority carriers generated in the substrate 10 do not approach the surface of the substrate 10 by the electric field generated by the highly doped region 10-3 of the first conductivity type impurity, and the second conductive
  • the surface recombination rate is remarkably higher than before. Is reduced.
  • dielectric layers 20 and 21 are formed on the upper and lower surfaces of the substrate 10 except for the portion where the front electrode 14 is formed, and silicon having dielectric properties is formed on the dielectric layer 20 formed on the upper surface of the substrate 10.
  • An anti-reflective coating (ARC) 13 composed of oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like is stacked.
  • the dielectric layers 20 and 21 may serve as passivation, for example, BSG (Boron Silicate Glass). If the first conductivity type is n-type, PSG (Phosphorus Silicate Glass) is formed. Can be.
  • the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
  • the front electrode 14 may be formed, for example, in a finger line pattern or the like, and may be formed on the substrate 10 so as to correspond to the formation position of the highly doped region 10-2 of the locally formed second conductive impurities. It is formed on the surface, it is formed with a line width (W) of about 20 ⁇ m 40 ⁇ m, it is preferable that the spacing (d) between the electrodes is formed to be about 450 ⁇ m to 2300 ⁇ m.
  • the front electrode 14 has a line width 1/2 to 1/4 of the size of a general solar cell, the spacing between electrodes is 1/2 to 1/4 in comparison with the distance between the front electrodes of a general solar cell. Even if it is narrowed enough, the light receiving surface of the same level as that of the general solar cell can be secured.
  • the front electrode 14 may include a seed layer 14-2 for lowering a contact resistivity in a lower layer directly contacting the substrate 10.
  • a first conductive silicon substrate 10 is prepared (S300).
  • step S300 a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • KOH potassium hydroxide
  • a portion where the front electrode 14 is to be formed that is, a highly doped region 10-2 of the second conductive impurity is formed.
  • a high concentration doped region 10-3 of the first conductive impurity is formed by locally heavy doping the first conductive impurity on the upper portion of the substrate 10, particularly the upper layer of the substrate 10 except for the portion to be formed. (S310).
  • step S310 an impurity ion implantation process, a laser doping, or a diffusion process using an impurity paste as a source may be performed.
  • the diffusion barrier may or may not be used in the diffusion process.
  • the high concentration doping region 10-3 of the first conductivity type impurity formed in the upper layer portion of the substrate 10 through step S310 may be formed of, for example, a p + region. It is responsible for forming an electric field to prevent.
  • the dielectric layers 20 and 21 are formed on the front surface, that is, the front and rear surfaces of the substrate 10 by performing a heat treatment process or a deposition process (S320).
  • step S320 As shown in Figure 27 through a chemical vapor deposition process, to form an anti-reflection film 13 on the front surface of the substrate 10 (S330).
  • the anti-reflection film 13 may be composed of a silicon nitride film (Si 3 N 4 ), for example, forming the silicon nitride film through a PECVD process, discharge and activate the source gas SiH 4 and NH 3 in a plasma state It can be implemented through a method for producing a silicon nitride film.
  • the anti-reflection film 13 may be made of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), or the like.
  • a metal material including aluminum (Al), silver (Ag), and the like is coated on the rear surface of the substrate 10, and a firing process is performed, as shown in FIG. 28, as shown in FIG. 28.
  • the rear electrode 15 is formed on the rear surface of the battery (S340).
  • the high-concentration doping layer 10-1 of the first conductive type impurity having aluminum (Al) as the source of the metal material applied to the rear surface of the substrate 10 is formed by the heat treatment during the baking process.
  • the dielectric layer 21 formed on the lower surface of the substrate through step S310 is formed of the first conductive impurity due to the doping of the first conductive impurity. It is preferably included in the heavily doped layer 10-1.
  • step S340 the laser doping process is performed to locally remove the antireflection film 13 and the dielectric layer 20 formed on the substrate 10, and to simultaneously remove the antireflection film ( 13) and heavily doped the second conductive impurity on the upper layer of the substrate 10 from which the dielectric layer 20 has been removed, and thus the heavily doped region 10-2 of the second conductive impurity on the upper layer of the substrate 10. ) Is formed by locally exposing (S350).
  • the high concentration doped region 10-2 of the second conductive impurity formed in the upper layer of the substrate 10 through step S350 is formed to alternate with the high concentration doped region 10-3 of the first conductive impurity.
  • it may consist, for example, of n ++ regions.
  • the front electrode 14 is formed to contact the high concentration doped region 10-2 of the second conductive impurity formed in the upper layer of the substrate 10 by performing the plating process (S360).
  • the front electrode 14 formed through the step S360 is not in contact with the high concentration doping region 10-3 of the first conductivity type impurity formed on the upper layer of the substrate 10, and the high concentration doping region 10 of the second conductivity type impurity 10 is formed. -2) is preferably formed in contact with the top.
  • step S360 only the metal plating is performed to directly contact the high concentration doped region 10-2 of the second conductivity type impurity, or the seed layer 14 lowering the specific resistance upon contact with the substrate 10. -2) may be deposited to directly contact the heavily doped region 10-2 of the second conductivity type impurity, and then the front electrode 14 may be formed by metal plating on the seed layer 14-2.
  • Localized emitter solar cells as illustrated in FIG. 22 may be manufactured by the above-described steps S300 to S360.
  • the substrate except for the region where the front electrode 14 is to be formed that is, the region where the highly doped region 10-2 of the second conductive impurity is to be formed.
  • a-Si a heavily doped amorphous silicon
  • a localized emitter solar cell is a silicon-based first conductive substrate having a front electrode 14 and a rear electrode 15 at upper and lower portions thereof.
  • a high concentration doping region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and has a high concentration doping of the second conductive impurity in the upper portion of the substrate 10.
  • a highly doped region 10-3 of the first conductivity type impurity is formed in a portion other than the region in which the region 10-2 is formed, and the dielectric layer 20 and the auxiliary electrode layer are formed between the substrate 10 and the front electrode 14. It has a structure in which 30 is laminated one by one.
  • the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
  • the highly doped region 10-2 of the second conductive type impurity is formed in the upper layer of the substrate 10 to form a pn junction in the substrate 10, thereby enabling the movement of the minority carriers photogenerated by solar incidence.
  • the potential difference can be generated inside the substrate 10.
  • the highly doped region 10-2 of the second conductive type impurity is formed in a dot pattern having a regular size and spacing on the upper layer of the substrate 10 as shown in FIG. 31A, or FIG. 31.
  • the upper layer of the substrate 10 is preferably formed with a line pattern having a regular line width and spacing, but has a dot pattern having an irregular size and spacing, or an irregular line width and spacing. It may also be formed in a line pattern. That is, the heavily doped region 10-2 of the second conductive type impurity may be formed in the upper layer of the substrate 10 in various forms without restriction of the pattern form.
  • the highly doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 ⁇ m to 2300 ⁇ m) in order to reduce the moving distance of the photo-generated minority transporter in the substrate 10. It is preferably formed to have a suitable width (for example, about 20 ⁇ m to 40 ⁇ m).
  • the heavily doped region 10-3 of the first conductive impurity is formed on the upper layer of the substrate 10 so as not to contact the heavily doped region 10-2 of the second conductive impurity and the auxiliary electrode layer 30. As a result, the surface of the substrate 10 of the photogenerated minority transporter is prevented.
  • the highly doped region 10-3 of the first conductivity type impurity may be formed on the substrate 10 so as to alternate with the heavily doped region 10-2 of the second conductivity type impurity at a predetermined interval.
  • the minority carriers generated in the substrate 10 do not approach the surface of the substrate 10 by the electric field generated by the highly doped region 10-3 of the first conductivity type impurity, and the second conductive
  • the high concentration doped region 10-2 of the dopant-type impurities and the auxiliary electrode layer 30 are collected by the front electrode 14, thereby allowing the In comparison, the surface recombination rate is significantly reduced.
  • the dielectric layer 20 is formed on a portion of the upper surface of the substrate 10 except for the exposed portion of the highly doped region 10-2 of the second conductive impurity.
  • the dielectric layer 20 may be formed of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like, and the front passivation of the substrate 10 may be performed. (Passivation) Plays a role.
  • the auxiliary electrode layer 30 is formed by being stacked on the dielectric layer 20 so as to contact the high concentration doped region 10-2 of the second conductivity type impurity directly or via a plating layer.
  • the auxiliary electrode layer 30 is photogenerated in the substrate 10, and a few carriers collected through the high concentration doping region 10-2 of the second conductivity type impurity can move to the front electrode 14 by moving. It is composed of a material that provides a migration path, for example, it may be made of a transparent conductive oxide film (TCO).
  • TCO transparent conductive oxide film
  • the dielectric layer 20 and the auxiliary electrode layer 30 are each formed to have a predetermined thickness in consideration of refractive index, so that an anti-reflection film (ARC) can prevent light reflection loss of the upper surface of the substrate 10, that is, the light receiving surface.
  • ARC anti-reflection film
  • the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
  • the front electrode 14 may trap a small number of carriers through the auxiliary electrode layer 30 stacked on the substrate 10 as a whole, the second conductive type impurities locally formed on the upper layer of the substrate 10 are dared. Since the patterning does not need to correspond to the formation position of the heavily doped region 10-2, the upper surface of the auxiliary electrode layer 30 does not correspond to the formation position of the heavily doped region 10-2 of the second conductive type impurity. Can be formed on. Of course, if necessary, the front electrode 14 may be formed on the upper surface of the auxiliary electrode layer 30 to correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity.
  • the front electrode 14 may be formed in a pattern such as a finger line shape, wherein the front electrode 14 has a narrow line width (W) of about 20 ⁇ m to 40 ⁇ m, and between electrodes of about 1800 ⁇ m to 2300 ⁇ m. It is formed to have a gap (d) or, if necessary, to have a gap (d) between the electrodes exceeding 2300 ⁇ m within a range that does not exceed the light receiving surface of the substrate 10, compared to the light receiving surface of a typical solar cell A wider light receiving surface can be secured.
  • the front electrode 14 may be formed in a direction parallel or perpendicular to the pattern of the highly doped region 10-2 of the second conductive impurity.
  • a first conductive silicon substrate 10 is prepared (S400).
  • step S400 a saw damage etching process is performed to etch the substrate 10 in a chemical manner in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • a saw damage etching process is performed to etch the substrate 10 in a chemical manner in order to remove a defect portion generated as a result of the cutting process of the substrate 10.
  • KOH potassium hydroxide
  • the upper portion of the substrate 10 except for the region where the high concentration doped region 10-2 of the second conductivity type impurity is to be formed In particular, the heavily doped first conductive impurities are locally formed on the upper layer of the substrate 10 to form a highly doped region 10-3 of the first conductive impurities (S410).
  • step S410 an impurity ion implantation process, a laser doping, or a diffusion process using an impurity paste as a source may be performed.
  • the diffusion barrier may or may not be used in the diffusion process.
  • the high concentration doping region 10-3 of the first conductivity type impurity formed in the upper layer of the substrate 10 through step S410 may be formed of, for example, a p + region. It is responsible for forming an electric field to prevent.
  • dielectric layers 20 and 21 are formed on the surface of the substrate 10 (S420).
  • the dielectric layer 20 including the silicon nitride layer Si 3 N 4 may be formed only on the upper surface of the substrate 10 by performing a chemical vapor deposition process such as a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal material including aluminum (Al), silver (Ag), and the like is applied to the rear surface of the substrate 10, and the firing process is performed, as shown in FIG. A rear electrode 15 is formed on the lower surface (S430).
  • a high concentration doping layer 10-1 of a first conductive type impurity having aluminum (Al) as a source of the metal material applied to the lower surface of the substrate 10 is formed by heat treatment during the firing process. It is naturally formed in the lower layer of the (10), wherein the dielectric layer 21 formed on the lower surface of the substrate 10 through the step S420 is the first due to the doping of the first conductive type impurities sourced from aluminum (Al) It is preferably included in the highly doped layer 10-1 of the conductive impurity.
  • step S430 the laser doping process is performed to locally remove the dielectric layer 20 formed on the substrate 10 and to remove the dielectric layer 20.
  • the second conductive impurity is heavy-doped on the upper layer of 10), and the high concentration doped region 10-2 of the second conductive impurity is locally exposed on the upper layer of the substrate 10 (S440).
  • the high concentration doped region 10-2 of the second conductive impurity formed in the upper layer portion of the substrate 10 through step S440 is formed to alternate with the high concentration doped region 10-3 of the first conductive impurity.
  • it may consist, for example, of n ++ regions.
  • the auxiliary electrode layer 30 is deposited on the substrate 10 (S450).
  • the auxiliary electrode layer 30 formed on the substrate 10 through the step S450 is not only deposited on the dielectric layer 20 but also a highly doped region of the second conductive impurity locally exposed on the substrate 10. It may be deposited so as to be in direct contact with (10-2).
  • step S450 as shown in FIG. 39 by performing a screen printing process, the front electrode 14 in a pattern such as to widen the interval (d) as much as possible to secure the maximum light receiving surface on the auxiliary electrode layer (30) To form (S460).
  • the front electrode 14 When forming the front electrode 14 in the step S460 described above, it is preferable to apply a metal material composed of silver (Ag) or the like on the auxiliary electrode layer 30 in a desired pattern, and then proceed with the firing process.
  • a metal material composed of silver (Ag) or the like on the auxiliary electrode layer 30 in a desired pattern, and then proceed with the firing process.
  • step S450 first, the plating layer 20-1, which lowers the specific resistance upon contact with the substrate 10, is heavily doped with the second conductive impurity. After the deposition is made in direct contact with the region 10-2, the entire auxiliary electrode layer 30 is deposited on the substrate 10, and then the above-described step S460 is performed to perform the localization emitter as shown in FIG. 41. Solar cells can be manufactured.
  • the first conductive type is formed on the upper surface of the substrate 10 except for the portion where the high concentration doped region 10-2 of the second conductive type impurity is to be formed.
  • a-Si doped heavy-doped amorphous silicon
  • Localized emitter solar cells having a structure stacked on the upper surface of the substrate 10 may be manufactured so as not to.
  • heat treatment is performed when the above steps S420 to S460 are performed, heat treatment is performed at a temperature of 400 ° C. or lower to prevent damage of the amorphous silicon (a-Si) thin film patterned on the upper surface of the substrate 10. It is preferable.
  • the localized emitter solar cell according to the present invention and a method of manufacturing the same are not limited to the above-described embodiment and can be carried out in various modifications within the range allowed by the technical idea of the present invention.
  • the emitter is electrically conductive to the light receiving site except for the emitter formation region of the light receiving site including the emitter and the electrode.
  • the localized emitter solar cell and a method for manufacturing the same while having a local emitter and an electrode at the light receiving portion of the substrate, a small number of carriers collected through the emitter between the emitter and the electrode
  • an auxiliary electrode layer for transferring to the electrode regardless of the shape of the electrode pattern, such as the line width, number and spacing of the electrode, it is possible to safely deliver a small number of carriers generated in the substrate to the electrode, the electrode to be formed on the light receiving portion of the substrate
  • the localized emitter solar cell and the manufacturing method according to the present invention there is no need to perform the cleaning process for removing the oxide film, the insulation process for forming the trench for disconnection, etc. It can shorten and reduce the manufacturing cost.

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Abstract

The present invention relates to a localized emitter solar cell and a method for manufacturing same, the localized emitter solar cell locally having on a light receiving region of a substrate an emitter and an electrode, and comprising: a step for preparing a first conductive substrate; a step for forming a dielectric layer on the surface of the substrate; a step for forming an antireflective film on the front surface of the substrate; a step for forming a rear surface electrode on the rear surface of the substrate; a step for locally removing the antireflective film and the dielectric layer formed on the front surface of the substrate, and forming locally on the front surface of the substrate a high-concentration doping area for a second conductive impurity; and a step for forming on top of the high-concentration doping area for the second conductive impurity a front surface electrode, the steps which enable manufacturing of the localized emitter solar cell, which minimizes the recombination rate of photo-produced minority carriers and increases the life time of the minority carriers, and forms an electrode pattern that can secure a light receiving surface of the substrate to the maximum, enhancing the efficiency of the solar cell.

Description

국부화 에미터 태양전지 및 그 제조 방법Localized emitter solar cell and its manufacturing method
본 발명은 국부화 에미터 태양전지 및 그 제조 방법에 관한 것으로, 특히 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비한 국부화 에미터 태양전지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a localized emitter solar cell and a method of manufacturing the same, and more particularly, to a localized emitter solar cell having a emitter and an electrode locally at a light receiving site of a substrate and a method of manufacturing the same.
태양전지는 태양광을 직접 전기로 변환시키는 태양광 발전의 핵심소자로서, 기본적으로 p-n 접합으로 이루어진 다이오드(Diode)라 할 수 있다.The solar cell is a key element of photovoltaic power generation that converts sunlight directly into electricity, and is basically a diode composed of a p-n junction.
태양광이 태양전지에 의해 전기로 변환되는 과정을 살펴보면, 태양전지에 태양광이 입사되어 태양전지 내부에 전자-정공 쌍이 생성되고, 전기장에 의해 전자는 n층으로, 정공은 p층으로 이동하게 되어 p-n 접합부 사이에 광기전력이 발생되며, 이때 태양전지의 양단에 부하나 시스템을 연결하면 전류가 흐르게 되어 전력을 생산할 수 있게 된다.In the process of converting sunlight into electricity by solar cells, solar light is incident on the solar cells to generate electron-hole pairs inside the solar cells, and electrons move to n layers and holes move to p layers by the electric field. Thus, photovoltaic power is generated between the pn junctions, and when a load or a system is connected to both ends of the solar cell, current flows to generate power.
한편, 태양전지는 p-n 접합층인 광흡수층의 형태나 불순물 이온 종류에 따라 다양하게 구분되는데 광흡수층으로는 대표적으로 실리콘(Si)을 들 수 있으며, 이와 같은 실리콘계 태양전지는 형태에 따라 실리콘 웨이퍼를 광흡수층으로 이용하는 실리콘 기판형과, 실리콘을 박막 형태로 증착하여 광흡수층을 형성하는 박막형으로 구분된다.On the other hand, solar cells are classified into various types according to the shape of the light absorption layer or the impurity ions, which are pn junction layers. Examples of the light absorption layer include silicon (Si). The silicon substrate type used as the light absorption layer is divided into a thin film type which forms a light absorption layer by depositing silicon in a thin film form.
실리콘계 태양전지 중 실리콘 기판형의 일반적인 구조를 예들 들어 살펴보면 다음과 같다.Looking at the general structure of the silicon substrate type of silicon-based solar cell as an example.
도 1에 도시한 바와 같이, 제1도전형 반도체층(11) 위에 에미터층인 제2도전형 반도체층(12)이 적층되며, 제2도전형 반도체층(12)의 상부면에 핑거 바 또는 버스 바 등의 패턴을 가진 전면전극(14)이 형성되고 제1도전형 반도체층(11)의 하부면에 후면전극(15)이 구비된 구조를 갖는다. As illustrated in FIG. 1, a second conductive semiconductor layer 12, which is an emitter layer, is stacked on the first conductive semiconductor layer 11, and a finger bar or the upper surface of the second conductive semiconductor layer 12 is formed. A front electrode 14 having a pattern such as a bus bar is formed and a rear electrode 15 is provided on a lower surface of the first conductive semiconductor layer 11.
이때, 제1도전형 반도체층(11) 및 제2도전형 반도체층(12)은 하나의 실리콘 기판(10)에 구현되는 것으로서, 실리콘 기판(10)의 하부는 제1도전형 반도체층(11), 실리콘 기판(10)의 상부는 제2도전형 반도체층(12)으로 구분되며, 제1도전형 반도체층(11)의 하부에는 후면 전계 형성을 위한 제1도전형 불순물의 고농도 도핑층(10-1)이 구비되고, 상부면에 전면전극(14)이 형성된 제2도전형 반도체층(12)에는 제2도전형 불순물의 고농도 도핑 영역(10-2)이 구비된다.In this case, the first conductive semiconductor layer 11 and the second conductive semiconductor layer 12 are implemented on one silicon substrate 10, and the lower portion of the silicon substrate 10 is the first conductive semiconductor layer 11. The upper portion of the silicon substrate 10 is divided into the second conductive semiconductor layer 12, and a lower concentration doped layer of the first conductive impurity for forming a backside electric field is formed below the first conductive semiconductor layer 11. 10-1) and the second conductive semiconductor layer 12 having the front electrode 14 formed on an upper surface thereof, are provided with a highly doped region 10-2 of the second conductive impurity.
이러한, 기판형 실리콘계 태양전지의 일반적인 제조 과정을 살펴보면, 먼저 제1도전형의 실리콘 기판(10)을 준비하고, 준비된 실리콘 기판(10)의 표면 텍스쳐링, 제2도전형의 불순물 이온 주입(Doping)·확산(Diffusion)을 통한 제2도전형 반도체층(12) 형성, 전면전극(14) 및 후면전극(15) 형성 등의 공정을 거쳐 제조된다.Looking at the general manufacturing process of such a substrate-type silicon solar cell, first preparing a silicon substrate 10 of the first conductivity type, surface texturing of the prepared silicon substrate 10, doping impurity ion (Doping) of the second conductivity type The second conductive semiconductor layer 12 is formed through diffusion, and the front electrode 14 and the rear electrode 15 are formed.
한편, 전면전극(14) 및 후면전극(15)의 형성 이전에는, 확산 공정에 의해 기판(10) 표면에 형성된 PSG(Phosphorus Silicate Glass)막 또는 BSG(Boron Silicate Glass)막 등의 불순물을 포함한 불순물 산화막을 제거하는 세정 공정 및 제2도전형 반도체층(12) 위에 반사방지막(13)을 형성하는 공정 등을 진행하고, 실리콘 기판(10)의 표면과 전면전극(14) 간의 접촉 저항을 감소시키기 위하여 전면전극(14)이 형성될 부위에 해당하는 제2도전형 반도체층(12)에는 제2도전형 불순물의 고농도 도핑 영역(10-2), 즉 에미터를 선택적으로 형성하게 된다.Meanwhile, before the front electrode 14 and the back electrode 15 are formed, impurities including impurities such as a PSG (Phosphorus Silicate Glass) film or a BSG (Boron Silicate Glass) film formed on the surface of the substrate 10 by a diffusion process are formed. A cleaning process for removing an oxide film and a process for forming an anti-reflection film 13 on the second conductive semiconductor layer 12, and the like, to reduce contact resistance between the surface of the silicon substrate 10 and the front electrode 14. In order to form the second conductive semiconductor layer 12 corresponding to the portion where the front electrode 14 is to be formed, a highly doped region 10-2, that is, an emitter, of the second conductive impurity is selectively formed.
여기서, 제1도전형 불순물의 고농도 도핑층(10-1)은 제1도전형 반도체층(11)에 비해 높은 에너지 장벽을 가진 후면 전계를 형성하기 때문에, 추후 제1도전형 반도체층(11) 내에서 태양광 입사에 의해 광생성된 소수 운송자(1)가 후면전극(15)으로 이동하는 것을 차단하는 역할을 수행하게 된다.Here, since the highly doped layer 10-1 of the first conductivity type impurity forms a backside electric field having a higher energy barrier than the first conductivity type semiconductor layer 11, the first conductivity type semiconductor layer 11 is later formed. The small number of carriers (1) generated by the solar light incident in the inside serves to block the movement to the rear electrode (15).
아울러, 전면전극(14) 및 후면전극(15)의 형성 이후에는, 소성 공정을 통해 제1도전형 반도체층(11)의 하부에 제1도전형 불순물의 고농도 도핑층(10-1)을 형성하고, 레이저를 이용하여 기판 전면의 둘레를 따라 일정 깊이의 단선용 트렌치를 형성하는 절연 공정을 진행하게 된다.In addition, after the formation of the front electrode 14 and the rear electrode 15, a high concentration doping layer 10-1 of the first conductivity type impurity is formed under the first conductivity type semiconductor layer 11 through a firing process. In addition, an insulating process of forming a trench for disconnection of a predetermined depth is performed along the circumference of the front surface of the substrate using a laser.
이는, 제2도전형 반도체층(12) 형성시, 제2도전형 불순물 이온이 포함된 용액에 실리콘 기판(10)을 담그고 후속으로 열처리 공정을 수행하여, 제2도전형 불순물 이온을 실리콘 기판(10) 내에 확산시키는 방식으로 진행되기 때문에, 실리콘 기판(10)의 상부 이외에 측부에도 제2도전형 반도체층이 형성되는데, 이와 같이 기판의 측부에 형성된 제2도전형 반도체층은 전면전극(14)과 후면전극(15)을 단락(short)시켜 태양전지의 광전변환 효율을 저하시키는 요인으로 작용하므로, 실리콘 기판(10)의 측부에 형성된 제2도전형 반도체층에 의한 전면전극(14)과 후면전극(15) 사이의 전기적 연결을 차단시킬 필요가 있기 때문이다.When the second conductive semiconductor layer 12 is formed, the silicon substrate 10 is immersed in a solution containing the second conductive impurity ions and subsequently subjected to a heat treatment process, thereby forming the second conductive impurity ions into a silicon substrate ( 10), the second conductive semiconductor layer is formed on the side of the substrate in addition to the upper portion of the silicon substrate 10. Thus, the second conductive semiconductor layer formed on the side of the substrate is the front electrode 14; Since the back electrode 15 is shorted to act as a factor of reducing photoelectric conversion efficiency of the solar cell, the front electrode 14 and the rear surface of the second conductive semiconductor layer formed on the side of the silicon substrate 10 are reduced. This is because it is necessary to interrupt the electrical connection between the electrodes 15.
이와 같은 일반적인 태양전지에서의 광 발전시 소수 운송자(1)의 이동 과정을 살펴보면, 예컨대 제1도전형이 p형, 제2도전형이 n형인 경우, 태양광이 입사됨에 따라 제1도전형 반도체층(11) 내에서 광생성된 소수 운송자(1)인 전자는 제2도전형 반도체층(12), 즉 에미터층이 형성되어 있는 실리콘 기판(10)의 전면 쪽으로 이동하게 된다. 이때, 다수 운송자(2)인 정공은 실리콘 기판(10)의 후면 쪽으로 이동하게 된다.Looking at the movement of the minority transporter (1) during photovoltaic power generation in such a general solar cell, for example, when the first conductivity type is p-type, the second conductivity type is n-type, as the solar light enters the first conductive semiconductor The electrons, which are the minority carriers 1 generated in the layer 11, move toward the front surface of the silicon substrate 10 on which the second conductive semiconductor layer 12, that is, the emitter layer, is formed. At this time, the hole which is the majority carrier 2 is moved toward the rear side of the silicon substrate 10.
이러한 일반적인 태양전지에는 깊이 방향에 따른 불순물 도핑 농도가 상부에서 가장 높고 하부쪽으로 내려갈수록 감소하는 특성을 보이며, 이에 따라 에너지 밴드 구조상 전도대(Conduction Band)가 상부쪽으로 갈수록 낮아지는 특성을 갖는 제2도전형 반도체층(12), 즉 에미터층이 실리콘 기판(10)의 수광면 전체에 형성되어 있으므로, 에미터층의 깊이 방향 에너지 밴드 구조에 의해, 제1도전형 반도체층(11)에서 광생성된 소수 운송자가 에미터층을 따라 이동하되, 특히 반사방지막(13)에 근접한 에미터층의 상부, 즉 실리콘 기판(10)의 표면을 따라 이동하다가 전면전극(14)으로 포집되게 된다.In such a general solar cell, the impurity doping concentration in the depth direction is highest at the top and decreases toward the bottom, and accordingly, the conduction band is lowered toward the top in the energy band structure. Since the semiconductor layer 12, that is, the emitter layer, is formed on the entire light-receiving surface of the silicon substrate 10, the minority transport photogenerated in the first conductive semiconductor layer 11 by the depth energy band structure of the emitter layer. The self moves along the emitter layer, and in particular, moves along the surface of the silicon substrate 10 above the emitter layer adjacent to the anti-reflection film 13 and is collected by the front electrode 14.
그러나, 이와 같은 종래의 태양전지는 소수 운송자(1)의 이동 경로인 실리콘 기판(10)의 표면 부위가 결정 결함 및 불순물 등이 다수 존재하는 결함 밀도가 높은 부위이기 때문에, 소수 운송자(1)가 전면전극(14)으로 포집되기 전에 재결합하여 쉽게 소실될 우려가 있다.However, since the surface area of the silicon substrate 10, which is the movement path of the minority transporter 1, is a high density of defects in which a large number of crystal defects and impurities exist, the minority transporter 1 has such a conventional solar cell. There is a fear that it may be easily lost by recombination before being collected by the front electrode 14.
더욱이, 종래의 태양전지는 100㎛ 내지 140㎛ 이내의 큰 선폭(W)을 가지는 전면전극(14)을 실리콘 기판(10)의 전면, 즉 수광면에 형성해야 하기 때문에, 수광율 유지를 위한 충분한 면적의 수광면을 확보하기 위해 전면전극(14) 간의 간격(d)이 1800㎛ 내지 2300㎛ 이내로 매우 크게 형성되어 있어, 제1도전형 반도체층(11)에서 광생성된 소수 운송자(1)가 실리콘 기판(10)의 표면 부위를 따라 전면전극(14)까지 이동하는 거리가 길어지게 되므로, 소수 운송자(1)가 전면전극(14)으로 포집되기 전에 실기콘 기판(10)의 표면에서 재결합하여 소실될 가능성이 증가하게 된다.Furthermore, in the conventional solar cell, since the front electrode 14 having a large line width W within a range of 100 µm to 140 µm must be formed on the front surface of the silicon substrate 10, that is, the light receiving surface, it is sufficient to maintain the light receiving rate. In order to secure the light receiving surface of the area, the distance d between the front electrodes 14 is very large, within 1800 μm to 2300 μm, so that the minority carriers 1 generated in the first conductive semiconductor layer 11 Since the distance to the front electrode 14 along the surface portion of the silicon substrate 10 becomes longer, the minority transporter 1 is recombined on the surface of the silicon substrate 10 before being collected by the front electrode 14. The likelihood of disappearance increases.
즉, 종래의 태양전지는 그 구조상, 실리콘 기판(10) 내에서 광생성된 소수 운송자(1)의 재결합율이 높아 광전 변환 효율이 떨어지는 문제점이 있다.That is, the conventional solar cell has a problem in that the photoelectric conversion efficiency is low due to its high recombination rate of the minority transporter 1 photogenerated in the silicon substrate 10.
또한, 종래의 태양전지는 제조시, 산화막 제거를 위한 세정 공정 및 단선용 트렌치를 형성하는 절연 공정 등의 복잡한 공정 절차가 필요함에 따라, 제조 기간 및 제조 비용이 많이 소요되는 문제점이 있다.In addition, a conventional solar cell requires a complicated process procedure such as a cleaning process for removing an oxide film and an insulation process for forming a trench for disconnection, and thus, a manufacturing period and a manufacturing cost are high.
본 발명은 전술한 바와 같은 문제점을 해결하기 위해 안출된 것으로, 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비한 국부화 에미터 태양전지 및 그 제조 방법을 제공하는데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and provides a localized emitter solar cell having an emitter and an electrode locally at a light receiving portion of a substrate, and an object thereof.
또한, 본 발명은 에미터와 전극 사이에 에미터를 통해 수집된 소수 운송자를 전극으로 전달하기 위한 보조전극층을 구비한 국부화 에미터 태양전지 및 그 제조 방법을 제공하는데, 그 목적이 있다.In addition, the present invention provides a localized emitter solar cell having a secondary electrode layer for transferring a small number of carriers collected through the emitter between the emitter and the electrode to the electrode, and a method thereof.
또한, 본 발명은 기판의 수광 부위 중 에미터 형성 영역을 제외한 수광 부위에 에미터의 도전형과 반대 극성을 가진 도전형 불순물의 도핑 영역을 구비한 국부화 에미터 태양전지 및 그 제조 방법을 제공하는데, 그 목적이 있다.The present invention also provides a localized emitter solar cell having a doped region of a conductive impurity having a polarity opposite to that of the emitter in a light receiving portion of the light receiving portion of the substrate except for the emitter forming region, and a method of manufacturing the same. There is a purpose.
전술한 바와 같은 목적을 달성하기 위한 본 발명의 제1실시예에 따른 국부화 에미터 태양전지는, 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며, 상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며, 상기 전면전극은 상기 제2도전형 불순물의 고농도 도핑 영역에 접촉 형성되는 것이 바람직하다.The localized emitter solar cell according to the first embodiment of the present invention for achieving the object as described above comprises a first conductive substrate of silicon material having a front electrode and a rear electrode on the upper and lower surfaces, The highly doped region of the second conductive impurity is locally formed in the upper layer of the substrate, and the front electrode is formed in contact with the heavily doped region of the second conductive impurity.
한편, 본 발명의 제1실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 상층부에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 후면에 후면 금속 물질을 도포하는 단계와; 스크린 프린팅 공정을 통해 상기 제2도전형 불순물의 고농도 도핑 영역 상부에 전면 금속 물질을 도포하는 단계와; 소성 공정을 진행하여 상기 기판의 전후면에 전면전극 및 후면전극을 형성하는 단계를 포함하여 이루어지는 것이 바람직하다.On the other hand, the method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention comprises the steps of preparing a substrate of the first conductive type; Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate; Applying a back metal material to a back side of the substrate; Applying a front metal material over the high concentration doped region of the second conductive impurity through a screen printing process; It is preferable to include the step of forming a front electrode and a back electrode on the front and rear surfaces of the substrate by the firing process.
다르게는, 본 발명의 제1실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 표면에 유전층을 형성하는 단계와; 상기 기판의 전면에 반사방지막을 형성하는 단계와; 상기 기판의 후면에 후면전극을 형성하는 단계와; 레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막 및 유전층을 국부적으로 제거하며, 상기 기판의 전면에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 도금 공정(Plating)을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어질 수 있다.Alternatively, the method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention includes the steps of preparing a substrate of a first conductivity type; Forming a dielectric layer on the surface of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; Locally removing the anti-reflection film and the dielectric layer formed on the front surface of the substrate through a laser doping method, and forming a highly doped region of the second conductive impurity locally on the front surface of the substrate; And forming a front electrode on the high concentration doped region of the second conductive impurity by performing a plating process.
또한, 본 발명의 제2실시예에 따른 국부화 에미터 태양전지는, 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며, 상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며, 상기 기판과 상기 전면전극 사이에 유전층 및 보조전극층이 차례로 적층되어 구성되는 것이 바람직하다.In addition, the localized emitter solar cell according to the second embodiment of the present invention includes a first conductive substrate of silicon material having a front electrode and a rear electrode on the upper and lower surfaces thereof, and a second layer on the upper portion of the substrate. A high concentration doped region of a conductive impurity is locally formed, and a dielectric layer and an auxiliary electrode layer are sequentially stacked between the substrate and the front electrode.
한편, 본 발명의 제2실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 표면에 유전층을 형성하는 단계와; 상기 기판의 하부면에 후면전극을 형성하는 단계와; 상기 기판의 상층부에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 상부에 보조전극층을 증착시키는 단계와; 상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어지는 것이 바람직하다.On the other hand, the method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention comprises the steps of preparing a substrate of the first conductive type; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate; Depositing an auxiliary electrode layer on the substrate; It is preferable to include forming a front electrode on the auxiliary electrode layer.
또한, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지는, 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며, 상기 기판의 상부에는 상기 전면전극이 접촉 형성되는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며, 상기 기판의 상부 중 상기 제2도전형 불순물의 고농도 도핑 영역의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역이 형성되되, 상기 제1도전형 불순물의 고농도 도핑 영역은 상기 제2도전형 분순물의 고농도 도핑 영역 및 상기 전면전극과 접촉되지 않도록 형성되는 것이 바람직하다.In addition, the localized emitter solar cell according to the third embodiment of the present invention includes a first conductive substrate made of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces, and the front of the substrate A high concentration doped region of the second conductive impurity in which the electrode is formed in contact is locally formed, and a high concentration doped region of the first conductive impurity is formed in a portion of the upper portion of the substrate except for the formation region of the high concentration doped region of the second conductive impurity. A region is formed, wherein the highly doped region of the first conductive impurity is formed so as not to contact the heavily doped region of the second conductive impurities and the front electrode.
한편, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 상층부에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 전면에 반사방지막을 형성하는 단계와; 상기 기판의 후면에 후면전극을 형성하는 단계와; 레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막을 국부적으로 제거하며, 상기 기판의 상층부에 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 도금 공정을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어지는 것이 바람직하다.On the other hand, the method of manufacturing a localized emitter solar cell according to a third embodiment of the present invention comprises the steps of preparing a substrate of the first conductive type; Forming a highly doped region of a first conductivity type impurity locally in an upper layer of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity. Making a step; It is preferable to include the step of forming a front electrode on top of the high concentration doped region of the second conductive type impurity by the plating process.
다르게는, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 상부면 위에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 전면에 반사방지막을 형성하는 단계와; 상기 기판의 후면에 후면전극을 형성하는 단계와; 레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막을 국부적으로 제거하며, 상기 기판의 상층부에 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 도금 공정을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어질 수 있다.Alternatively, the method of manufacturing a localized emitter solar cell according to the third embodiment of the present invention includes the steps of preparing a substrate of a first conductivity type; Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate; Forming an anti-reflection film on the entire surface of the substrate; Forming a rear electrode on a rear surface of the substrate; The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity. Making a step; And forming a front electrode on the high concentration doped region of the second conductive impurity by performing a plating process.
또한, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지는, 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며, 상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며, 상기 기판의 상부 중 상기 제2도전형 불순물의 고농도 도핑 영역의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역이 형성되며, 상기 기판과 상기 전면전극 사이에 유전층 및 보조전극층이 차례로 적층되어 구성되는 것이 바람작하다.In addition, the localized emitter solar cell according to the fourth embodiment of the present invention includes a first conductive substrate of silicon material having a front electrode and a rear electrode on upper and lower surfaces thereof, and a second layer formed on an upper layer of the substrate. A high concentration doped region of a conductive impurity is locally formed, and a high concentration doped region of a first conductive impurity is formed in a portion of the upper portion of the substrate except for a portion of the high concentration doped region of the second conductive impurity. It is preferable that a dielectric layer and an auxiliary electrode layer are sequentially stacked between the front electrode and the front electrode.
한편, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 상부에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 표면에 유전층을 형성하는 단계와; 상기 기판의 하부면에 후면전극을 형성하는 단계와; 레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 유전층을 국부적으로 제거하며, 상기 기판의 상층부에 상기 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 상부에 보조전극층을 증착시키는 단계와; 상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어지는 것이 바람직하다.On the other hand, the method of manufacturing a localized emitter solar cell according to a fourth embodiment of the present invention comprises the steps of preparing a substrate of the first conductive type; Forming a heavily doped region of a first conductivity type impurity locally on the substrate; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity. Making a step; Depositing an auxiliary electrode layer on the substrate; It is preferable to include forming a front electrode on the auxiliary electrode layer.
다르게는, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지 제조 방법은, 제1도전형의 기판을 준비하는 단계와; 상기 기판의 상부면 위에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 표면에 유전층을 형성하는 단계와; 상기 기판의 하부면에 후면전극을 형성하는 단계와; 레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 유전층을 국부적으로 제거하며, 상기 기판의 상층부에 상기 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와; 상기 기판의 상부에 보조전극층을 증착시키는 단계와; 상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어질 수 있다.Alternatively, the method of manufacturing a localized emitter solar cell according to the fourth embodiment of the present invention includes the steps of preparing a substrate of a first conductivity type; Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate; Forming a dielectric layer on the surface of the substrate; Forming a rear electrode on the lower surface of the substrate; The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity. Making a step; Depositing an auxiliary electrode layer on the substrate; And forming a front electrode on the auxiliary electrode layer.
본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비하되, 기판의 수광 부위 중 에미터 형성 영역을 제외한 수광 부위에 에미터의 도전형과 반대 극성을 가진 도전형 불순물의 도핑 영역을 구비함으로써, 광생성된 소수 운송자의 재결합율를 극소화시켜 소수 운송자의 라이프 타임을 증가시킬 수 있고, 에미터에 접촉되어 소수 운송자를 포집하는 전극의 선폭을 감소시킬 수 있어, 수광면을 최대한 확보하면서 태양전지의 광전 변환 효율을 극대화시킬 수 있는 효과가 있다.According to the localized emitter solar cell according to the present invention and a method for manufacturing the same, the emitter is electrically conductive to the light receiving site except for the emitter formation region of the light receiving site including the emitter and the electrode. By providing a doped region of a conductive impurity having a polarity opposite to the type, the recombination rate of the photogenerated minority carriers can be minimized to increase the lifetime of the minority carriers, and the line width of the electrode contacting the emitter to capture the minority carriers Since it can be reduced, there is an effect that can maximize the photoelectric conversion efficiency of the solar cell while ensuring the light receiving surface to the maximum.
또한, 본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비하되, 에미터와 전극 사이에 에미터를 통해 수집된 소수 운송자를 전극으로 전달하기 위한 보조전극층을 구비함으로써, 전극의 선폭, 개수 및 간격 등과 같은 전극 패턴 형태에 상관없이, 기판 내에서 광생성된 소수 운송자를 안전하게 전극으로 전달할 수 있어, 기판의 수광 부위에 형성될 전극의 선폭 및 개수를 감소시키고 전극 간 간격을 최대화시키는 등, 기판의 수광면을 최대로 확보할 수 있는 전극 패턴을 형성할 수 있고, 이로 인해 태양전지의 수광율을 극대화시켜 태양전지의 효율을 증가시킬 수 있는 효과가 있다.In addition, according to the localized emitter solar cell and a method for manufacturing the same according to the present invention, while having a local emitter and an electrode at the light receiving portion of the substrate, a small number of carriers collected through the emitter between the emitter and the electrode By providing an auxiliary electrode layer for transferring to the electrode, regardless of the shape of the electrode pattern, such as the line width, number and spacing of the electrode, it is possible to safely deliver a small number of carriers generated in the substrate to the electrode, the electrode to be formed on the light receiving portion of the substrate It is possible to form an electrode pattern that can maximize the light receiving surface of the substrate, such as reducing the line width and number of electrodes and maximizing the distance between the electrodes, thereby maximizing the light reception rate of the solar cell, thereby increasing the efficiency of the solar cell. It can be effected.
또한, 본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 산화막 제거를 위한 세정 공정이나 단선용 트렌치 형성을 위한 절연 공정 등을 수행할 필요가 없어, 공정 절차를 간소화하여 제조 기간을 단축시킬 수 있으며, 제조 비용도 절감할 수 있는 효과가 있다.In addition, according to the localized emitter solar cell and the manufacturing method according to the present invention, there is no need to perform the cleaning process for removing the oxide film, the insulation process for forming the trench for disconnection, etc. It can shorten and reduce the manufacturing cost.
도 1은 일반적인 태양전지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a typical solar cell.
도 2는 본 발명의 제1실시예에 따른 국부화 에미터 태양전지의 구조를 나타낸 단면도.Figure 2 is a cross-sectional view showing the structure of a localized emitter solar cell according to a first embodiment of the present invention.
도 3은 본 발명의 제1실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 순서도.3 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention.
도 4 내지 도 10은 본 발명의 제1실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 단면도.4 to 10 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a first embodiment of the present invention.
도 11은 본 발명의 제2실시예에 따른 국부화 에미터 태양전지의 평면도.11 is a plan view of a localized emitter solar cell according to a second embodiment of the present invention.
도 12는 도 11에 있어서, A-A'에 따른 국부화 에미터 태양전지의 단면도.12 is a cross-sectional view of the localized emitter solar cell according to AA ′ in FIG. 11.
도 13은 본 발명의 제2실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 순서도.FIG. 13 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention. FIG.
도 14 내지 도 21은 본 발명의 제2실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 단면도.14 to 21 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention.
도 22는 본 발명의 제3실시예에 따른 국부화 에미터 태양전지의 구조를 나타낸 단면도.22 is a cross-sectional view illustrating a structure of a localized emitter solar cell according to a third embodiment of the present invention.
도 23은 도 22에 있어서, 전면전극의 구조를 나타낸 단면도.FIG. 23 is a cross-sectional view showing the structure of a front electrode in FIG. 22; FIG.
도 24는 본 발명의 제3실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 순서도.24 is a process flowchart illustrating a method of manufacturing a localized emitter solar cell according to the third embodiment of the present invention.
도 25 내지 도 30은 본 발명의 제3실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 단면도.25 to 30 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a third embodiment of the present invention.
도 31은 본 발명의 제4실시예에 따른 국부화 에미터 태양전지의 평면도.31 is a plan view of a localized emitter solar cell according to a fourth embodiment of the present invention.
도 32은 도 31에 있어서, A-A'에 따른 국부화 에미터 태양전지의 단면도.32 is a cross-sectional view of the localized emitter solar cell according to AA ′ in FIG. 31.
도 33는 본 발명의 제4실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 순서도.33 is a flowchart illustrating a method of manufacturing a localized emitter solar cell according to the fourth embodiment of the present invention.
도 34 내지 도 42는 본 발명의 제4실시예에 따른 국부화 에미터 태양전지의 제조 방법을 설명하기 위한 공정 단면도.34 to 42 are cross-sectional views illustrating a method of manufacturing a localized emitter solar cell according to a fourth embodiment of the present invention.
이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 따른 국부화 에미터 태양전지 및 그 제조 방법에 대하여 상세하게 설명한다.Hereinafter, a localized emitter solar cell and a method of manufacturing the same according to a preferred embodiment of the present invention with reference to the accompanying drawings will be described in detail.
본 발명의 제1실시예에 따른 국부화 에미터 태양전지 및 그 제조 방법에 대하여 설명하면 아래와 같다.A localized emitter solar cell and a method for manufacturing the same according to the first embodiment of the present invention will be described below.
도 2를 참조하면, 본 발명의 제1실시예에 따른 국부화 에미터 태양전지는 상하부면에 전면전극(14) 및 후면전극(15)이 구비된 실리콘 재질의 제1도전형의 기판(10)을 포함하며, 이때 기판(10)의 상층부에는 제2도전형 불순물의 고농도 도핑 영역(10-2)이 국부적으로 형성되며, 전면전극(14)이 제2도전형 불순물의 고농도 도핑 영역(10-2)에 접촉 형성된 구조를 가진다. 여기서, 제1도전형은 n형 또는 p형일 수 있으며, 이하에서는 제1도전형은 p형, 제2도전형은 n형인 것을 일 예로 들어 설명하기로 한다.Referring to FIG. 2, the localized emitter solar cell according to the first embodiment of the present invention includes a first conductive substrate 10 made of silicon material having front and rear electrodes 14 and 15 disposed on upper and lower surfaces thereof. Wherein a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and the front electrode 14 has a high concentration doped region 10 of the second conductive impurity. It has a structure formed in contact with -2). Here, the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
이때, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에서 p-n 접합을 형성함으로써, 태양광 입사에 의해 광생성된 소수 운송자의 이동을 가능케 하여 기판(10) 내부에서 전위차를 발생시킬 수 있으며, 금속성의 전면전극(14)과 기판(10)의 경계면의 접촉 저항을 감소시키는 역할을 수행하게 된다.At this time, the heavily doped region 10-2 of the second conductive type impurity forms a pn junction in the substrate 10, thereby enabling movement of a small number of phototransmitters generated by solar incidence, thereby allowing the inside of the substrate 10 to be moved. A potential difference may be generated and serves to reduce the contact resistance between the metallic front electrode 14 and the interface between the substrate 10.
이러한, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에 광생성된 소수 운송자의 이동 거리를 감소시켜 주기 위하여 좁은 간격(예를 들어, 450㎛ 내지 2300㎛ 정도)을 갖고 형성되되, 상부면에 접촉 형성될 전면전극(14)의 간격을 너무 좁게하면 전극에 의한 빛 가림 손실(Shading Loss)의 우려가 있으므로, 상부면에 접촉 형성될 전면전극(14)의 간격을 고려하여 적절한 폭(예를 들어, 20㎛ 내지 40㎛ 정도)을 갖도록 형성되는 것이 바람직하다. The high concentration doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 μm to 2300 μm) in order to reduce the moving distance of the few carriers generated in the substrate 10. If the distance between the front electrode 14 to be formed in contact with the upper surface is too narrow, there is a risk of shading loss due to the electrode, so the distance between the front electrode 14 to be formed in contact with the upper surface is reduced. It is preferable to be formed to have an appropriate width (for example, about 20 to 40 ㎛) in consideration.
또한, 기판(10)의 상하부면에는 전면전극(14)이 형성된 부위를 제외하고 유전층(20, 21)이 형성되고, 기판(10)의 상부면에 형성된 유전층(20) 위에는 유전 특성을 보유한 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3), 티타늄 산화물(TiO2) 또는 실리콘 질화물(Si3N4) 등으로 구성된 반사방지막(ARC: Anti-Reflective Coating)(13)이 적층된다. 여기서, 유전층(20, 21)은 패시베이션(Passivation) 역할을 수행하며, 예컨대 BSG(Boron Silicate Glass) 등으로 이루어질 수 있는데, 만일 제1도전형이 n형인 경우에는 PSG(Phosphorus Silicate Glass) 등으로 이루어질 수 있다.In addition, dielectric layers 20 and 21 are formed on the upper and lower surfaces of the substrate 10 except for the portion where the front electrode 14 is formed, and silicon having dielectric properties is formed on the dielectric layer 20 formed on the upper surface of the substrate 10. An anti-reflective coating (ARC) 13 composed of oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like is stacked. Here, the dielectric layers 20 and 21 may serve as passivation, for example, BSG (Boron Silicate Glass). If the first conductivity type is n-type, PSG (Phosphorus Silicate Glass) is formed. Can be.
한편, 기판(10)의 하층부에는 광생성된 소수 운송자의 후면쪽 이동을 차단하기 위한 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층(10-1)이 구비된다.On the other hand, the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
아울러, 전면전극(14)은 예컨대, 핑거 라인 형태 등의 패턴으로 형성될 수 있으며, 국부적으로 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 기판(10)의 표면에 형성되므로, 약 20㎛ 내지 40㎛ 정도의 선폭(W)으로 형성되되, 전극 간의 간격(d)은 약 450㎛ 내지 2300㎛ 정도가 되도록 형성되는 것이 바람직하다. In addition, the front electrode 14 may be formed, for example, in a finger line pattern or the like, and may be formed on the substrate 10 so as to correspond to the formation position of the highly doped region 10-2 of the locally formed second conductive impurities. Since it is formed on the surface, it is preferably formed with a line width (W) of about 20㎛ 40㎛, the spacing (d) between the electrodes is preferably formed to be about 450㎛ 2300㎛.
즉, 본 발명에 따른 전면전극(14)은 선폭이 일반적인 태양전지에 비해 1/2 내지 1/4 정도의 크기를 가지므로, 일반적인 태양전지의 전면전극 간 간격에 비해 전극 간 간격을 1/2 내지 1/4 정도로 좁혀도 일반적인 태양전지의 수광면과 동일한 수준의 수광면을 확보할 수 있다.That is, since the front electrode 14 according to the present invention has a line width of about 1/2 to 1/4 of the size of a general solar cell, the distance between electrodes is 1/2 of the gap between the front electrodes of a general solar cell. Even if it is narrowed to about 1/4, the light receiving surface of the same level as the light receiving surface of a general solar cell can be ensured.
이하, 본 발명의 제1실시예에 따른 국부화 에미터 태양전지의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a localized emitter solar cell according to the first embodiment of the present invention will be described.
먼저, 도 3에 도시된 바와 같이, 제1도전형의 실리콘 재질의 기판(10)을 준비한다(S100).First, as shown in FIG. 3, a first conductive silicon substrate 10 is prepared (S100).
상기한 단계 S100에서는 기판(10)의 커팅 공정의 결과로 생성된 결함 부분을 제거하기 위하여 화학적 방식으로 기판(10)을 식각하는 쏘 데미지 에칭(Saw Damage Etching) 공정을 진행하게 된다. 이때 식각 용액으로 수산화칼륨(KOH) 용액 등을 사용하여 기판(10)의 표면을 전체적으로 일정 깊이만큼 식각한 후, DIW(Deionized Water) 등을 사용하여 세정하는 것이 바람직하다. In step S100, a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defective portion generated as a result of the cutting process of the substrate 10. At this time, it is preferable to etch the surface of the substrate 10 by a predetermined depth using a potassium hydroxide (KOH) solution or the like as an etching solution, and then wash using DIW (Deionized Water).
아울러, 쏘 데미지 에칭(Saw Damage Etching) 공정 이후에는, 산(Acid) 또는 알카리(Alkaline) 등을 이용한 습식 텍스쳐링 공정이나 건식 텍스쳐링 공정을 진행하게 된다. 이러한 텍스쳐링 공정에 의해 형성되는 기판(10)의 표면 요철 구조는 도면의 간략화를 위해 도면상에 도시하지 않았다.In addition, after the saw damage etching (Saw Damage Etching) process, a wet texturing process or a dry texturing process using an acid or alkaline (Alkaline), etc. are performed. The surface uneven structure of the substrate 10 formed by this texturing process is not shown in the drawings for the sake of simplicity.
상기한 단계 S100을 통해 기판(10)이 준비된 상태에서, 전면전극(14)이 형성될 부위에 해당하는 기판(10)의 상층부에 국부적으로 제2도전형 불순물의 고농도 도핑 영역(10-2)을 형성한다(S110). In the state in which the substrate 10 is prepared through the above step S100, the highly doped region 10-2 of the second conductive type impurity is locally formed on the upper layer of the substrate 10 corresponding to the portion where the front electrode 14 is to be formed. To form (S110).
상기한 단계 S110에서는 불순물 이온 주입 공정이나 레이져 도핑 등을 수행할 수도 있으나, 본 발명에서는 도 4 내지 도 5에 도시된 바와 같이, 제2도전형의 불순물 페이스트(5)를 소스로 한 확산 공정을 수행한다. 이때 확산 방지막을 사용할 수도 있고 사용하지 않을 수도 있다.In the step S110, an impurity ion implantation process or laser doping may be performed. However, in the present invention, as shown in FIGS. 4 to 5, the diffusion process using the impurity paste 5 of the second conductive type as a source is performed. Perform. In this case, the diffusion barrier may or may not be used.
즉, 상기한 단계 S110에서는 도 4에 도시된 바와 같이, 기판(10)의 전면에 제2도전형의 불순물 페이스트(5)를 국부적으로 패터닝하고, 제2도전형의 불순물 페이스트(5)에 함유된 불순물이 기판(10) 내부로 확산하도록 열처리 공정을 시행하여 도 5에 도시된 바와 같이, 기판(10)의 상층부에 국부적으로 헤비 도핑(Heavy Doping)된 제2도전형 불순물의 고농도 도핑 영역(10-2)을 형성하는 것이 바람직하다.That is, in the step S110 described above, as shown in FIG. 4, the second conductive type impurity paste 5 is locally patterned on the entire surface of the substrate 10, and is contained in the second conductive type impurity paste 5. As shown in FIG. 5, a high concentration doped region of a second conductive type impurity that is locally heavily doped on the upper layer of the substrate 10 may be subjected to a heat treatment process to diffuse the impurity into the substrate 10. It is preferable to form 10-2).
상기한 단계 S110을 통해 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)은 예컨대, n++ 영역으로 이루어지며, 기판(10)의 전면에서 전계를 형성하는 역할을 담당한다.The highly doped region 10-2 of the second conductive impurity formed in the upper layer portion of the substrate 10 through step S110 is formed of, for example, an n ++ region, and serves to form an electric field on the entire surface of the substrate 10. In charge.
한편, 상기한 단계 S110에서 확산 공정 시의 열처리에 의해, 제2도전형의 불순물 페이스트(5)가 패터닝된 부위를 제외한 기판(10)의 표면, 즉 전후면에는 도 5에 도시된 바와 같이, 유전층(20, 21)이 자연 형성된다(S120).Meanwhile, as illustrated in FIG. 5, the surface of the substrate 10, ie, the front and rear surfaces, except for the portion where the second conductive type impurity paste 5 is patterned by the heat treatment during the diffusion process in step S110 described above, is illustrated in FIG. 5. The dielectric layers 20 and 21 are naturally formed (S120).
상기한 단계 S120 이후, 도 6에 도시된 바와 같이, 화학기상증착 공정 등을 통해 기판(10)의 전면에 반사방지막(13)을 형성한다(S130). After the above step S120, as shown in FIG. 6, an antireflection film 13 is formed on the entire surface of the substrate 10 through a chemical vapor deposition process (S130).
상기한 단계 S130에서의 반사방지막(13) 형성 시에는, PECVD(Plasma Enhanced Chemical Vapor Deposition) 공정을 사용하는 것이 바람직하다. 여기서, 반사방지막(13)은 실리콘 질화막(Si3N4)으로 구성될 수 있는데, 일 예로 PECVD 공정을 통해 실리콘 질화막을 형성하는 것은, 원료가스인 SiH4와 NH3을 플라즈마 상태로 방전, 활성화시켜 실리콘 질화막을 생성시키는 방법을 통해 구현될 수 있다. 아울러, 반사방지막(13)은 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3) 또는 티타늄 산화물(TiO2) 등으로도 이루어질 수 있다.In forming the anti-reflection film 13 in step S130, it is preferable to use a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Here, the anti-reflection film 13 may be composed of a silicon nitride film (Si 3 N 4 ), for example, forming the silicon nitride film through a PECVD process, discharge and activate the source gas SiH 4 and NH 3 in a plasma state It can be implemented through a method for producing a silicon nitride film. In addition, the anti-reflection film 13 may be made of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), or the like.
상기한 단계 S130 다음에는, 스크린 프린팅 공정을 통해 도 7에 도시된 바와 같이, 기판(10)의 후면에 알루미늄(Al) 및 은(Ag) 등을 포함하는 후면 금속 물질(15-1)을 도포하고, 도 8에 도시된 바와 같이, 기판(10)의 전면, 특히 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 상부에 은(Ag) 등으로 구성된 전면 금속 물질(14-1)을 도포한 후, 소성 공정을 진행하여 기판(10)의 전후면에 전면전극(14) 및 후면전극(15)을 형성한다(S140).After the step S130, as shown in FIG. 7 through a screen printing process, the back metal material 15-1 including aluminum (Al), silver (Ag), and the like is applied to the back of the substrate 10. As shown in FIG. 8, silver (Ag) or the like is formed on the entire surface of the substrate 10, particularly on the high concentration doped region 10-2 of the second conductive impurities formed on the upper layer of the substrate 10. After applying the front metal material 14-1, the firing process is performed to form the front electrode 14 and the rear electrode 15 on the front and rear surfaces of the substrate 10 (S140).
상기한 단계 S140에서는 소성 공정 시의 열처리에 의해, 기판(10)의 하부면에 도포된 금속 물질 중 알루미늄(Al)을 소스로 한 제1도전형 불순물의 고농도 도핑층(10-1)이 기판(10)의 하층부에 자연 형성된다.In the step S140 described above, the high concentration doping layer 10-1 of the first conductivity type impurity, which is made of aluminum (Al) as a source, of the metal material applied to the lower surface of the substrate 10 by the heat treatment during the firing process is performed. It forms naturally in the lower layer of (10).
전술한 단계 S100 내지 S140에 의해 최종적으로 도 2에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수 있다.By the steps S100 to S140 described above, a localized emitter solar cell as shown in FIG. 2 may be finally manufactured.
다르게는, 상기한 단계 S100을 통해 기판(10)이 준비된 상태에서, 열처리 공정을 수행하여 상기한 단계 S120을 수행한 후, 상기한 단계 S130을 수행하고, 그 다음으로 기판(10)의 후면에 알루미늄(Al) 및 은(Ag) 등을 포함하는 후면 금속 물질(15-1)을 도포하고, 소성 공정을 진행하여 기판(10)의 후면에 후면전극(15)을 형성한 다음, 기판(10)의 전면에 형성된 반사방지막(13) 및 유전층(20)을 국부적으로 제거하면서 기판(10)의 상층부에 국부적으로 제2도전형 불순물을 도핑시킬 수 있는 레이져 도핑 방식을 통해 도 9에 도시된 바와 같이, 기판(10)의 전면에 국부적으로 제2도전형 불순물의 고농도 도핑 영역(10-2)을 형성한 후, 도금 공정(Plating)을 진행하여 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 상부에 전면전극(14)을 형성함으로써, 최종적으로 도 2에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수도 있다.Alternatively, in a state in which the substrate 10 is prepared through the above step S100, after performing the heat treatment process to perform the above step S120, the above step S130 is performed, and then on the rear surface of the substrate 10. The back metal material 15-1 including aluminum (Al), silver (Ag), and the like is coated, and a firing process is performed to form the back electrode 15 on the back of the substrate 10. As shown in FIG. 9 through a laser doping method capable of locally doping the second conductive impurities in the upper layer of the substrate 10 while locally removing the antireflection film 13 and the dielectric layer 20 formed on the entire surface of Likewise, after forming the heavily doped region 10-2 of the second conductive type impurity locally on the entire surface of the substrate 10, the second conductive type formed on the upper layer of the substrate 10 by plating is performed. By forming the front electrode 14 on top of the highly doped region 10-2 of impurities, As also it may be produced the localized emitter solar cell as shown in Fig.
이때, 전면전극(14)을 형성 시에는 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 금속 도금만을 시행하거나, 기판(10)과의 접촉시 비저항을 낮추어 주는 씨앗층(Seed Layer)(14-2)을 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 증착시킨 후, 씨앗층(14-2) 위에 금속 도금하여 전면전극(14)을 형성할 수 있다. 이에 따라, 도 10에 도시된 바와 같이, 전면전극(14)은 기판(10)과 직접 접촉되는 하층부에 씨앗층(14-2)을 구비할 수 있다.At this time, when the front electrode 14 is formed, the seed layer may be formed by only performing metal plating so as to directly contact the high concentration doped region 10-2 of the second conductivity type impurity, or lowering the specific resistance when contacting the substrate 10. After depositing the Seed Layer 14-2 so as to be in direct contact with the heavily doped region 10-2 of the second conductivity type impurity, the front electrode 14 may be formed by metal plating on the seed layer 14-2. Can be. Accordingly, as shown in FIG. 10, the front electrode 14 may include a seed layer 14-2 in a lower layer directly contacting the substrate 10.
다음으로, 본 발명의 제2실시예에 따른 국부화 에미터 태양전지 및 그 제조 방법에 대하여 설명하면 아래와 같다.Next, a description will be given of a localized emitter solar cell according to a second embodiment of the present invention and a manufacturing method thereof.
도 11 내지 도 12를 참조하면, 본 발명의 제2실시예에 따른 국부화 에미터 태양전지는 상하부에 전면전극(14) 및 후면전극(15)이 구비된 실리콘 재질의 제1도전형의 기판(10)을 포함하며, 이때 기판(10)의 상층부에는 제2도전형 불순물의 고농도 도핑 영역(10-2)이 국부적으로 형성되며, 기판(10)과 전면전극(14) 사이에 유전층(20) 및 보조전극층(30)이 차례로 적층된 구조를 가진다. 여기서, 제1도전형은 n형 또는 p형일 수 있으며, 이하에서는 제1도전형은 p형, 제2도전형은 n형인 것을 일 예로 들어 설명하기로 한다.11 to 12, the localized emitter solar cell according to the second embodiment of the present invention is a silicon-based substrate having a first conductive type having a front electrode 14 and a rear electrode 15 at upper and lower portions thereof. And a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and the dielectric layer 20 is formed between the substrate 10 and the front electrode 14. ) And the auxiliary electrode layer 30 are sequentially stacked. Here, the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
이때, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에서 p-n 접합을 형성함으로써, 태양광 입사에 의해 광생성된 소수 운송자의 이동을 가능케 하여 기판(10) 내부에서 전위차를 발생시킬 수 있으며, 금속성의 전면전극(14)과 기판(10)의 경계면의 접촉 저항을 감소시키는 역할을 수행하게 된다.At this time, the heavily doped region 10-2 of the second conductive type impurity forms a pn junction in the substrate 10, thereby enabling movement of a small number of phototransmitters generated by solar incidence, thereby allowing the inside of the substrate 10 to be moved. A potential difference may be generated and serves to reduce the contact resistance between the metallic front electrode 14 and the interface between the substrate 10.
이러한, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 도 11의 (a)에 도시된 바와 같이 기판(10)의 상층부에 규칙적인 크기 및 간격을 갖는 점 패턴으로 형성되거나, 도 11의 (b)에 도시된 바와 같이 기판(10)의 상층부에 규칙적인 선폭 및 간격을 갖는 선 패턴으로 형성되는 것이 바람직하나, 불규칙적인 크기 및 간격을 갖는 점 패턴, 또는 불규칙적인 선폭 및 간격을 갖는 선 패턴으로도 형성될 수 있다. 즉, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 패턴 형태의 제약 없이 다양한 형태로 기판(10)의 상층부에 형성될 수 있다. 단, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에서 광생성된 소수 운송자의 이동 거리를 감소시켜 주기 위하여 좁은 간격(예를 들어, 450㎛ 내지 2300㎛ 정도)을 갖고 형성되되, 적절한 폭(예를 들어, 20㎛ 내지 40㎛ 정도)을 갖도록 형성되는 것이 바람직하다.The highly doped region 10-2 of the second conductive type impurity is formed in a dot pattern having a regular size and spacing on the upper layer of the substrate 10 as shown in FIG. 11A, or FIG. 11. As shown in (b) of FIG. 1, the upper layer of the substrate 10 is preferably formed with a line pattern having a regular line width and spacing, but has a dot pattern having an irregular size and spacing, or an irregular line width and spacing. It may also be formed in a line pattern. That is, the heavily doped region 10-2 of the second conductive type impurity may be formed in the upper layer of the substrate 10 in various forms without restriction of the pattern form. However, the highly doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 μm to 2300 μm) in order to reduce the moving distance of the photo-generated minority transporter in the substrate 10. It is preferably formed to have a suitable width (for example, about 20㎛ to 40㎛).
한편, 유전층(20)은 기판(10)의 상부면 중 제2도전형 불순물의 고농도 도핑 영역(10-2)의 노출 부위를 제외한 부위에 형성된다.Meanwhile, the dielectric layer 20 is formed on a portion of the upper surface of the substrate 10 except for the exposed portion of the highly doped region 10-2 of the second conductive impurity.
이러한, 유전층(20)은 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3), 티타늄 산화물(TiO2) 또는 실리콘 질화물(Si3N4) 등으로 구성될 수 있으며, 기판(10)의 전면 패시베이션(Passivation) 역할을 수행한다.The dielectric layer 20 may be formed of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like, and the front passivation of the substrate 10 may be performed. (Passivation) Plays a role.
한편, 보조전극층(30)은 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 유전층(20) 위에 적층되어 형성된다.Meanwhile, the auxiliary electrode layer 30 is formed by being stacked on the dielectric layer 20 so as to directly contact the heavily doped region 10-2 of the second conductive impurity.
이러한, 보조전극층(30)은 기판(10)의 내부에서 광생성되어 제2도전형 불순물의 고농도 도핑 영역(10-2)을 통해 수집된 소수 운송자가 전면전극(14)까지 표동하여 이동할 수 있는 이동 경로를 제공하는 물질로 구성되는데, 예컨대 투명전도산화막(TCO) 등으로 이루어질 수 있다.The auxiliary electrode layer 30 is photogenerated in the substrate 10, and a few carriers collected through the high concentration doping region 10-2 of the second conductivity type impurity can move to the front electrode 14 by moving. It is composed of a material that provides a migration path, for example, it may be made of a transparent conductive oxide film (TCO).
이와 같은, 유전층(20) 및 보조전극층(30)은 굴절률을 고려한 소정의 두께로 각각 형성되어 기판(10)의 상부면, 즉 수광면의 빛 반사 손실을 방지하는 수 있는 반사방지막(ARC: Anti-Reflective Coating) 역할을 수행하게 된다.As described above, the dielectric layer 20 and the auxiliary electrode layer 30 are each formed to have a predetermined thickness in consideration of refractive index, so that an anti-reflection film (ARC) can prevent light reflection loss of the upper surface of the substrate 10, that is, the light receiving surface. -Reflective Coating
한편, 기판(10)의 하층부에는 광생성된 소수 운송자의 후면쪽 이동을 차단하기 위한 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층(10-1)이 구비된다.On the other hand, the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
아울러, 전면전극(14)은 기판(10)의 상부면 전체에 적층된 보조전극층(30)을 통해 소수 운송자를 포집할 수 있기 때문에, 굳이 기판(10)의 상부층에 국부적으로 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 패턴화할 필요가 없으므로, 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하지 않도록 보조전극층(30)의 상부면에 형성될 수 있다. 물론, 필요에 따라 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 보조전극층(30)의 상부면에 전면전극(14)이 형성될 수도 있다.In addition, since the front electrode 14 may trap a small number of carriers through the auxiliary electrode layer 30 stacked on the entire upper surface of the substrate 10, the second conductive type is locally formed on the upper layer of the substrate 10. Since the patterning does not have to correspond to the formation position of the highly doped region 10-2 of the impurity, the upper portion of the auxiliary electrode layer 30 does not correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity. It can be formed on the side. Of course, if necessary, the front electrode 14 may be formed on the upper surface of the auxiliary electrode layer 30 to correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity.
예를 들어, 전면전극(14)은 핑거 라인 형태 등의 패턴으로 형성될 수 있으며, 이때 약 20㎛ 내지 40㎛ 정도의 좁은 선폭(W)을 갖고, 약 1800㎛ 내지 2300㎛ 이내 정도의 전극 간의 간격(d)을 갖도록 형성되거나, 필요에 따라 기판(10)의 수광면을 초과하지 않는 범위 이내에서 2300㎛를 초과하여 형성됨으로써, 일반적인 태양전지의 수광면에 비해 월등히 넓은 수광면을 확보할 수 있다. 아울러 전면전극(14)은 제2도전형 불순물의 고농도 도핑 영역(10-2)의 패턴에 평행하거나 직교하는 방향으로 형성될 수 있다.For example, the front electrode 14 may be formed in a pattern such as a finger line shape, wherein the front electrode 14 has a narrow line width (W) of about 20 μm to 40 μm, and between electrodes of about 1800 μm to 2300 μm. It is formed to have a distance (d) or, if necessary, is formed to exceed 2300㎛ within a range that does not exceed the light receiving surface of the substrate 10, thereby ensuring a much wider light receiving surface than the light receiving surface of a typical solar cell. have. In addition, the front electrode 14 may be formed in a direction parallel or perpendicular to the pattern of the highly doped region 10-2 of the second conductive impurity.
이하, 본 발명의 제2실시예에 따른 국부화 에미터 태양전지의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a localized emitter solar cell according to a second embodiment of the present invention will be described.
먼저, 도 13에 도시된 바와 같이, 제1도전형의 실리콘 재질의 기판(10)을 준비한다(S200).First, as shown in FIG. 13, a first conductive silicon substrate 10 is prepared (S200).
상기한 단계 S200에서는 기판(10)의 커팅 공정의 결과로 생성된 결함 부분을 제거하기 위하여 화학적 방식으로 기판(10)을 식각하는 쏘 데미지 에칭(Saw Damage Etching) 공정을 진행하게 된다. 이때 식각 용액으로 수산화칼륨(KOH) 용액 등을 사용하여 기판(10)의 표면을 전체적으로 일정 깊이만큼 식각한 후, DIW(Deionized Water) 등을 사용하여 세정하는 것이 바람직하다. In step S200, a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10. At this time, it is preferable to etch the surface of the substrate 10 by a predetermined depth using a potassium hydroxide (KOH) solution or the like as an etching solution, and then wash using DIW (Deionized Water).
아울러, 쏘 데미지 에칭(Saw Damage Etching) 공정 이후에는, 산(Acid) 또는 알카리(Alkaline) 등을 이용한 습식 텍스쳐링 공정이나 건식 텍스쳐링 공정을 진행하게 된다. 이러한 텍스쳐링 공정에 의해 형성되는 기판(10)의 표면 요철 구조는 도면의 간략화를 위해 도면상에 도시하지 않았다.In addition, after the saw damage etching (Saw Damage Etching) process, a wet texturing process or a dry texturing process using an acid or alkaline (Alkaline), etc. are performed. The surface uneven structure of the substrate 10 formed by this texturing process is not shown in the drawings for the sake of simplicity.
상기한 단계 S200을 통해 기판(10)이 준비된 상태에서, 도 14에 도시된 바와 같이, 열처리 공정을 수행하여 기판(10)의 표면에 유전층(20, 21)을 형성한다(S210).In the state in which the substrate 10 is prepared through the above step S200, as shown in FIG. 14, the dielectric layers 20 and 21 are formed on the surface of the substrate 10 by performing a heat treatment process (S210).
상기한 단계 S210에서 유전층(20, 21)은 BSG(Boron Silicate Glass) 등으로 이루어지되, 만일 제1도전형이 n형인 경우에는 PSG(Phosphorus Silicate Glass) 등으로 이루어지는 것이 바람직하다.In the step S210, the dielectric layers 20 and 21 are made of BSG (Boron Silicate Glass) or the like. If the first conductivity type is n-type, it is preferable that the dielectric layers 20 and 21 are made of PSG (Phosphorus Silicate Glass).
한편, 상기한 단계 S210에서는 PECVD(Plasma Enhanced Chemical Vapor Deposition) 공정 등의 화학기상증착 공정 등을 수행하여 기판(10)의 상부면에만 실리콘 질화막(Si3N4)으로 구성된 유전층(20)을 형성할 수 있다.Meanwhile, in step S210, the dielectric layer 20 including the silicon nitride layer Si 3 N 4 is formed only on the upper surface of the substrate 10 by performing a chemical vapor deposition process such as a plasma enhanced chemical vapor deposition (PECVD) process. can do.
상기한 단계 S210 이후, 도 15에 도시된 바와 같이, 기판(10)의 후면에 알루미늄(Al) 및 은(Ag) 등을 포함하는 후면 금속 물질(15-1)을 도포하고, 소성 공정을 진행하여 도 16에 도시된 바와 같이, 기판(10)의 하부면에 후면전극(15)을 형성한다(S220).After the above step S210, as shown in FIG. 15, a rear metal material 15-1 including aluminum (Al), silver (Ag), and the like is applied to the rear surface of the substrate 10, and the firing process is performed. 16, the rear electrode 15 is formed on the lower surface of the substrate 10 (S220).
상기한 단계 S220에서는 소성 공정 시의 열처리에 의해, 기판(10)의 하부면에 도포된 금속 물질 중 알루미늄(Al)을 소스로 한 제1도전형 불순물의 고농도 도핑층(10-1)이 기판(10)의 하층부에 자연 형성되는데, 이때 상기한 단계 S210을 통해 기판의 하부면에 형성된 유전층(21)은 알루미늄(Al)을 소스로 한 제1도전형 불순물의 도핑으로 인해 제1도전형 불순물의 고농도 도핑층(10-1) 내에 포함되는 것이 바람직하다.In the step S220, a high concentration doping layer 10-1 of the first conductive type impurity, which is made of aluminum (Al) as a source, of the metal material applied to the lower surface of the substrate 10 by the heat treatment during the firing process is performed. It is naturally formed in the lower layer of (10), wherein the dielectric layer 21 formed on the lower surface of the substrate through the above step S210 is the first conductive impurity due to the doping of the first conductive impurity sourced from aluminum (Al). It is preferably included in the high concentration doping layer (10-1).
상기한 단계 S220 다음에는, 레이져 도핑 공정을 수행하여 도 17에 도시된 바와 같이, 기판(10)의 상부에 형성된 유전층(20)을 국부적으로 제거함과 동시에, 그 유전층(20)이 제거된 기판(10)의 상층부에 제2도전형 불순물을 도핑시켜 기판(10)의 상층부에 제2도전형 불순물의 고농도 도핑 영역(10-2)을 국부적으로 노출시켜 형성한다(S230).After the step S220, as illustrated in FIG. 17, the laser doping process is performed to locally remove the dielectric layer 20 formed on the substrate 10 and to remove the dielectric layer 20. 10, a second conductive dopant is doped in the upper layer of the substrate 10, and a high concentration doped region 10-2 of the second conductive dopant is locally exposed in the upper layer of the substrate 10 (S230).
상기한 단계 S230을 통해 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)은 예컨대, 헤비 도핑(Heavy Doping)된 n++ 영역으로 이루어질 수 있으며, 기판(10)의 전면에서 전계를 형성하는 역할을 담당한다.The high concentration doped region 10-2 of the second conductive impurity formed on the upper layer of the substrate 10 through step S230 may be formed of, for example, a heavy doped n ++ region, and may be formed of the substrate 10. It is responsible for forming the electric field from the front.
상기한 단계 S230 이후, 도 18에 도시된 바와 같이, 기판(10)의 상부에 보조전극층(30)을 증착시킨다(S240).After the above step S230, as shown in FIG. 18, the auxiliary electrode layer 30 is deposited on the substrate 10 (S240).
상기한 단계 S240를 통해 기판(10)의 상부에 형성된 보조전극층(30)은 유전층(20) 위에 증착될 뿐 아니라, 기판(10)의 상층부에 국부적으로 노출된 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉되도록 증착된다.The auxiliary electrode layer 30 formed on the substrate 10 through the step S240 is not only deposited on the dielectric layer 20 but also a highly doped region of the second conductive impurity locally exposed in the upper layer of the substrate 10. It is deposited to be in direct contact with (10-2).
상기한 단계 S240 이후, 스크린 프린팅 공정을 수행하여 도 19에 도시된 바와 같이, 보조전극층(30) 위에 수광면을 최대한 확보할 수 있도록 간격(d)을 최대한 넓히는 등의 패턴으로 전면전극(14)을 형성한다(S250).After the above step S240, as shown in FIG. 19 by performing a screen printing process, the front electrode 14 in a pattern such as to widen the interval (d) as much as possible to secure the maximum light receiving surface on the auxiliary electrode layer (30) To form (S250).
상기한 단계 S250에서 전면전극(14) 형성 시에는 보조전극층(30) 위에 원하는 패턴으로 은(Ag) 등으로 구성된 전면 금속 물질을 도포한 후, 소성 공정을 진행하는 것이 바람직하다.When the front electrode 14 is formed in step S250, the front metal material including silver (Ag) is coated on the auxiliary electrode layer 30 in a desired pattern, and then the firing process is preferably performed.
전술한 단계 S200 내지 S250에 의해 도 11 내지 도 12에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수 있다.Localized emitter solar cells as illustrated in FIGS. 11 to 12 may be manufactured by the above-described steps S200 to S250.
다르게는, 상기한 단계 S230 이후, 도 20에 도시된 바와 같이, 기판(10)과의 접촉시 비저항을 낮추어 주는 도금층(Seed Layer)(20-1)을, 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 증착시킨 후, 도 21에 도시된 바와 같이, 기판(10)의 상부에 보조전극층(30)을 증착시킨 다음에, 상기한 단계 S250을 수행함으로써, 도 11 내지 도 12에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수도 있다. Alternatively, after the step S230 described above, as shown in FIG. 20, the seed layer 20-1, which lowers the specific resistance upon contact with the substrate 10, is formed of a high concentration doped region of the second conductive impurity. After the deposition is performed in direct contact with (10-2), as shown in FIG. 21, the auxiliary electrode layer 30 is deposited on the substrate 10, and then, the above-described step S250 is performed to perform the above-described step S250. Localized emitter solar cells as shown in FIG. 12 may be fabricated.
이 경우, 기판(10)의 상부에 형성된 보조전극층(30)은 유전층(20) 위에도 증착되되, 기판(10)의 상층부에 국부적으로 노출 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)에는 도금층(20-1)을 매개로 접촉되도록 증착된다.In this case, the auxiliary electrode layer 30 formed on the substrate 10 is also deposited on the dielectric layer 20, but the high concentration doped region 10-2 of the second conductive impurity formed locally exposed on the upper layer of the substrate 10. Is deposited to contact the plating layer 20-1.
다음으로, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지 및 그 제조 방법에 대하여 설명하면 아래와 같다.Next, a description will be given of a localized emitter solar cell according to a third embodiment of the present invention and a manufacturing method thereof.
도 22를 참조하면, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지는 상하부면에 전면전극(14) 및 후면전극(15)이 구비된 실리콘 재질의 제1도전형의 기판(10)을 포함하며, 이때 기판(10)의 상층부에는 제2도전형 불순물의 고농도 도핑 영역(10-2)이 국부적으로 형성되되, 기판(10)의 상부 중 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역(10-3)이 형성된다. 아울러 전면전극(14)은 제2도전형 불순물의 고농도 도핑 영역(10-2)에 접촉 형성된 구조를 가진다. 여기서, 제1도전형은 n형 또는 p형일 수 있으며, 이하에서는 제1도전형은 p형, 제2도전형은 n형인 것을 일 예로 들어 설명하기로 한다.Referring to FIG. 22, in the localized emitter solar cell according to the third embodiment of the present invention, a first conductive substrate 10 made of silicon material having a front electrode 14 and a rear electrode 15 disposed on upper and lower surfaces thereof. In this case, a high concentration doped region 10-2 of the second conductive impurity is locally formed in the upper layer of the substrate 10, and a high concentration doped region of the second conductive impurity in the upper portion of the substrate 10 ( The highly doped region 10-3 of the first conductivity type impurity is formed in a portion other than the formation portion of 10-2). In addition, the front electrode 14 has a structure in contact with the highly doped region 10-2 of the second conductive type impurity. Here, the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10)의 상층부에 형성되어 기판(10) 내에서 p-n 접합을 형성함으로써, 태양광 입사에 의해 광생성된 소수 운송자의 이동을 가능케 하여 기판(10) 내부에서 전위차를 발생시킬 수 있으며, 금속성의 전면전극(14)과 기판(10)의 경계면의 접촉 저항을 감소시키는 역할을 수행하게 된다.The highly doped region 10-2 of the second conductive type impurity is formed in the upper layer of the substrate 10 to form a pn junction in the substrate 10, thereby enabling the movement of the minority carriers photogenerated by solar incidence. As a result, a potential difference may be generated in the substrate 10, and the contact resistance between the metallic front electrode 14 and the interface between the substrate 10 may be reduced.
이러한, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에 광생성된 소수 운송자의 이동 거리를 감소시켜 주기 위하여 좁은 간격(예를 들어, 450㎛ 내지 2300㎛ 정도)을 갖고 형성되되, 상부면에 접촉 형성될 전면전극(14)의 간격을 너무 좁게하면 전극에 의한 빛 가림 손실(Shading Loss)의 우려가 있으므로, 상부면에 접촉 형성될 전면전극(14)의 간격을 고려하여 적절한 폭(예를 들어, 20㎛ 내지 40㎛ 정도)을 갖도록 형성되는 것이 바람직하다. The high concentration doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 μm to 2300 μm) in order to reduce the moving distance of the few carriers generated in the substrate 10. If the distance between the front electrode 14 to be formed in contact with the upper surface is too narrow, there is a risk of shading loss due to the electrode, so the distance between the front electrode 14 to be formed in contact with the upper surface is reduced. It is preferable to be formed to have an appropriate width (for example, about 20 to 40 ㎛) in consideration.
한편, 제1도전형 불순물의 고농도 도핑 영역(10-3)은 제2도전형 불순물의 고농도 도핑 영역(10-2) 및 전면전극(14)과 접촉하지 않도록 기판(10)의 상층부에 형성되어, 광생성된 소수 운송자의 기판(10) 표면 이동을 방지하게 된다.Meanwhile, the heavily doped region 10-3 of the first conductive impurity is formed on the upper layer of the substrate 10 so as not to contact the heavily doped region 10-2 of the second conductive impurity and the front electrode 14. As a result, the surface of the substrate 10 of the photogenerated minority transporter is prevented.
즉, 제1도전형 불순물의 고농도 도핑 영역(10-3)은 기판(10)의 상부에 제2도전형 불순물의 고농도 도핑 영역(10-2)과 일정 간격을 갖고 교번하도록 형성되는 것이 바람직하다.That is, the highly doped region 10-3 of the first conductivity type impurity may be formed on the substrate 10 so as to alternate with the heavily doped region 10-2 of the second conductivity type impurity at a predetermined interval. .
이로 인해, 기판(10) 내에서 광생성된 소수 운송자는 제1도전형 불순물의 고농도 도핑 영역(10-3)에 의해 생성되는 전계에 의해 기판(10)의 표면으로 접근하지 못하고, 제2도전형 불순물의 고농도 도핑 영역(10-2) 까지 최단 거리를 이동하여 제2도전형 불순물의 고농도 도핑 영역(10-2)을 통해 전면전극(14)으로 포집됨으로써, 기존에 비해 표면 재결합율이 현저히 감소된다.As a result, the minority carriers generated in the substrate 10 do not approach the surface of the substrate 10 by the electric field generated by the highly doped region 10-3 of the first conductivity type impurity, and the second conductive By moving the shortest distance to the high concentration doped region 10-2 of the dopant-type impurities and collecting the front electrode 14 through the high concentration doped region 10-2 of the second conductive dopant, the surface recombination rate is remarkably higher than before. Is reduced.
또한, 기판(10)의 상하부면에는 전면전극(14)이 형성된 부위를 제외하고 유전층(20, 21)이 형성되고, 기판(10)의 상부면에 형성된 유전층(20) 위에는 유전 특성을 보유한 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3), 티타늄 산화물(TiO2) 또는 실리콘 질화물(Si3N4) 등으로 구성된 반사방지막(ARC: Anti-Reflective Coating)(13)이 적층된다. 여기서, 유전층(20, 21)은 패시베이션(Passivation) 역할을 수행하며, 예컨대 BSG(Boron Silicate Glass) 등으로 이루어질 수 있는데, 만일 제1도전형이 n형인 경우에는 PSG(Phosphorus Silicate Glass) 등으로 이루어질 수 있다.In addition, dielectric layers 20 and 21 are formed on the upper and lower surfaces of the substrate 10 except for the portion where the front electrode 14 is formed, and silicon having dielectric properties is formed on the dielectric layer 20 formed on the upper surface of the substrate 10. An anti-reflective coating (ARC) 13 composed of oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like is stacked. Here, the dielectric layers 20 and 21 may serve as passivation, for example, BSG (Boron Silicate Glass). If the first conductivity type is n-type, PSG (Phosphorus Silicate Glass) is formed. Can be.
한편, 기판(10)의 하층부에는 광생성된 소수 운송자의 후면쪽 이동을 차단하기 위한 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층(10-1)이 구비된다.On the other hand, the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
아울러, 전면전극(14)은 예컨대, 핑거 라인 형태 등의 패턴으로 형성될 수 있으며, 국부적으로 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 기판(10)의 표면에 형성되며, 약 20㎛ 내지 40㎛ 정도의 선폭(W)으로 형성되되, 전극 간의 간격(d)은 약 450㎛ 내지 2300㎛ 정도가 되도록 형성되는 것이 바람직하다.In addition, the front electrode 14 may be formed, for example, in a finger line pattern or the like, and may be formed on the substrate 10 so as to correspond to the formation position of the highly doped region 10-2 of the locally formed second conductive impurities. It is formed on the surface, it is formed with a line width (W) of about 20㎛ 40㎛, it is preferable that the spacing (d) between the electrodes is formed to be about 450㎛ to 2300㎛.
이와 같은 전면전극(14)은 선폭이 일반적인 태양전지에 비해 1/2 내지 1/4 정도의 크기를 가지므로, 일반적인 태양전지의 전면전극 간 간격에 비해 전극 간 간격을 1/2 내지 1/4 정도로 좁혀도 일반적인 태양전지의 수광면과 동일한 수준의 수광면을 확보할 수 있다.Since the front electrode 14 has a line width 1/2 to 1/4 of the size of a general solar cell, the spacing between electrodes is 1/2 to 1/4 in comparison with the distance between the front electrodes of a general solar cell. Even if it is narrowed enough, the light receiving surface of the same level as that of the general solar cell can be secured.
또한, 전면전극(14)은 도 23에 도시된 바와 같이, 기판(10)과 직접 접촉되는 하층부에 접촉 비저항을 낮추기 위한 씨앗층(14-2)을 구비할 수 있다.In addition, as illustrated in FIG. 23, the front electrode 14 may include a seed layer 14-2 for lowering a contact resistivity in a lower layer directly contacting the substrate 10.
이하, 본 발명의 제3실시예에 따른 국부화 에미터 태양전지의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a localized emitter solar cell according to a third embodiment of the present invention will be described.
먼저, 도 24에 도시된 바와 같이, 제1도전형의 실리콘 재질의 기판(10)을 준비한다(S300).First, as shown in FIG. 24, a first conductive silicon substrate 10 is prepared (S300).
상기한 단계 S300에서는 기판(10)의 커팅 공정의 결과로 생성된 결함 부분을 제거하기 위하여 화학적 방식으로 기판(10)을 식각하는 쏘 데미지 에칭(Saw Damage Etching) 공정을 진행하게 된다. 이때 식각 용액으로 수산화칼륨(KOH) 용액 등을 사용하여 기판(10)의 표면을 전체적으로 일정 깊이만큼 식각한 후, DIW(Deionized Water) 등을 사용하여 세정하는 것이 바람직하다. In step S300, a saw damage etching process of etching the substrate 10 in a chemical manner is performed in order to remove a defect portion generated as a result of the cutting process of the substrate 10. At this time, it is preferable to etch the surface of the substrate 10 by a predetermined depth using a potassium hydroxide (KOH) solution or the like as an etching solution, and then wash using DIW (Deionized Water).
아울러, 쏘 데미지 에칭(Saw Damage Etching) 공정 이후에는, 산(Acid) 또는 알카리(Alkaline) 등을 이용한 습식 텍스쳐링 공정이나 건식 텍스쳐링 공정을 진행하게 된다. 이러한 텍스쳐링 공정에 의해 형성되는 기판(10)의 표면 요철 구조는 도면의 간략화를 위해 도면상에 도시하지 않았다.In addition, after the saw damage etching (Saw Damage Etching) process, a wet texturing process or a dry texturing process using an acid or alkaline (Alkaline), etc. are performed. The surface uneven structure of the substrate 10 formed by this texturing process is not shown in the drawings for the sake of simplicity.
상기한 단계 S300을 통해 기판(10)이 준비된 상태에서, 도 25에 도시된 바와 같이, 전면전극(14)이 형성될 부위, 즉 제2도전형 불순물의 고농도 도핑 영역(10-2)이 형성될 부위를 제외한 기판(10)의 상부, 특히 기판(10)의 상층부에 제1도전형 불순물을 국부적으로 헤비 도핑(Heavy Doping)시켜 제1도전형 불순물의 고농도 도핑 영역(10-3)을 형성한다(S310).In the state in which the substrate 10 is prepared through the above step S300, as shown in FIG. 25, a portion where the front electrode 14 is to be formed, that is, a highly doped region 10-2 of the second conductive impurity is formed. A high concentration doped region 10-3 of the first conductive impurity is formed by locally heavy doping the first conductive impurity on the upper portion of the substrate 10, particularly the upper layer of the substrate 10 except for the portion to be formed. (S310).
상기한 단계 S310에서는 불순물 이온 주입 공정이나 레이져 도핑 또는 불순물 페이스트를 소스로 한 확산 공정을 등을 수행할 수 있다. 이때 확산 공정시에는 확산 방지막을 사용할 수도 있고 사용하지 않을 수도 있다.In step S310, an impurity ion implantation process, a laser doping, or a diffusion process using an impurity paste as a source may be performed. In this case, the diffusion barrier may or may not be used in the diffusion process.
상기한 단계 S310을 통해 기판(10)의 상층부에 형성된 제1도전형 불순물의 고농도 도핑 영역(10-3)은 예컨대, p+ 영역으로 이루어질 수 있며, 기판(10)의 전면에서 소수 운송자의 접근을 방지하기 위한 전계를 형성하는 역할을 담당하게 된다.The high concentration doping region 10-3 of the first conductivity type impurity formed in the upper layer portion of the substrate 10 through step S310 may be formed of, for example, a p + region. It is responsible for forming an electric field to prevent.
상기한 단계 S310 이후에는, 열처리 공정 또는 증착 공정 등을 수행하여 도 26에 도시된 바와 같이, 기판(10)의 표면, 즉 전후면에 유전층(20, 21)을 형성한다(S320).After the above step S310, as shown in FIG. 26, the dielectric layers 20 and 21 are formed on the front surface, that is, the front and rear surfaces of the substrate 10 by performing a heat treatment process or a deposition process (S320).
상기한 단계 S320 이후에는, 화학기상증착 공정 등을 통해 도 27에 도시된 바와 같이, 기판(10)의 전면에 반사방지막(13)을 형성한다(S330). After the above step S320, as shown in Figure 27 through a chemical vapor deposition process, to form an anti-reflection film 13 on the front surface of the substrate 10 (S330).
상기한 단계 S330에서의 반사방지막(13) 형성 시에는, PECVD(Plasma Enhanced Chemical Vapor Deposition) 공정을 사용하는 것이 바람직하다. 여기서, 반사방지막(13)은 실리콘 질화막(Si3N4)으로 구성될 수 있는데, 일 예로 PECVD 공정을 통해 실리콘 질화막을 형성하는 것은, 원료가스인 SiH4와 NH3을 플라즈마 상태로 방전, 활성화시켜 실리콘 질화막을 생성시키는 방법을 통해 구현될 수 있다. 아울러, 반사방지막(13)은 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3) 또는 티타늄 산화물(TiO2) 등으로도 이루어질 수 있다.In forming the anti-reflection film 13 in step S330, it is preferable to use a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Here, the anti-reflection film 13 may be composed of a silicon nitride film (Si 3 N 4 ), for example, forming the silicon nitride film through a PECVD process, discharge and activate the source gas SiH 4 and NH 3 in a plasma state It can be implemented through a method for producing a silicon nitride film. In addition, the anti-reflection film 13 may be made of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), or the like.
상기한 단계 S330 다음에는, 기판(10)의 후면에 알루미늄(Al) 및 은(Ag) 등을 포함하는 금속 물질을 도포하고, 소성 공정을 진행하여 도 28에 도시된 바와 같이, 기판(10)의 후면에 후면전극(15)을 형성한다(S340).After the above step S330, a metal material including aluminum (Al), silver (Ag), and the like is coated on the rear surface of the substrate 10, and a firing process is performed, as shown in FIG. 28, as shown in FIG. 28. The rear electrode 15 is formed on the rear surface of the battery (S340).
상기한 단계 S340에서는 소성 공정 시의 열처리에 의해, 기판(10)의 후면에 도포된 금속 물질 중 알루미늄(Al)을 소스로 한 제1도전형 불순물의 고농도 도핑층(10-1)이 기판(10)의 하층부에 자연 형성되는데, 이때 상기한 단계 S310을 통해 기판의 하부면에 형성된 유전층(21)은 알루미늄(Al)을 소스로 한 제1도전형 불순물의 도핑으로 인해 제1도전형 불순물의 고농도 도핑층(10-1) 내에 포함되는 것이 바람직하다.In the step S340, the high-concentration doping layer 10-1 of the first conductive type impurity having aluminum (Al) as the source of the metal material applied to the rear surface of the substrate 10 is formed by the heat treatment during the baking process. 10, which is naturally formed in the lower layer, wherein the dielectric layer 21 formed on the lower surface of the substrate through step S310 is formed of the first conductive impurity due to the doping of the first conductive impurity. It is preferably included in the heavily doped layer 10-1.
상기한 단계 S340 다음에는, 레이져 도핑 공정을 수행하여 도 29에 도시된 바와 같이, 기판(10)의 상부에 형성된 반사방지막(13) 및 유전층(20)을 국부적으로 제거함과 동시에, 그 반사방지막(13) 및 유전층(20)이 제거된 기판(10)의 상층부에 제2도전형 불순물을 헤비 도핑(Heavy Doping)시켜 기판(10)의 상층부에 제2도전형 불순물의 고농도 도핑 영역(10-2)을 국부적으로 노출시켜 형성한다(S350).Next to step S340, as illustrated in FIG. 29, the laser doping process is performed to locally remove the antireflection film 13 and the dielectric layer 20 formed on the substrate 10, and to simultaneously remove the antireflection film ( 13) and heavily doped the second conductive impurity on the upper layer of the substrate 10 from which the dielectric layer 20 has been removed, and thus the heavily doped region 10-2 of the second conductive impurity on the upper layer of the substrate 10. ) Is formed by locally exposing (S350).
상기한 단계 S350을 통해 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)은 제1도전형 불순물의 고농도 도핑 영역(10-3)과 접촉없이 교번하도록 형성되는 것이 바람직하며, 예컨대 n++ 영역으로 이루어질 수 있다.The high concentration doped region 10-2 of the second conductive impurity formed in the upper layer of the substrate 10 through step S350 is formed to alternate with the high concentration doped region 10-3 of the first conductive impurity. Preferably, it may consist, for example, of n ++ regions.
상기한 단계 S350 다음에는, 도금 공정을 진행하여 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)에 접촉하도록 전면전극(14)을 형성한다(S360).After the above step S350, the front electrode 14 is formed to contact the high concentration doped region 10-2 of the second conductive impurity formed in the upper layer of the substrate 10 by performing the plating process (S360).
상기한 단계 S360를 통해 형성된 전면전극(14)은 기판(10)의 상층부에 형성된 제1도전형 불순물의 고농도 도핑 영역(10-3)과 접촉없이, 제2도전형 불순물의 고농도 도핑 영역(10-2) 상부에 접촉되도록 형성되는 것이 바람직하다.The front electrode 14 formed through the step S360 is not in contact with the high concentration doping region 10-3 of the first conductivity type impurity formed on the upper layer of the substrate 10, and the high concentration doping region 10 of the second conductivity type impurity 10 is formed. -2) is preferably formed in contact with the top.
상기한 단계 S360에서는, 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 금속 도금만을 시행하거나, 기판(10)과의 접촉시 비저항을 낮추어 주는 씨앗층(Seed Layer)(14-2)을 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 증착시킨 후, 씨앗층(14-2) 위에 금속 도금하여 전면전극(14)을 형성할 수 있다. In the step S360 described above, only the metal plating is performed to directly contact the high concentration doped region 10-2 of the second conductivity type impurity, or the seed layer 14 lowering the specific resistance upon contact with the substrate 10. -2) may be deposited to directly contact the heavily doped region 10-2 of the second conductivity type impurity, and then the front electrode 14 may be formed by metal plating on the seed layer 14-2.
전술한 단계 S300 내지 S360에 의해 도 22에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수 있다.Localized emitter solar cells as illustrated in FIG. 22 may be manufactured by the above-described steps S300 to S360.
다르게는, 상기한 단계 S300을 통해 기판(10)이 준비된 상태에서, 전면전극(14)이 형성될 부위, 즉 제2도전형 불순물의 고농도 도핑 영역(10-2)이 형성될 부위를 제외한 기판(10)의 상부면 위에 제1도전형 불순물이 헤비 도핑된 비정질 실리콘(a-Si) 박막을 패터닝함으로써, 기판(10)의 상부면 위에 제1도전형 불순물의 고농도 도핑 영역(10-3)을 국부적으로 형성한 다음, 상기한 단계 S320 내지 S360을 수행하여 도 30에 도시된 바와 같이, 제1도전형 불순물의 고농도 도핑 영역(10-3)이 제2도전형 불순물의 고농도 도핑 영역(10-2) 및 전면전극(14)과 접촉하지 않도록 기판(10)의 상부면 위에 적층된 구조를 갖는 국부화 에미터 태양전지를 제조할 수 있다.Alternatively, in the state in which the substrate 10 is prepared through the above step S300, the substrate except for the region where the front electrode 14 is to be formed, that is, the region where the highly doped region 10-2 of the second conductive impurity is to be formed. By patterning a heavily doped amorphous silicon (a-Si) thin film on the upper surface of the first conductive impurity (10), the highly doped region 10-3 of the first conductive impurity on the upper surface of the substrate 10 Is formed locally, and then the steps S320 to S360 described above are performed, and as shown in FIG. 30, the heavily doped region 10-3 of the first conductive impurity is heavily doped region 10 of the second conductive impurity. -2) and a localized emitter solar cell having a structure laminated on the upper surface of the substrate 10 so as not to contact the front electrode 14 can be manufactured.
다음으로, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지 및 그 제조 방법에 대하여 설명하면 아래와 같다.Next, a description will be given of a localized emitter solar cell and a manufacturing method according to a fourth embodiment of the present invention.
도 31 내지 도 32를 참조하면, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지는 상하부에 전면전극(14) 및 후면전극(15)이 구비된 실리콘 재질의 제1도전형의 기판(10)을 포함하며, 이때 기판(10)의 상층부에는 제2도전형 불순물의 고농도 도핑 영역(10-2)이 국부적으로 형성되되, 기판(10)의 상부 중 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역(10-3)이 형성되며, 기판(10)과 전면전극(14) 사이에 유전층(20) 및 보조전극층(30)이 차례로 적층된 구조를 가진다. 여기서, 제1도전형은 n형 또는 p형일 수 있으며, 이하에서는 제1도전형은 p형, 제2도전형은 n형인 것을 일 예로 들어 설명하기로 한다.31 to 32, a localized emitter solar cell according to a fourth embodiment of the present invention is a silicon-based first conductive substrate having a front electrode 14 and a rear electrode 15 at upper and lower portions thereof. And a high concentration doping region 10-2 of the second conductive impurity is locally formed in the upper layer portion of the substrate 10, and has a high concentration doping of the second conductive impurity in the upper portion of the substrate 10. A highly doped region 10-3 of the first conductivity type impurity is formed in a portion other than the region in which the region 10-2 is formed, and the dielectric layer 20 and the auxiliary electrode layer are formed between the substrate 10 and the front electrode 14. It has a structure in which 30 is laminated one by one. Here, the first conductivity type may be n type or p type, hereinafter, the first conductive type is p type, and the second conductive type is n type.
제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10)의 상층부에 형성되어 기판(10) 내에서 p-n 접합을 형성함으로써, 태양광 입사에 의해 광생성된 소수 운송자의 이동을 가능케 하여 기판(10) 내부에서 전위차를 발생시킬 수 있다.The highly doped region 10-2 of the second conductive type impurity is formed in the upper layer of the substrate 10 to form a pn junction in the substrate 10, thereby enabling the movement of the minority carriers photogenerated by solar incidence. The potential difference can be generated inside the substrate 10.
이러한, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 도 31의 (a)에 도시된 바와 같이 기판(10)의 상층부에 규칙적인 크기 및 간격을 갖는 점 패턴으로 형성되거나, 도 31의 (b)에 도시된 바와 같이 기판(10)의 상층부에 규칙적인 선폭 및 간격을 갖는 선 패턴으로 형성되는 것이 바람직하나, 불규칙적인 크기 및 간격을 갖는 점 패턴, 또는 불규칙적인 선폭 및 간격을 갖는 선 패턴으로도 형성될 수 있다. 즉, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 패턴 형태의 제약 없이 다양한 형태로 기판(10)의 상층부에 형성될 수 있다. 단, 제2도전형 불순물의 고농도 도핑 영역(10-2)은 기판(10) 내에서 광생성된 소수 운송자의 이동 거리를 감소시켜 주기 위하여 좁은 간격(예를 들어, 450㎛ 내지 2300㎛ 정도)을 갖고 형성되되, 적절한 폭(예를 들어, 20㎛ 내지 40㎛ 정도)을 갖도록 형성되는 것이 바람직하다.The highly doped region 10-2 of the second conductive type impurity is formed in a dot pattern having a regular size and spacing on the upper layer of the substrate 10 as shown in FIG. 31A, or FIG. 31. As shown in (b) of FIG. 1, the upper layer of the substrate 10 is preferably formed with a line pattern having a regular line width and spacing, but has a dot pattern having an irregular size and spacing, or an irregular line width and spacing. It may also be formed in a line pattern. That is, the heavily doped region 10-2 of the second conductive type impurity may be formed in the upper layer of the substrate 10 in various forms without restriction of the pattern form. However, the highly doped region 10-2 of the second conductive type impurity has a narrow spacing (for example, about 450 μm to 2300 μm) in order to reduce the moving distance of the photo-generated minority transporter in the substrate 10. It is preferably formed to have a suitable width (for example, about 20㎛ to 40㎛).
한편, 제1도전형 불순물의 고농도 도핑 영역(10-3)은 제2도전형 불순물의 고농도 도핑 영역(10-2) 및 보조전극층(30)과 접촉하지 않도록 기판(10)의 상층부에 형성되어, 광생성된 소수 운송자의 기판(10) 표면 이동을 방지하게 된다.Meanwhile, the heavily doped region 10-3 of the first conductive impurity is formed on the upper layer of the substrate 10 so as not to contact the heavily doped region 10-2 of the second conductive impurity and the auxiliary electrode layer 30. As a result, the surface of the substrate 10 of the photogenerated minority transporter is prevented.
즉, 제1도전형 불순물의 고농도 도핑 영역(10-3)은 기판(10)의 상부에 제2도전형 불순물의 고농도 도핑 영역(10-2)과 일정 간격을 갖고 교번하도록 형성되는 것이 바람직하다.That is, the highly doped region 10-3 of the first conductivity type impurity may be formed on the substrate 10 so as to alternate with the heavily doped region 10-2 of the second conductivity type impurity at a predetermined interval. .
이로 인해, 기판(10) 내에서 광생성된 소수 운송자는 제1도전형 불순물의 고농도 도핑 영역(10-3)에 의해 생성되는 전계에 의해 기판(10)의 표면으로 접근하지 못하고, 제2도전형 불순물의 고농도 도핑 영역(10-2) 까지 최단 거리를 이동하여 제2도전형 불순물의 고농도 도핑 영역(10-2) 및 보조전극층(30)을 통해 전면전극(14)으로 포집됨으로써, 기존에 비해 표면 재결합율이 현저히 감소된다.As a result, the minority carriers generated in the substrate 10 do not approach the surface of the substrate 10 by the electric field generated by the highly doped region 10-3 of the first conductivity type impurity, and the second conductive By moving the shortest distance to the high concentration doped region 10-2 of the dopant-type impurities, the high concentration doped region 10-2 of the second conductive impurity and the auxiliary electrode layer 30 are collected by the front electrode 14, thereby allowing the In comparison, the surface recombination rate is significantly reduced.
한편, 유전층(20)은 기판(10)의 상부면 중 제2도전형 불순물의 고농도 도핑 영역(10-2)의 노출 부위를 제외한 부위에 형성된다.Meanwhile, the dielectric layer 20 is formed on a portion of the upper surface of the substrate 10 except for the exposed portion of the highly doped region 10-2 of the second conductive impurity.
이러한, 유전층(20)은 실리콘 산화물(SiO2), 알루미늄 산화물(AlO3), 티타늄 산화물(TiO2) 또는 실리콘 질화물(Si3N4) 등으로 구성될 수 있으며, 기판(10)의 전면 패시베이션(Passivation) 역할을 수행한다.The dielectric layer 20 may be formed of silicon oxide (SiO 2 ), aluminum oxide (AlO 3 ), titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), or the like, and the front passivation of the substrate 10 may be performed. (Passivation) Plays a role.
한편, 보조전극층(30)은 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 또는 도금층을 매개로 접촉하도록 유전층(20) 위에 적층되어 형성된다.On the other hand, the auxiliary electrode layer 30 is formed by being stacked on the dielectric layer 20 so as to contact the high concentration doped region 10-2 of the second conductivity type impurity directly or via a plating layer.
이러한, 보조전극층(30)은 기판(10)의 내부에서 광생성되어 제2도전형 불순물의 고농도 도핑 영역(10-2)을 통해 수집된 소수 운송자가 전면전극(14)까지 표동하여 이동할 수 있는 이동 경로를 제공하는 물질로 구성되는데, 예컨대 투명전도산화막(TCO) 등으로 이루어질 수 있다.The auxiliary electrode layer 30 is photogenerated in the substrate 10, and a few carriers collected through the high concentration doping region 10-2 of the second conductivity type impurity can move to the front electrode 14 by moving. It is composed of a material that provides a migration path, for example, it may be made of a transparent conductive oxide film (TCO).
이와 같은, 유전층(20) 및 보조전극층(30)은 굴절률을 고려한 소정의 두께로 각각 형성되어 기판(10)의 상부면, 즉 수광면의 빛 반사 손실을 방지하는 수 있는 반사방지막(ARC: Anti-Reflective Coating) 역할을 수행하게 된다.As described above, the dielectric layer 20 and the auxiliary electrode layer 30 are each formed to have a predetermined thickness in consideration of refractive index, so that an anti-reflection film (ARC) can prevent light reflection loss of the upper surface of the substrate 10, that is, the light receiving surface. -Reflective Coating
한편, 기판(10)의 하층부에는 광생성된 소수 운송자의 후면쪽 이동을 차단하기 위한 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층(10-1)이 구비된다.On the other hand, the lower layer portion of the substrate 10 is provided with a high concentration doping layer 10-1 of the first conductivity type impurity forming a rear electric field for blocking the rear side movement of the photo-generated minority transporter.
아울러, 전면전극(14)은 기판(10)의 상부에 전체적으로 적층된 보조전극층(30)을 통해 소수 운송자를 포집할 수 있기 때문에, 굳이 기판(10)의 상층부에 국부적으로 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 패턴화할 필요가 없으므로, 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하지 않도록 보조전극층(30)의 상부면에 형성될 수 있다. 물론, 필요에 따라 제2도전형 불순물의 고농도 도핑 영역(10-2)의 형성 위치에 대응하도록 보조전극층(30)의 상부면에 전면전극(14)이 형성될 수도 있다.In addition, since the front electrode 14 may trap a small number of carriers through the auxiliary electrode layer 30 stacked on the substrate 10 as a whole, the second conductive type impurities locally formed on the upper layer of the substrate 10 are dared. Since the patterning does not need to correspond to the formation position of the heavily doped region 10-2, the upper surface of the auxiliary electrode layer 30 does not correspond to the formation position of the heavily doped region 10-2 of the second conductive type impurity. Can be formed on. Of course, if necessary, the front electrode 14 may be formed on the upper surface of the auxiliary electrode layer 30 to correspond to the formation position of the highly doped region 10-2 of the second conductivity type impurity.
예를 들어, 전면전극(14)은 핑거 라인 형태 등의 패턴으로 형성될 수 있으며, 이때 약 20㎛ 내지 40㎛ 정도의 좁은 선폭(W)을 갖고, 약 1800㎛ 내지 2300㎛ 이내 정도의 전극 간의 간격(d)을 갖도록 형성되거나, 필요에 따라 기판(10)의 수광면을 초과하지 않는 범위 이내에서 2300㎛를 초과하는 전극 간의 간격(d)을 갖도록 형성됨으로써, 일반적인 태양전지의 수광면에 비해 월등히 넓은 수광면을 확보할 수 있다. 아울러 전면전극(14)은 제2도전형 불순물의 고농도 도핑 영역(10-2)의 패턴에 평행하거나 직교하는 방향으로 형성될 수 있다.For example, the front electrode 14 may be formed in a pattern such as a finger line shape, wherein the front electrode 14 has a narrow line width (W) of about 20 μm to 40 μm, and between electrodes of about 1800 μm to 2300 μm. It is formed to have a gap (d) or, if necessary, to have a gap (d) between the electrodes exceeding 2300㎛ within a range that does not exceed the light receiving surface of the substrate 10, compared to the light receiving surface of a typical solar cell A wider light receiving surface can be secured. In addition, the front electrode 14 may be formed in a direction parallel or perpendicular to the pattern of the highly doped region 10-2 of the second conductive impurity.
이하, 본 발명의 제4실시예에 따른 국부화 에미터 태양전지의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a localized emitter solar cell according to a fourth embodiment of the present invention will be described.
먼저, 도 33에 도시된 바와 같이, 제1도전형의 실리콘 재질의 기판(10)을 준비한다(S400).First, as shown in FIG. 33, a first conductive silicon substrate 10 is prepared (S400).
상기한 단계 S400에서는 기판(10)의 커팅 공정의 결과로 생성된 결함 부분을 제거하기 위하여 화학적 방식으로 기판(10)을 식각하는 쏘 데미지 에칭(Saw Damage Etching) 공정을 진행하게 된다. 이때 식각 용액으로 수산화칼륨(KOH) 용액 등을 사용하여 기판(10)의 표면을 전체적으로 일정 깊이만큼 식각한 후, DIW(Deionized Water) 등을 사용하여 세정하는 것이 바람직하다. In step S400, a saw damage etching process is performed to etch the substrate 10 in a chemical manner in order to remove a defect portion generated as a result of the cutting process of the substrate 10. At this time, it is preferable to etch the surface of the substrate 10 by a predetermined depth using a potassium hydroxide (KOH) solution or the like as an etching solution, and then wash using DIW (Deionized Water).
아울러, 쏘 데미지 에칭(Saw Damage Etching) 공정 이후에는, 산(Acid) 또는 알카리(Alkaline) 등을 이용한 습식 텍스쳐링 공정이나 건식 텍스쳐링 공정을 진행하게 된다. 이러한 텍스쳐링 공정에 의해 형성되는 기판(10)의 표면 요철 구조는 도면의 간략화를 위해 도면상에 도시하지 않았다.In addition, after the saw damage etching (Saw Damage Etching) process, a wet texturing process or a dry texturing process using an acid or alkaline (Alkaline), etc. are performed. The surface uneven structure of the substrate 10 formed by this texturing process is not shown in the drawings for the sake of simplicity.
상기한 단계 S400을 통해 기판(10)이 준비된 상태에서, 도 34에 도시된 바와 같이, 제2도전형 불순물의 고농도 도핑 영역(10-2)이 형성될 부위를 제외한 기판(10)의 상부, 특히 기판(10)의 상층부에 제1도전형 불순물을 국부적으로 헤비 도핑(Heavy Doping)시켜 제1도전형 불순물의 고농도 도핑 영역(10-3)을 형성한다(S410).In the state where the substrate 10 is prepared through the above step S400, as shown in FIG. 34, the upper portion of the substrate 10 except for the region where the high concentration doped region 10-2 of the second conductivity type impurity is to be formed, In particular, the heavily doped first conductive impurities are locally formed on the upper layer of the substrate 10 to form a highly doped region 10-3 of the first conductive impurities (S410).
상기한 단계 S410에서는 불순물 이온 주입 공정이나 레이져 도핑 또는 불순물 페이스트를 소스로 한 확산 공정을 등을 수행할 수 있다. 이때 확산 공정시에는 확산 방지막을 사용할 수도 있고 사용하지 않을 수도 있다.In step S410, an impurity ion implantation process, a laser doping, or a diffusion process using an impurity paste as a source may be performed. In this case, the diffusion barrier may or may not be used in the diffusion process.
상기한 단계 S410을 통해 기판(10)의 상층부에 형성된 제1도전형 불순물의 고농도 도핑 영역(10-3)은 예컨대, p+ 영역으로 이루어질 수 있으며, 기판(10)의 전면에서 소수 운송자의 접근을 방지하기 위한 전계를 형성하는 역할을 담당하게 된다.The high concentration doping region 10-3 of the first conductivity type impurity formed in the upper layer of the substrate 10 through step S410 may be formed of, for example, a p + region. It is responsible for forming an electric field to prevent.
상기한 단계 S410 이후에는, 열처리 공정 또는 증착 공정 등을 수행하여 도 35에 도시된 바와 같이, 기판(10)의 표면에 유전층(20, 21)을 형성한다(S420).After the above step S410, as shown in FIG. 35 by performing a heat treatment process or a deposition process, dielectric layers 20 and 21 are formed on the surface of the substrate 10 (S420).
상기한 단계 S410에서는 PECVD(Plasma Enhanced Chemical Vapor Deposition) 공정 등의 화학기상증착 공정 등을 수행하여 기판(10)의 상부면에만 실리콘 질화막(Si3N4)으로 구성된 유전층(20)을 형성할 수 있다.In step S410, the dielectric layer 20 including the silicon nitride layer Si 3 N 4 may be formed only on the upper surface of the substrate 10 by performing a chemical vapor deposition process such as a plasma enhanced chemical vapor deposition (PECVD) process. have.
상기한 단계 S410 이후, 기판(10)의 후면에 알루미늄(Al) 및 은(Ag) 등을 포함하는 금속 물질을 도포하고, 소성 공정을 진행하여 도 36에 도시된 바와 같이, 기판(10)의 하부면에 후면전극(15)을 형성한다(S430).After the above step S410, a metal material including aluminum (Al), silver (Ag), and the like is applied to the rear surface of the substrate 10, and the firing process is performed, as shown in FIG. A rear electrode 15 is formed on the lower surface (S430).
상기한 단계 S430에서는 소성 공정 시의 열처리에 의해, 기판(10)의 하부면에 도포된 금속 물질 중 알루미늄(Al)을 소스로 한 제1도전형 불순물의 고농도 도핑층(10-1)이 기판(10)의 하층부에 자연 형성되는데, 이때 상기한 단계 S420을 통해 기판(10)의 하부면에 형성된 유전층(21)은 알루미늄(Al)을 소스로 한 제1도전형 불순물의 도핑으로 인해 제1도전형 불순물의 고농도 도핑층(10-1) 내에 포함되는 것이 바람직하다.In the step S430 described above, a high concentration doping layer 10-1 of a first conductive type impurity having aluminum (Al) as a source of the metal material applied to the lower surface of the substrate 10 is formed by heat treatment during the firing process. It is naturally formed in the lower layer of the (10), wherein the dielectric layer 21 formed on the lower surface of the substrate 10 through the step S420 is the first due to the doping of the first conductive type impurities sourced from aluminum (Al) It is preferably included in the highly doped layer 10-1 of the conductive impurity.
상기한 단계 S430 다음에는, 레이져 도핑 공정을 수행하여 도 37에 도시된 바와 같이, 기판(10)의 상부에 형성된 유전층(20)을 국부적으로 제거함과 동시에, 그 유전층(20)이 제거된 기판(10)의 상층부에 제2도전형 불순물을 헤비 도핑시켜 기판(10)의 상층부에 제2도전형 불순물의 고농도 도핑 영역(10-2)을 국부적으로 노출시켜 형성한다(S440).Next to step S430, as illustrated in FIG. 37, the laser doping process is performed to locally remove the dielectric layer 20 formed on the substrate 10 and to remove the dielectric layer 20. The second conductive impurity is heavy-doped on the upper layer of 10), and the high concentration doped region 10-2 of the second conductive impurity is locally exposed on the upper layer of the substrate 10 (S440).
상기한 단계 S440을 통해 기판(10)의 상층부에 형성된 제2도전형 불순물의 고농도 도핑 영역(10-2)은 제1도전형 불순물의 고농도 도핑 영역(10-3)과 접촉없이 교번하도록 형성되는 것이 바람직하며, 예컨대 n++ 영역으로 이루어질 수 있다.The high concentration doped region 10-2 of the second conductive impurity formed in the upper layer portion of the substrate 10 through step S440 is formed to alternate with the high concentration doped region 10-3 of the first conductive impurity. Preferably, it may consist, for example, of n ++ regions.
상기한 단계 S440 이후, 도 38에 도시된 바와 같이, 기판(10)의 상부에 보조전극층(30)을 증착시킨다(S450).After the above step S440, as shown in FIG. 38, the auxiliary electrode layer 30 is deposited on the substrate 10 (S450).
상기한 단계 S450를 통해 기판(10)의 상부에 형성된 보조전극층(30)은 유전층(20) 위에 증착될 뿐 아니라, 기판(10)의 상부에 국부적으로 노출된 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉되도록 증착될 수 있다.The auxiliary electrode layer 30 formed on the substrate 10 through the step S450 is not only deposited on the dielectric layer 20 but also a highly doped region of the second conductive impurity locally exposed on the substrate 10. It may be deposited so as to be in direct contact with (10-2).
상기한 단계 S450 이후, 스크린 프린팅 공정을 수행하여 도 39에 도시된 바와 같이, 보조전극층(30) 위에 수광면을 최대한 확보할 수 있도록 간격(d)을 최대한 넓히는 등의 패턴으로 전면전극(14)을 형성한다(S460).After the above step S450, as shown in FIG. 39 by performing a screen printing process, the front electrode 14 in a pattern such as to widen the interval (d) as much as possible to secure the maximum light receiving surface on the auxiliary electrode layer (30) To form (S460).
상기한 단계 S460에서 전면전극(14) 형성 시에는 보조전극층(30) 위에 원하는 패턴으로 은(Ag) 등으로 구성된 금속 물질을 도포한 후, 소성 공정을 진행하는 것이 바람직하다.When forming the front electrode 14 in the step S460 described above, it is preferable to apply a metal material composed of silver (Ag) or the like on the auxiliary electrode layer 30 in a desired pattern, and then proceed with the firing process.
한편으로는, 상기한 단계 S450에서 도 40에 도시된 바와 같이, 우선 기판(10)과의 접촉시 비저항을 낮추어 주는 도금층(Seed Layer)(20-1)을, 제2도전형 불순물의 고농도 도핑 영역(10-2)에 직접 접촉하도록 증착시킨 후, 기판(10)의 상부에 전체적으로 보조전극층(30)을 증착시킨 다음, 상기한 단계 S460을 수행하여 도 41에 도시된 바와 같은 국부화 에미터 태양전지를 제조할 수 있다.On the other hand, as shown in FIG. 40 in step S450 described above, first, the plating layer 20-1, which lowers the specific resistance upon contact with the substrate 10, is heavily doped with the second conductive impurity. After the deposition is made in direct contact with the region 10-2, the entire auxiliary electrode layer 30 is deposited on the substrate 10, and then the above-described step S460 is performed to perform the localization emitter as shown in FIG. 41. Solar cells can be manufactured.
다르게는, 상기한 단계 S400을 통해 기판(10)이 준비된 상태에서, 제2도전형 불순물의 고농도 도핑 영역(10-2)이 형성될 부위를 제외한 기판(10)의 상부면 위에 제1도전형 불순물이 헤비 도핑된 비정질 실리콘(a-Si) 박막을 패터닝함으로써, 기판(10)의 상부면 위에 제1도전형 불순물의 고농도 도핑 영역(10-3)을 국부적으로 형성한 다음, 상기한 단계 S420 내지 S460을 수행하여 도 42에 도시된 바와 같이, 제1도전형 불순물의 고농도 도핑 영역(10-3)이 제2도전형 불순물의 고농도 도핑 영역(10-2) 및 보조전극층(14)과 접촉하지 않도록 기판(10)의 상부면 위에 적층된 구조를 갖는 국부화 에미터 태양전지를 제조할 수 있다. 다만, 상기한 단계 S420 내지 S460 수행시, 열처리 공정을 수행하는 경우에는 기판(10)의 상부면 위에 패터닝되어 있는 비정질 실리콘(a-Si) 박막의 손상 방지를 위하여 400℃ 이하의 온도로 열처리 하는 것이 바람직하다.Alternatively, in the state in which the substrate 10 is prepared through the above-described step S400, the first conductive type is formed on the upper surface of the substrate 10 except for the portion where the high concentration doped region 10-2 of the second conductive type impurity is to be formed. By patterning the doped heavy-doped amorphous silicon (a-Si) thin film, a high concentration doped region 10-3 of the first conductivity type impurity is locally formed on the upper surface of the substrate 10, and then the step S420 As shown in FIG. 42, the heavily doped region 10-3 of the first conductivity type impurity is in contact with the heavily doped region 10-2 of the second conductivity type impurity and the auxiliary electrode layer 14. Localized emitter solar cells having a structure stacked on the upper surface of the substrate 10 may be manufactured so as not to. However, when the heat treatment process is performed when the above steps S420 to S460 are performed, heat treatment is performed at a temperature of 400 ° C. or lower to prevent damage of the amorphous silicon (a-Si) thin film patterned on the upper surface of the substrate 10. It is preferable.
본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법은 전술한 실시예에 국한되지 않고 본 발명의 기술사상이 허용하는 범위 내에서 다양하게 변경하여 실시할 수 있다.The localized emitter solar cell according to the present invention and a method of manufacturing the same are not limited to the above-described embodiment and can be carried out in various modifications within the range allowed by the technical idea of the present invention.
본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비하되, 기판의 수광 부위 중 에미터 형성 영역을 제외한 수광 부위에 에미터의 도전형과 반대 극성을 가진 도전형 불순물의 도핑 영역을 구비함으로써, 광생성된 소수 운송자의 재결합율를 극소화시켜 소수 운송자의 라이프 타임을 증가시킬 수 있고, 에미터에 접촉되어 소수 운송자를 포집하는 전극의 선폭을 감소시킬 수 있어, 수광면을 최대한 확보하면서 태양전지의 광전 변환 효율을 극대화시킬 수 있는 효과가 있다.According to the localized emitter solar cell according to the present invention and a method for manufacturing the same, the emitter is electrically conductive to the light receiving site except for the emitter formation region of the light receiving site including the emitter and the electrode. By providing a doped region of a conductive impurity having a polarity opposite to the type, the recombination rate of the photogenerated minority carriers can be minimized to increase the lifetime of the minority carriers, and the line width of the electrode contacting the emitter to capture the minority carriers Since it can be reduced, there is an effect that can maximize the photoelectric conversion efficiency of the solar cell while ensuring the light receiving surface to the maximum.
또한, 본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 기판의 수광 부위에 국부적으로 에미터 및 전극을 구비하되, 에미터와 전극 사이에 에미터를 통해 수집된 소수 운송자를 전극으로 전달하기 위한 보조전극층을 구비함으로써, 전극의 선폭, 개수 및 간격 등과 같은 전극 패턴 형태에 상관없이, 기판 내에서 광생성된 소수 운송자를 안전하게 전극으로 전달할 수 있어, 기판의 수광 부위에 형성될 전극의 선폭 및 개수를 감소시키고 전극 간 간격을 최대화시키는 등, 기판의 수광면을 최대로 확보할 수 있는 전극 패턴을 형성할 수 있고, 이로 인해 태양전지의 수광율을 극대화시켜 태양전지의 효율을 증가시킬 수 있는 효과가 있다.In addition, according to the localized emitter solar cell and a method for manufacturing the same according to the present invention, while having a local emitter and an electrode at the light receiving portion of the substrate, a small number of carriers collected through the emitter between the emitter and the electrode By providing an auxiliary electrode layer for transferring to the electrode, regardless of the shape of the electrode pattern, such as the line width, number and spacing of the electrode, it is possible to safely deliver a small number of carriers generated in the substrate to the electrode, the electrode to be formed on the light receiving portion of the substrate It is possible to form an electrode pattern that can maximize the light receiving surface of the substrate, such as reducing the line width and number of electrodes and maximizing the distance between the electrodes, thereby maximizing the light reception rate of the solar cell, thereby increasing the efficiency of the solar cell. It can be effected.
또한, 본 발명에 따른 국부화 에미터 태양전지 및 그 제조 방법에 의하면, 산화막 제거를 위한 세정 공정이나 단선용 트렌치 형성을 위한 절연 공정 등을 수행할 필요가 없어, 공정 절차를 간소화하여 제조 기간을 단축시킬 수 있으며, 제조 비용도 절감할 수 있는 효과가 있다.In addition, according to the localized emitter solar cell and the manufacturing method according to the present invention, there is no need to perform the cleaning process for removing the oxide film, the insulation process for forming the trench for disconnection, etc. It can shorten and reduce the manufacturing cost.

Claims (39)

  1. 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며,It includes a first conductive substrate of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces,
    상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며,A high concentration doped region of the second conductive impurity is locally formed in the upper layer of the substrate,
    상기 전면전극은 상기 제2도전형 불순물의 고농도 도핑 영역에 접촉 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The front electrode is a localized emitter solar cell, characterized in that formed in contact with the high concentration doping region of the second conductivity type impurities.
  2. 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며,It includes a first conductive substrate of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces,
    상기 기판의 상부에는 상기 전면전극이 접촉 형성되는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며,A high concentration doped region of a second conductive impurity in which the front electrode is in contact with the front electrode is locally formed on the substrate.
    상기 기판의 상부 중 상기 제2도전형 불순물의 고농도 도핑 영역의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역이 형성되되,A high concentration doped region of the first conductive impurity is formed at a portion of the upper portion of the substrate except for a portion of the high concentration doped region of the second conductive impurity,
    상기 제1도전형 불순물의 고농도 도핑 영역은 상기 제2도전형 분순물의 고농도 도핑 영역 및 상기 전면전극과 접촉되지 않도록 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The high concentration doped region of the first conductive impurity is formed so as not to contact the high concentration doped region of the second conductive impurities and the front electrode.
  3. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2,
    상기 기판의 상하부면에는 상기 전면전극이 형성된 부위를 제외하고 유전층이 형성되며,Dielectric layers are formed on upper and lower surfaces of the substrate except for the portion where the front electrode is formed.
    상기 기판의 상부면에 형성된 유전층 위에는 반사방지막(ARC: Anti-Reflective Coating)이 적층되고,An anti-reflective coating (ARC) is stacked on the dielectric layer formed on the upper surface of the substrate,
    상기 기판의 하층부에는 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층이 구비되는 것을 특징으로 하는 국부화 에미터 태양전지.The lower layer of the substrate is a localized emitter solar cell, characterized in that provided with a high concentration doping layer of the first conductivity type impurities forming a back electric field.
  4. 제3항에 있어서,The method of claim 3,
    상기 전면전극은 상기 기판과 직접 접촉되는 하층부에 씨앗층을 구비하는 것을 특징으로 하는 국부화 에미터 태양전지.The front electrode is a localized emitter solar cell, characterized in that the seed layer is provided in the lower layer in direct contact with the substrate.
  5. 제3항에 있어서,The method of claim 3,
    상기 전면전극은 핑거 라인 형태의 패턴으로 형성되되, 20㎛ 내지 40㎛의 선폭으로 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The front electrode is formed in a pattern of a finger line, localized emitter solar cell, characterized in that formed in a line width of 20㎛ to 40㎛.
  6. 제5항에 있어서,The method of claim 5,
    상기 전면전극은 450㎛ 내지 2300㎛의 간격으로 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The front electrode is a localized emitter solar cell, characterized in that formed at intervals of 450㎛ to 2300㎛.
  7. 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며,It includes a first conductive substrate of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces,
    상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며,A high concentration doped region of the second conductive impurity is locally formed in the upper layer of the substrate,
    상기 기판과 상기 전면전극 사이에 유전층 및 보조전극층이 차례로 적층되어 구성되는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell, wherein a dielectric layer and an auxiliary electrode layer are sequentially stacked between the substrate and the front electrode.
  8. 상하부면에 전면전극 및 후면전극이 구비된 실리콘 재질의 제1도전형의 기판을 포함하며,It includes a first conductive substrate of a silicon material having a front electrode and a rear electrode on the upper and lower surfaces,
    상기 기판의 상층부에는 제2도전형 불순물의 고농도 도핑 영역이 국부적으로 형성되며,A high concentration doped region of the second conductive impurity is locally formed in the upper layer of the substrate,
    상기 기판의 상부 중 상기 제2도전형 불순물의 고농도 도핑 영역의 형성 부위를 제외한 부위에는 제1도전형 불순물의 고농도 도핑 영역이 형성되며,A high concentration doped region of the first conductive impurity is formed in a portion of the upper portion of the substrate except for a portion of the high concentration doped region of the second conductive impurity,
    상기 기판과 상기 전면전극 사이에 유전층 및 보조전극층이 차례로 적층되어 구성되는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell, wherein a dielectric layer and an auxiliary electrode layer are sequentially stacked between the substrate and the front electrode.
  9. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8,
    상기 유전층은,The dielectric layer is
    상기 기판의 상부면 중 제2도전형 불순물의 고농도 도핑 영역의 형성 부위를 제외한 부위에 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The localized emitter solar cell of claim 1, wherein the emitter is formed on a portion of the upper surface of the substrate other than a portion of a high concentration doped region of the second conductive impurity.
  10. 제9항에 있어서,The method of claim 9,
    상기 유전층은,The dielectric layer is
    실리콘 산화물, 알루미늄 산화물, 티타늄 산화물 또는 실리콘 질화물로 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell comprising silicon oxide, aluminum oxide, titanium oxide or silicon nitride.
  11. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8,
    상기 보조전극층은,The auxiliary electrode layer,
    상기 제2도전형 불순물의 고농도 도핑 영역에 직접 접촉하거나, 도금층을 매개로 접촉하도록 상기 유전층 위에 적층되어 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The localized emitter solar cell of claim 2, wherein the emitter solar cell is formed on the dielectric layer to be in direct contact with the heavily doped region of the second conductive impurity or to be in contact with the plating layer.
  12. 제11항에 있어서,The method of claim 11,
    상기 보조전극층은,The auxiliary electrode layer,
    투명전도산화막으로 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell comprising a transparent conductive oxide film.
  13. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8,
    상기 유전층 및 상기 보조전극층은,The dielectric layer and the auxiliary electrode layer,
    반사방지막(ARC: Anti-Reflective Coating) 역할을 수행하는 것을 특징으로 하는 국부화 에미터 태양전지.Localized emitter solar cell, characterized in that it serves as an anti-reflective coating (ARC).
  14. 제13항에 있어서,The method of claim 13,
    상기 기판은,The substrate,
    하층부에 후면 전계를 형성하는 제1도전형 불순물의 고농도 도핑층을 구비하는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell comprising a highly doped layer of a first conductivity type impurity that forms a rear electric field in a lower layer portion.
  15. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8,
    상기 제2도전형 불순물의 고농도 도핑 영역은,The highly doped region of the second conductive impurity is
    규칙 또는 불규칙적인 선폭 및 간격을 갖는 선 패턴으로 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell, characterized in that it is formed in a line pattern with regular or irregular line widths and spacing.
  16. 제15항에 있어서,The method of claim 15,
    상기 전면전극은,The front electrode,
    상기 제2도전형 불순물의 고농도 도핑 영역의 패턴에 평행하거나 직교하는 방향으로 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The localized emitter solar cell of claim 2, wherein the emitter is formed in a direction parallel to or perpendicular to the pattern of the heavily doped region of the second conductive impurity.
  17. 제7항 또는 제8항에 있어서,The method according to claim 7 or 8,
    상기 제2도전형 불순물의 고농도 도핑 영역은,The highly doped region of the second conductive impurity is
    규칙 또는 불규칙적인 크기 및 간격을 갖는 점 패턴으로 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell, characterized in that it is formed in a dot pattern with regular or irregular size and spacing.
  18. 제8항에 있어서,The method of claim 8,
    상기 제1도전형 불순물의 고농도 도핑 영역은,The highly doped region of the first conductive type impurity is
    상기 제2도전형 불순물의 고농도 도핑 영역 및 상기 보조전극층과 접촉하지 않도록 형성되는 것을 특징으로 하는 국부화 에미터 태양전지.The localized emitter solar cell of claim 2, wherein the doped region of the second conductive impurity is not in contact with the auxiliary electrode layer.
  19. 제2항 또는 제8항에 있어서,The method according to claim 2 or 8,
    상기 제1도전형 불순물의 고농도 도핑 영역은,The highly doped region of the first conductive type impurity is
    상기 기판의 상층부에 형성되어, 광생성된 소수 운송자의 기판 표면 이동을 방지하는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell formed on an upper layer of the substrate to prevent movement of the substrate surface of the photogenerated minority transporter.
  20. 제2항 또는 제8항에 있어서,The method according to claim 2 or 8,
    상기 제1도전형 불순물의 고농도 도핑 영역은,The highly doped region of the first conductive type impurity is
    상기 기판의 상부면 위에 적층된 구조로 형성되어 광생성된 소수 운송자의 기판 표면 이동을 방지하는 것을 특징으로 하는 국부화 에미터 태양전지.The localized emitter solar cell of claim 1, wherein the light emitter is formed on the upper surface of the substrate to prevent movement of the substrate surface of the photo-generated minority transporter.
  21. 제2항 또는 제8항에 있어서,The method according to claim 2 or 8,
    상기 제1도전형 불순물의 고농도 도핑 영역은,The highly doped region of the first conductive type impurity is
    제1도전형 불순물이 헤비 도핑된 비정질 실리콘 박막으로 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지.A localized emitter solar cell, wherein the first conductive impurity is made of a heavily doped amorphous silicon thin film.
  22. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 상층부에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate;
    상기 기판의 후면에 후면 금속 물질을 도포하는 단계와;Applying a back metal material to a back side of the substrate;
    스크린 프린팅 공정을 통해 상기 제2도전형 불순물의 고농도 도핑 영역 상부에 전면 금속 물질을 도포하는 단계와;Applying a front metal material over the high concentration doped region of the second conductive impurity through a screen printing process;
    소성 공정을 진행하여 상기 기판의 전후면에 전면전극 및 후면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a front electrode and a back electrode on the front and back surfaces of the substrate by firing.
  23. 제22항에 있어서,The method of claim 22,
    상기 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계는,Forming a high concentration doped region of the second conductive impurity,
    제2도전형의 불순물 페이스트를 소스로 한 확산 공정을 수행하는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A method of manufacturing a localized emitter solar cell, comprising performing a diffusion process using a second conductive impurity paste as a source.
  24. 제23항에 있어서,The method of claim 23, wherein
    상기 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계는,Forming a high concentration doped region of the second conductive impurity,
    상기 기판의 전면에 상기 제2도전형의 불순물 페이스트를 국부적으로 패터닝하는 단계와;Locally patterning the impurity paste of the second conductivity type on an entire surface of the substrate;
    상기 제2도전형의 불순물 페이스트에 함유된 불순물이 상기 기판 내부로 확산하도록 열처리 공정을 시행하는 단계와;Performing a heat treatment process to diffuse the impurities contained in the second conductive type impurity paste into the substrate;
    상기 열처리 공정에 의해 상기 제2도전형의 불순물 페이스트가 패터닝된 부위를 제외한 상기 기판의 표면에 유전층이 형성되는 단계와;Forming a dielectric layer on a surface of the substrate except for a portion where the second conductive type impurity paste is patterned by the heat treatment process;
    상기 기판의 전면에 반사방지막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 제조 방법.And forming an anti-reflection film on the entire surface of the substrate.
  25. 제24항에 있어서,The method of claim 24,
    상기 전면전극 및 후면전극을 형성하는 단계는, Forming the front electrode and the back electrode,
    상기 소성 공정 시의 열처리에 의해, 상기 후면 금속 물질 중 알루미늄(Al)을 소스로 한 제1도전형 불순물의 고농도 도핑층이 상기 기판의 하층부에 형성되는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 제조 방법.And by forming a highly doped layer of a first conductive impurity sourced from aluminum (Al) as the source of the back metal material in the lower layer of the substrate by the heat treatment during the baking process. Emitter manufacturing method.
  26. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 표면에 유전층을 형성하는 단계와;Forming a dielectric layer on the surface of the substrate;
    상기 기판의 전면에 반사방지막을 형성하는 단계와;Forming an anti-reflection film on the entire surface of the substrate;
    상기 기판의 후면에 후면전극을 형성하는 단계와;Forming a rear electrode on a rear surface of the substrate;
    레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막 및 유전층을 국부적으로 제거하며, 상기 기판의 전면에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Locally removing the anti-reflection film and the dielectric layer formed on the front surface of the substrate through a laser doping method, and forming a highly doped region of the second conductive impurity locally on the front surface of the substrate;
    도금 공정(Plating)을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a front electrode on the high concentration doped region of the second conductivity type impurity by plating.
  27. 제26항에 있어서,The method of claim 26,
    상기 전면전극을 형성하는 단계는,Forming the front electrode,
    비저항을 낮추어 주는 씨앗층(Seed Layer)을 상기 제2도전형 불순물의 고농도 도핑 영역에 직접 접촉하도록 증착시키고, 상기 씨앗층 위에 금속 도금하여 전면전극을 형성하는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A localized emitter solar cell, comprising: depositing a seed layer that lowers a specific resistance so as to be in direct contact with a high concentration doped region of the second conductive impurity, and metal plating the seed layer to form a front electrode; Manufacturing method.
  28. 제22항 내지 제27항 중 어느 하나에 있어서,The method according to any one of claims 22 to 27,
    상기 기판을 준비하는 단계에서는,In the step of preparing the substrate,
    쏘 데미지 에칭(Saw Damage Etching) 공정 및 텍스쳐링 공정을 진행하는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A method of manufacturing a localized emitter solar cell, characterized by performing a saw damage etching process and a texturing process.
  29. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 표면에 유전층을 형성하는 단계와;Forming a dielectric layer on the surface of the substrate;
    상기 기판의 하부면에 후면전극을 형성하는 단계와;Forming a rear electrode on the lower surface of the substrate;
    상기 기판의 상층부에 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a highly doped region of a second conductive impurity locally in an upper layer of the substrate;
    상기 기판의 상부에 보조전극층을 증착시키는 단계와;Depositing an auxiliary electrode layer on the substrate;
    상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A method of manufacturing a localized emitter solar cell, comprising: forming a front electrode on the auxiliary electrode layer.
  30. 제29항에 있어서,The method of claim 29,
    상기 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계에서는,In the step of forming a highly doped region of the second conductivity type impurity,
    레이져 도핑 공정을 수행하여 상기 기판의 상부에 형성된 상기 유전층을 국부적으로 제거하며, 상기 유전층이 제거된 상기 기판의 상층부에 상기 제2도전형 불순물을 도핑시키는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.Locally removing the dielectric layer formed on the substrate by performing a laser doping process, and doping the second conductive type impurity on the upper layer of the substrate from which the dielectric layer is removed, manufacturing a localized emitter solar cell Way.
  31. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 상층부에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a highly doped region of a first conductivity type impurity locally in an upper layer of the substrate;
    상기 기판의 전면에 반사방지막을 형성하는 단계와;Forming an anti-reflection film on the entire surface of the substrate;
    상기 기판의 후면에 후면전극을 형성하는 단계와;Forming a rear electrode on a rear surface of the substrate;
    레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막을 국부적으로 제거하며, 상기 기판의 상층부에 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity. Making a step;
    도금 공정을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a front electrode on the high concentration doped region of the second conductivity type impurity by performing a plating process.
  32. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 상부면 위에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate;
    상기 기판의 전면에 반사방지막을 형성하는 단계와;Forming an anti-reflection film on the entire surface of the substrate;
    상기 기판의 후면에 후면전극을 형성하는 단계와;Forming a rear electrode on a rear surface of the substrate;
    레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 반사방지막을 국부적으로 제거하며, 상기 기판의 상층부에 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;The anti-reflection film formed on the entire surface of the substrate is locally removed through a laser doping method, and a high concentration doped region of the second conductive impurity is formed locally so as not to contact the high concentration doped region of the first conductive impurity. Making a step;
    도금 공정을 진행하여 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a front electrode on the high concentration doped region of the second conductivity type impurity by performing a plating process.
  33. 제31항 또는 제32항에 있어서,33. The method of claim 31 or 32,
    상기 전면전극을 형성하는 단계는,Forming the front electrode,
    상기 제1도전형 불순물의 고농도 도핑 영역과 접촉없이, 상기 제2도전형 불순물의 고농도 도핑 영역의 상부에 접촉되도록 전면전극을 형성하는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a front electrode so as to be in contact with an upper portion of the high concentration doped region of the second conductive impurity without contacting the high concentration doped region of the first conductive impurity.
  34. 제31항 또는 제32항에 있어서,33. The method of claim 31 or 32,
    상기 기판의 표면에 유전층을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And forming a dielectric layer on the surface of the substrate.
  35. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 상부에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a heavily doped region of a first conductivity type impurity locally on the substrate;
    상기 기판의 표면에 유전층을 형성하는 단계와;Forming a dielectric layer on the surface of the substrate;
    상기 기판의 하부면에 후면전극을 형성하는 단계와;Forming a rear electrode on the lower surface of the substrate;
    레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 유전층을 국부적으로 제거하며, 상기 기판의 상층부에 상기 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity. Making a step;
    상기 기판의 상부에 보조전극층을 증착시키는 단계와;Depositing an auxiliary electrode layer on the substrate;
    상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A method of manufacturing a localized emitter solar cell, comprising: forming a front electrode on the auxiliary electrode layer.
  36. 제1도전형의 기판을 준비하는 단계와;Preparing a substrate of a first conductivity type;
    상기 기판의 상부면 위에 국부적으로 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;Forming a heavily doped region of a first conductivity type impurity locally on an upper surface of the substrate;
    상기 기판의 표면에 유전층을 형성하는 단계와;Forming a dielectric layer on the surface of the substrate;
    상기 기판의 하부면에 후면전극을 형성하는 단계와;Forming a rear electrode on the lower surface of the substrate;
    레이져 도핑 방식을 통해 상기 기판의 전면에 형성된 유전층을 국부적으로 제거하며, 상기 기판의 상층부에 상기 제1도전형 불순물의 고농도 도핑 영역과 접촉하지 않도록 국부적으로 제2도전형 불순물의 고농도 도핑 영역을 형성하는 단계와;The dielectric layer formed on the front surface of the substrate is locally removed through a laser doping method, and a locally heavily doped region of the second conductive impurity is formed on the upper layer of the substrate so as not to contact the heavily doped region of the first conductive impurity. Making a step;
    상기 기판의 상부에 보조전극층을 증착시키는 단계와;Depositing an auxiliary electrode layer on the substrate;
    상기 보조전극층 위에 전면전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.A method of manufacturing a localized emitter solar cell, comprising: forming a front electrode on the auxiliary electrode layer.
  37. 제32항 또는 제36항에 있어서,37. The method of claim 32 or 36,
    상기 제1도전형 불순물의 고농도 도핑 영역을 형성하는 단계는,Forming a high concentration doped region of the first conductivity type impurity,
    상기 제2도전형 불순물의 고농도 도핑 영역이 형성될 부위를 제외한 상기 기판의 상부면 위에 제1도전형 불순물이 헤비 도핑된 비정질 실리콘(a-Si) 박막을 패터닝하는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.Patterning an amorphous silicon (a-Si) thin film doped with a first conductive impurity on an upper surface of the substrate except for a portion where a high concentration doped region of the second conductive impurity is to be formed. Localized emitter solar cell manufacturing method.
  38. 제29항, 제31항, 제32항, 제35항 및 제36항 중 어느 하나의 항에 있어서,The method according to any one of claims 29, 31, 32, 35 and 36,
    상기 후면전극을 형성하는 단계는,Forming the back electrode,
    상기 기판의 후면에 금속 물질을 도포하고, 소성 공정을 진행하는 단계와;Applying a metal material to a rear surface of the substrate and performing a firing process;
    상기 소성 공정 시의 열처리에 의해, 상기 기판의 후면에 도포된 금속 물질을 소스로 한 제1도전형 불순물의 고농도 도핑층이 상기 기판의 하층부에 형성되는 단계를 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And a high concentration doped layer of a first conductivity type impurity having a metal material applied to the rear surface of the substrate as a source by heat treatment during the firing process, is formed on the lower layer of the substrate. Emitter solar cell manufacturing method.
  39. 제29항, 제30항, 제35항 및 제36항 중 어느 하나의 항에 있어서,The method according to any one of claims 29, 30, 35 and 36,
    상기 제2도전형 불순물의 고농도 도핑 영역에 직접 접촉하도록 도금층(Seed Layer)을 증착하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 국부화 에미터 태양전지 제조 방법.And depositing a seed layer in direct contact with the heavily doped region of the second conductivity type impurity.
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