WO2012083983A1

WO2012083983A1 - Silicon photoelectric multiplier with optical cross-talk suppression due to special properties of the substrate

Info

Publication number: WO2012083983A1
Application number: PCT/EP2010/007833
Authority: WO
Inventors: Razmick Mirzoyan
Original assignee: MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V.
Priority date: 2010-12-21
Filing date: 2010-12-21
Publication date: 2012-06-28
Also published as: US20130277564A1; EP2656400B1; JP2014507784A; CA2821578C; JP5908497B2; EP2656400A1; CA2821578A1; US9209329B2

Abstract

A cell (1) for a silicon based photoelectric multiplier comprises a substrate (21) of a second conductivity type, a first layer (2) of a first conductivity type, a second layer (3) of a second conductivity type formed on the first layer (2), wherein the first layer (2) and the second layer (3) form a first p-n junction, and wherein the substrate (21) is configured such that in operation of the photoelectric multiplier from a quantity of light stemming from photons produced in the multiplier and propagating towards a backside or side walls of the multiplier a negligible portion returns to a frontside of the multiplier.

Description

DESCRIPTION

SILICON PHOTOELECTRIC MULTIPLIER WITH OPTICAL CROSS-TALK

SUPPRESSION DUE TO SPECIAL PROPERTIES OF THE SUBSTRATE

FIELD^' OF THE INVENTION

The present invention is related to a cell for a silicon-based photoelectric multiplier, a silicon-based photoelectric multi- plier, a radiation detector, and a method for fabricating a cell for a silicon-based photoelectric multiplier.

The invention in general relates to the field of semiconductor optoelectronic devices, particularly to photo-detectors with high efficiency of light detection, including the visible part of the spectrum. The photo-detectors according to the invention can be used in a wide field of applications, which employ the detection of very weak and fast optical signals as, for example, industrial and medical tomography, life science, nuclear, particle and astro-particle physics etc.

A silicon-based photoelectric multiplier (SiPM) according to the state of the art (see e.g. EP 1 755 171 Bl) is composed of an array of individual cells. In particular the SiPM comprises a silicon substrate and a plurality of cells which are located on a surface of said substrate, for example, in an epitaxial layer. Each cell comprises an internal individual quenching resistor made of, for example, high resistant polysilicon and located on top of a silicon oxide layer which covers all cells. In operation each cell is supplied with reverse bias that exceeds the break-down voltage. When a photon is absorbed in the cell, a Geiger discharge takes place, the discharge being limited by the quenching resistor.

One major problem of these devices can be described as „optical cross-talk" wherein different forms of optical cross-talk can appear in the devices. One form of optical cross-talk originates from photons created in the Geiger discharge of a neighbouring cell. Another form of optical cross-talk, which is addressed by the present invention, originates from photons produced in the multiplier at an inclined angle at a first cell, being totally internally reflected at the back or side surface of the device and impinging into another cell from the back side or side wall and initiating a Geiger discharge in there. Such a situation is depicted in Fig. 1 in which a schematic cross-sectional representation of a silicon photoelectric multiplier is shown. Because the total internal reflection efficiency is 100% the back reflected photon can survive several reflections from the walls of the SiPM before being absorbed by one of the cells and firing it.

Fig. 1 shows a silicon photoelectric multiplier comprising an array of individual cells 1 located next to each other at a front entrance surface of the device. A light beam produced in the device at a cell at the outward left position under an angle Θ will be totally internally reflected at the back surface of the device so that it impinges into another cell at the outward right position of the array shown. The critical angle for the total internal reflection in silicon can be easily calculated to ©_to_t = arcsin 1/3,5 = 16,6° for light in the red spectral region. The photons can thus propagate to another not primarily fired pixel and initiate a discharge there. It is also obvious that for larger size photo-multipliers the angular range where the total internal reflection happens is larger. Even in the case when the incident light hits the backside surface of the photo-multiplier at an angle < 16,6°, only ~ 70% of the light is leaving the sample and 30% of the light is reflected back.

It is therefore an object of the present invention to provide a cell for a silicon-based photoelectric multiplier, a method for fabricating the same, and a silicon-based photoelectric multi- plier composed of a plurality of cells in which optical crosstalk between the cells, due to total internal reflection and partial back-reflection, is significantly reduced without significantly reducing the optical detection efficiency.

This object is solved by the features of the independent claims. Advantageous embodiments are subject of the dependent claims. It is an essential idea of the present invention to prevent or reduce total internal reflection and partial reflection of light within the silicon-based photoelectric multiplier by configuring a substrate in a way so that light having entered the device at the front surface and having penetrated the device in a direction to the back surface or side wall will not return to the front surface in a considerable amount. The result is that in practice only a small amount of incident light returns to the front surface and optical cross-talk is thus reduced to a tolerable level.

The present invention is therefore directed to a cell for a silicon-based photoelectric multiplier which comprises a substrate of a second conductivity type, a first layer of a first conductivity type, a second layer of a second conductivity type formed on the first layer, wherein the first layer and the second layer form a first p-n junction, wherein the substrate is configured such that in operation of the photoelectric multiplier from a quantity of light propagating towards a backside or side wall of the multiplier a negligible portion returns to a frontside of the multiplier, which means that less than 50%, more preferably less than 25% should return to the frontside.

According to an embodiment of the invention, a material layer is applied onto the back surface of the substrate, wherein the material type of the material layer is chosen such that the reflectivity of light with a wavelength « 1000 nm incident on the interface between the substrate and the material layer is well below 100%, in particular smaller than 50% or smaller than 25%.

In particular, the material of the material layer can be one or more of a metal, a metal compound, a metal alloy, or a semiconductor of pure or composite type. The material layer can be formed from one and only one of an element metal. However, it is also possible to form an alloy of two or more metals or of one metal and another element to form the material of the mate- rial layer. Besides metals also semiconductor materials can be used as the material of the material layer. It is also possible to use an alloy semiconductor as material for the material layer. According to an embodiment, the material layer can be deposited onto the backside surface of the substrate by an evaporation technique or by sputtering or any other conventional technique. The thickness of the material layer can be in the range of 5 nm to 1000 nm, in particular 5 nm to 500 nm, in particular 5 nm to 100 nm.

According to another embodiment, the back surface of the substrate is processed by an ion implantation step wherein the parameters of the ion implantation are selected such that, due to an implantation-induced damage of the crystal lattice, an absorption length of light with a wavelength in a range of « 1000 nm is decreased so that light incident on the front side will not be transmitted to the back side of the device. According to an embodiment thereof the back surface of the substrate is processed by an ion implantation step comprising an ion dose in the range of 10¹³ to 10¹⁵ cm^"2 and an ion energy in the range of 1 MeV to 10 MeV.

According to an embodiment, in addition, the side surfaces of the multiplier or the substrate are also treated in the same way as the backside surface of the substrate. According to another embodiment, the doping concentration of the substrate lies in a range of 10¹⁹ to 10²⁰ cm^-3 of the second conductivity type. Due to free carrier absorption of the doping material, an absorption length of light with a wavelength in a range of « 1000 nm is significantly decreased so that light incident on the front side will not be transmitted to the back side of the device. The SiPM structure, in particular the above-mentioned first and second layers, can be then grown epi- taxially on top of it.

According to another embodiment, the back surface of the substrate comprises a structure fabricated so as to trap or to diffuse light incident on the back surface from inside the sub- strate. The structure can, for example, consist of a plurality of indentations, grooves or recesses so that light beams are deflected or diffused and only a small to zero amount of incident light is reflected back to the front surface of the device. This embodiment can be either alternative or supplemental to any one of the other embodiments described herein.

According to an embodiment, the cell further comprises a doped buried layer of the first conductivity type, wherein the substrate and the buried layer form a second p-n conjunction. In the case that the surface treatment is done by an ion implantation, the doped buried layer could be fabricated at the same time by the same ion implantation step.

The present invention also relates to a silicon-based photoe- lectric multiplier comprising a plurality of cells such as those described before, wherein the cells are all fabricated on one common substrate.

The present invention also relates to a radiation detector com- prising a scintillator and an array of silicon-based photoelectric multipliers such as those as described in the preceding paragraph, wherein the silicon-based photoelectric multipliers are arranged to receive bursts of light produced by the scintillator in response to received radiation.

The present invention is also directed to a method for fabricating a cell for a silicon-based photoelectric multiplier, comprising providing a substrate of a second conductivity type, providing a first layer of a first conductivity type and a second layer of a second conductivity type, wherein the first layer and the second layer form a first p-n junction, and configuring the substrate such that in operation of the photoelectric multiplier from a quantity of light propagating towards a backside of the multiplier a negligible portion returns to a frontside of the multiplier.

According to an embodiment, the method further comprises applying a material layer onto the back surface of the substrate, wherein the material of the material layer is chosen such that the reflectivity of light with a wavelength in a range of « 1000 nm incident on the interface between the substrate and the material layer is well below 100%, in particular smaller than 50% or smaller than 25%.

According to an embodiment, the material layer is deposited by one of evaporation, sputtering or chemical vapor deposition. An advantage is that the application of the material layer can be performed in a very early stage, in particular in a wafer level stage when several multiplier devices are still joined together before the devices are packaged and the wafer is singulated into single packaged multiplier devices.

According to an embodiment, the material of the material layer comprises one or more of a metal, a metal compound, a metal alloy, or a semiconductor. According to an embodiment, the method further comprises processing the back surface of the substrate by an ion implantation step wherein the parameters of the ion implantation are selected such that, due to an implantation-induced damage of the crystal lattice, an absorption length of light with a wavelength in a range of « 1000 nm is decreased. According to an embodiment thereof, the ion implantation step comprises an ion dose in the range of 10¹³ to 10¹⁵ cm^-2 and an ion energy in the range of 1 MeV to 10 MeV.

According to another embodiment, the silicon substrate is provided with a doping concentration in a range of 10¹⁹ to 10²⁰ cm^"3 of a second conductivity type. Afterwards a silicon layer is grown epitaxially on the upper surface of the substrate and the photoelectric multiplier is fabricated within the epitaxial layer. The epitaxial growth can start with growing the first layer of first conductivity type on the highly doped silicon substrate of second conductivity type. Afterwards the second layer, the quenching resistor layer, the voltage distribution lines and, if necessary, the buried layer can be fabricated by ion implantation.

According to a further alternative embodiment, the method for fabricating starts with providing a substrate of second conduc- tivity type having a low or medium doping level of, for example, 5 x 10¹⁴ - 5 x 10¹⁶ cm^"3, then gluing the back surface of the low doped substrate to a another substrate having special absorbing characteristics, e.g. a highly doped substrate of second conductivity type having a doping range of, for example, 10¹⁹ to 10²⁰ cm^"3, and then fabricating the second layer, the quenching resistor layer, the voltage distribution lines and, if necessary, the buried layer on the low doped substrate.

According to another embodiment the method comprises fabricat- ing a structure into the back surface of the substrate so as to trap or to diffuse light incident from inside the substrate. According to an embodiment, the method further comprises generating a doped buried layer of the first conductivity type, so that the substrate and the doped buried layer form a second p-n junction.

According to an embodiment also the side surfaces of the substrate are treated in the same way as the backside surface of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further un- derstanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description.

Fig. 1 shows a schematic cross-sectional representation of a conventional silicon-based photoelectric multiplier illustrat- ing the problem of total internal reflection;

Figs. 2A,B show top view representation (A) and a cross- sectional representation (B) of a cell of a silicon-based photoelectric multiplier according to a first embodiment;

Fig. 3 shows a top view representation of a section of a sili^¬ con-based photoelectric multiplier according to a first embodi^¬ ment ; Fig. 4 show a cross-sectional representation along line A-A of Fig. 3 of the silicon-based photoelectric multiplier according to a first embodiment;

Fig. 5 shows a side view representation of a cell of a silicon- based photoelectric multiplier according to a second embodiment; and

Fig. 6 shows a cross-sectional representation of a radiation detector according to an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The aspects and embodiments are now described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the embodiments. It may be evident, however, to one skilled in the art that one or more aspects of the embodiments may be practiced with a lesser degree of the specific details. In other instances, known structures and elements are shown in schematic form in order to facilitate describing one or more aspects of the embodiments. The following description is therefore not to be taken in a limiting sense, and the scope is defined by the appended claims. It should also be noted that the representations of the various layers, sheets or substrates in the Figures are not necessarily to scale.

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "upper", "lower", "left-hand", "right- hand", "front side", "backside", etc., is used with reference to the orientation of the Figure (s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.

Fig. 2A shows a top view representation of a cell of a silicon- based photoelectric multiplier according to a first embodiment and Fig. 2B shows a cross-sectional representation of the cell along line B-B of Fig. 2A, wherein only a section down to a first layer 2 is shown. The cell 1 comprises a first layer 2 of a first conductivity type and a second layer 3 of a second conductivity type formed on the first layer 2 so that the first layer 2 and the second layer 3 form a first p-n junction. The cell 1 further comprises a quenching resistor layer 5 formed on the first layer 2 later- ally besides the second layer 3 and connected to a lateral side face of the second layer 3.

The cell 1 and in particular the second layer 3 can have a rectangular or quadratic shape and the quenching resistor layer 5 can be connected to one of the side edges of the second layer 3, in particular in the center of the side edge. The quenching resistor layer 5 extends in a direction away from the second layer 3 to make electrical contact to a voltage distribution line (not shown) remote from the second layer 3. The cell 1 can also comprise an insulation layer 7 covering the first layer 2, the second layer 3 and the quenching resistor layer 5. The insulation layer 7 can be such that it covers the whole matrix of cells with only one opening at an edge portion of the device for the purpose of electrically contacting the voltage distri- bution line. The second layer 3 and the quenching resistor layer 5 can be formed as well areas into the first layer 2 by using conventional ion implantation processes as known in CMOS fabrication technology. As can be seen in Fig. 2B, the implantation region of the second layer 3 is shown left-hatched and the implantation region of the quenching resistor layer 5 is shown right-hatched and an overlap between both regions can be provided when conducting the implantation steps so as to provide for a satisfactory electrical contact between both regions . It is to be noted that the elements as shown in Fig. 2A are not necessarily to scale as regards their dimensions with respect to each other as well as the geometric dimensions of the elements themselves. For example the quenching resistor layer 5 is shown to have a strip-like shape wherein the strip-like quench- ing resistor layer 5 can have, for example, a length to width ratio of greater than 10, more preferably greater than 20, more preferably greater than 30. Moreover the ratio of the length of a side edge of the cell 1 or of the second layer 3 to the width of the strip-like quenching resistor layer 5 can be, for exam- pie, greater than 10, more preferably greater than 20, more preferably greater than 30.

Furthermore the quenching resistor layer 5 can have a resistivity in the range of 10 to 50 KOhm/square. With such a resistiv- ity the quenching resistor layer 5 can efficiently act as a quenching resistor for quenching the avalanche current in operation of the photodiode. The value of the resistivity can be adjusted by the geometric dimensions and the dopant concentration of the quenching resistor layer 5.

The second layer 3 can have a relatively high level dopant concentration which can, for example, be in the range of 10¹⁸ to

Fig. 3 shows a top view representation of a section of a silicon-based photoelectric multiplier according to an embodiment. The photoelectric multiplier 10 depicted in Fig. 3 is comprised of a plurality of cells 1 such as that shown in Figs. 2A,B. They are arranged along rows wherein the cells 1 of one row are laterally displaced with respect to the cells 1 of an adjacent row wherein the displacement can be, for example, half the length of one side edge of a quadratically shaped cell 1.

The photoelectric multiplier 10 can have a plurality of voltage distribution lines 6. In the section of the photoelectric multiplier 10 as shown in Fig. 3 there are shown two voltage distribution lines 6 which are arranged along outer side edges of two adjacent rows of cells.1. The quenching resistor layers 5 of each cell 1 of one row extend in the narrow space between two neighboring cells 1 of an adjacent row and are electrically connected with the voltage distribution line 6 extending along the adjacent row. The voltage distribution lines 6 can also be made of a well area formed within the first layer 2. In particular the voltage distribution lines 6 can be formed of well areas having a dopant concentration of about 10¹⁹ cm^"3 or 5 x 10¹⁸ cm^"3 to 5 x 10¹⁹ cm^-3 or more so that they function as conductive wires. Thus the fabrication of the voltage distribution lines 6 can also be part of and embedded within the CMOS fabrication process.

Fig. 4 shows a cross-sectional representation along line A-A of Fig. 3 of the silicon-based photoelectric multiplier according to an embodiment .

The section of the photoelectric multiplier 20 shown in Fig. 4 includes the right part of one cell 1 shown on the left side of the drawing and the left part of a further cell 1 shown on the right side of the drawing and a region in between the adjacent cells 1, the region comprising a quenching resistor layer 5. The photoelectric multiplier 20 comprises a substrate 21 of a second conductivity type having a doping agent concentration in the range of 5 x 10¹⁴ - 5 x 10¹⁶ cm^-3 and a buried layer 22 of a first conductivity type having, for example, a peak doping agent concentration in the range of 5 x 10¹⁷ - 5 x 10¹⁸ cm^"3. The buried layer 22 is generated by an ion implantation.

Above the buried layer 22 the plurality of identical cells 1 is located, wherein each cell 1 is formed by the first layer 2 and the second layer 3. The first layer 2 is common for all cells 1 and it is contiguous throughout the photoelectric multiplier 20. The second layer 3 is formed as a thin layer of second conductivity type having a relatively high doping agent concentration like, for example, 10¹⁸ to 10¹⁹ cm^-3, and disposed on top of the first layer 2. The second layer 3 functions as an entrance window of the photoelectric multiplier 20. The first layer 2 and the second layer 3 form a first N-P junction at an interface between them, wherein in operation a reverse bias voltage is applied to the first N-P junction to such an extent that the photodiode operates in the Geiger mode. The thin strip-like silicon quenching resistor layers 5 of second conductance type connect each cell 1 with one of the voltage distribution lines 6 and serve as quenching resistors having a resistance of 10 - 50 KOhm/square. The voltage distribution lines 6 are made of second conductivity type silicon layers having a relatively high doping agent concentration like, for example, about 10¹⁹ cm^-3 or 5 x 10¹⁸ cm^"3 to 5 x 10¹⁹ cm^-3 or more of a doping agent concentration. The upper surface of the photoelectric multiplier 20 is covered by an insulation layer 7, in particular a silicon oxide layer, with corresponding antireflection properties at an upper surface thereof. Said strip-like quenching re- sistor layers 5 and voltage distribution lines 6 are disposed between the first layer 2 and the insulation layer 7. The voltage distribution lines 6 are connected together on the periphery of the photoelectric multiplier and there is only a single input power supply contact through a single opening window in the insulation layer 7. Finally a grid-like aluminum layer 8 which is serving for the output of the SiPM signal is disposed on top of the silicon oxide layer 7.

The cell 1 also comprises on the back surface of the substrate 21 a material layer 25, the material of which can be one of those mentioned above. If, for example, chromium is used as material of the material layer 25, a reflectivity of R = 21,38% can be calculated for a light beam having a wavelength of 1000 nm at the interface between the substrate 21 and the material layer 25.

The photoelectric multiplier 20 according to Fig. 4 is an embodiment of a highly efficient CMOS-technology compatible photoelectric multiplier. The buried layer 22 can be formed by an ion implantation step which can be carried out at an appropriate time in the course of the CMOS fabrication process. Also the other layers like the second layer 3, the quenching resistor layers 5 and the voltage distribution lines 6 can be processed by further ion implantation steps at appropriate times in the course of the CMOS fabrication process.

The silicon based photoelectric multiplier 20 thus contains the substrate 21 of the second conductivity type, the material layer 25, the buried layer 22 of the first conductivity type, a first layer 2 of first conductivity type, a second layer 3 of second conductivity type (entrance window) , strip-like quenching resistor layers 5 (quenching resistors) of first conductiv- ■ ity type, voltage distribution buses 6, the insulation layer 7, and the grid-like layer 8 on top of the insulation layer 7. As an example, the substrate 21 can have p-type (n-type) conductivity, the buried layer 22 can have n-type (p-type) conduc^¬ tivity, the layer 2 can have n-type (p-type) conductivity, the layers 3 can have p-type (n-type) conductivity, and the quenching resistor layers 5 and the voltage distribution lines 6 can have p-type (n-type) conductivity. It should further be noted that, according to the embodiment of Fig. 4, the buried layer 22 is fabricated as a non-planar layer, in particular it is fabricated such that it comprises varying depth throughout the device. In Fig. 4 it can be seen that in areas between the cells 1 the buried layer 22 is located deeper within the substrate as compared to the areas of the cells 1. The reason for this is that the electric field will be higher within the cells 1 as compared to the areas between the cells 1 so that only light which is incident on the cell 1 will be efficiently detected only by cell 1.

The highly efficient light detection in a broad part of the spectrum along with high uniformity of an electrical field is reached in a structure as that shown in Fig. 4, which is made by a CMOS-technology process. A high electric field needed for Geiger-type discharge (voltage above the breakdown value) is created in the N-P junction between the second layer 3

(entrance window) and the first layer 2. In addition in the embodiment of Fig. 4, another N-P junction is made between the substrate 21 and the buried layer 22, said junction preventing penetration of photoelectrons, created by secondary photons of the Geiger discharge, into the volume of adjacent cells. It should be noted, however, that the buried layer 22 can also be omitted, in particular if there is no need for an N-P junction for preventing penetration of photoelectrons from neighboring cells.

As mentioned above, according to an alternative embodiment in- stead of the material layer 25 a backside ion implantation can be employed with parameters as described above.

According to a further alternative embodiment instead of the material layer 25 the substrate 21 can be provided with a high doping level in the range of 10¹⁹ to 10²⁰ cm^"3 of second conductivity type. Highly Efficient CMOS-technology compatible photoelectric multipliers according to one of the above embodiments comprise in dependent cells typically having 20-100 microns of size, that is, for example, length of one side edge of one cell 1 or second layer 3. All the cells are jointed through quenching resis tors 5 with voltage distribution buses 6, and the identical bias voltage, exceeding the breakdown voltage, is applied to the cells 1, that provides working in the Geiger mode. The quenched Geiger discharge develops in the active region of the cell when a photon gets there. The quenching, that is stopping the discharge, takes place due to fluctuations of the number o the charge carriers up to zero when the voltage of the p-n boundary drops, due to availability of quenching resistor 5 (current-limiting resistor) in each cell. The current signals from the fired cells are summed up on a common load. The ampli fication of each cell constitutes up to 10⁷. The spread of amplification value is defined by technological spread of the cell capacity and breakdown voltage of the cell, and consti- tutes less than 5%. As all the cells are identical, the response of the detector to low intensity light flashes is proportional to the number of the worked cells, i.e. to light intensity. Fig. 5 shows a side view representation of a silicon-based pho toelectric multiplier according to a second embodiment. The silicon-based photoelectric multiplier 30 is not fabricated by a CMOS fabrication process. Instead the fabrication process starts from a light or medium n-doped silicon substrate 31 on the upper surface of which a heavily doped p++ layer 32 (5 x

10¹⁷ cm^-3 to 5 x 10¹⁸ cm^"3, for example) is generated by, for example, diffusion doping. Thereafter, a light or medium doped p layer 33 is epitaxially grown onto the layer 32. Within the epitaxially grown layer 33 a first p- doped layer 34 and a sec ond n+ layer 35 are embedded so that they form a first n-p junction in the vicinity of the surface of the cell. There- after, on top of the layer stack an insulation layer 36 is deposited which can be fabricated of a silicon oxide layer. A through-hole is formed in the insulation layer 36 at one end of it so that later the second layer 35 can be electrically con- tacted. Thereafter, a resistor layer 37 is deposited on the insulating layer 36 wherein the resistor layer 37 can be fabricated of undoped or lightly doped polysilicon. The resistor layer 37 acts as a quenching resistor to quench the Geiger discharge. Thereafter, the resistor layers 37 of the cells are connected together and with a voltage distribution line 38. At any desired and appropriate stage within the above process a material layer 25 can be deposited onto the back surface of the substrate 31 or a backside ion implantation can be employed. Further embodiments of the multiplier of Fig. 5 can be formed along the embodiments described above. For example, the layer 32 can be omitted and the substrate can be provided with a relatively high second conductivity type doping level of, for example, 5 x 10¹⁷ cm^"3 to 5 x 10¹⁸ cm^"3. Or the material layer 25 can be omitted and instead a highly doped substrate, a heavily implanted substrate and/or a structured substrate back surface can be provided.

Fig. 6 shows a cross-sectional representation of a radiation detector according to an embodiment. The radiation detector 40 includes a scintillator 41 that produces a scintillation or burst of light when a gamma-ray strikes the scintillator 41. The burst of light is received by an array of silicon-based photoelectric multipliers 42 as described above monolithically disposed a silicon substrate 43. The material of the scintilla- tor 41 can be one of LSO, LYSO, MLS, LGSO, LaBr and mixtures thereof. Also other scintillator materials can be used. The scintillator 41 can be composed of a single crystal or an array of crystals. In addition an optional planar light pipe 44 can be interposed between the scintillator 41 and the multipliers 42 to improve the transmission of photons of the light bursts to the multipliers 42. A plurality of radiation detectors 40 as shown in Fig. 6 can arranged within a positron emission tomography (PET) imaging system.

Claims

1. A cell (1) for a silicon based photoelectric multiplier, comprising :

- a substrate (21) of a second conductivity type,

- a first layer (2) of a first conductivity type,

- a second layer (3) of a second conductivity¹ type formed on the first layer (2) , wherein

- the first layer (2) and the second layer (3) form a first p-n junction,

c h a r a c t e r i z e d i n t h a t

- the substrate (21) is configured such that in operation of the photoelectric multiplier from a quantity of light propagating towards a backside or side wall of the multiplier a negligible portion returns to a frontside of the multiplier.

2. The cell according to claim 1, wherein

a material layer (25) is applied onto the back surface of the substrate (21) , wherein the material of the material layer (25) is chosen such that the reflectivity of light with a wavelength in a range of ~ 1000 nm incident on the interface between the substrate (21) and the material layer (25) is smaller than 25%.

3. The cell according to claim 2, wherein

the material of the material layer (25) comprises one or more of a metal, a metal compound, a metal alloy, or a semiconductor .

4. The cell according to claim 1, wherein

the back surface of the substrate (21) is processed by an ion implantation step wherein the parameters of the ion implantation are selected such that, due to an implantation-induced damage of the crystal lattice, an absorption length of light with a wavelength in a range of « 1000 nm is decreased.

5. The cell according to claim 1 or 4, wherein

the back surface of the substrate (21) is processed by an ion implantation step comprising an ion dose in the range of 10¹³ to 10¹⁵ cm^"2 and an ion energy in the range of 1 MeV to 10 MeV.

6. The cell according to claim 1, wherein

the doping concentration of the substrate (21) lies in a range of 10¹⁹ to 10²⁰ cm^"3.

7. The cell according to one of claims 1 to 6, wherein

the back surface of the substrate (21) comprises a structure fabricated so as to trap or to diffuse light incident from inside the substrate.

8. A silicon-based photoelectric multiplier, comprising:

a plurality of cells (1) according to one or more of the preceding claims, wherein

the cells (1) are fabricated on one common substrate (21).

9. A radiation detector (40) comprising:

a scintillator (41) ; and

an array of silicon-based photoelectric multipliers according to claim 9 arranged to receive bursts of light produced by the scintillator (41) in response to received radiation.

10. A method for fabricating a cell for a silicon-based photoelectric multiplier, comprising:

providing a substrate of a second conductivity type,

providing a first layer of a first conductivity type and a sec- ond layer of a second conductivity type, wherein

the first layer and the second layer form a first p-n junction, the substrate is configured such that in operation of the photoelectric multiplier from a quantity of light propagating towards a backside of the multiplier a negligible portion in- ternally returns to a frontside of the multiplier.

11. The method according to claim 10, further comprising:

applying a material layer onto the back surface of the substrate, wherein the material of the material layer is chosen such that the reflectivity of light with a wavelength in a range of « 1000 nm incident on the interface between the substrate and the material layer is smaller than 25%.

12. The method according to claim 11, wherein

the material of the material layer comprises one or more of a metal, a metal compound, a metal alloy, or a semiconductor.

13. The method according to claim 10, further comprising:

processing the back surface of the substrate by an ion implantation step wherein the parameters of the ion implantation are selected such that, due to an implantation-induced damage of the crystal lattice, an absorption length light with a wavelength in a range of « 1000 nm is decreased.

14. The method according to claim 10 or 11, further comprising: processing the back surface of the substrate by an ion implantation step comprising an ion dose in the range of 10¹³ to 10¹⁵ cm^-2 and an ion energy in the range 1 MeV to 10 MeV.

15. The method according to claim 11, wherein

the substrate is provided with a doping concentration in a range of 10¹⁹ to 10²⁰ cm^"3.

16. The method according to one of claims 10 to 15, further comprising

fabricating a structure into the back surface of the substrate so as to trap or to diffuse light incident from inside the substrate .